Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32783

1

T1

21

T2

10

T3

21

auto[1]

315

1

T116

5

T117

9

T141

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	32793	1			T1	21		T2	10		T3	21
auto[134217728:268435455]	7	1			T142	1		T330	1		T241	1
auto[268435456:402653183]	8	1			T116	1		T390	1		T297	1
auto[402653184:536870911]	4	1			T117	1		T133	1		T390	1
auto[536870912:671088639]	10	1			T116	1		T142	1		T131	1
auto[671088640:805306367]	7	1			T241	1		T390	1		T248	1
auto[805306368:939524095]	8	1			T117	1		T232	1		T330	1
auto[939524096:1073741823]	10	1			T142	1		T131	1		T133	1
auto[1073741824:1207959551]	13	1			T232	1		T234	1		T243	1
auto[1207959552:1342177279]	7	1			T232	1		T133	1		T330	1
auto[1342177280:1476395007]	13	1			T116	1		T133	1		T325	1
auto[1476395008:1610612735]	5	1			T406	1		T387	1		T252	2
auto[1610612736:1744830463]	12	1			T142	1		T134	1		T229	1
auto[1744830464:1879048191]	10	1			T131	1		T243	1		T407	1
auto[1879048192:2013265919]	11	1			T141	1		T142	1		T234	1
auto[2013265920:2147483647]	10	1			T131	1		T132	1		T133	1
auto[2147483648:2281701375]	13	1			T116	1		T117	1		T229	1
auto[2281701376:2415919103]	13	1			T232	1		T225	1		T243	1
auto[2415919104:2550136831]	10	1			T234	1		T330	1		T390	1
auto[2550136832:2684354559]	9	1			T132	1		T261	1		T360	1
auto[2684354560:2818572287]	13	1			T142	3		T133	1		T134	1
auto[2818572288:2952790015]	10	1			T134	1		T390	1		T407	1
auto[2952790016:3087007743]	10	1			T117	1		T131	1		T132	1
auto[3087007744:3221225471]	9	1			T117	1		T225	1		T241	1
auto[3221225472:3355443199]	8	1			T134	1		T225	1		T365	1
auto[3355443200:3489660927]	12	1			T141	1		T234	1		T390	2
auto[3489660928:3623878655]	16	1			T117	2		T142	2		T131	2
auto[3623878656:3758096383]	15	1			T116	1		T232	1		T234	1
auto[3758096384:3892314111]	10	1			T133	1		T390	1		T408	1
auto[3892314112:4026531839]	5	1			T133	1		T134	1		T261	1
auto[4026531840:4160749567]	12	1			T117	1		T131	1		T134	1
auto[4160749568:4294967295]	5	1			T132	1		T330	1		T297	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	32783	1			T1	21		T2	10		T3	21
auto[0:134217727]	auto[1]	10	1			T117	1		T133	2		T229	1
auto[134217728:268435455]	auto[1]	7	1			T142	1		T330	1		T241	1
auto[268435456:402653183]	auto[1]	8	1			T116	1		T390	1		T297	1
auto[402653184:536870911]	auto[1]	4	1			T117	1		T133	1		T390	1
auto[536870912:671088639]	auto[1]	10	1			T116	1		T142	1		T131	1
auto[671088640:805306367]	auto[1]	7	1			T241	1		T390	1		T248	1
auto[805306368:939524095]	auto[1]	8	1			T117	1		T232	1		T330	1
auto[939524096:1073741823]	auto[1]	10	1			T142	1		T131	1		T133	1
auto[1073741824:1207959551]	auto[1]	13	1			T232	1		T234	1		T243	1
auto[1207959552:1342177279]	auto[1]	7	1			T232	1		T133	1		T330	1
auto[1342177280:1476395007]	auto[1]	13	1			T116	1		T133	1		T325	1
auto[1476395008:1610612735]	auto[1]	5	1			T406	1		T387	1		T252	2
auto[1610612736:1744830463]	auto[1]	12	1			T142	1		T134	1		T229	1
auto[1744830464:1879048191]	auto[1]	10	1			T131	1		T243	1		T407	1
auto[1879048192:2013265919]	auto[1]	11	1			T141	1		T142	1		T234	1
auto[2013265920:2147483647]	auto[1]	10	1			T131	1		T132	1		T133	1
auto[2147483648:2281701375]	auto[1]	13	1			T116	1		T117	1		T229	1
auto[2281701376:2415919103]	auto[1]	13	1			T232	1		T225	1		T243	1
auto[2415919104:2550136831]	auto[1]	10	1			T234	1		T330	1		T390	1
auto[2550136832:2684354559]	auto[1]	9	1			T132	1		T261	1		T360	1
auto[2684354560:2818572287]	auto[1]	13	1			T142	3		T133	1		T134	1
auto[2818572288:2952790015]	auto[1]	10	1			T134	1		T390	1		T407	1
auto[2952790016:3087007743]	auto[1]	10	1			T117	1		T131	1		T132	1
auto[3087007744:3221225471]	auto[1]	9	1			T117	1		T225	1		T241	1
auto[3221225472:3355443199]	auto[1]	8	1			T134	1		T225	1		T365	1
auto[3355443200:3489660927]	auto[1]	12	1			T141	1		T234	1		T390	2
auto[3489660928:3623878655]	auto[1]	16	1			T117	2		T142	2		T131	2
auto[3623878656:3758096383]	auto[1]	15	1			T116	1		T232	1		T234	1
auto[3758096384:3892314111]	auto[1]	10	1			T133	1		T390	1		T408	1
auto[3892314112:4026531839]	auto[1]	5	1			T133	1		T134	1		T261	1
auto[4026531840:4160749567]	auto[1]	12	1			T117	1		T131	1		T134	1
auto[4160749568:4294967295]	auto[1]	5	1			T132	1		T330	1		T297	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1645

1

T16

4

T17

2

T19

1

auto[1]

1753

1

T2

1

T4

2

T16

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	97	1			T17	1		T62	1		T56	1
auto[134217728:268435455]	78	1			T116	1		T56	1		T183	1
auto[268435456:402653183]	111	1			T124	1		T29	2		T185	1
auto[402653184:536870911]	117	1			T62	1		T44	1		T184	1
auto[536870912:671088639]	99	1			T16	1		T17	1		T25	1
auto[671088640:805306367]	103	1			T16	1		T70	2		T40	1
auto[805306368:939524095]	101	1			T20	1		T117	1		T27	1
auto[939524096:1073741823]	105	1			T116	1		T26	1		T185	1
auto[1073741824:1207959551]	92	1			T41	1		T86	1		T28	1
auto[1207959552:1342177279]	102	1			T116	1		T187	1		T186	1
auto[1342177280:1476395007]	112	1			T25	1		T187	1		T183	1
auto[1476395008:1610612735]	103	1			T116	1		T51	1		T141	1
auto[1610612736:1744830463]	104	1			T85	1		T57	3		T71	1
auto[1744830464:1879048191]	119	1			T16	1		T17	1		T187	1
auto[1879048192:2013265919]	100	1			T27	1		T67	1		T188	1
auto[2013265920:2147483647]	110	1			T116	1		T62	1		T44	1
auto[2147483648:2281701375]	113	1			T16	1		T117	1		T44	1
auto[2281701376:2415919103]	137	1			T124	1		T188	2		T71	1
auto[2415919104:2550136831]	85	1			T20	1		T57	1		T55	1
auto[2550136832:2684354559]	121	1			T85	2		T124	1		T63	1
auto[2684354560:2818572287]	114	1			T85	1		T25	1		T193	1
auto[2818572288:2952790015]	120	1			T117	1		T196	1		T36	2
auto[2952790016:3087007743]	105	1			T117	2		T184	2		T27	1
auto[3087007744:3221225471]	91	1			T16	1		T36	1		T21	1
auto[3221225472:3355443199]	104	1			T19	1		T47	1		T25	1
auto[3355443200:3489660927]	99	1			T17	1		T41	1		T124	1
auto[3489660928:3623878655]	106	1			T16	1		T19	1		T116	1
auto[3623878656:3758096383]	104	1			T4	1		T124	1		T185	1
auto[3758096384:3892314111]	111	1			T4	1		T44	2		T27	1
auto[3892314112:4026531839]	109	1			T17	1		T54	1		T64	1
auto[4026531840:4160749567]	115	1			T19	1		T26	1		T185	1
auto[4160749568:4294967295]	111	1			T2	1		T19	1		T124	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	48	1			T141	1		T28	1		T57	1
auto[0:134217727]	auto[1]	49	1			T17	1		T62	1		T56	1
auto[134217728:268435455]	auto[0]	43	1			T116	1		T56	1		T70	1
auto[134217728:268435455]	auto[1]	35	1			T183	1		T72	1		T201	1
auto[268435456:402653183]	auto[0]	49	1			T124	1		T29	1		T188	1
auto[268435456:402653183]	auto[1]	62	1			T29	1		T185	1		T57	2
auto[402653184:536870911]	auto[0]	65	1			T62	1		T44	1		T26	2
auto[402653184:536870911]	auto[1]	52	1			T184	1		T186	1		T6	1
auto[536870912:671088639]	auto[0]	44	1			T25	1		T188	1		T87	1
auto[536870912:671088639]	auto[1]	55	1			T16	1		T17	1		T101	1
auto[671088640:805306367]	auto[0]	56	1			T16	1		T40	1		T178	1
auto[671088640:805306367]	auto[1]	47	1			T70	2		T142	1		T46	1
auto[805306368:939524095]	auto[0]	52	1			T27	1		T36	1		T86	1
auto[805306368:939524095]	auto[1]	49	1			T20	1		T117	1		T36	1
auto[939524096:1073741823]	auto[0]	47	1			T116	1		T178	1		T99	1
auto[939524096:1073741823]	auto[1]	58	1			T26	1		T185	1		T57	1
auto[1073741824:1207959551]	auto[0]	43	1			T28	1		T57	1		T409	1
auto[1073741824:1207959551]	auto[1]	49	1			T41	1		T86	1		T245	1
auto[1207959552:1342177279]	auto[0]	46	1			T187	1		T63	1		T64	1
auto[1207959552:1342177279]	auto[1]	56	1			T116	1		T186	1		T86	1
auto[1342177280:1476395007]	auto[0]	57	1			T25	1		T183	1		T45	1
auto[1342177280:1476395007]	auto[1]	55	1			T187	1		T86	1		T69	1
auto[1476395008:1610612735]	auto[0]	45	1			T116	1		T51	1		T26	1
auto[1476395008:1610612735]	auto[1]	58	1			T141	1		T70	1		T40	1
auto[1610612736:1744830463]	auto[0]	50	1			T57	1		T73	1		T46	1
auto[1610612736:1744830463]	auto[1]	54	1			T85	1		T57	2		T71	1
auto[1744830464:1879048191]	auto[0]	53	1			T16	1		T17	1		T26	1
auto[1744830464:1879048191]	auto[1]	66	1			T187	1		T183	1		T67	1
auto[1879048192:2013265919]	auto[0]	53	1			T27	1		T28	1		T57	1
auto[1879048192:2013265919]	auto[1]	47	1			T67	1		T188	1		T57	1
auto[2013265920:2147483647]	auto[0]	50	1			T116	1		T185	1		T28	1
auto[2013265920:2147483647]	auto[1]	60	1			T62	1		T44	1		T57	1
auto[2147483648:2281701375]	auto[0]	50	1			T36	1		T188	1		T57	1
auto[2147483648:2281701375]	auto[1]	63	1			T16	1		T117	1		T44	1
auto[2281701376:2415919103]	auto[0]	77	1			T124	1		T188	1		T45	1
auto[2281701376:2415919103]	auto[1]	60	1			T188	1		T71	1		T301	1
auto[2415919104:2550136831]	auto[0]	40	1			T76	1		T94	1		T125	1
auto[2415919104:2550136831]	auto[1]	45	1			T20	1		T57	1		T55	1
auto[2550136832:2684354559]	auto[0]	53	1			T85	2		T63	1		T57	1
auto[2550136832:2684354559]	auto[1]	68	1			T124	1		T64	1		T57	1
auto[2684354560:2818572287]	auto[0]	49	1			T85	1		T25	1		T193	1
auto[2684354560:2818572287]	auto[1]	65	1			T141	2		T57	1		T71	2
auto[2818572288:2952790015]	auto[0]	56	1			T196	1		T36	1		T188	1
auto[2818572288:2952790015]	auto[1]	64	1			T117	1		T36	1		T57	3
auto[2952790016:3087007743]	auto[0]	51	1			T117	1		T184	1		T27	1
auto[2952790016:3087007743]	auto[1]	54	1			T117	1		T184	1		T57	1
auto[3087007744:3221225471]	auto[0]	46	1			T16	1		T36	1		T21	1
auto[3087007744:3221225471]	auto[1]	45	1			T60	2		T46	1		T22	1
auto[3221225472:3355443199]	auto[0]	48	1			T36	1		T70	1		T55	1
auto[3221225472:3355443199]	auto[1]	56	1			T19	1		T47	1		T25	1
auto[3355443200:3489660927]	auto[0]	42	1			T41	1		T55	1		T6	1
auto[3355443200:3489660927]	auto[1]	57	1			T17	1		T124	1		T63	1
auto[3489660928:3623878655]	auto[0]	60	1			T16	1		T116	1		T141	1
auto[3489660928:3623878655]	auto[1]	46	1			T19	1		T62	1		T63	1
auto[3623878656:3758096383]	auto[0]	47	1			T185	1		T86	1		T40	2
auto[3623878656:3758096383]	auto[1]	57	1			T4	1		T124	1		T36	1
auto[3758096384:3892314111]	auto[0]	62	1			T44	2		T27	1		T196	1
auto[3758096384:3892314111]	auto[1]	49	1			T4	1		T57	1		T88	2
auto[3892314112:4026531839]	auto[0]	53	1			T17	1		T40	1		T99	1
auto[3892314112:4026531839]	auto[1]	56	1			T54	1		T64	1		T185	1
auto[4026531840:4160749567]	auto[0]	62	1			T19	1		T26	1		T185	1
auto[4026531840:4160749567]	auto[1]	53	1			T57	1		T71	1		T179	1
auto[4160749568:4294967295]	auto[0]	48	1			T124	1		T183	1		T28	1
auto[4160749568:4294967295]	auto[1]	63	1			T2	1		T19	1		T62	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1644

1

T16

4

T17

2

T19

2

auto[1]

1754

1

T2

1

T4

2

T16

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	109	1			T47	1		T20	1		T117	1
auto[134217728:268435455]	94	1			T141	1		T29	1		T186	1
auto[268435456:402653183]	88	1			T4	1		T187	1		T188	1
auto[402653184:536870911]	108	1			T17	1		T44	1		T188	1
auto[536870912:671088639]	123	1			T16	2		T26	1		T40	1
auto[671088640:805306367]	102	1			T16	1		T41	1		T51	1
auto[805306368:939524095]	121	1			T116	1		T193	1		T26	1
auto[939524096:1073741823]	107	1			T124	1		T26	1		T63	1
auto[1073741824:1207959551]	109	1			T19	1		T62	1		T27	1
auto[1207959552:1342177279]	119	1			T116	1		T71	1		T59	1
auto[1342177280:1476395007]	125	1			T124	1		T62	1		T186	1
auto[1476395008:1610612735]	102	1			T186	1		T27	1		T57	2
auto[1610612736:1744830463]	105	1			T17	1		T62	1		T183	1
auto[1744830464:1879048191]	92	1			T62	1		T141	1		T188	1
auto[1879048192:2013265919]	96	1			T16	1		T17	1		T44	1
auto[2013265920:2147483647]	102	1			T36	1		T57	3		T267	1
auto[2147483648:2281701375]	104	1			T183	1		T28	1		T70	2
auto[2281701376:2415919103]	114	1			T2	1		T25	1		T117	1
auto[2415919104:2550136831]	118	1			T117	1		T184	1		T187	1
auto[2550136832:2684354559]	97	1			T85	2		T25	1		T116	1
auto[2684354560:2818572287]	117	1			T19	1		T85	1		T124	1
auto[2818572288:2952790015]	99	1			T16	1		T17	1		T27	1
auto[2952790016:3087007743]	89	1			T41	1		T26	1		T57	2
auto[3087007744:3221225471]	113	1			T116	1		T193	1		T71	1
auto[3221225472:3355443199]	97	1			T54	1		T85	1		T124	1
auto[3355443200:3489660927]	105	1			T16	1		T117	1		T26	1
auto[3489660928:3623878655]	86	1			T19	1		T116	1		T187	1
auto[3623878656:3758096383]	141	1			T20	1		T62	1		T44	1
auto[3758096384:3892314111]	102	1			T4	1		T25	1		T44	1
auto[3892314112:4026531839]	113	1			T17	1		T117	1		T36	1
auto[4026531840:4160749567]	99	1			T116	1		T188	1		T71	2
auto[4160749568:4294967295]	102	1			T19	1		T25	1		T184	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	51	1			T124	1		T301	1		T45	2
auto[0:134217727]	auto[1]	58	1			T47	1		T20	1		T117	1
auto[134217728:268435455]	auto[0]	42	1			T141	1		T29	1		T57	1
auto[134217728:268435455]	auto[1]	52	1			T186	1		T92	1		T10	1
auto[268435456:402653183]	auto[0]	49	1			T187	1		T188	1		T203	1
auto[268435456:402653183]	auto[1]	39	1			T4	1		T57	1		T55	1
auto[402653184:536870911]	auto[0]	58	1			T44	1		T28	1		T71	1
auto[402653184:536870911]	auto[1]	50	1			T17	1		T188	1		T28	1
auto[536870912:671088639]	auto[0]	57	1			T16	2		T26	1		T40	1
auto[536870912:671088639]	auto[1]	66	1			T57	1		T87	1		T30	1
auto[671088640:805306367]	auto[0]	44	1			T41	1		T51	1		T57	2
auto[671088640:805306367]	auto[1]	58	1			T16	1		T184	1		T63	1
auto[805306368:939524095]	auto[0]	66	1			T26	1		T57	1		T71	1
auto[805306368:939524095]	auto[1]	55	1			T116	1		T193	1		T185	1
auto[939524096:1073741823]	auto[0]	53	1			T26	1		T63	1		T99	1
auto[939524096:1073741823]	auto[1]	54	1			T124	1		T57	1		T60	1
auto[1073741824:1207959551]	auto[0]	50	1			T27	1		T28	1		T40	1
auto[1073741824:1207959551]	auto[1]	59	1			T19	1		T62	1		T63	1
auto[1207959552:1342177279]	auto[0]	59	1			T116	1		T88	1		T190	1
auto[1207959552:1342177279]	auto[1]	60	1			T71	1		T59	1		T21	1
auto[1342177280:1476395007]	auto[0]	57	1			T124	1		T27	1		T63	1
auto[1342177280:1476395007]	auto[1]	68	1			T62	1		T186	1		T188	1
auto[1476395008:1610612735]	auto[0]	50	1			T27	1		T57	2		T73	1
auto[1476395008:1610612735]	auto[1]	52	1			T186	1		T71	2		T45	1
auto[1610612736:1744830463]	auto[0]	45	1			T185	1		T88	1		T76	1
auto[1610612736:1744830463]	auto[1]	60	1			T17	1		T62	1		T183	1
auto[1744830464:1879048191]	auto[0]	41	1			T188	1		T86	1		T245	1
auto[1744830464:1879048191]	auto[1]	51	1			T62	1		T141	1		T88	1
auto[1879048192:2013265919]	auto[0]	51	1			T16	1		T17	1		T28	1
auto[1879048192:2013265919]	auto[1]	45	1			T44	1		T184	1		T64	1
auto[2013265920:2147483647]	auto[0]	44	1			T36	1		T267	1		T87	1
auto[2013265920:2147483647]	auto[1]	58	1			T57	3		T22	1		T102	1
auto[2147483648:2281701375]	auto[0]	55	1			T183	1		T28	1		T70	1
auto[2147483648:2281701375]	auto[1]	49	1			T70	1		T57	2		T71	1
auto[2281701376:2415919103]	auto[0]	54	1			T25	1		T44	1		T27	1
auto[2281701376:2415919103]	auto[1]	60	1			T2	1		T117	1		T141	1
auto[2415919104:2550136831]	auto[0]	57	1			T184	1		T29	1		T26	1
auto[2415919104:2550136831]	auto[1]	61	1			T117	1		T187	1		T67	1
auto[2550136832:2684354559]	auto[0]	49	1			T85	1		T141	1		T71	1
auto[2550136832:2684354559]	auto[1]	48	1			T85	1		T25	1		T116	1
auto[2684354560:2818572287]	auto[0]	52	1			T85	1		T124	1		T183	1
auto[2684354560:2818572287]	auto[1]	65	1			T19	1		T56	1		T36	1
auto[2818572288:2952790015]	auto[0]	56	1			T16	1		T17	1		T27	1
auto[2818572288:2952790015]	auto[1]	43	1			T185	2		T57	1		T59	1
auto[2952790016:3087007743]	auto[0]	43	1			T26	1		T45	1		T46	2
auto[2952790016:3087007743]	auto[1]	46	1			T41	1		T57	2		T101	1
auto[3087007744:3221225471]	auto[0]	49	1			T116	1		T55	1		T46	1
auto[3087007744:3221225471]	auto[1]	64	1			T193	1		T71	1		T301	1
auto[3221225472:3355443199]	auto[0]	47	1			T85	1		T124	1		T36	1
auto[3221225472:3355443199]	auto[1]	50	1			T54	1		T185	1		T86	2
auto[3355443200:3489660927]	auto[0]	56	1			T26	1		T36	1		T40	1
auto[3355443200:3489660927]	auto[1]	49	1			T16	1		T117	1		T57	1
auto[3489660928:3623878655]	auto[0]	44	1			T19	1		T116	1		T45	1
auto[3489660928:3623878655]	auto[1]	42	1			T187	1		T57	1		T6	1
auto[3623878656:3758096383]	auto[0]	66	1			T40	1		T45	1		T88	1
auto[3623878656:3758096383]	auto[1]	75	1			T20	1		T62	1		T44	1
auto[3758096384:3892314111]	auto[0]	53	1			T25	1		T44	1		T64	1
auto[3758096384:3892314111]	auto[1]	49	1			T4	1		T36	1		T71	1
auto[3892314112:4026531839]	auto[0]	53	1			T117	1		T178	1		T409	1
auto[3892314112:4026531839]	auto[1]	60	1			T17	1		T36	1		T57	2
auto[4026531840:4160749567]	auto[0]	41	1			T116	1		T71	1		T6	1
auto[4026531840:4160749567]	auto[1]	58	1			T188	1		T71	1		T55	1
auto[4160749568:4294967295]	auto[0]	52	1			T19	1		T25	1		T184	1
auto[4160749568:4294967295]	auto[1]	50	1			T56	1		T64	1		T36	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1637

1

T16

3

T17

2

T19

1

auto[1]

1760

1

T2

1

T4

2

T16

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	101	1			T16	1		T41	1		T124	1
auto[134217728:268435455]	101	1			T27	1		T70	1		T57	1
auto[268435456:402653183]	101	1			T4	1		T116	1		T184	1
auto[402653184:536870911]	96	1			T41	1		T117	1		T56	1
auto[536870912:671088639]	109	1			T19	2		T54	1		T36	1
auto[671088640:805306367]	109	1			T116	1		T187	1		T86	1
auto[805306368:939524095]	97	1			T17	1		T62	1		T56	1
auto[939524096:1073741823]	110	1			T63	1		T57	1		T71	1
auto[1073741824:1207959551]	113	1			T44	1		T185	1		T28	1
auto[1207959552:1342177279]	106	1			T25	1		T62	1		T183	1
auto[1342177280:1476395007]	114	1			T85	1		T63	1		T57	1
auto[1476395008:1610612735]	92	1			T85	1		T63	1		T188	1
auto[1610612736:1744830463]	92	1			T19	1		T184	1		T141	1
auto[1744830464:1879048191]	99	1			T116	1		T51	1		T44	1
auto[1879048192:2013265919]	109	1			T2	1		T4	1		T16	1
auto[2013265920:2147483647]	99	1			T85	1		T141	1		T187	1
auto[2147483648:2281701375]	117	1			T25	2		T20	1		T188	1
auto[2281701376:2415919103]	105	1			T16	1		T17	1		T116	1
auto[2415919104:2550136831]	102	1			T124	1		T141	1		T26	1
auto[2550136832:2684354559]	106	1			T116	1		T186	1		T27	1
auto[2684354560:2818572287]	127	1			T16	1		T25	1		T185	1
auto[2818572288:2952790015]	120	1			T17	1		T124	1		T26	1
auto[2952790016:3087007743]	95	1			T117	1		T124	1		T141	1
auto[3087007744:3221225471]	94	1			T62	1		T184	1		T185	1
auto[3221225472:3355443199]	103	1			T27	1		T57	4		T71	1
auto[3355443200:3489660927]	107	1			T117	1		T184	1		T29	1
auto[3489660928:3623878655]	112	1			T64	1		T36	1		T188	1
auto[3623878656:3758096383]	114	1			T19	1		T44	1		T193	1
auto[3758096384:3892314111]	125	1			T16	1		T85	1		T20	1
auto[3892314112:4026531839]	98	1			T47	1		T124	1		T141	1
auto[4026531840:4160749567]	105	1			T16	1		T26	2		T63	1
auto[4160749568:4294967295]	119	1			T117	1		T124	1		T44	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	48	1			T28	1		T88	1		T257	1
auto[0:134217727]	auto[1]	53	1			T16	1		T41	1		T124	1
auto[134217728:268435455]	auto[0]	46	1			T27	1		T182	1		T6	1
auto[134217728:268435455]	auto[1]	55	1			T70	1		T57	1		T59	1
auto[268435456:402653183]	auto[0]	39	1			T116	1		T187	1		T26	1
auto[268435456:402653183]	auto[1]	62	1			T4	1		T184	1		T40	1
auto[402653184:536870911]	auto[0]	45	1			T41	1		T36	1		T188	1
auto[402653184:536870911]	auto[1]	51	1			T117	1		T56	1		T86	1
auto[536870912:671088639]	auto[0]	48	1			T188	1		T6	1		T30	1
auto[536870912:671088639]	auto[1]	61	1			T19	2		T54	1		T36	1
auto[671088640:805306367]	auto[0]	59	1			T116	1		T86	1		T178	2
auto[671088640:805306367]	auto[1]	50	1			T187	1		T70	1		T71	1
auto[805306368:939524095]	auto[0]	45	1			T17	1		T196	1		T88	3
auto[805306368:939524095]	auto[1]	52	1			T62	1		T56	1		T36	1
auto[939524096:1073741823]	auto[0]	55	1			T45	1		T60	1		T93	1
auto[939524096:1073741823]	auto[1]	55	1			T63	1		T57	1		T71	1
auto[1073741824:1207959551]	auto[0]	55	1			T28	1		T57	1		T45	1
auto[1073741824:1207959551]	auto[1]	58	1			T44	1		T185	1		T57	1
auto[1207959552:1342177279]	auto[0]	57	1			T25	1		T183	1		T28	1
auto[1207959552:1342177279]	auto[1]	49	1			T62	1		T86	1		T142	1
auto[1342177280:1476395007]	auto[0]	53	1			T85	1		T63	1		T57	1
auto[1342177280:1476395007]	auto[1]	61	1			T55	1		T92	2		T267	1
auto[1476395008:1610612735]	auto[0]	42	1			T63	1		T188	1		T55	1
auto[1476395008:1610612735]	auto[1]	50	1			T85	1		T182	1		T263	1
auto[1610612736:1744830463]	auto[0]	49	1			T19	1		T184	1		T196	1
auto[1610612736:1744830463]	auto[1]	43	1			T141	1		T86	1		T182	1
auto[1744830464:1879048191]	auto[0]	43	1			T51	1		T44	1		T40	1
auto[1744830464:1879048191]	auto[1]	56	1			T116	1		T6	1		T46	1
auto[1879048192:2013265919]	auto[0]	50	1			T17	1		T116	1		T36	1
auto[1879048192:2013265919]	auto[1]	59	1			T2	1		T4	1		T16	1
auto[2013265920:2147483647]	auto[0]	43	1			T187	1		T57	1		T71	1
auto[2013265920:2147483647]	auto[1]	56	1			T85	1		T141	1		T57	2
auto[2147483648:2281701375]	auto[0]	56	1			T25	2		T57	1		T71	1
auto[2147483648:2281701375]	auto[1]	61	1			T20	1		T188	1		T57	1
auto[2281701376:2415919103]	auto[0]	56	1			T16	1		T116	1		T117	1
auto[2281701376:2415919103]	auto[1]	49	1			T17	1		T62	1		T183	1
auto[2415919104:2550136831]	auto[0]	46	1			T124	1		T88	1		T76	1
auto[2415919104:2550136831]	auto[1]	56	1			T141	1		T26	1		T67	1
auto[2550136832:2684354559]	auto[0]	56	1			T27	1		T57	1		T267	1
auto[2550136832:2684354559]	auto[1]	50	1			T116	1		T186	1		T183	1
auto[2684354560:2818572287]	auto[0]	69	1			T16	1		T188	1		T40	1
auto[2684354560:2818572287]	auto[1]	58	1			T25	1		T185	1		T71	1
auto[2818572288:2952790015]	auto[0]	57	1			T124	1		T26	1		T27	1
auto[2818572288:2952790015]	auto[1]	63	1			T17	1		T7	3		T245	1
auto[2952790016:3087007743]	auto[0]	39	1			T141	1		T55	1		T178	1
auto[2952790016:3087007743]	auto[1]	56	1			T117	1		T124	1		T301	1
auto[3087007744:3221225471]	auto[0]	57	1			T184	1		T88	1		T46	2
auto[3087007744:3221225471]	auto[1]	37	1			T62	1		T185	1		T73	1
auto[3221225472:3355443199]	auto[0]	55	1			T27	1		T57	1		T71	1
auto[3221225472:3355443199]	auto[1]	48	1			T57	3		T10	1		T60	1
auto[3355443200:3489660927]	auto[0]	53	1			T29	1		T27	1		T188	1
auto[3355443200:3489660927]	auto[1]	54	1			T117	1		T184	1		T36	1
auto[3489660928:3623878655]	auto[0]	54	1			T70	1		T57	2		T71	1
auto[3489660928:3623878655]	auto[1]	58	1			T64	1		T36	1		T188	1
auto[3623878656:3758096383]	auto[0]	58	1			T193	1		T36	1		T267	1
auto[3623878656:3758096383]	auto[1]	56	1			T19	1		T44	1		T185	1
auto[3758096384:3892314111]	auto[0]	59	1			T16	1		T26	1		T185	1
auto[3758096384:3892314111]	auto[1]	66	1			T85	1		T20	1		T28	1
auto[3892314112:4026531839]	auto[0]	43	1			T124	1		T71	2		T92	1
auto[3892314112:4026531839]	auto[1]	55	1			T47	1		T141	1		T9	1
auto[4026531840:4160749567]	auto[0]	51	1			T26	2		T28	1		T88	1
auto[4026531840:4160749567]	auto[1]	54	1			T16	1		T63	1		T188	1
auto[4160749568:4294967295]	auto[0]	51	1			T44	1		T36	1		T40	1
auto[4160749568:4294967295]	auto[1]	68	1			T117	1		T124	1		T29	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1652

1

T16

4

T17

2

T19

1

auto[1]

1745

1

T2

1

T4

2

T16

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	112	1			T41	1		T184	1		T26	1
auto[134217728:268435455]	105	1			T19	1		T57	2		T71	1
auto[268435456:402653183]	108	1			T116	1		T29	1		T27	1
auto[402653184:536870911]	82	1			T16	1		T19	1		T25	1
auto[536870912:671088639]	112	1			T85	1		T116	1		T62	1
auto[671088640:805306367]	103	1			T17	1		T41	1		T85	1
auto[805306368:939524095]	92	1			T17	1		T62	1		T44	1
auto[939524096:1073741823]	107	1			T17	1		T47	1		T63	1
auto[1073741824:1207959551]	107	1			T62	1		T44	1		T64	1
auto[1207959552:1342177279]	105	1			T26	1		T183	1		T67	1
auto[1342177280:1476395007]	107	1			T116	1		T124	1		T28	1
auto[1476395008:1610612735]	102	1			T16	2		T186	1		T183	1
auto[1610612736:1744830463]	116	1			T4	1		T85	1		T56	1
auto[1744830464:1879048191]	106	1			T17	1		T117	1		T57	1
auto[1879048192:2013265919]	119	1			T20	1		T117	1		T62	1
auto[2013265920:2147483647]	99	1			T124	1		T196	1		T57	1
auto[2147483648:2281701375]	107	1			T4	1		T25	1		T116	1
auto[2281701376:2415919103]	103	1			T25	1		T116	1		T28	1
auto[2415919104:2550136831]	123	1			T187	1		T63	1		T36	3
auto[2550136832:2684354559]	106	1			T63	2		T36	1		T57	1
auto[2684354560:2818572287]	114	1			T16	1		T54	1		T117	1
auto[2818572288:2952790015]	111	1			T70	1		T45	1		T267	1
auto[2952790016:3087007743]	102	1			T19	1		T20	1		T184	1
auto[3087007744:3221225471]	117	1			T187	1		T183	1		T36	1
auto[3221225472:3355443199]	106	1			T124	1		T62	1		T36	1
auto[3355443200:3489660927]	90	1			T56	1		T186	1		T185	2
auto[3489660928:3623878655]	97	1			T16	1		T124	2		T193	1
auto[3623878656:3758096383]	102	1			T2	1		T19	1		T85	1
auto[3758096384:3892314111]	111	1			T16	1		T17	1		T25	1
auto[3892314112:4026531839]	101	1			T186	1		T67	1		T28	1
auto[4026531840:4160749567]	97	1			T124	1		T44	1		T27	1
auto[4160749568:4294967295]	128	1			T117	1		T51	1		T141	2