Unified Coverage Report :: Group Instance : salt_4

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2939

1

T2

1

T4

2

T16

6

auto[1]

320

1

T116

2

T117

9

T141

6

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	101	1			T116	1		T124	1		T141	3
auto[134217728:268435455]	114	1			T187	1		T67	1		T188	1
auto[268435456:402653183]	92	1			T4	1		T116	1		T184	1
auto[402653184:536870911]	100	1			T41	1		T44	1		T185	1
auto[536870912:671088639]	91	1			T17	1		T25	1		T117	1
auto[671088640:805306367]	112	1			T62	1		T56	1		T188	1
auto[805306368:939524095]	109	1			T19	1		T124	1		T29	1
auto[939524096:1073741823]	118	1			T17	1		T117	1		T183	2
auto[1073741824:1207959551]	105	1			T117	1		T193	1		T26	1
auto[1207959552:1342177279]	84	1			T85	1		T20	1		T116	1
auto[1342177280:1476395007]	85	1			T27	1		T67	1		T57	1
auto[1476395008:1610612735]	106	1			T4	1		T25	1		T124	1
auto[1610612736:1744830463]	116	1			T54	1		T25	1		T51	1
auto[1744830464:1879048191]	105	1			T117	1		T124	1		T56	1
auto[1879048192:2013265919]	106	1			T116	1		T117	1		T184	1
auto[2013265920:2147483647]	99	1			T26	1		T188	2		T88	1
auto[2147483648:2281701375]	97	1			T17	1		T47	1		T27	1
auto[2281701376:2415919103]	102	1			T116	2		T193	1		T184	1
auto[2415919104:2550136831]	105	1			T117	2		T62	1		T141	1
auto[2550136832:2684354559]	107	1			T41	1		T117	2		T183	1
auto[2684354560:2818572287]	104	1			T44	2		T28	1		T57	3
auto[2818572288:2952790015]	101	1			T116	2		T63	1		T185	1
auto[2952790016:3087007743]	106	1			T141	1		T26	1		T64	1
auto[3087007744:3221225471]	92	1			T16	3		T117	1		T186	1
auto[3221225472:3355443199]	98	1			T184	1		T64	1		T36	1
auto[3355443200:3489660927]	78	1			T20	1		T117	1		T187	1
auto[3489660928:3623878655]	99	1			T85	1		T25	1		T117	2
auto[3623878656:3758096383]	106	1			T16	2		T17	1		T26	1
auto[3758096384:3892314111]	107	1			T2	1		T85	1		T141	1
auto[3892314112:4026531839]	92	1			T19	1		T117	1		T124	1
auto[4026531840:4160749567]	112	1			T16	1		T17	1		T26	1
auto[4160749568:4294967295]	110	1			T85	1		T124	1		T62	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	87	1			T124	1		T141	1		T36	1
auto[0:134217727]	auto[1]	14	1			T116	1		T141	2		T142	1
auto[134217728:268435455]	auto[0]	102	1			T187	1		T67	1		T188	1
auto[134217728:268435455]	auto[1]	12	1			T142	1		T232	1		T133	1
auto[268435456:402653183]	auto[0]	89	1			T4	1		T116	1		T184	1
auto[268435456:402653183]	auto[1]	3	1			T142	1		T131	1		T390	1
auto[402653184:536870911]	auto[0]	86	1			T41	1		T44	1		T185	1
auto[402653184:536870911]	auto[1]	14	1			T243	2		T241	1		T360	1
auto[536870912:671088639]	auto[0]	79	1			T17	1		T25	1		T185	1
auto[536870912:671088639]	auto[1]	12	1			T117	1		T141	1		T132	1
auto[671088640:805306367]	auto[0]	102	1			T62	1		T56	1		T188	1
auto[671088640:805306367]	auto[1]	10	1			T142	1		T232	1		T132	2
auto[805306368:939524095]	auto[0]	96	1			T19	1		T124	1		T29	1
auto[805306368:939524095]	auto[1]	13	1			T232	1		T132	1		T133	1
auto[939524096:1073741823]	auto[0]	112	1			T17	1		T117	1		T183	2
auto[939524096:1073741823]	auto[1]	6	1			T133	1		T390	1		T360	1
auto[1073741824:1207959551]	auto[0]	96	1			T117	1		T193	1		T26	1
auto[1073741824:1207959551]	auto[1]	9	1			T132	1		T330	1		T225	1
auto[1207959552:1342177279]	auto[0]	79	1			T85	1		T20	1		T116	1
auto[1207959552:1342177279]	auto[1]	5	1			T134	1		T330	1		T365	1
auto[1342177280:1476395007]	auto[0]	75	1			T27	1		T67	1		T57	1
auto[1342177280:1476395007]	auto[1]	10	1			T232	1		T229	1		T330	1
auto[1476395008:1610612735]	auto[0]	94	1			T4	1		T25	1		T124	1
auto[1476395008:1610612735]	auto[1]	12	1			T141	1		T131	1		T232	2
auto[1610612736:1744830463]	auto[0]	106	1			T54	1		T25	1		T51	1
auto[1610612736:1744830463]	auto[1]	10	1			T232	1		T243	1		T241	1
auto[1744830464:1879048191]	auto[0]	92	1			T124	1		T56	1		T70	1
auto[1744830464:1879048191]	auto[1]	13	1			T117	1		T225	1		T390	1
auto[1879048192:2013265919]	auto[0]	93	1			T116	1		T184	1		T196	1
auto[1879048192:2013265919]	auto[1]	13	1			T117	1		T142	1		T132	1
auto[2013265920:2147483647]	auto[0]	91	1			T26	1		T188	2		T88	1
auto[2013265920:2147483647]	auto[1]	8	1			T234	1		T241	1		T360	1
auto[2147483648:2281701375]	auto[0]	87	1			T17	1		T47	1		T27	1
auto[2147483648:2281701375]	auto[1]	10	1			T225	1		T243	1		T241	1
auto[2281701376:2415919103]	auto[0]	92	1			T116	1		T193	1		T184	1
auto[2281701376:2415919103]	auto[1]	10	1			T116	1		T390	1		T248	1
auto[2415919104:2550136831]	auto[0]	88	1			T117	1		T62	1		T183	1
auto[2415919104:2550136831]	auto[1]	17	1			T117	1		T141	1		T142	1
auto[2550136832:2684354559]	auto[0]	96	1			T41	1		T183	1		T185	1
auto[2550136832:2684354559]	auto[1]	11	1			T117	2		T131	1		T132	1
auto[2684354560:2818572287]	auto[0]	94	1			T44	2		T28	1		T57	3
auto[2684354560:2818572287]	auto[1]	10	1			T142	2		T234	1		T330	1
auto[2818572288:2952790015]	auto[0]	91	1			T116	2		T63	1		T185	1
auto[2818572288:2952790015]	auto[1]	10	1			T225	1		T407	1		T365	1
auto[2952790016:3087007743]	auto[0]	98	1			T26	1		T64	1		T36	1
auto[2952790016:3087007743]	auto[1]	8	1			T141	1		T225	1		T360	1
auto[3087007744:3221225471]	auto[0]	86	1			T16	3		T117	1		T186	1
auto[3087007744:3221225471]	auto[1]	6	1			T232	1		T229	1		T330	2
auto[3221225472:3355443199]	auto[0]	87	1			T184	1		T64	1		T36	1
auto[3221225472:3355443199]	auto[1]	11	1			T232	1		T234	1		T132	1
auto[3355443200:3489660927]	auto[0]	75	1			T20	1		T187	1		T26	1
auto[3355443200:3489660927]	auto[1]	3	1			T117	1		T414	1		T416	1
auto[3489660928:3623878655]	auto[0]	85	1			T85	1		T25	1		T117	1
auto[3489660928:3623878655]	auto[1]	14	1			T117	1		T142	1		T133	1
auto[3623878656:3758096383]	auto[0]	97	1			T16	2		T17	1		T26	1
auto[3623878656:3758096383]	auto[1]	9	1			T131	1		T133	1		T225	1
auto[3758096384:3892314111]	auto[0]	98	1			T2	1		T85	1		T141	1
auto[3758096384:3892314111]	auto[1]	9	1			T142	1		T330	1		T225	1
auto[3892314112:4026531839]	auto[0]	87	1			T19	1		T124	1		T141	1
auto[3892314112:4026531839]	auto[1]	5	1			T117	1		T243	1		T386	1
auto[4026531840:4160749567]	auto[0]	95	1			T16	1		T17	1		T26	1
auto[4026531840:4160749567]	auto[1]	17	1			T142	1		T131	1		T232	1
auto[4160749568:4294967295]	auto[0]	104	1			T85	1		T124	1		T62	1
auto[4160749568:4294967295]	auto[1]	6	1			T142	1		T132	1		T325	1