Unified Coverage Report :: Group Instance : max_owner_int_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4678

1

T2

2

T4

2

T16

10

auto[1]

2120

1

T4

2

T16

2

T19

8

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	236	1			T54	2		T116	2		T117	2
auto[134217728:268435455]	206	1			T17	2		T63	2		T185	2
auto[268435456:402653183]	196	1			T44	2		T186	4		T27	2
auto[402653184:536870911]	198	1			T56	2		T63	2		T196	2
auto[536870912:671088639]	232	1			T19	2		T25	2		T44	2
auto[671088640:805306367]	170	1			T117	2		T183	2		T196	2
auto[805306368:939524095]	214	1			T47	2		T116	2		T117	2
auto[939524096:1073741823]	204	1			T4	2		T44	2		T27	2
auto[1073741824:1207959551]	252	1			T19	2		T57	8		T71	4
auto[1207959552:1342177279]	238	1			T25	2		T117	2		T36	2
auto[1342177280:1476395007]	208	1			T19	2		T85	2		T184	2
auto[1476395008:1610612735]	208	1			T85	2		T124	2		T188	2
auto[1610612736:1744830463]	234	1			T17	2		T85	2		T40	2
auto[1744830464:1879048191]	234	1			T17	2		T117	2		T51	2
auto[1879048192:2013265919]	236	1			T16	2		T19	2		T25	4
auto[2013265920:2147483647]	174	1			T62	2		T40	2		T57	4
auto[2147483648:2281701375]	246	1			T16	2		T41	2		T116	2
auto[2281701376:2415919103]	164	1			T16	4		T55	2		T101	2
auto[2415919104:2550136831]	206	1			T26	4		T28	2		T57	4
auto[2550136832:2684354559]	200	1			T116	2		T62	2		T26	2
auto[2684354560:2818572287]	208	1			T4	2		T20	2		T185	2
auto[2818572288:2952790015]	240	1			T16	2		T62	2		T86	2
auto[2952790016:3087007743]	214	1			T85	2		T20	2		T124	2
auto[3087007744:3221225471]	202	1			T17	2		T41	2		T124	2
auto[3221225472:3355443199]	206	1			T116	2		T124	2		T44	2
auto[3355443200:3489660927]	254	1			T116	2		T62	2		T141	6
auto[3489660928:3623878655]	230	1			T17	2		T62	2		T193	2
auto[3623878656:3758096383]	214	1			T2	2		T141	4		T187	4
auto[3758096384:3892314111]	170	1			T56	2		T26	2		T71	2
auto[3892314112:4026531839]	204	1			T16	2		T29	2		T183	2
auto[4026531840:4160749567]	204	1			T124	2		T27	2		T185	2
auto[4160749568:4294967295]	196	1			T27	2		T185	2		T28	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	166	1			T116	2		T117	2		T124	2
auto[0:134217727]	auto[1]	70	1			T54	2		T184	2		T40	2
auto[134217728:268435455]	auto[0]	152	1			T17	2		T63	2		T185	2
auto[134217728:268435455]	auto[1]	54	1			T71	2		T412	2		T201	2
auto[268435456:402653183]	auto[0]	146	1			T44	2		T186	4		T27	2
auto[268435456:402653183]	auto[1]	50	1			T46	2		T131	2		T336	2
auto[402653184:536870911]	auto[0]	132	1			T56	2		T63	2		T57	4
auto[402653184:536870911]	auto[1]	66	1			T196	2		T40	2		T267	2
auto[536870912:671088639]	auto[0]	162	1			T25	2		T64	2		T188	4
auto[536870912:671088639]	auto[1]	70	1			T19	2		T44	2		T57	4
auto[671088640:805306367]	auto[0]	114	1			T183	2		T196	2		T57	2
auto[671088640:805306367]	auto[1]	56	1			T117	2		T36	2		T86	2
auto[805306368:939524095]	auto[0]	146	1			T117	2		T184	2		T187	2
auto[805306368:939524095]	auto[1]	68	1			T47	2		T116	2		T70	2
auto[939524096:1073741823]	auto[0]	152	1			T4	2		T86	2		T57	2
auto[939524096:1073741823]	auto[1]	52	1			T44	2		T27	2		T74	2
auto[1073741824:1207959551]	auto[0]	158	1			T57	2		T71	2		T55	2
auto[1073741824:1207959551]	auto[1]	94	1			T19	2		T57	6		T71	2
auto[1207959552:1342177279]	auto[0]	154	1			T36	2		T67	2		T71	2
auto[1207959552:1342177279]	auto[1]	84	1			T25	2		T117	2		T57	2
auto[1342177280:1476395007]	auto[0]	126	1			T40	2		T57	2		T59	2
auto[1342177280:1476395007]	auto[1]	82	1			T19	2		T85	2		T184	2
auto[1476395008:1610612735]	auto[0]	146	1			T85	2		T124	2		T71	2
auto[1476395008:1610612735]	auto[1]	62	1			T188	2		T40	2		T57	2
auto[1610612736:1744830463]	auto[0]	152	1			T17	2		T85	2		T40	2
auto[1610612736:1744830463]	auto[1]	82	1			T46	2		T265	2		T190	2
auto[1744830464:1879048191]	auto[0]	152	1			T17	2		T51	2		T193	2
auto[1744830464:1879048191]	auto[1]	82	1			T117	2		T184	2		T36	4
auto[1879048192:2013265919]	auto[0]	168	1			T16	2		T25	4		T63	4
auto[1879048192:2013265919]	auto[1]	68	1			T19	2		T71	4		T22	2
auto[2013265920:2147483647]	auto[0]	108	1			T40	2		T57	4		T301	2
auto[2013265920:2147483647]	auto[1]	66	1			T62	2		T71	2		T55	2
auto[2147483648:2281701375]	auto[0]	180	1			T16	2		T41	2		T116	2
auto[2147483648:2281701375]	auto[1]	66	1			T57	2		T99	2		T87	2
auto[2281701376:2415919103]	auto[0]	102	1			T16	4		T55	2		T245	2
auto[2281701376:2415919103]	auto[1]	62	1			T101	2		T100	2		T46	2
auto[2415919104:2550136831]	auto[0]	146	1			T26	2		T28	2		T57	4
auto[2415919104:2550136831]	auto[1]	60	1			T26	2		T92	2		T60	2
auto[2550136832:2684354559]	auto[0]	140	1			T116	2		T26	2		T36	2
auto[2550136832:2684354559]	auto[1]	60	1			T62	2		T45	2		T69	2
auto[2684354560:2818572287]	auto[0]	154	1			T20	2		T185	2		T57	2
auto[2684354560:2818572287]	auto[1]	54	1			T4	2		T71	2		T94	2
auto[2818572288:2952790015]	auto[0]	166	1			T86	2		T28	2		T40	2
auto[2818572288:2952790015]	auto[1]	74	1			T16	2		T62	2		T46	2
auto[2952790016:3087007743]	auto[0]	154	1			T85	2		T20	2		T124	2
auto[2952790016:3087007743]	auto[1]	60	1			T93	2		T69	2		T125	2
auto[3087007744:3221225471]	auto[0]	146	1			T17	2		T41	2		T124	2
auto[3087007744:3221225471]	auto[1]	56	1			T60	2		T412	2		T240	2
auto[3221225472:3355443199]	auto[0]	146	1			T116	2		T124	2		T44	2
auto[3221225472:3355443199]	auto[1]	60	1			T70	2		T100	2		T182	2
auto[3355443200:3489660927]	auto[0]	152	1			T116	2		T141	6		T64	2
auto[3355443200:3489660927]	auto[1]	102	1			T62	2		T57	2		T101	2
auto[3489660928:3623878655]	auto[0]	152	1			T17	2		T193	2		T27	2
auto[3489660928:3623878655]	auto[1]	78	1			T62	2		T57	2		T179	2
auto[3623878656:3758096383]	auto[0]	146	1			T2	2		T141	4		T187	4
auto[3623878656:3758096383]	auto[1]	68	1			T29	2		T55	2		T234	2
auto[3758096384:3892314111]	auto[0]	124	1			T56	2		T26	2		T71	2
auto[3758096384:3892314111]	auto[1]	46	1			T46	2		T77	2		T207	2
auto[3892314112:4026531839]	auto[0]	152	1			T16	2		T29	2		T28	2
auto[3892314112:4026531839]	auto[1]	52	1			T183	2		T301	2		T88	2
auto[4026531840:4160749567]	auto[0]	150	1			T124	2		T27	2		T36	2
auto[4026531840:4160749567]	auto[1]	54	1			T185	2		T33	2		T60	2
auto[4160749568:4294967295]	auto[0]	134	1			T27	2		T185	2		T28	2
auto[4160749568:4294967295]	auto[1]	62	1			T409	2		T396	2		T206	2