Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.80 99.07 98.03 98.29 100.00 99.19 98.41 91.61


Total test records in report: 1071
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1007 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2469709244 Apr 25 12:34:29 PM PDT 24 Apr 25 12:34:35 PM PDT 24 305974222 ps
T1008 /workspace/coverage/cover_reg_top/7.keymgr_intr_test.1805886745 Apr 25 12:34:24 PM PDT 24 Apr 25 12:34:27 PM PDT 24 34152213 ps
T1009 /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.1783743702 Apr 25 12:34:12 PM PDT 24 Apr 25 12:34:17 PM PDT 24 63894365 ps
T1010 /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.1740947964 Apr 25 12:34:17 PM PDT 24 Apr 25 12:34:20 PM PDT 24 92938856 ps
T1011 /workspace/coverage/cover_reg_top/8.keymgr_intr_test.2765402749 Apr 25 12:34:21 PM PDT 24 Apr 25 12:34:24 PM PDT 24 13487581 ps
T1012 /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.4286811158 Apr 25 12:34:33 PM PDT 24 Apr 25 12:34:38 PM PDT 24 413889029 ps
T1013 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.791331510 Apr 25 12:34:22 PM PDT 24 Apr 25 12:34:33 PM PDT 24 538067023 ps
T1014 /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.2252608978 Apr 25 12:34:22 PM PDT 24 Apr 25 12:34:26 PM PDT 24 24133213 ps
T160 /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.94427745 Apr 25 12:34:18 PM PDT 24 Apr 25 12:34:26 PM PDT 24 1256732682 ps
T1015 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3976086945 Apr 25 12:34:16 PM PDT 24 Apr 25 12:34:22 PM PDT 24 192512235 ps
T1016 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1122277162 Apr 25 12:34:28 PM PDT 24 Apr 25 12:34:45 PM PDT 24 386754443 ps
T1017 /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3838949548 Apr 25 12:34:30 PM PDT 24 Apr 25 12:34:34 PM PDT 24 38038688 ps
T1018 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.2655635633 Apr 25 12:34:28 PM PDT 24 Apr 25 12:34:35 PM PDT 24 171944950 ps
T1019 /workspace/coverage/cover_reg_top/49.keymgr_intr_test.2881240442 Apr 25 12:34:33 PM PDT 24 Apr 25 12:34:36 PM PDT 24 108386036 ps
T1020 /workspace/coverage/cover_reg_top/28.keymgr_intr_test.1340165517 Apr 25 12:34:28 PM PDT 24 Apr 25 12:34:32 PM PDT 24 14740089 ps
T1021 /workspace/coverage/cover_reg_top/24.keymgr_intr_test.4042323280 Apr 25 12:34:27 PM PDT 24 Apr 25 12:34:30 PM PDT 24 14706534 ps
T1022 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.2093523363 Apr 25 12:34:21 PM PDT 24 Apr 25 12:34:34 PM PDT 24 1129133149 ps
T1023 /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.4045405732 Apr 25 12:34:06 PM PDT 24 Apr 25 12:34:09 PM PDT 24 17926135 ps
T1024 /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.2836413245 Apr 25 12:34:10 PM PDT 24 Apr 25 12:34:16 PM PDT 24 72764374 ps
T1025 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.2099914419 Apr 25 12:34:50 PM PDT 24 Apr 25 12:34:53 PM PDT 24 12326218 ps
T1026 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.512666385 Apr 25 12:34:18 PM PDT 24 Apr 25 12:34:22 PM PDT 24 157666034 ps
T1027 /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.2438618889 Apr 25 12:34:17 PM PDT 24 Apr 25 12:34:20 PM PDT 24 48319395 ps
T1028 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3449153859 Apr 25 12:34:04 PM PDT 24 Apr 25 12:34:09 PM PDT 24 392301744 ps
T1029 /workspace/coverage/cover_reg_top/23.keymgr_intr_test.4243993115 Apr 25 12:34:32 PM PDT 24 Apr 25 12:34:35 PM PDT 24 28260511 ps
T1030 /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2919033601 Apr 25 12:34:28 PM PDT 24 Apr 25 12:34:32 PM PDT 24 53465009 ps
T1031 /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.1586166006 Apr 25 12:34:28 PM PDT 24 Apr 25 12:34:34 PM PDT 24 73117612 ps
T1032 /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.2158219207 Apr 25 12:34:20 PM PDT 24 Apr 25 12:34:23 PM PDT 24 17787767 ps
T378 /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.4047428472 Apr 25 12:34:05 PM PDT 24 Apr 25 12:34:11 PM PDT 24 158744915 ps
T153 /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.288491572 Apr 25 12:34:21 PM PDT 24 Apr 25 12:34:31 PM PDT 24 236174871 ps
T1033 /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3778567187 Apr 25 12:34:24 PM PDT 24 Apr 25 12:34:27 PM PDT 24 13784074 ps
T1034 /workspace/coverage/cover_reg_top/31.keymgr_intr_test.3207104592 Apr 25 12:34:42 PM PDT 24 Apr 25 12:34:46 PM PDT 24 12926821 ps
T159 /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.582522248 Apr 25 12:34:10 PM PDT 24 Apr 25 12:34:16 PM PDT 24 95828881 ps
T1035 /workspace/coverage/cover_reg_top/17.keymgr_intr_test.688717085 Apr 25 12:34:27 PM PDT 24 Apr 25 12:34:31 PM PDT 24 9938033 ps
T1036 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3134045548 Apr 25 12:34:27 PM PDT 24 Apr 25 12:34:36 PM PDT 24 319816606 ps
T1037 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.1293764988 Apr 25 12:34:16 PM PDT 24 Apr 25 12:34:23 PM PDT 24 319744048 ps
T1038 /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.3513334159 Apr 25 12:34:30 PM PDT 24 Apr 25 12:34:36 PM PDT 24 109447642 ps
T1039 /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.2584293767 Apr 25 12:34:21 PM PDT 24 Apr 25 12:34:28 PM PDT 24 1243851125 ps
T1040 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3099967221 Apr 25 12:34:06 PM PDT 24 Apr 25 12:34:20 PM PDT 24 609876307 ps
T1041 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.2586398422 Apr 25 12:34:18 PM PDT 24 Apr 25 12:34:22 PM PDT 24 87860078 ps
T1042 /workspace/coverage/cover_reg_top/39.keymgr_intr_test.2522607722 Apr 25 12:34:33 PM PDT 24 Apr 25 12:34:38 PM PDT 24 11054890 ps
T1043 /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.214293555 Apr 25 12:34:21 PM PDT 24 Apr 25 12:34:28 PM PDT 24 117665128 ps
T1044 /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.1632512999 Apr 25 12:34:11 PM PDT 24 Apr 25 12:34:16 PM PDT 24 119349912 ps
T1045 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3620584145 Apr 25 12:34:21 PM PDT 24 Apr 25 12:34:30 PM PDT 24 619477978 ps
T1046 /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.2542954381 Apr 25 12:34:21 PM PDT 24 Apr 25 12:34:27 PM PDT 24 200966429 ps
T1047 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.2795212253 Apr 25 12:34:07 PM PDT 24 Apr 25 12:34:19 PM PDT 24 449868836 ps
T1048 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.3559237156 Apr 25 12:34:20 PM PDT 24 Apr 25 12:34:24 PM PDT 24 14450583 ps
T1049 /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.3910504518 Apr 25 12:34:22 PM PDT 24 Apr 25 12:34:25 PM PDT 24 51872106 ps
T1050 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.1153720837 Apr 25 12:34:29 PM PDT 24 Apr 25 12:34:34 PM PDT 24 519897700 ps
T163 /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.1292082637 Apr 25 12:34:06 PM PDT 24 Apr 25 12:34:15 PM PDT 24 154828904 ps
T1051 /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.3924933771 Apr 25 12:34:19 PM PDT 24 Apr 25 12:34:24 PM PDT 24 122864662 ps
T1052 /workspace/coverage/cover_reg_top/41.keymgr_intr_test.3002554806 Apr 25 12:34:35 PM PDT 24 Apr 25 12:34:39 PM PDT 24 13093609 ps
T1053 /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.3934747774 Apr 25 12:34:24 PM PDT 24 Apr 25 12:34:28 PM PDT 24 61100196 ps
T1054 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.4185140490 Apr 25 12:34:31 PM PDT 24 Apr 25 12:34:38 PM PDT 24 240417785 ps
T1055 /workspace/coverage/cover_reg_top/21.keymgr_intr_test.293670978 Apr 25 12:34:30 PM PDT 24 Apr 25 12:34:34 PM PDT 24 18386543 ps
T1056 /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.2497825207 Apr 25 12:34:19 PM PDT 24 Apr 25 12:34:22 PM PDT 24 13864595 ps
T1057 /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.989800093 Apr 25 12:34:07 PM PDT 24 Apr 25 12:34:12 PM PDT 24 534774377 ps
T1058 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.3789566124 Apr 25 12:34:08 PM PDT 24 Apr 25 12:34:24 PM PDT 24 426949563 ps
T1059 /workspace/coverage/cover_reg_top/3.keymgr_intr_test.3524928447 Apr 25 12:34:11 PM PDT 24 Apr 25 12:34:13 PM PDT 24 11597095 ps
T1060 /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2911239613 Apr 25 12:34:16 PM PDT 24 Apr 25 12:34:21 PM PDT 24 126862991 ps
T1061 /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.1910726550 Apr 25 12:34:22 PM PDT 24 Apr 25 12:34:28 PM PDT 24 458577553 ps
T1062 /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.1691906905 Apr 25 12:34:28 PM PDT 24 Apr 25 12:34:33 PM PDT 24 69680799 ps
T1063 /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.2128383486 Apr 25 12:34:26 PM PDT 24 Apr 25 12:34:29 PM PDT 24 15470133 ps
T1064 /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.3900348388 Apr 25 12:34:17 PM PDT 24 Apr 25 12:34:19 PM PDT 24 15404236 ps
T1065 /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.2250555403 Apr 25 12:34:27 PM PDT 24 Apr 25 12:34:30 PM PDT 24 40674490 ps
T148 /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.192030073 Apr 25 12:34:35 PM PDT 24 Apr 25 12:34:45 PM PDT 24 550508304 ps
T1066 /workspace/coverage/cover_reg_top/12.keymgr_intr_test.1003641633 Apr 25 12:34:22 PM PDT 24 Apr 25 12:34:26 PM PDT 24 57743614 ps
T1067 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.4112077500 Apr 25 12:34:15 PM PDT 24 Apr 25 12:34:18 PM PDT 24 78701465 ps
T1068 /workspace/coverage/cover_reg_top/20.keymgr_intr_test.3480639547 Apr 25 12:34:32 PM PDT 24 Apr 25 12:34:36 PM PDT 24 42236365 ps
T1069 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.535682450 Apr 25 12:34:19 PM PDT 24 Apr 25 12:34:26 PM PDT 24 392469570 ps
T1070 /workspace/coverage/cover_reg_top/36.keymgr_intr_test.707631188 Apr 25 12:34:51 PM PDT 24 Apr 25 12:34:53 PM PDT 24 11322503 ps
T1071 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.3026889611 Apr 25 12:34:11 PM PDT 24 Apr 25 12:34:20 PM PDT 24 238534835 ps

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.998497124
Short name T4
Test name
Test status
Simulation time 2490747811 ps
CPU time 10.29 seconds
Started Apr 25 12:53:03 PM PDT 24
Finished Apr 25 12:53:14 PM PDT 24
Peak memory 222424 kb
Host smart-0cde43c9-d5b4-4749-8861-1674fba4cbb3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998497124 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.998497124
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.3768129388
Short name T57
Test name
Test status
Simulation time 2410441916 ps
CPU time 38.07 seconds
Started Apr 25 12:55:08 PM PDT 24
Finished Apr 25 12:55:47 PM PDT 24
Peak memory 214860 kb
Host smart-891e27e9-eb65-4bdf-8f87-17c1d42cfeae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768129388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.3768129388
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.3825858113
Short name T36
Test name
Test status
Simulation time 280136403 ps
CPU time 8.97 seconds
Started Apr 25 12:53:46 PM PDT 24
Finished Apr 25 12:53:56 PM PDT 24
Peak memory 214148 kb
Host smart-3badfd5c-0940-47a4-a52d-ff7eb35d2506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825858113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.3825858113
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.3635148646
Short name T12
Test name
Test status
Simulation time 42884756758 ps
CPU time 118.75 seconds
Started Apr 25 12:53:02 PM PDT 24
Finished Apr 25 12:55:02 PM PDT 24
Peak memory 261484 kb
Host smart-14078588-7180-412e-9c51-62a2c60a289e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635148646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.3635148646
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.2000222374
Short name T71
Test name
Test status
Simulation time 457661278 ps
CPU time 14 seconds
Started Apr 25 12:53:58 PM PDT 24
Finished Apr 25 12:54:16 PM PDT 24
Peak memory 222548 kb
Host smart-610549fb-5f55-4250-b1da-311658c84b89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000222374 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.2000222374
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.3058674769
Short name T116
Test name
Test status
Simulation time 57317090 ps
CPU time 4.24 seconds
Started Apr 25 12:53:27 PM PDT 24
Finished Apr 25 12:53:34 PM PDT 24
Peak memory 215464 kb
Host smart-044d8a5e-b6b4-45b0-9d62-5b26b3992224
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3058674769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.3058674769
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.2244268742
Short name T60
Test name
Test status
Simulation time 1152584041 ps
CPU time 23.83 seconds
Started Apr 25 12:54:40 PM PDT 24
Finished Apr 25 12:55:05 PM PDT 24
Peak memory 222300 kb
Host smart-1848ea3b-d4e2-45f9-828b-ee41712f5f7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244268742 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.2244268742
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.3087462101
Short name T77
Test name
Test status
Simulation time 11227987767 ps
CPU time 41.24 seconds
Started Apr 25 12:53:26 PM PDT 24
Finished Apr 25 12:54:10 PM PDT 24
Peak memory 215604 kb
Host smart-12687181-4493-471c-9aba-3add6af24598
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087462101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.3087462101
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.4003016979
Short name T27
Test name
Test status
Simulation time 4162917115 ps
CPU time 44.56 seconds
Started Apr 25 12:53:51 PM PDT 24
Finished Apr 25 12:54:37 PM PDT 24
Peak memory 212148 kb
Host smart-d5aa666c-3ca8-4664-bc5b-3f2576a1e4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003016979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.4003016979
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.1755843278
Short name T114
Test name
Test status
Simulation time 414889178 ps
CPU time 12.91 seconds
Started Apr 25 12:34:20 PM PDT 24
Finished Apr 25 12:34:36 PM PDT 24
Peak memory 220604 kb
Host smart-4ad32d0c-7d9b-40a4-bbe9-65746c1b6194
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755843278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.1755843278
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.4209022632
Short name T9
Test name
Test status
Simulation time 256714272 ps
CPU time 5.48 seconds
Started Apr 25 12:53:24 PM PDT 24
Finished Apr 25 12:53:31 PM PDT 24
Peak memory 221488 kb
Host smart-7f5964ea-2f16-4891-8c0f-7926ae121e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209022632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.4209022632
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.1824871513
Short name T206
Test name
Test status
Simulation time 150487727040 ps
CPU time 384.8 seconds
Started Apr 25 12:53:43 PM PDT 24
Finished Apr 25 01:00:10 PM PDT 24
Peak memory 232524 kb
Host smart-9f18a945-deff-49ee-8292-2dac02c4b872
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824871513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.1824871513
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.2247647534
Short name T48
Test name
Test status
Simulation time 100953573 ps
CPU time 2.14 seconds
Started Apr 25 12:54:41 PM PDT 24
Finished Apr 25 12:54:50 PM PDT 24
Peak memory 214128 kb
Host smart-827935d1-ecab-4b61-8a90-a2e40d60ea8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247647534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.2247647534
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.1676270767
Short name T133
Test name
Test status
Simulation time 8918107488 ps
CPU time 120.57 seconds
Started Apr 25 12:54:07 PM PDT 24
Finished Apr 25 12:56:11 PM PDT 24
Peak memory 220808 kb
Host smart-de5d7c07-9fd2-4a34-bd84-33a03b293f8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1676270767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.1676270767
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.2704542184
Short name T46
Test name
Test status
Simulation time 3157401230 ps
CPU time 48.1 seconds
Started Apr 25 12:52:54 PM PDT 24
Finished Apr 25 12:53:44 PM PDT 24
Peak memory 220856 kb
Host smart-339cd060-be0c-4e6a-93d7-ad9640f3ab6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704542184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.2704542184
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.3881570248
Short name T261
Test name
Test status
Simulation time 250312668 ps
CPU time 12.79 seconds
Started Apr 25 12:53:59 PM PDT 24
Finished Apr 25 12:54:16 PM PDT 24
Peak memory 214060 kb
Host smart-ac495a74-9b5e-4e9f-86b1-bc636be94563
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3881570248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.3881570248
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.2333973679
Short name T16
Test name
Test status
Simulation time 542100586 ps
CPU time 8.46 seconds
Started Apr 25 12:53:54 PM PDT 24
Finished Apr 25 12:54:04 PM PDT 24
Peak memory 209628 kb
Host smart-6c3ccbc3-6551-44aa-b292-c69cee388534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333973679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.2333973679
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.754570795
Short name T330
Test name
Test status
Simulation time 870949573 ps
CPU time 46.62 seconds
Started Apr 25 12:53:17 PM PDT 24
Finished Apr 25 12:54:05 PM PDT 24
Peak memory 214680 kb
Host smart-340a4b25-d3e2-4e69-9e8e-fcca5eddce8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=754570795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.754570795
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.1036850560
Short name T87
Test name
Test status
Simulation time 893762168 ps
CPU time 26.52 seconds
Started Apr 25 12:53:06 PM PDT 24
Finished Apr 25 12:53:36 PM PDT 24
Peak memory 214012 kb
Host smart-6ae73ef7-893e-4978-a168-6df71ac9d804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036850560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.1036850560
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.218853359
Short name T117
Test name
Test status
Simulation time 7453871995 ps
CPU time 42.02 seconds
Started Apr 25 12:54:05 PM PDT 24
Finished Apr 25 12:54:50 PM PDT 24
Peak memory 214592 kb
Host smart-d241361e-5748-4823-a8db-88c6266a6645
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=218853359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.218853359
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.3799669798
Short name T35
Test name
Test status
Simulation time 411002322 ps
CPU time 4.03 seconds
Started Apr 25 12:53:01 PM PDT 24
Finished Apr 25 12:53:14 PM PDT 24
Peak memory 209612 kb
Host smart-4fa7202d-a146-4f98-880b-1dee4bf16f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799669798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.3799669798
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.1895806862
Short name T62
Test name
Test status
Simulation time 188232786 ps
CPU time 7.15 seconds
Started Apr 25 12:55:11 PM PDT 24
Finished Apr 25 12:55:21 PM PDT 24
Peak memory 222456 kb
Host smart-f41e4d27-afc3-48e7-8c6f-329874720509
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895806862 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.1895806862
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.1818450910
Short name T125
Test name
Test status
Simulation time 3277512356 ps
CPU time 19.04 seconds
Started Apr 25 12:53:24 PM PDT 24
Finished Apr 25 12:53:44 PM PDT 24
Peak memory 221648 kb
Host smart-cdd81d53-2e20-48dd-b0fd-885b7a9fa3ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818450910 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.1818450910
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.4159772165
Short name T410
Test name
Test status
Simulation time 321611727 ps
CPU time 16.65 seconds
Started Apr 25 12:54:10 PM PDT 24
Finished Apr 25 12:54:30 PM PDT 24
Peak memory 214128 kb
Host smart-a5e051bc-9b2a-4954-a34b-e3cc8ec5c1ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4159772165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.4159772165
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.1621600919
Short name T37
Test name
Test status
Simulation time 51768260 ps
CPU time 2.6 seconds
Started Apr 25 12:53:59 PM PDT 24
Finished Apr 25 12:54:05 PM PDT 24
Peak memory 219696 kb
Host smart-d1b73b38-e39c-419c-87cf-ee9f0553c56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621600919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.1621600919
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.4116188121
Short name T32
Test name
Test status
Simulation time 1423907249 ps
CPU time 4.23 seconds
Started Apr 25 12:53:58 PM PDT 24
Finished Apr 25 12:54:06 PM PDT 24
Peak memory 220008 kb
Host smart-904ac1ab-e89f-4a7f-a552-5c918170e2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116188121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.4116188121
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.2620294216
Short name T225
Test name
Test status
Simulation time 342699479 ps
CPU time 19.32 seconds
Started Apr 25 12:54:36 PM PDT 24
Finished Apr 25 12:54:58 PM PDT 24
Peak memory 214132 kb
Host smart-fabb8da6-73ea-43a4-b8c5-8b426743b683
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2620294216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.2620294216
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.287940279
Short name T936
Test name
Test status
Simulation time 150143924 ps
CPU time 2.94 seconds
Started Apr 25 12:34:30 PM PDT 24
Finished Apr 25 12:34:35 PM PDT 24
Peak memory 222592 kb
Host smart-a202feab-5074-4ef0-96b9-ee9adbcca669
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287940279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shado
w_reg_errors.287940279
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.2331196161
Short name T23
Test name
Test status
Simulation time 117546436 ps
CPU time 3.04 seconds
Started Apr 25 12:52:54 PM PDT 24
Finished Apr 25 12:52:59 PM PDT 24
Peak memory 214124 kb
Host smart-d0ad94da-1eb6-40a1-9b88-2854cdac64ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331196161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.2331196161
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.2469802581
Short name T45
Test name
Test status
Simulation time 2025805756 ps
CPU time 46.93 seconds
Started Apr 25 12:53:59 PM PDT 24
Finished Apr 25 12:54:50 PM PDT 24
Peak memory 216136 kb
Host smart-318eda2a-c5e2-40d6-896f-d574103902a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469802581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.2469802581
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.2006356500
Short name T252
Test name
Test status
Simulation time 275745709 ps
CPU time 14.92 seconds
Started Apr 25 12:54:16 PM PDT 24
Finished Apr 25 12:54:35 PM PDT 24
Peak memory 214560 kb
Host smart-943a9d1f-e9c4-4d3f-95fd-905f67737b26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2006356500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.2006356500
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.3863106388
Short name T93
Test name
Test status
Simulation time 3372335129 ps
CPU time 12.67 seconds
Started Apr 25 12:53:19 PM PDT 24
Finished Apr 25 12:53:33 PM PDT 24
Peak memory 214080 kb
Host smart-3beea4ea-9165-45de-9600-3402447e2c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863106388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.3863106388
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.1838420082
Short name T61
Test name
Test status
Simulation time 3560201163 ps
CPU time 55.47 seconds
Started Apr 25 12:54:15 PM PDT 24
Finished Apr 25 12:55:14 PM PDT 24
Peak memory 216928 kb
Host smart-649f78aa-4abc-4971-98aa-1d53821668e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838420082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.1838420082
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.2425400167
Short name T69
Test name
Test status
Simulation time 1707383560 ps
CPU time 46.94 seconds
Started Apr 25 12:52:47 PM PDT 24
Finished Apr 25 12:53:35 PM PDT 24
Peak memory 217848 kb
Host smart-7c4d448d-4110-4ce0-a2ac-3406247cef00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425400167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.2425400167
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.2369773777
Short name T390
Test name
Test status
Simulation time 1115976045 ps
CPU time 14.96 seconds
Started Apr 25 12:52:40 PM PDT 24
Finished Apr 25 12:52:57 PM PDT 24
Peak memory 214032 kb
Host smart-f2468dd0-1c5d-4239-becf-a1a852a26ce9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2369773777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.2369773777
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.1564290573
Short name T33
Test name
Test status
Simulation time 78041306 ps
CPU time 2.14 seconds
Started Apr 25 12:53:36 PM PDT 24
Finished Apr 25 12:53:39 PM PDT 24
Peak memory 217500 kb
Host smart-3b1ff34a-74b7-4c14-b320-a4a7dfd4af29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564290573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.1564290573
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.111861221
Short name T177
Test name
Test status
Simulation time 3518741165 ps
CPU time 60.06 seconds
Started Apr 25 12:53:30 PM PDT 24
Finished Apr 25 12:54:32 PM PDT 24
Peak memory 216304 kb
Host smart-90789702-578f-46f9-b111-51713d05e5bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111861221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.111861221
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.3332833843
Short name T205
Test name
Test status
Simulation time 12146904397 ps
CPU time 321.55 seconds
Started Apr 25 12:54:33 PM PDT 24
Finished Apr 25 12:59:57 PM PDT 24
Peak memory 220048 kb
Host smart-5b16e6c0-81a5-4db0-860c-d0b4abe8c21a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332833843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.3332833843
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.1371610680
Short name T418
Test name
Test status
Simulation time 16452328 ps
CPU time 0.73 seconds
Started Apr 25 12:52:52 PM PDT 24
Finished Apr 25 12:52:54 PM PDT 24
Peak memory 205648 kb
Host smart-fab359c3-ed32-4110-8ff3-95bc13f4907b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371610680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.1371610680
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.3097805124
Short name T141
Test name
Test status
Simulation time 327622176 ps
CPU time 10.34 seconds
Started Apr 25 12:53:10 PM PDT 24
Finished Apr 25 12:53:23 PM PDT 24
Peak memory 214240 kb
Host smart-3fe4261c-6542-4e11-b0d2-fdb5c112bfc4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3097805124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.3097805124
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.507764902
Short name T55
Test name
Test status
Simulation time 1008182008 ps
CPU time 13.37 seconds
Started Apr 25 12:53:07 PM PDT 24
Finished Apr 25 12:53:24 PM PDT 24
Peak memory 222284 kb
Host smart-22f8c483-f188-4b21-ac63-2ef24bd71a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507764902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.507764902
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.1397795606
Short name T157
Test name
Test status
Simulation time 205671737 ps
CPU time 6.5 seconds
Started Apr 25 12:34:11 PM PDT 24
Finished Apr 25 12:34:20 PM PDT 24
Peak memory 209180 kb
Host smart-f5e4f037-f3dc-48db-9c05-18307eb67df7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397795606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.1397795606
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.3005949525
Short name T190
Test name
Test status
Simulation time 6067719575 ps
CPU time 56.95 seconds
Started Apr 25 12:54:43 PM PDT 24
Finished Apr 25 12:55:41 PM PDT 24
Peak memory 222288 kb
Host smart-8825b77e-060e-4a22-a696-0a80b4831e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005949525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.3005949525
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.667088195
Short name T792
Test name
Test status
Simulation time 1041153067 ps
CPU time 28.29 seconds
Started Apr 25 12:53:26 PM PDT 24
Finished Apr 25 12:53:57 PM PDT 24
Peak memory 214652 kb
Host smart-beedb30d-b1a9-4b1e-87b9-09c1e9735224
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667088195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.667088195
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.3618007201
Short name T147
Test name
Test status
Simulation time 1102981477 ps
CPU time 10.39 seconds
Started Apr 25 12:34:19 PM PDT 24
Finished Apr 25 12:34:31 PM PDT 24
Peak memory 209764 kb
Host smart-f4ebe2bf-4af9-453a-8298-310231a4a739
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618007201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.3618007201
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.1211397888
Short name T40
Test name
Test status
Simulation time 140377583 ps
CPU time 5.77 seconds
Started Apr 25 12:53:26 PM PDT 24
Finished Apr 25 12:53:34 PM PDT 24
Peak memory 222208 kb
Host smart-bdbedeee-9f84-4b33-901d-4858702c9b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211397888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.1211397888
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.879833499
Short name T416
Test name
Test status
Simulation time 380348584 ps
CPU time 21.24 seconds
Started Apr 25 12:53:22 PM PDT 24
Finished Apr 25 12:53:45 PM PDT 24
Peak memory 215108 kb
Host smart-bc276c03-c97a-4b4c-9c5d-ed890a3f08b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=879833499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.879833499
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.838128228
Short name T211
Test name
Test status
Simulation time 19706693886 ps
CPU time 345.48 seconds
Started Apr 25 12:55:00 PM PDT 24
Finished Apr 25 01:00:48 PM PDT 24
Peak memory 222284 kb
Host smart-3a2ad095-3069-4232-b655-d7128c952f57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838128228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.838128228
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.2483036833
Short name T144
Test name
Test status
Simulation time 1836896639 ps
CPU time 23.34 seconds
Started Apr 25 12:54:04 PM PDT 24
Finished Apr 25 12:54:31 PM PDT 24
Peak memory 218224 kb
Host smart-060ab2c5-7621-4e52-af19-f6f727bec587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483036833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.2483036833
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_random.4177288644
Short name T188
Test name
Test status
Simulation time 1755545934 ps
CPU time 39.23 seconds
Started Apr 25 12:53:23 PM PDT 24
Finished Apr 25 12:54:04 PM PDT 24
Peak memory 213980 kb
Host smart-3697fcf9-9102-45bd-9d0d-6821e07dd571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177288644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.4177288644
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.1144669042
Short name T88
Test name
Test status
Simulation time 550836359 ps
CPU time 6.77 seconds
Started Apr 25 12:54:48 PM PDT 24
Finished Apr 25 12:54:57 PM PDT 24
Peak memory 221424 kb
Host smart-3422ef77-1748-4169-8e0e-7d62b48e84f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144669042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.1144669042
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.2349775390
Short name T844
Test name
Test status
Simulation time 531807590 ps
CPU time 15.18 seconds
Started Apr 25 12:54:39 PM PDT 24
Finished Apr 25 12:54:56 PM PDT 24
Peak memory 214400 kb
Host smart-40ff7e76-812f-45ae-ab14-850019796b4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2349775390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.2349775390
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.3531362804
Short name T235
Test name
Test status
Simulation time 48809928 ps
CPU time 3 seconds
Started Apr 25 12:53:04 PM PDT 24
Finished Apr 25 12:53:09 PM PDT 24
Peak memory 211128 kb
Host smart-05ba71b6-4d66-48fe-8667-d22b50ce8ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531362804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.3531362804
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.1862433763
Short name T34
Test name
Test status
Simulation time 778429153 ps
CPU time 7.97 seconds
Started Apr 25 12:54:45 PM PDT 24
Finished Apr 25 12:54:54 PM PDT 24
Peak memory 214400 kb
Host smart-063bdc5a-9be2-4318-b467-7e36e1d1cb06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862433763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.1862433763
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.1386832560
Short name T143
Test name
Test status
Simulation time 206564266 ps
CPU time 2.94 seconds
Started Apr 25 12:54:06 PM PDT 24
Finished Apr 25 12:54:12 PM PDT 24
Peak memory 222444 kb
Host smart-546773bb-b5ed-41be-b3c0-26e8eb4a050a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386832560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.1386832560
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.2420172307
Short name T151
Test name
Test status
Simulation time 73956026 ps
CPU time 2.43 seconds
Started Apr 25 12:54:31 PM PDT 24
Finished Apr 25 12:54:37 PM PDT 24
Peak memory 209840 kb
Host smart-cf542ab2-7e1c-4218-b4d2-8f847b84cc1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420172307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.2420172307
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.192030073
Short name T148
Test name
Test status
Simulation time 550508304 ps
CPU time 5.68 seconds
Started Apr 25 12:34:35 PM PDT 24
Finished Apr 25 12:34:45 PM PDT 24
Peak memory 209680 kb
Host smart-f050a522-b5c9-4f91-a673-80ec5ecb3803
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192030073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_err
.192030073
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.230028208
Short name T220
Test name
Test status
Simulation time 1302117074 ps
CPU time 19.14 seconds
Started Apr 25 12:54:30 PM PDT 24
Finished Apr 25 12:54:52 PM PDT 24
Peak memory 215216 kb
Host smart-508e6184-a13a-4f56-89f6-65603beb2451
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230028208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.230028208
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.191985424
Short name T227
Test name
Test status
Simulation time 787472688 ps
CPU time 5.04 seconds
Started Apr 25 12:54:41 PM PDT 24
Finished Apr 25 12:54:48 PM PDT 24
Peak memory 206596 kb
Host smart-8d3f2a41-8015-45b9-b90a-ff9c098ba437
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191985424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.191985424
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.2295586429
Short name T290
Test name
Test status
Simulation time 521019625 ps
CPU time 19.09 seconds
Started Apr 25 12:55:01 PM PDT 24
Finished Apr 25 12:55:22 PM PDT 24
Peak memory 222284 kb
Host smart-bc22f0ce-8fd5-4cec-8169-e20b8574fdee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295586429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.2295586429
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.3240088259
Short name T156
Test name
Test status
Simulation time 7425204823 ps
CPU time 27.31 seconds
Started Apr 25 12:34:17 PM PDT 24
Finished Apr 25 12:34:46 PM PDT 24
Peak memory 214408 kb
Host smart-84e773bc-664b-4203-8257-3730fd15ed64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240088259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.3240088259
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.1391985214
Short name T318
Test name
Test status
Simulation time 48741598 ps
CPU time 3.08 seconds
Started Apr 25 12:53:29 PM PDT 24
Finished Apr 25 12:53:35 PM PDT 24
Peak memory 219280 kb
Host smart-99eaf094-77dc-4a38-a369-00d7415c18fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391985214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.1391985214
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.3915733223
Short name T145
Test name
Test status
Simulation time 77287369 ps
CPU time 3.89 seconds
Started Apr 25 12:53:19 PM PDT 24
Finished Apr 25 12:53:24 PM PDT 24
Peak memory 217400 kb
Host smart-d727e3d7-9e10-423f-87ae-6ba87b7f5379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915733223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.3915733223
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.3647932757
Short name T100
Test name
Test status
Simulation time 100598123 ps
CPU time 3.72 seconds
Started Apr 25 12:53:29 PM PDT 24
Finished Apr 25 12:53:35 PM PDT 24
Peak memory 222480 kb
Host smart-cbb199e0-e758-4bf0-9f12-d3e8deded9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647932757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.3647932757
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.832916095
Short name T238
Test name
Test status
Simulation time 23784329603 ps
CPU time 117.58 seconds
Started Apr 25 12:52:42 PM PDT 24
Finished Apr 25 12:54:42 PM PDT 24
Peak memory 236144 kb
Host smart-e530833e-f86a-48df-8037-9a8d15a6c925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832916095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.832916095
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.658792334
Short name T283
Test name
Test status
Simulation time 3229294654 ps
CPU time 31.09 seconds
Started Apr 25 12:53:07 PM PDT 24
Finished Apr 25 12:53:41 PM PDT 24
Peak memory 211168 kb
Host smart-83c507ce-33bd-4cc6-85e6-496315eb5553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658792334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.658792334
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.3300175460
Short name T377
Test name
Test status
Simulation time 5254302669 ps
CPU time 31.53 seconds
Started Apr 25 12:53:25 PM PDT 24
Finished Apr 25 12:53:58 PM PDT 24
Peak memory 222308 kb
Host smart-8710c334-53f5-463e-9b46-432d5db41531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300175460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.3300175460
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.2530081553
Short name T334
Test name
Test status
Simulation time 116147796 ps
CPU time 6.37 seconds
Started Apr 25 12:53:22 PM PDT 24
Finished Apr 25 12:53:30 PM PDT 24
Peak memory 215224 kb
Host smart-83057e23-7afc-46b7-a3bf-a71a2b121200
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2530081553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.2530081553
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_sideload.3710128605
Short name T506
Test name
Test status
Simulation time 755916742 ps
CPU time 4.95 seconds
Started Apr 25 12:53:37 PM PDT 24
Finished Apr 25 12:53:44 PM PDT 24
Peak memory 208396 kb
Host smart-1588139d-fbfd-4612-97de-064d2e460234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710128605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.3710128605
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_random.2309064384
Short name T267
Test name
Test status
Simulation time 87188619 ps
CPU time 3.18 seconds
Started Apr 25 12:53:37 PM PDT 24
Finished Apr 25 12:53:41 PM PDT 24
Peak memory 214160 kb
Host smart-ec626581-21d8-45e4-a49d-7a91cc7faf4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309064384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.2309064384
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.4012923041
Short name T74
Test name
Test status
Simulation time 98976497 ps
CPU time 2.07 seconds
Started Apr 25 12:54:14 PM PDT 24
Finished Apr 25 12:54:20 PM PDT 24
Peak memory 214164 kb
Host smart-2e72883e-215a-4a1c-98a2-a8a8b04b24bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012923041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.4012923041
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.2392672898
Short name T68
Test name
Test status
Simulation time 343731271 ps
CPU time 3.94 seconds
Started Apr 25 12:53:58 PM PDT 24
Finished Apr 25 12:54:05 PM PDT 24
Peak memory 209420 kb
Host smart-24b1458b-6aa3-4f7f-978f-147e81739faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392672898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.2392672898
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.1547423927
Short name T258
Test name
Test status
Simulation time 82588908 ps
CPU time 4.35 seconds
Started Apr 25 12:53:04 PM PDT 24
Finished Apr 25 12:53:11 PM PDT 24
Peak memory 211008 kb
Host smart-01ccb56a-d6d6-48a8-84c1-ee6f0a1e3892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547423927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.1547423927
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.1262616888
Short name T219
Test name
Test status
Simulation time 2651260331 ps
CPU time 49.4 seconds
Started Apr 25 12:53:27 PM PDT 24
Finished Apr 25 12:54:19 PM PDT 24
Peak memory 220928 kb
Host smart-0b841382-096d-4c1b-92a7-fd4e546dbf96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262616888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.1262616888
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.1292082637
Short name T163
Test name
Test status
Simulation time 154828904 ps
CPU time 6.43 seconds
Started Apr 25 12:34:06 PM PDT 24
Finished Apr 25 12:34:15 PM PDT 24
Peak memory 209692 kb
Host smart-1011ee7a-7505-42b7-a194-de73df78cc29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292082637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.1292082637
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.1992082698
Short name T149
Test name
Test status
Simulation time 183192044 ps
CPU time 5.84 seconds
Started Apr 25 12:34:25 PM PDT 24
Finished Apr 25 12:34:34 PM PDT 24
Peak memory 209788 kb
Host smart-ebce448d-deea-41a7-8a65-7818685cea68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992082698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.1992082698
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.3774482260
Short name T152
Test name
Test status
Simulation time 348750543 ps
CPU time 5.43 seconds
Started Apr 25 12:34:29 PM PDT 24
Finished Apr 25 12:34:37 PM PDT 24
Peak memory 209444 kb
Host smart-83f3ee39-ddb2-4b37-adf3-db221a24629f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774482260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.3774482260
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.1127706768
Short name T161
Test name
Test status
Simulation time 326741907 ps
CPU time 4.72 seconds
Started Apr 25 12:34:17 PM PDT 24
Finished Apr 25 12:34:23 PM PDT 24
Peak memory 209680 kb
Host smart-034a440c-fb85-4edb-9ad7-c2cc19f611a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127706768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.1127706768
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.288491572
Short name T153
Test name
Test status
Simulation time 236174871 ps
CPU time 7.72 seconds
Started Apr 25 12:34:21 PM PDT 24
Finished Apr 25 12:34:31 PM PDT 24
Peak memory 214328 kb
Host smart-e368da68-b4f7-4130-bca6-33fb45798938
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288491572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err.
288491572
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.1520227270
Short name T164
Test name
Test status
Simulation time 102196702 ps
CPU time 2.37 seconds
Started Apr 25 12:55:13 PM PDT 24
Finished Apr 25 12:55:19 PM PDT 24
Peak memory 209576 kb
Host smart-ea79226e-0cc4-4a62-997b-327670be4055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520227270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.1520227270
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.1473044316
Short name T165
Test name
Test status
Simulation time 66988304 ps
CPU time 2.09 seconds
Started Apr 25 12:52:56 PM PDT 24
Finished Apr 25 12:52:59 PM PDT 24
Peak memory 209448 kb
Host smart-bf049abe-68ee-486b-9887-cdc3d339d727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473044316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.1473044316
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_random.1018756023
Short name T703
Test name
Test status
Simulation time 325099495 ps
CPU time 3.22 seconds
Started Apr 25 12:53:08 PM PDT 24
Finished Apr 25 12:53:15 PM PDT 24
Peak memory 208384 kb
Host smart-04a2a5af-70cb-4701-b820-d50022d2b4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018756023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.1018756023
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.110788336
Short name T7
Test name
Test status
Simulation time 373301282 ps
CPU time 15.81 seconds
Started Apr 25 12:52:57 PM PDT 24
Finished Apr 25 12:53:14 PM PDT 24
Peak memory 222264 kb
Host smart-df8d4a01-7e35-47aa-97b8-eb2aeb962c8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110788336 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.110788336
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.1932852649
Short name T306
Test name
Test status
Simulation time 5318135030 ps
CPU time 55.34 seconds
Started Apr 25 12:53:08 PM PDT 24
Finished Apr 25 12:54:07 PM PDT 24
Peak memory 214088 kb
Host smart-6eb52954-0d85-475e-9f6c-e381be78b877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932852649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.1932852649
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.4187009607
Short name T217
Test name
Test status
Simulation time 32736170 ps
CPU time 2.6 seconds
Started Apr 25 12:53:04 PM PDT 24
Finished Apr 25 12:53:09 PM PDT 24
Peak memory 215368 kb
Host smart-fcddf8df-af7f-4028-937b-3a50574f2a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187009607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.4187009607
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.618211338
Short name T65
Test name
Test status
Simulation time 247801921 ps
CPU time 2.52 seconds
Started Apr 25 12:53:05 PM PDT 24
Finished Apr 25 12:53:10 PM PDT 24
Peak memory 210020 kb
Host smart-7b79c1dc-02cd-4c29-a720-4ff5c1dd5816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618211338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.618211338
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.2741652712
Short name T356
Test name
Test status
Simulation time 531496813 ps
CPU time 7.05 seconds
Started Apr 25 12:53:13 PM PDT 24
Finished Apr 25 12:53:23 PM PDT 24
Peak memory 213900 kb
Host smart-fe7ac877-faa5-4267-95ff-b0ac8cf54c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741652712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.2741652712
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.1492123840
Short name T222
Test name
Test status
Simulation time 314845537 ps
CPU time 4.38 seconds
Started Apr 25 12:53:26 PM PDT 24
Finished Apr 25 12:53:33 PM PDT 24
Peak memory 217064 kb
Host smart-e47e7089-b01b-4dfb-8fdf-92dfa579c864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492123840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.1492123840
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.833343730
Short name T370
Test name
Test status
Simulation time 794269130 ps
CPU time 30.22 seconds
Started Apr 25 12:53:27 PM PDT 24
Finished Apr 25 12:54:00 PM PDT 24
Peak memory 216644 kb
Host smart-a7d7e6ea-5dec-41e9-b545-e95cc86b5c64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833343730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.833343730
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.4165890815
Short name T89
Test name
Test status
Simulation time 754728083 ps
CPU time 6.77 seconds
Started Apr 25 12:53:27 PM PDT 24
Finished Apr 25 12:53:36 PM PDT 24
Peak memory 210824 kb
Host smart-fa9d6692-d6fe-4edb-af67-d600222eab05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165890815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.4165890815
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.2423270291
Short name T208
Test name
Test status
Simulation time 12751371363 ps
CPU time 60 seconds
Started Apr 25 12:52:57 PM PDT 24
Finished Apr 25 12:53:58 PM PDT 24
Peak memory 222300 kb
Host smart-9b704354-c1ed-42b5-bf4a-a7ba8b11ead9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423270291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.2423270291
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.2614947856
Short name T255
Test name
Test status
Simulation time 126991296 ps
CPU time 5.62 seconds
Started Apr 25 12:53:39 PM PDT 24
Finished Apr 25 12:53:46 PM PDT 24
Peak memory 210212 kb
Host smart-961734d8-995e-422b-bb57-3cf77d2b32f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614947856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2614947856
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.2403421795
Short name T313
Test name
Test status
Simulation time 697531478 ps
CPU time 11.29 seconds
Started Apr 25 12:53:47 PM PDT 24
Finished Apr 25 12:54:00 PM PDT 24
Peak memory 214060 kb
Host smart-9b3263cc-f2db-4f63-826e-58a3437bfc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403421795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.2403421795
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.1366347502
Short name T215
Test name
Test status
Simulation time 1318548883 ps
CPU time 9.17 seconds
Started Apr 25 12:53:56 PM PDT 24
Finished Apr 25 12:54:07 PM PDT 24
Peak memory 221828 kb
Host smart-e716ffd2-154a-4d0f-8b89-ffdcc9ae410a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366347502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.1366347502
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.3114731895
Short name T201
Test name
Test status
Simulation time 143533118 ps
CPU time 3.59 seconds
Started Apr 25 12:53:42 PM PDT 24
Finished Apr 25 12:53:47 PM PDT 24
Peak memory 220072 kb
Host smart-1b8683f0-86c8-4123-a579-1dfd80c910f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114731895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.3114731895
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.2765170046
Short name T367
Test name
Test status
Simulation time 18326775269 ps
CPU time 245.67 seconds
Started Apr 25 12:54:06 PM PDT 24
Finished Apr 25 12:58:15 PM PDT 24
Peak memory 222356 kb
Host smart-0a1785c4-65bb-4cdc-804f-1a1c75498ec1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765170046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.2765170046
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.3256047587
Short name T325
Test name
Test status
Simulation time 60985733 ps
CPU time 4.27 seconds
Started Apr 25 12:53:57 PM PDT 24
Finished Apr 25 12:54:05 PM PDT 24
Peak memory 214144 kb
Host smart-9d9f40c0-0d8f-4065-bc74-c0be6b0facde
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3256047587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.3256047587
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.2008858517
Short name T346
Test name
Test status
Simulation time 6279576057 ps
CPU time 98.45 seconds
Started Apr 25 12:53:56 PM PDT 24
Finished Apr 25 12:55:37 PM PDT 24
Peak memory 216412 kb
Host smart-ed1ea52c-9a1f-4cc3-9efd-348f4ca2899c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008858517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.2008858517
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.3402860240
Short name T224
Test name
Test status
Simulation time 271696213 ps
CPU time 11.34 seconds
Started Apr 25 12:54:20 PM PDT 24
Finished Apr 25 12:54:35 PM PDT 24
Peak memory 222332 kb
Host smart-32d55dfc-37e7-467e-a234-3574d5de91d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402860240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.3402860240
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.1939772762
Short name T349
Test name
Test status
Simulation time 136690937 ps
CPU time 3.05 seconds
Started Apr 25 12:54:32 PM PDT 24
Finished Apr 25 12:54:38 PM PDT 24
Peak memory 209500 kb
Host smart-207043de-fe77-4f79-a24e-88e56d79a099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939772762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.1939772762
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.3783742311
Short name T375
Test name
Test status
Simulation time 108762296 ps
CPU time 3.63 seconds
Started Apr 25 12:54:29 PM PDT 24
Finished Apr 25 12:54:36 PM PDT 24
Peak memory 222236 kb
Host smart-55bb0e7c-c11c-4a63-9b1d-123b36c03d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783742311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.3783742311
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_random.2437369012
Short name T268
Test name
Test status
Simulation time 5490711588 ps
CPU time 96.33 seconds
Started Apr 25 12:53:04 PM PDT 24
Finished Apr 25 12:54:42 PM PDT 24
Peak memory 209220 kb
Host smart-325fd8fc-3e72-4165-a798-7bc15f719a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437369012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.2437369012
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.24299885
Short name T301
Test name
Test status
Simulation time 1820163852 ps
CPU time 15.46 seconds
Started Apr 25 12:54:20 PM PDT 24
Finished Apr 25 12:54:39 PM PDT 24
Peak memory 214024 kb
Host smart-28f2e5e6-6825-4272-a3ac-9356a1bd6bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24299885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.24299885
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.3776176716
Short name T372
Test name
Test status
Simulation time 510428173 ps
CPU time 5.43 seconds
Started Apr 25 12:54:56 PM PDT 24
Finished Apr 25 12:55:04 PM PDT 24
Peak memory 222232 kb
Host smart-a060dcad-c5c2-4fc4-a2a4-715f286adc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776176716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.3776176716
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.3152007215
Short name T935
Test name
Test status
Simulation time 1909387832 ps
CPU time 11.22 seconds
Started Apr 25 12:34:08 PM PDT 24
Finished Apr 25 12:34:22 PM PDT 24
Peak memory 206020 kb
Host smart-dda45ced-63d5-4ce3-8954-22c8d7ef804f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152007215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.3
152007215
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.272318225
Short name T923
Test name
Test status
Simulation time 664241398 ps
CPU time 8.45 seconds
Started Apr 25 12:34:06 PM PDT 24
Finished Apr 25 12:34:17 PM PDT 24
Peak memory 206032 kb
Host smart-1b86e99d-8699-4bb7-b971-205478430dd1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272318225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.272318225
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.3318149956
Short name T945
Test name
Test status
Simulation time 42860803 ps
CPU time 1.61 seconds
Started Apr 25 12:34:07 PM PDT 24
Finished Apr 25 12:34:11 PM PDT 24
Peak memory 206020 kb
Host smart-6a5ebcaf-e684-45ba-9ada-037084e02a14
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318149956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.3
318149956
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.713901556
Short name T912
Test name
Test status
Simulation time 302231949 ps
CPU time 1.43 seconds
Started Apr 25 12:34:13 PM PDT 24
Finished Apr 25 12:34:16 PM PDT 24
Peak memory 214360 kb
Host smart-6a51a4da-9737-4765-90de-a343ec8d3fb2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713901556 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.713901556
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.166930504
Short name T988
Test name
Test status
Simulation time 34061650 ps
CPU time 1.55 seconds
Started Apr 25 12:34:03 PM PDT 24
Finished Apr 25 12:34:06 PM PDT 24
Peak memory 206004 kb
Host smart-ee2a243d-2a2a-4cfd-8031-27cb3d2207cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166930504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.166930504
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2234939852
Short name T970
Test name
Test status
Simulation time 41406612 ps
CPU time 0.79 seconds
Started Apr 25 12:34:08 PM PDT 24
Finished Apr 25 12:34:11 PM PDT 24
Peak memory 205772 kb
Host smart-9e5c9975-e030-4918-8085-250db97e05f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234939852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.2234939852
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.989800093
Short name T1057
Test name
Test status
Simulation time 534774377 ps
CPU time 2.74 seconds
Started Apr 25 12:34:07 PM PDT 24
Finished Apr 25 12:34:12 PM PDT 24
Peak memory 206104 kb
Host smart-db57b401-5ea6-48bb-a060-efaa77605cc5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989800093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sam
e_csr_outstanding.989800093
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.639675098
Short name T971
Test name
Test status
Simulation time 633944408 ps
CPU time 5.05 seconds
Started Apr 25 12:34:06 PM PDT 24
Finished Apr 25 12:34:14 PM PDT 24
Peak memory 214664 kb
Host smart-25273263-9baf-443d-889d-a40147c645f7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639675098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow
_reg_errors.639675098
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.3789566124
Short name T1058
Test name
Test status
Simulation time 426949563 ps
CPU time 14.24 seconds
Started Apr 25 12:34:08 PM PDT 24
Finished Apr 25 12:34:24 PM PDT 24
Peak memory 214512 kb
Host smart-2617573d-5181-46a8-9da9-6581150d5165
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789566124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.3789566124
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.3207946390
Short name T993
Test name
Test status
Simulation time 174197167 ps
CPU time 1.51 seconds
Started Apr 25 12:34:07 PM PDT 24
Finished Apr 25 12:34:11 PM PDT 24
Peak memory 206012 kb
Host smart-76e2b055-c58a-45b9-b788-de848f938b1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207946390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.3207946390
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.4047428472
Short name T378
Test name
Test status
Simulation time 158744915 ps
CPU time 5.78 seconds
Started Apr 25 12:34:05 PM PDT 24
Finished Apr 25 12:34:11 PM PDT 24
Peak memory 209352 kb
Host smart-ab1d9a99-039b-4948-af63-f62a363d9f43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047428472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.4047428472
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.315857088
Short name T905
Test name
Test status
Simulation time 449739377 ps
CPU time 16.55 seconds
Started Apr 25 12:34:05 PM PDT 24
Finished Apr 25 12:34:22 PM PDT 24
Peak memory 206012 kb
Host smart-27c4b9be-fcf8-499a-b71a-fffbd3319f22
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315857088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.315857088
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.900365564
Short name T972
Test name
Test status
Simulation time 876731266 ps
CPU time 15 seconds
Started Apr 25 12:34:06 PM PDT 24
Finished Apr 25 12:34:24 PM PDT 24
Peak memory 206036 kb
Host smart-48ddb7f4-5dcd-460f-865f-2c3058b5f273
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900365564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.900365564
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.4045405732
Short name T1023
Test name
Test status
Simulation time 17926135 ps
CPU time 0.92 seconds
Started Apr 25 12:34:06 PM PDT 24
Finished Apr 25 12:34:09 PM PDT 24
Peak memory 205784 kb
Host smart-3df4f27b-d1ca-4bcb-b9f8-3d98889134e0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045405732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.4
045405732
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1497627142
Short name T958
Test name
Test status
Simulation time 40428734 ps
CPU time 1.55 seconds
Started Apr 25 12:34:04 PM PDT 24
Finished Apr 25 12:34:06 PM PDT 24
Peak memory 214380 kb
Host smart-f454315e-deb1-479c-88b1-8288a9cd23e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497627142 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.1497627142
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.802543248
Short name T965
Test name
Test status
Simulation time 89631805 ps
CPU time 1.07 seconds
Started Apr 25 12:34:12 PM PDT 24
Finished Apr 25 12:34:16 PM PDT 24
Peak memory 205932 kb
Host smart-7d1d95ee-b640-4791-bd3f-99fc900d5f7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802543248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.802543248
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.3175171220
Short name T934
Test name
Test status
Simulation time 45715924 ps
CPU time 0.88 seconds
Started Apr 25 12:34:08 PM PDT 24
Finished Apr 25 12:34:11 PM PDT 24
Peak memory 205772 kb
Host smart-5e0c6708-ba16-42ef-aa5a-46fd12e4c95c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175171220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.3175171220
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.1763192840
Short name T992
Test name
Test status
Simulation time 88284737 ps
CPU time 1.6 seconds
Started Apr 25 12:34:08 PM PDT 24
Finished Apr 25 12:34:12 PM PDT 24
Peak memory 206032 kb
Host smart-df8b6bd9-e251-48b7-a831-8369f08e1f7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763192840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.1763192840
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3449153859
Short name T1028
Test name
Test status
Simulation time 392301744 ps
CPU time 4.11 seconds
Started Apr 25 12:34:04 PM PDT 24
Finished Apr 25 12:34:09 PM PDT 24
Peak memory 214580 kb
Host smart-8e82d4af-afc0-48ef-b02f-0c06c7c44d8d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449153859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.3449153859
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3099967221
Short name T1040
Test name
Test status
Simulation time 609876307 ps
CPU time 12.24 seconds
Started Apr 25 12:34:06 PM PDT 24
Finished Apr 25 12:34:20 PM PDT 24
Peak memory 214516 kb
Host smart-a1da1539-6d38-4f2c-8030-f0c7a7ea168e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099967221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.3099967221
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.4165205267
Short name T908
Test name
Test status
Simulation time 294894556 ps
CPU time 2.23 seconds
Started Apr 25 12:34:05 PM PDT 24
Finished Apr 25 12:34:08 PM PDT 24
Peak memory 215612 kb
Host smart-86483ccb-90db-4f46-92ef-4ef72b117ddf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165205267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.4165205267
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1548321803
Short name T946
Test name
Test status
Simulation time 14032791 ps
CPU time 1.17 seconds
Started Apr 25 12:34:21 PM PDT 24
Finished Apr 25 12:34:25 PM PDT 24
Peak memory 206340 kb
Host smart-5217c169-7e56-47e9-bb28-c6be727766b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548321803 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.1548321803
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.3068320737
Short name T964
Test name
Test status
Simulation time 25345369 ps
CPU time 1.03 seconds
Started Apr 25 12:34:21 PM PDT 24
Finished Apr 25 12:34:25 PM PDT 24
Peak memory 205948 kb
Host smart-f9f8a3a9-1b70-45a0-9a5a-f5eec62e74d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068320737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.3068320737
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.2099914419
Short name T1025
Test name
Test status
Simulation time 12326218 ps
CPU time 0.84 seconds
Started Apr 25 12:34:50 PM PDT 24
Finished Apr 25 12:34:53 PM PDT 24
Peak memory 205752 kb
Host smart-2cf1a2a1-176d-4eff-a2a8-01d7333272b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099914419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.2099914419
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.407437299
Short name T1004
Test name
Test status
Simulation time 70200195 ps
CPU time 1.5 seconds
Started Apr 25 12:34:18 PM PDT 24
Finished Apr 25 12:34:22 PM PDT 24
Peak memory 206096 kb
Host smart-7cbbb6d2-b11c-483e-ad73-f358c6d80506
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407437299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_sa
me_csr_outstanding.407437299
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.928737846
Short name T940
Test name
Test status
Simulation time 557352725 ps
CPU time 11.56 seconds
Started Apr 25 12:34:22 PM PDT 24
Finished Apr 25 12:34:36 PM PDT 24
Peak memory 214516 kb
Host smart-5d6ddaf3-222a-463b-83c6-783a4a6d6391
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928737846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shado
w_reg_errors.928737846
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.487098568
Short name T955
Test name
Test status
Simulation time 158791253 ps
CPU time 3.73 seconds
Started Apr 25 12:34:19 PM PDT 24
Finished Apr 25 12:34:25 PM PDT 24
Peak memory 220544 kb
Host smart-a19ccc83-1b41-42b5-8a5b-6bc62a9260be
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487098568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
keymgr_shadow_reg_errors_with_csr_rw.487098568
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.512666385
Short name T1026
Test name
Test status
Simulation time 157666034 ps
CPU time 2.63 seconds
Started Apr 25 12:34:18 PM PDT 24
Finished Apr 25 12:34:22 PM PDT 24
Peak memory 217360 kb
Host smart-d1e7f3b2-cd9e-44df-ae25-8802a6ac7402
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512666385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.512666385
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.2660978233
Short name T150
Test name
Test status
Simulation time 97220834 ps
CPU time 2.94 seconds
Started Apr 25 12:34:22 PM PDT 24
Finished Apr 25 12:34:28 PM PDT 24
Peak memory 209628 kb
Host smart-11acc84e-9b62-4ce1-b32a-f6ef284e22c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660978233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.2660978233
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3938016979
Short name T947
Test name
Test status
Simulation time 58934128 ps
CPU time 1.58 seconds
Started Apr 25 12:34:20 PM PDT 24
Finished Apr 25 12:34:24 PM PDT 24
Peak memory 214256 kb
Host smart-21de2074-d845-4bdc-acaa-77b3f7f7ab5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938016979 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.3938016979
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.3910504518
Short name T1049
Test name
Test status
Simulation time 51872106 ps
CPU time 1 seconds
Started Apr 25 12:34:22 PM PDT 24
Finished Apr 25 12:34:25 PM PDT 24
Peak memory 205948 kb
Host smart-722c7ee2-0bac-4cb9-aa31-3c5a75188bb0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910504518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.3910504518
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.878129983
Short name T907
Test name
Test status
Simulation time 20932383 ps
CPU time 0.75 seconds
Started Apr 25 12:34:26 PM PDT 24
Finished Apr 25 12:34:29 PM PDT 24
Peak memory 205804 kb
Host smart-7c06a898-077b-44a2-a610-09ceec6587b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878129983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.878129983
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.2164255559
Short name T924
Test name
Test status
Simulation time 73426335 ps
CPU time 2.39 seconds
Started Apr 25 12:34:19 PM PDT 24
Finished Apr 25 12:34:23 PM PDT 24
Peak memory 206056 kb
Host smart-10175f93-d6e3-41f7-9a53-1d68e8d2b7f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164255559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.2164255559
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.2093523363
Short name T1022
Test name
Test status
Simulation time 1129133149 ps
CPU time 10.27 seconds
Started Apr 25 12:34:21 PM PDT 24
Finished Apr 25 12:34:34 PM PDT 24
Peak memory 214480 kb
Host smart-d3cd6608-1c99-4c7a-8296-9612aeedbb6c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093523363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.2093523363
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3620584145
Short name T1045
Test name
Test status
Simulation time 619477978 ps
CPU time 6.42 seconds
Started Apr 25 12:34:21 PM PDT 24
Finished Apr 25 12:34:30 PM PDT 24
Peak memory 214484 kb
Host smart-06e3a9e9-c305-481d-b97e-e87f2949587f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620584145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.3620584145
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.2000416103
Short name T902
Test name
Test status
Simulation time 545070783 ps
CPU time 5.21 seconds
Started Apr 25 12:34:20 PM PDT 24
Finished Apr 25 12:34:27 PM PDT 24
Peak memory 214300 kb
Host smart-faba0c8b-5855-4a7d-84c7-59ed21ddf45d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000416103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.2000416103
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.558557129
Short name T985
Test name
Test status
Simulation time 32501660 ps
CPU time 1.18 seconds
Started Apr 25 12:34:26 PM PDT 24
Finished Apr 25 12:34:30 PM PDT 24
Peak memory 206080 kb
Host smart-51afe913-6b5c-4547-9753-71877239acfb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558557129 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.558557129
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.2497825207
Short name T1056
Test name
Test status
Simulation time 13864595 ps
CPU time 1.08 seconds
Started Apr 25 12:34:19 PM PDT 24
Finished Apr 25 12:34:22 PM PDT 24
Peak memory 205872 kb
Host smart-a3e5b866-2f3e-4dc5-8c74-299ce5576565
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497825207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.2497825207
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.1003641633
Short name T1066
Test name
Test status
Simulation time 57743614 ps
CPU time 0.84 seconds
Started Apr 25 12:34:22 PM PDT 24
Finished Apr 25 12:34:26 PM PDT 24
Peak memory 205788 kb
Host smart-523d8052-217b-459c-97da-c684a7406a9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003641633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.1003641633
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.2586398422
Short name T1041
Test name
Test status
Simulation time 87860078 ps
CPU time 1.39 seconds
Started Apr 25 12:34:18 PM PDT 24
Finished Apr 25 12:34:22 PM PDT 24
Peak memory 206076 kb
Host smart-6fd7d2fc-e587-4747-aa21-a6b315d4618e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586398422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.2586398422
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2700675691
Short name T990
Test name
Test status
Simulation time 208260663 ps
CPU time 3.87 seconds
Started Apr 25 12:34:22 PM PDT 24
Finished Apr 25 12:34:29 PM PDT 24
Peak memory 214588 kb
Host smart-372678ab-657e-4e31-a175-148ea4ce512f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700675691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.2700675691
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.850407203
Short name T925
Test name
Test status
Simulation time 944480832 ps
CPU time 4.96 seconds
Started Apr 25 12:34:24 PM PDT 24
Finished Apr 25 12:34:32 PM PDT 24
Peak memory 214540 kb
Host smart-1936fbcb-9d5f-47b1-86c8-279009865acc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850407203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
keymgr_shadow_reg_errors_with_csr_rw.850407203
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.2542954381
Short name T1046
Test name
Test status
Simulation time 200966429 ps
CPU time 3.55 seconds
Started Apr 25 12:34:21 PM PDT 24
Finished Apr 25 12:34:27 PM PDT 24
Peak memory 214296 kb
Host smart-00c39f78-6c5e-4341-9c8c-665fe12c074f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542954381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.2542954381
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.1142598721
Short name T975
Test name
Test status
Simulation time 189905493 ps
CPU time 5.5 seconds
Started Apr 25 12:34:22 PM PDT 24
Finished Apr 25 12:34:30 PM PDT 24
Peak memory 209692 kb
Host smart-e8c68465-3b16-4644-818c-b009da878cb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142598721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.1142598721
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.3021458247
Short name T973
Test name
Test status
Simulation time 26658545 ps
CPU time 1.09 seconds
Started Apr 25 12:34:27 PM PDT 24
Finished Apr 25 12:34:30 PM PDT 24
Peak memory 214332 kb
Host smart-05b32d80-249d-4a56-bb66-539f4cce63e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021458247 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.3021458247
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.993538723
Short name T1002
Test name
Test status
Simulation time 60173750 ps
CPU time 1 seconds
Started Apr 25 12:34:28 PM PDT 24
Finished Apr 25 12:34:31 PM PDT 24
Peak memory 205848 kb
Host smart-38b7477a-b9f3-4394-84cc-f88ee340620a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993538723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.993538723
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3778567187
Short name T1033
Test name
Test status
Simulation time 13784074 ps
CPU time 0.74 seconds
Started Apr 25 12:34:24 PM PDT 24
Finished Apr 25 12:34:27 PM PDT 24
Peak memory 205800 kb
Host smart-70df3975-4685-4c67-960c-8c6598cc1f95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778567187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.3778567187
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.734600294
Short name T942
Test name
Test status
Simulation time 70253784 ps
CPU time 2.14 seconds
Started Apr 25 12:34:23 PM PDT 24
Finished Apr 25 12:34:28 PM PDT 24
Peak memory 206196 kb
Host smart-2acacefc-35bd-4f2a-a321-9ae97e7e30e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734600294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_sa
me_csr_outstanding.734600294
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1456153978
Short name T113
Test name
Test status
Simulation time 1047499196 ps
CPU time 14.96 seconds
Started Apr 25 12:34:21 PM PDT 24
Finished Apr 25 12:34:39 PM PDT 24
Peak memory 214580 kb
Host smart-2481e957-ed20-4588-bfa4-9a24edb46675
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456153978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.1456153978
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.1301131262
Short name T122
Test name
Test status
Simulation time 1756397537 ps
CPU time 15.47 seconds
Started Apr 25 12:34:18 PM PDT 24
Finished Apr 25 12:34:35 PM PDT 24
Peak memory 214664 kb
Host smart-b08f79c4-8cb1-416b-b020-db78d45c3c5f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301131262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.1301131262
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.2252608978
Short name T1014
Test name
Test status
Simulation time 24133213 ps
CPU time 1.62 seconds
Started Apr 25 12:34:22 PM PDT 24
Finished Apr 25 12:34:26 PM PDT 24
Peak memory 214376 kb
Host smart-4322c31d-e5e3-41e4-98ba-37c3dcc80fc4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252608978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.2252608978
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.214293555
Short name T1043
Test name
Test status
Simulation time 117665128 ps
CPU time 4.75 seconds
Started Apr 25 12:34:21 PM PDT 24
Finished Apr 25 12:34:28 PM PDT 24
Peak memory 214340 kb
Host smart-698eed02-b5d9-4e3b-8b07-589c36c61437
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214293555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err
.214293555
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.3934747774
Short name T1053
Test name
Test status
Simulation time 61100196 ps
CPU time 2.09 seconds
Started Apr 25 12:34:24 PM PDT 24
Finished Apr 25 12:34:28 PM PDT 24
Peak memory 214412 kb
Host smart-c45dbcde-1143-4eda-ad85-45ea1db977d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934747774 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.3934747774
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.786637230
Short name T974
Test name
Test status
Simulation time 23728958 ps
CPU time 1.12 seconds
Started Apr 25 12:34:20 PM PDT 24
Finished Apr 25 12:34:23 PM PDT 24
Peak memory 206020 kb
Host smart-31859fb4-7498-4372-8c95-4818defe8c07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786637230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.786637230
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.462989159
Short name T909
Test name
Test status
Simulation time 93011553 ps
CPU time 0.85 seconds
Started Apr 25 12:34:24 PM PDT 24
Finished Apr 25 12:34:27 PM PDT 24
Peak memory 205612 kb
Host smart-256327d9-9860-45fa-81aa-f9a4b338d3e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462989159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.462989159
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.1516403804
Short name T1000
Test name
Test status
Simulation time 330298737 ps
CPU time 2.66 seconds
Started Apr 25 12:34:24 PM PDT 24
Finished Apr 25 12:34:29 PM PDT 24
Peak memory 206040 kb
Host smart-2dfbe97b-743e-44cd-9e59-5d1f0672323a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516403804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.1516403804
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.2770670920
Short name T994
Test name
Test status
Simulation time 1385090851 ps
CPU time 8.49 seconds
Started Apr 25 12:34:22 PM PDT 24
Finished Apr 25 12:34:33 PM PDT 24
Peak memory 213564 kb
Host smart-37b8e6e4-ab14-4848-8801-2ba2421a4b1b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770670920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.2770670920
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.791331510
Short name T1013
Test name
Test status
Simulation time 538067023 ps
CPU time 7.65 seconds
Started Apr 25 12:34:22 PM PDT 24
Finished Apr 25 12:34:33 PM PDT 24
Peak memory 219708 kb
Host smart-4059d20f-aacd-44ba-ba9d-06ca7ff026e0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791331510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
keymgr_shadow_reg_errors_with_csr_rw.791331510
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.1910726550
Short name T1061
Test name
Test status
Simulation time 458577553 ps
CPU time 3.2 seconds
Started Apr 25 12:34:22 PM PDT 24
Finished Apr 25 12:34:28 PM PDT 24
Peak memory 216272 kb
Host smart-d4e1a384-f0fe-4207-a292-19c78066f8e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910726550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.1910726550
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.4091160335
Short name T943
Test name
Test status
Simulation time 508711450 ps
CPU time 5.51 seconds
Started Apr 25 12:34:22 PM PDT 24
Finished Apr 25 12:34:31 PM PDT 24
Peak memory 214280 kb
Host smart-d723cd8d-7001-4180-bbae-9fcfd51a66d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091160335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.4091160335
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3838949548
Short name T1017
Test name
Test status
Simulation time 38038688 ps
CPU time 1.49 seconds
Started Apr 25 12:34:30 PM PDT 24
Finished Apr 25 12:34:34 PM PDT 24
Peak memory 206152 kb
Host smart-060f226a-64f0-4b54-be95-4569e8026e88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838949548 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.3838949548
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.2128383486
Short name T1063
Test name
Test status
Simulation time 15470133 ps
CPU time 1.04 seconds
Started Apr 25 12:34:26 PM PDT 24
Finished Apr 25 12:34:29 PM PDT 24
Peak memory 205988 kb
Host smart-6a97c303-cf6a-4634-9735-df76b1a605fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128383486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.2128383486
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.3919523326
Short name T991
Test name
Test status
Simulation time 26614275 ps
CPU time 0.83 seconds
Started Apr 25 12:34:29 PM PDT 24
Finished Apr 25 12:34:33 PM PDT 24
Peak memory 205724 kb
Host smart-e7029099-50e2-438d-829b-c57f45aabb37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919523326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.3919523326
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.1586166006
Short name T1031
Test name
Test status
Simulation time 73117612 ps
CPU time 2.63 seconds
Started Apr 25 12:34:28 PM PDT 24
Finished Apr 25 12:34:34 PM PDT 24
Peak memory 206100 kb
Host smart-611153ed-8779-4467-84f8-eb443db9013f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586166006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.1586166006
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.2655635633
Short name T1018
Test name
Test status
Simulation time 171944950 ps
CPU time 4.78 seconds
Started Apr 25 12:34:28 PM PDT 24
Finished Apr 25 12:34:35 PM PDT 24
Peak memory 222732 kb
Host smart-fa1a079a-db7a-4e09-88fa-8db0b77716dd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655635633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.2655635633
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1002343910
Short name T995
Test name
Test status
Simulation time 93520878 ps
CPU time 3.87 seconds
Started Apr 25 12:34:24 PM PDT 24
Finished Apr 25 12:34:30 PM PDT 24
Peak memory 214496 kb
Host smart-9db2efe0-167c-4c8f-bfc7-919d1666584a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002343910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.1002343910
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.1506234449
Short name T929
Test name
Test status
Simulation time 46431271 ps
CPU time 2.82 seconds
Started Apr 25 12:34:28 PM PDT 24
Finished Apr 25 12:34:33 PM PDT 24
Peak memory 214316 kb
Host smart-4a47c66d-640e-4bb9-9047-85b2904e49a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506234449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.1506234449
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.684635049
Short name T913
Test name
Test status
Simulation time 68768296 ps
CPU time 2.06 seconds
Started Apr 25 12:34:32 PM PDT 24
Finished Apr 25 12:34:37 PM PDT 24
Peak memory 214068 kb
Host smart-8fe6af9a-1224-4fb2-a3e0-f47fd099a36e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684635049 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.684635049
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.2242248361
Short name T962
Test name
Test status
Simulation time 21113295 ps
CPU time 1.14 seconds
Started Apr 25 12:34:36 PM PDT 24
Finished Apr 25 12:34:40 PM PDT 24
Peak memory 205976 kb
Host smart-ce0655a6-8ecf-4984-8af1-3a61caa99ecb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242248361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.2242248361
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.2791795788
Short name T918
Test name
Test status
Simulation time 19504194 ps
CPU time 0.82 seconds
Started Apr 25 12:34:25 PM PDT 24
Finished Apr 25 12:34:28 PM PDT 24
Peak memory 205632 kb
Host smart-ece83e73-b232-4563-a946-84f49290212e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791795788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.2791795788
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.1691906905
Short name T1062
Test name
Test status
Simulation time 69680799 ps
CPU time 2.07 seconds
Started Apr 25 12:34:28 PM PDT 24
Finished Apr 25 12:34:33 PM PDT 24
Peak memory 206144 kb
Host smart-449e4b0f-1351-4d1d-b028-80beb1039c87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691906905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.1691906905
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.2642872339
Short name T984
Test name
Test status
Simulation time 297147013 ps
CPU time 2.57 seconds
Started Apr 25 12:34:28 PM PDT 24
Finished Apr 25 12:34:33 PM PDT 24
Peak memory 222672 kb
Host smart-5f8920cb-ff1d-4135-825d-ec45c23e331a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642872339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.2642872339
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3134045548
Short name T1036
Test name
Test status
Simulation time 319816606 ps
CPU time 5.88 seconds
Started Apr 25 12:34:27 PM PDT 24
Finished Apr 25 12:34:36 PM PDT 24
Peak memory 214556 kb
Host smart-3f849570-c584-4e77-84e4-2291056197a5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134045548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.3134045548
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.1016748739
Short name T932
Test name
Test status
Simulation time 253950084 ps
CPU time 2.83 seconds
Started Apr 25 12:34:29 PM PDT 24
Finished Apr 25 12:34:34 PM PDT 24
Peak memory 216396 kb
Host smart-1d342db2-4985-483e-a2ff-9a65fe6917aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016748739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.1016748739
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.3513334159
Short name T1038
Test name
Test status
Simulation time 109447642 ps
CPU time 3.19 seconds
Started Apr 25 12:34:30 PM PDT 24
Finished Apr 25 12:34:36 PM PDT 24
Peak memory 214276 kb
Host smart-bef4cfdb-0768-498a-b637-3c29bf487feb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513334159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.3513334159
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1136313023
Short name T916
Test name
Test status
Simulation time 32168837 ps
CPU time 1.54 seconds
Started Apr 25 12:34:32 PM PDT 24
Finished Apr 25 12:34:36 PM PDT 24
Peak memory 214344 kb
Host smart-44abc451-4889-49f9-955b-7178dfe2d01f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136313023 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.1136313023
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.2250555403
Short name T1065
Test name
Test status
Simulation time 40674490 ps
CPU time 0.98 seconds
Started Apr 25 12:34:27 PM PDT 24
Finished Apr 25 12:34:30 PM PDT 24
Peak memory 205864 kb
Host smart-01ecb4ef-7cb2-4b04-b8b1-c76ae228c8e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250555403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.2250555403
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.688717085
Short name T1035
Test name
Test status
Simulation time 9938033 ps
CPU time 0.73 seconds
Started Apr 25 12:34:27 PM PDT 24
Finished Apr 25 12:34:31 PM PDT 24
Peak memory 205780 kb
Host smart-987821a0-5a49-485c-a409-b5a1b85daa67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688717085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.688717085
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.4286811158
Short name T1012
Test name
Test status
Simulation time 413889029 ps
CPU time 1.79 seconds
Started Apr 25 12:34:33 PM PDT 24
Finished Apr 25 12:34:38 PM PDT 24
Peak memory 206112 kb
Host smart-36a4d895-047e-4596-a1bc-b02cf652fa0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286811158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.4286811158
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2469709244
Short name T1007
Test name
Test status
Simulation time 305974222 ps
CPU time 3.47 seconds
Started Apr 25 12:34:29 PM PDT 24
Finished Apr 25 12:34:35 PM PDT 24
Peak memory 214604 kb
Host smart-f9dd8c0a-16d1-4a63-a562-f51bdadd0a25
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469709244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.2469709244
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.4154064619
Short name T933
Test name
Test status
Simulation time 169280937 ps
CPU time 2.31 seconds
Started Apr 25 12:34:33 PM PDT 24
Finished Apr 25 12:34:38 PM PDT 24
Peak memory 214276 kb
Host smart-773c6fe7-4718-45fb-bc6c-c58340de871c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154064619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.4154064619
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2919033601
Short name T1030
Test name
Test status
Simulation time 53465009 ps
CPU time 1.09 seconds
Started Apr 25 12:34:28 PM PDT 24
Finished Apr 25 12:34:32 PM PDT 24
Peak memory 214360 kb
Host smart-7d9b7ec6-d423-474f-a76c-79ec03321d9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919033601 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.2919033601
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.2297542551
Short name T968
Test name
Test status
Simulation time 75586249 ps
CPU time 0.97 seconds
Started Apr 25 12:34:29 PM PDT 24
Finished Apr 25 12:34:33 PM PDT 24
Peak memory 205768 kb
Host smart-0b38b895-ca6e-4384-83a2-f02897b6ca93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297542551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.2297542551
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.4276205909
Short name T903
Test name
Test status
Simulation time 102431856 ps
CPU time 0.93 seconds
Started Apr 25 12:34:25 PM PDT 24
Finished Apr 25 12:34:29 PM PDT 24
Peak memory 205800 kb
Host smart-6d1d7412-02aa-4650-a2dd-a890bda964d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276205909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.4276205909
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.3606186682
Short name T139
Test name
Test status
Simulation time 271512640 ps
CPU time 4.13 seconds
Started Apr 25 12:34:29 PM PDT 24
Finished Apr 25 12:34:36 PM PDT 24
Peak memory 206180 kb
Host smart-facb6535-de09-40d3-9a0f-f4a492288f84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606186682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.3606186682
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.4185140490
Short name T1054
Test name
Test status
Simulation time 240417785 ps
CPU time 4.56 seconds
Started Apr 25 12:34:31 PM PDT 24
Finished Apr 25 12:34:38 PM PDT 24
Peak memory 214668 kb
Host smart-2d25c82d-fca1-45e5-8e09-2692109b8c8b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185140490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.4185140490
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2547305457
Short name T986
Test name
Test status
Simulation time 1068571366 ps
CPU time 15.97 seconds
Started Apr 25 12:34:33 PM PDT 24
Finished Apr 25 12:34:52 PM PDT 24
Peak memory 221540 kb
Host smart-f3924a1c-c313-43b2-98bc-16deb288510a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547305457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.2547305457
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.2700379090
Short name T951
Test name
Test status
Simulation time 34556695 ps
CPU time 2.2 seconds
Started Apr 25 12:34:28 PM PDT 24
Finished Apr 25 12:34:33 PM PDT 24
Peak memory 214336 kb
Host smart-92235bc9-6fe4-4685-aa81-8c17dac063be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700379090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.2700379090
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.3962368503
Short name T379
Test name
Test status
Simulation time 1007266409 ps
CPU time 12.8 seconds
Started Apr 25 12:34:26 PM PDT 24
Finished Apr 25 12:34:42 PM PDT 24
Peak memory 209672 kb
Host smart-65138069-d5ae-4488-b337-2bf02505006b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962368503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.3962368503
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3772385373
Short name T949
Test name
Test status
Simulation time 409461661 ps
CPU time 2.18 seconds
Started Apr 25 12:34:32 PM PDT 24
Finished Apr 25 12:34:37 PM PDT 24
Peak memory 218408 kb
Host smart-a4d9b33d-3650-47f2-b635-69e6161b33b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772385373 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.3772385373
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.1056559491
Short name T137
Test name
Test status
Simulation time 15787296 ps
CPU time 0.93 seconds
Started Apr 25 12:34:27 PM PDT 24
Finished Apr 25 12:34:30 PM PDT 24
Peak memory 205736 kb
Host smart-eb9507de-c6d1-4e50-809a-0f89f2d10489
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056559491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.1056559491
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.2698825139
Short name T930
Test name
Test status
Simulation time 99809218 ps
CPU time 0.78 seconds
Started Apr 25 12:34:30 PM PDT 24
Finished Apr 25 12:34:33 PM PDT 24
Peak memory 205748 kb
Host smart-ab34afb6-d9dd-4fcf-b7e7-9c19e59ab34c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698825139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.2698825139
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.238478357
Short name T998
Test name
Test status
Simulation time 126544835 ps
CPU time 1.71 seconds
Started Apr 25 12:34:29 PM PDT 24
Finished Apr 25 12:34:33 PM PDT 24
Peak memory 206168 kb
Host smart-ee54e6d6-68e7-4075-94fe-0e0416b43a03
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238478357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_sa
me_csr_outstanding.238478357
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.1153720837
Short name T1050
Test name
Test status
Simulation time 519897700 ps
CPU time 2.98 seconds
Started Apr 25 12:34:29 PM PDT 24
Finished Apr 25 12:34:34 PM PDT 24
Peak memory 214552 kb
Host smart-8633de27-9ca2-4438-b9e6-bbf8da6d241f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153720837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.1153720837
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1122277162
Short name T1016
Test name
Test status
Simulation time 386754443 ps
CPU time 14.43 seconds
Started Apr 25 12:34:28 PM PDT 24
Finished Apr 25 12:34:45 PM PDT 24
Peak memory 214616 kb
Host smart-6c720bc9-4a2f-4e90-a0f6-cb709056a958
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122277162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.1122277162
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.472388917
Short name T954
Test name
Test status
Simulation time 100596363 ps
CPU time 2.82 seconds
Started Apr 25 12:34:29 PM PDT 24
Finished Apr 25 12:34:35 PM PDT 24
Peak memory 214164 kb
Host smart-12a64c0f-13d8-45c0-9824-b84dd021036d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472388917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.472388917
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3916801496
Short name T967
Test name
Test status
Simulation time 536141137 ps
CPU time 8.89 seconds
Started Apr 25 12:34:09 PM PDT 24
Finished Apr 25 12:34:20 PM PDT 24
Peak memory 206080 kb
Host smart-1d23829c-3847-4486-a6f5-fb95933ec0e1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916801496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.3
916801496
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.2639335482
Short name T989
Test name
Test status
Simulation time 132280371 ps
CPU time 7.71 seconds
Started Apr 25 12:34:06 PM PDT 24
Finished Apr 25 12:34:16 PM PDT 24
Peak memory 205984 kb
Host smart-cebec729-a3e5-4a3f-8cc8-de1e3e294723
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639335482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.2
639335482
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.3282715946
Short name T1001
Test name
Test status
Simulation time 13130928 ps
CPU time 0.9 seconds
Started Apr 25 12:34:05 PM PDT 24
Finished Apr 25 12:34:07 PM PDT 24
Peak memory 205872 kb
Host smart-e83eb307-82f3-4305-a832-22d32994befc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282715946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.3
282715946
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.3033404748
Short name T146
Test name
Test status
Simulation time 107365574 ps
CPU time 1.12 seconds
Started Apr 25 12:34:16 PM PDT 24
Finished Apr 25 12:34:18 PM PDT 24
Peak memory 206188 kb
Host smart-f369e4c5-2f1f-4f66-ab36-380c0b2f8f05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033404748 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.3033404748
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3899784369
Short name T382
Test name
Test status
Simulation time 25863602 ps
CPU time 1.32 seconds
Started Apr 25 12:34:06 PM PDT 24
Finished Apr 25 12:34:10 PM PDT 24
Peak memory 205984 kb
Host smart-9dd1d01d-8eab-42a2-9068-0c3d69ed8849
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899784369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.3899784369
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.3314268229
Short name T917
Test name
Test status
Simulation time 15112711 ps
CPU time 0.75 seconds
Started Apr 25 12:34:04 PM PDT 24
Finished Apr 25 12:34:06 PM PDT 24
Peak memory 205732 kb
Host smart-3eaeb13f-4a63-47a5-8851-c474b2b39af9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314268229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.3314268229
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.3604119070
Short name T937
Test name
Test status
Simulation time 136123177 ps
CPU time 2.16 seconds
Started Apr 25 12:34:11 PM PDT 24
Finished Apr 25 12:34:16 PM PDT 24
Peak memory 214296 kb
Host smart-8692503b-c598-4ed5-b810-eca0d540e031
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604119070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.3604119070
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.4112077500
Short name T1067
Test name
Test status
Simulation time 78701465 ps
CPU time 2.07 seconds
Started Apr 25 12:34:15 PM PDT 24
Finished Apr 25 12:34:18 PM PDT 24
Peak memory 214584 kb
Host smart-558accef-a634-4ea5-95d9-0238ea5c686e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112077500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.4112077500
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.2795212253
Short name T1047
Test name
Test status
Simulation time 449868836 ps
CPU time 9.39 seconds
Started Apr 25 12:34:07 PM PDT 24
Finished Apr 25 12:34:19 PM PDT 24
Peak memory 214476 kb
Host smart-47a2d00d-be57-42dd-a2fd-1f15f5911f7d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795212253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.2795212253
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.2239010923
Short name T978
Test name
Test status
Simulation time 156744489 ps
CPU time 2.88 seconds
Started Apr 25 12:34:07 PM PDT 24
Finished Apr 25 12:34:12 PM PDT 24
Peak memory 214272 kb
Host smart-7daf3807-c323-45e2-9e76-fd7e554a5a5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239010923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.2239010923
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.1596841041
Short name T928
Test name
Test status
Simulation time 11390452459 ps
CPU time 79.21 seconds
Started Apr 25 12:34:03 PM PDT 24
Finished Apr 25 12:35:24 PM PDT 24
Peak memory 227420 kb
Host smart-7aa41171-d527-4be1-bf4c-284eb9ba60b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596841041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.1596841041
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.3480639547
Short name T1068
Test name
Test status
Simulation time 42236365 ps
CPU time 0.81 seconds
Started Apr 25 12:34:32 PM PDT 24
Finished Apr 25 12:34:36 PM PDT 24
Peak memory 205512 kb
Host smart-3937d460-6608-492c-a5c6-7d1ce269a9c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480639547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.3480639547
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.293670978
Short name T1055
Test name
Test status
Simulation time 18386543 ps
CPU time 0.72 seconds
Started Apr 25 12:34:30 PM PDT 24
Finished Apr 25 12:34:34 PM PDT 24
Peak memory 205840 kb
Host smart-3e960d0d-48f9-4523-a58a-a185fe9a673f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293670978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.293670978
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.1877962090
Short name T999
Test name
Test status
Simulation time 12967887 ps
CPU time 0.76 seconds
Started Apr 25 12:34:26 PM PDT 24
Finished Apr 25 12:34:29 PM PDT 24
Peak memory 205844 kb
Host smart-53e532a4-4223-4472-b819-24663a009ee4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877962090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.1877962090
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.4243993115
Short name T1029
Test name
Test status
Simulation time 28260511 ps
CPU time 0.83 seconds
Started Apr 25 12:34:32 PM PDT 24
Finished Apr 25 12:34:35 PM PDT 24
Peak memory 205808 kb
Host smart-b8093410-d7c2-4542-ada3-c13ed0199942
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243993115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.4243993115
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.4042323280
Short name T1021
Test name
Test status
Simulation time 14706534 ps
CPU time 0.82 seconds
Started Apr 25 12:34:27 PM PDT 24
Finished Apr 25 12:34:30 PM PDT 24
Peak memory 205696 kb
Host smart-5be25159-1194-4115-a69d-c1fdc3e88e57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042323280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.4042323280
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.264156536
Short name T950
Test name
Test status
Simulation time 19592168 ps
CPU time 0.72 seconds
Started Apr 25 12:34:26 PM PDT 24
Finished Apr 25 12:34:29 PM PDT 24
Peak memory 205772 kb
Host smart-ef6cbd0b-4f4c-44f9-9d05-63095d10e90f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264156536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.264156536
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.178381720
Short name T915
Test name
Test status
Simulation time 30295338 ps
CPU time 0.76 seconds
Started Apr 25 12:34:31 PM PDT 24
Finished Apr 25 12:34:34 PM PDT 24
Peak memory 205812 kb
Host smart-4b98a6ec-b966-45c1-8d17-ac29a97a55e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178381720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.178381720
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.3778937249
Short name T982
Test name
Test status
Simulation time 73557469 ps
CPU time 0.74 seconds
Started Apr 25 12:34:27 PM PDT 24
Finished Apr 25 12:34:31 PM PDT 24
Peak memory 205844 kb
Host smart-c4e797a7-c81e-4d91-94a0-14cdc3264742
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778937249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.3778937249
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.1340165517
Short name T1020
Test name
Test status
Simulation time 14740089 ps
CPU time 0.76 seconds
Started Apr 25 12:34:28 PM PDT 24
Finished Apr 25 12:34:32 PM PDT 24
Peak memory 205752 kb
Host smart-4b906cc0-764d-4f7f-9d33-e908555ee8ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340165517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.1340165517
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.2566977804
Short name T961
Test name
Test status
Simulation time 26036388 ps
CPU time 0.94 seconds
Started Apr 25 12:34:37 PM PDT 24
Finished Apr 25 12:34:42 PM PDT 24
Peak memory 205796 kb
Host smart-4e2280e8-5582-4ef2-bd45-f1147c6109dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566977804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.2566977804
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.3026889611
Short name T1071
Test name
Test status
Simulation time 238534835 ps
CPU time 5.93 seconds
Started Apr 25 12:34:11 PM PDT 24
Finished Apr 25 12:34:20 PM PDT 24
Peak memory 206076 kb
Host smart-58ace326-f71b-44c8-a408-fa66a23298ac
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026889611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.3
026889611
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.608092368
Short name T997
Test name
Test status
Simulation time 1335360133 ps
CPU time 32.01 seconds
Started Apr 25 12:34:16 PM PDT 24
Finished Apr 25 12:34:50 PM PDT 24
Peak memory 205868 kb
Host smart-d3000efc-ffa2-4856-927a-072b17a6db14
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608092368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.608092368
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.1740947964
Short name T1010
Test name
Test status
Simulation time 92938856 ps
CPU time 1.23 seconds
Started Apr 25 12:34:17 PM PDT 24
Finished Apr 25 12:34:20 PM PDT 24
Peak memory 206032 kb
Host smart-2a51e084-8a53-433e-a108-8953fbea7ade
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740947964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.1
740947964
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.738735076
Short name T960
Test name
Test status
Simulation time 171574430 ps
CPU time 2.16 seconds
Started Apr 25 12:34:11 PM PDT 24
Finished Apr 25 12:34:16 PM PDT 24
Peak memory 214328 kb
Host smart-86834d41-8cb6-4de3-bd81-6a66156c3704
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738735076 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.738735076
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.964020017
Short name T138
Test name
Test status
Simulation time 42857824 ps
CPU time 1.05 seconds
Started Apr 25 12:34:17 PM PDT 24
Finished Apr 25 12:34:19 PM PDT 24
Peak memory 205976 kb
Host smart-6579345a-0c26-47c2-ab96-96f6255dd9e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964020017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.964020017
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.3524928447
Short name T1059
Test name
Test status
Simulation time 11597095 ps
CPU time 0.74 seconds
Started Apr 25 12:34:11 PM PDT 24
Finished Apr 25 12:34:13 PM PDT 24
Peak memory 205672 kb
Host smart-80ac71ac-3bac-49b1-b228-14cc826c61ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524928447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.3524928447
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.3529409525
Short name T921
Test name
Test status
Simulation time 180774471 ps
CPU time 1.61 seconds
Started Apr 25 12:34:12 PM PDT 24
Finished Apr 25 12:34:16 PM PDT 24
Peak memory 206044 kb
Host smart-b37709b7-ae98-4783-89be-3a68abf090f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529409525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.3529409525
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.973171518
Short name T120
Test name
Test status
Simulation time 1436142676 ps
CPU time 7.56 seconds
Started Apr 25 12:34:17 PM PDT 24
Finished Apr 25 12:34:26 PM PDT 24
Peak memory 214580 kb
Host smart-44cd88f5-f63d-4c66-8277-a6bf097dc83c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973171518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow
_reg_errors.973171518
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.2158517983
Short name T115
Test name
Test status
Simulation time 291153301 ps
CPU time 7.7 seconds
Started Apr 25 12:34:17 PM PDT 24
Finished Apr 25 12:34:26 PM PDT 24
Peak memory 214624 kb
Host smart-019c539e-283e-4f11-a32e-393d6ee709e7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158517983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.2158517983
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.1783743702
Short name T1009
Test name
Test status
Simulation time 63894365 ps
CPU time 2.41 seconds
Started Apr 25 12:34:12 PM PDT 24
Finished Apr 25 12:34:17 PM PDT 24
Peak memory 216512 kb
Host smart-d5adaa31-5d72-4485-847e-4e09470c15a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783743702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.1783743702
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.582522248
Short name T159
Test name
Test status
Simulation time 95828881 ps
CPU time 4.1 seconds
Started Apr 25 12:34:10 PM PDT 24
Finished Apr 25 12:34:16 PM PDT 24
Peak memory 214196 kb
Host smart-cc64d7cd-d4d9-4e70-b7e4-e440ce87b24e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582522248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.
582522248
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.222656792
Short name T911
Test name
Test status
Simulation time 59454363 ps
CPU time 0.79 seconds
Started Apr 25 12:34:35 PM PDT 24
Finished Apr 25 12:34:39 PM PDT 24
Peak memory 205752 kb
Host smart-5a556af2-8a5a-4c30-83e5-f28c2b28186d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222656792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.222656792
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.3207104592
Short name T1034
Test name
Test status
Simulation time 12926821 ps
CPU time 0.86 seconds
Started Apr 25 12:34:42 PM PDT 24
Finished Apr 25 12:34:46 PM PDT 24
Peak memory 205948 kb
Host smart-4760a9e2-066c-4964-8a15-5f3401e5f623
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207104592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.3207104592
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.567397775
Short name T910
Test name
Test status
Simulation time 37833431 ps
CPU time 0.77 seconds
Started Apr 25 12:34:34 PM PDT 24
Finished Apr 25 12:34:38 PM PDT 24
Peak memory 205808 kb
Host smart-97f3a27b-84c0-4d65-a367-8ba7af8eb360
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567397775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.567397775
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.1150393167
Short name T983
Test name
Test status
Simulation time 16182984 ps
CPU time 0.84 seconds
Started Apr 25 12:34:36 PM PDT 24
Finished Apr 25 12:34:40 PM PDT 24
Peak memory 205860 kb
Host smart-da776f79-37b8-4397-b20b-0e75cb6aab7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150393167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.1150393167
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.364461002
Short name T919
Test name
Test status
Simulation time 14797551 ps
CPU time 0.73 seconds
Started Apr 25 12:34:43 PM PDT 24
Finished Apr 25 12:34:47 PM PDT 24
Peak memory 205808 kb
Host smart-bba5fcf0-223c-4f15-b8ac-772f1f6e4cc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364461002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.364461002
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.752270994
Short name T900
Test name
Test status
Simulation time 76906402 ps
CPU time 0.71 seconds
Started Apr 25 12:34:35 PM PDT 24
Finished Apr 25 12:34:40 PM PDT 24
Peak memory 205680 kb
Host smart-1fa4c958-db1b-4123-bb0d-a8d782149093
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752270994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.752270994
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.707631188
Short name T1070
Test name
Test status
Simulation time 11322503 ps
CPU time 0.72 seconds
Started Apr 25 12:34:51 PM PDT 24
Finished Apr 25 12:34:53 PM PDT 24
Peak memory 205748 kb
Host smart-2d7e96c7-7083-4793-9490-1a399f9f8561
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707631188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.707631188
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.1257095406
Short name T920
Test name
Test status
Simulation time 24095925 ps
CPU time 0.72 seconds
Started Apr 25 12:34:34 PM PDT 24
Finished Apr 25 12:34:43 PM PDT 24
Peak memory 205824 kb
Host smart-986c3f8a-dcf1-4ddc-b0d5-72f72e3b2894
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257095406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.1257095406
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.909634246
Short name T906
Test name
Test status
Simulation time 19879277 ps
CPU time 0.71 seconds
Started Apr 25 12:34:35 PM PDT 24
Finished Apr 25 12:34:39 PM PDT 24
Peak memory 205644 kb
Host smart-b316bbd5-bdfb-468b-9a7a-2e8d57de338d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909634246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.909634246
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.2522607722
Short name T1042
Test name
Test status
Simulation time 11054890 ps
CPU time 0.73 seconds
Started Apr 25 12:34:33 PM PDT 24
Finished Apr 25 12:34:38 PM PDT 24
Peak memory 205800 kb
Host smart-3f22ca7e-6bc1-4f1e-9060-a3257dbe69d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522607722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.2522607722
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.2836413245
Short name T1024
Test name
Test status
Simulation time 72764374 ps
CPU time 4.02 seconds
Started Apr 25 12:34:10 PM PDT 24
Finished Apr 25 12:34:16 PM PDT 24
Peak memory 206036 kb
Host smart-5cc97d9f-38ec-467a-b6ab-91477987a29c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836413245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.2
836413245
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.3485610267
Short name T914
Test name
Test status
Simulation time 255357274 ps
CPU time 13.61 seconds
Started Apr 25 12:34:22 PM PDT 24
Finished Apr 25 12:34:38 PM PDT 24
Peak memory 206056 kb
Host smart-1afd130a-a2cd-4113-a701-debcf71a5f03
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485610267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.3
485610267
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.449168934
Short name T904
Test name
Test status
Simulation time 47218099 ps
CPU time 0.89 seconds
Started Apr 25 12:34:15 PM PDT 24
Finished Apr 25 12:34:18 PM PDT 24
Peak memory 205804 kb
Host smart-df02a26c-4f95-41a8-8413-4afc0cae195d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449168934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.449168934
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.1496934104
Short name T931
Test name
Test status
Simulation time 39958634 ps
CPU time 1.55 seconds
Started Apr 25 12:34:13 PM PDT 24
Finished Apr 25 12:34:16 PM PDT 24
Peak memory 214332 kb
Host smart-562dada1-993b-428d-90a0-a4a62972b59f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496934104 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.1496934104
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.1340946469
Short name T977
Test name
Test status
Simulation time 106558772 ps
CPU time 1.22 seconds
Started Apr 25 12:34:15 PM PDT 24
Finished Apr 25 12:34:17 PM PDT 24
Peak memory 205948 kb
Host smart-2a50fe36-e2d5-41f8-9e7e-636f6aa8fbf3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340946469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.1340946469
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.2507573960
Short name T901
Test name
Test status
Simulation time 42853389 ps
CPU time 0.9 seconds
Started Apr 25 12:34:13 PM PDT 24
Finished Apr 25 12:34:16 PM PDT 24
Peak memory 205696 kb
Host smart-073dbeae-a376-4fce-a8e5-94c5f3f7b7c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507573960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.2507573960
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2911239613
Short name T1060
Test name
Test status
Simulation time 126862991 ps
CPU time 2.77 seconds
Started Apr 25 12:34:16 PM PDT 24
Finished Apr 25 12:34:21 PM PDT 24
Peak memory 206124 kb
Host smart-c453db16-61e0-40a9-89ff-abe746d3cbd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911239613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.2911239613
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.2695265914
Short name T123
Test name
Test status
Simulation time 254786894 ps
CPU time 4.08 seconds
Started Apr 25 12:34:13 PM PDT 24
Finished Apr 25 12:34:19 PM PDT 24
Peak memory 214524 kb
Host smart-e0b10ff7-8992-49ad-9274-07f6c437d389
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695265914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.2695265914
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.4193426223
Short name T121
Test name
Test status
Simulation time 263842805 ps
CPU time 4.28 seconds
Started Apr 25 12:34:14 PM PDT 24
Finished Apr 25 12:34:20 PM PDT 24
Peak memory 220736 kb
Host smart-8653a111-062a-4993-8c0b-e43aa3e89c2b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193426223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.4193426223
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.3032116903
Short name T953
Test name
Test status
Simulation time 141169004 ps
CPU time 2.11 seconds
Started Apr 25 12:34:14 PM PDT 24
Finished Apr 25 12:34:17 PM PDT 24
Peak memory 217380 kb
Host smart-ce6bcc9e-54c8-46fe-819b-9f09a711295b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032116903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.3032116903
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.504066055
Short name T980
Test name
Test status
Simulation time 467338103 ps
CPU time 4.94 seconds
Started Apr 25 12:34:12 PM PDT 24
Finished Apr 25 12:34:19 PM PDT 24
Peak memory 214320 kb
Host smart-b90c6a9f-0f5f-4d30-a92f-243ad9a1e240
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504066055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err.
504066055
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.4033442980
Short name T963
Test name
Test status
Simulation time 12902872 ps
CPU time 0.73 seconds
Started Apr 25 12:34:33 PM PDT 24
Finished Apr 25 12:34:38 PM PDT 24
Peak memory 205768 kb
Host smart-31073a6d-1dc8-49b1-a02e-db6643a40e77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033442980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.4033442980
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.3002554806
Short name T1052
Test name
Test status
Simulation time 13093609 ps
CPU time 0.77 seconds
Started Apr 25 12:34:35 PM PDT 24
Finished Apr 25 12:34:39 PM PDT 24
Peak memory 205748 kb
Host smart-6f209b9f-3f2c-4b2c-9c4d-3fb293610857
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002554806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.3002554806
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.2722912530
Short name T957
Test name
Test status
Simulation time 11423875 ps
CPU time 0.73 seconds
Started Apr 25 12:34:35 PM PDT 24
Finished Apr 25 12:34:39 PM PDT 24
Peak memory 205704 kb
Host smart-06af0840-75ee-4dbb-823c-9113971004b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722912530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.2722912530
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.1429960211
Short name T927
Test name
Test status
Simulation time 24300114 ps
CPU time 0.75 seconds
Started Apr 25 12:34:33 PM PDT 24
Finished Apr 25 12:34:36 PM PDT 24
Peak memory 205760 kb
Host smart-40c2c287-61d9-4c84-8863-84a6a6846d4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429960211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.1429960211
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.583619383
Short name T938
Test name
Test status
Simulation time 34912902 ps
CPU time 0.76 seconds
Started Apr 25 12:34:34 PM PDT 24
Finished Apr 25 12:34:38 PM PDT 24
Peak memory 205700 kb
Host smart-97f35d9f-485c-499f-8a4e-5baba349caa5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583619383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.583619383
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.3351533448
Short name T941
Test name
Test status
Simulation time 16791481 ps
CPU time 0.74 seconds
Started Apr 25 12:34:33 PM PDT 24
Finished Apr 25 12:34:36 PM PDT 24
Peak memory 205732 kb
Host smart-0ac179c1-d868-4d62-865e-83215c0cdc17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351533448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.3351533448
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.3400626744
Short name T966
Test name
Test status
Simulation time 23370032 ps
CPU time 0.84 seconds
Started Apr 25 12:34:36 PM PDT 24
Finished Apr 25 12:34:41 PM PDT 24
Peak memory 205744 kb
Host smart-312614e3-c7f4-4836-a236-7bc45af43060
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400626744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.3400626744
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.2087386956
Short name T926
Test name
Test status
Simulation time 11757806 ps
CPU time 0.71 seconds
Started Apr 25 12:34:35 PM PDT 24
Finished Apr 25 12:34:40 PM PDT 24
Peak memory 205776 kb
Host smart-24ffad18-0d3e-4487-9b7a-266c967d8fb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087386956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.2087386956
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.3830987208
Short name T959
Test name
Test status
Simulation time 11719113 ps
CPU time 0.83 seconds
Started Apr 25 12:34:35 PM PDT 24
Finished Apr 25 12:34:39 PM PDT 24
Peak memory 205800 kb
Host smart-67e2e008-6ec5-43ee-ab48-bf53369820b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830987208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.3830987208
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.2881240442
Short name T1019
Test name
Test status
Simulation time 108386036 ps
CPU time 0.78 seconds
Started Apr 25 12:34:33 PM PDT 24
Finished Apr 25 12:34:36 PM PDT 24
Peak memory 205752 kb
Host smart-c053d250-152d-4353-b21d-1d5a67623077
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881240442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.2881240442
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.1689215141
Short name T979
Test name
Test status
Simulation time 110186039 ps
CPU time 1.2 seconds
Started Apr 25 12:34:14 PM PDT 24
Finished Apr 25 12:34:16 PM PDT 24
Peak memory 214336 kb
Host smart-1f97758b-d304-4e8f-ab04-65c84c522857
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689215141 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.1689215141
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.3900348388
Short name T1064
Test name
Test status
Simulation time 15404236 ps
CPU time 1.14 seconds
Started Apr 25 12:34:17 PM PDT 24
Finished Apr 25 12:34:19 PM PDT 24
Peak memory 206024 kb
Host smart-1842230c-b888-4ad3-9648-889cd411f19b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900348388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.3900348388
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.1273928553
Short name T944
Test name
Test status
Simulation time 14645987 ps
CPU time 0.71 seconds
Started Apr 25 12:34:17 PM PDT 24
Finished Apr 25 12:34:20 PM PDT 24
Peak memory 205768 kb
Host smart-911eb40c-3a87-4a76-a231-92b25fae5ad5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273928553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.1273928553
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.4276286604
Short name T1005
Test name
Test status
Simulation time 21196435 ps
CPU time 1.72 seconds
Started Apr 25 12:34:13 PM PDT 24
Finished Apr 25 12:34:17 PM PDT 24
Peak memory 214348 kb
Host smart-1360336a-9da7-45e7-9be3-c64e57f111fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276286604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.4276286604
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1546758320
Short name T996
Test name
Test status
Simulation time 392237540 ps
CPU time 6.79 seconds
Started Apr 25 12:34:17 PM PDT 24
Finished Apr 25 12:34:26 PM PDT 24
Peak memory 214580 kb
Host smart-b79bb2ec-0ebd-4b62-b7fa-bca505921a89
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546758320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.1546758320
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.1944662217
Short name T119
Test name
Test status
Simulation time 1007941031 ps
CPU time 6.34 seconds
Started Apr 25 12:34:12 PM PDT 24
Finished Apr 25 12:34:21 PM PDT 24
Peak memory 220260 kb
Host smart-5bfad495-5d08-4941-b3a2-349a06d7959b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944662217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.1944662217
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.1632512999
Short name T1044
Test name
Test status
Simulation time 119349912 ps
CPU time 3.08 seconds
Started Apr 25 12:34:11 PM PDT 24
Finished Apr 25 12:34:16 PM PDT 24
Peak memory 214208 kb
Host smart-9ae4694b-5d8d-4ccd-9180-8551410561dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632512999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.1632512999
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.2658715169
Short name T381
Test name
Test status
Simulation time 135755220 ps
CPU time 1.32 seconds
Started Apr 25 12:34:16 PM PDT 24
Finished Apr 25 12:34:19 PM PDT 24
Peak memory 214408 kb
Host smart-0f1d088e-28db-4750-a8bc-19fa1620bd8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658715169 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.2658715169
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.2154737162
Short name T136
Test name
Test status
Simulation time 44525070 ps
CPU time 0.93 seconds
Started Apr 25 12:34:17 PM PDT 24
Finished Apr 25 12:34:19 PM PDT 24
Peak memory 205788 kb
Host smart-18544bc0-df51-4af0-b15d-dba947c55ce3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154737162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.2154737162
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.3590640079
Short name T1006
Test name
Test status
Simulation time 36464212 ps
CPU time 0.86 seconds
Started Apr 25 12:34:16 PM PDT 24
Finished Apr 25 12:34:18 PM PDT 24
Peak memory 205744 kb
Host smart-d5f97a3e-92b7-4c9b-a4e5-f501c00a45e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590640079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.3590640079
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.274002978
Short name T969
Test name
Test status
Simulation time 206535633 ps
CPU time 2.13 seconds
Started Apr 25 12:34:13 PM PDT 24
Finished Apr 25 12:34:17 PM PDT 24
Peak memory 206184 kb
Host smart-f28ecb18-905c-4e75-a4d4-5463c81112d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274002978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sam
e_csr_outstanding.274002978
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.1293764988
Short name T1037
Test name
Test status
Simulation time 319744048 ps
CPU time 5.46 seconds
Started Apr 25 12:34:16 PM PDT 24
Finished Apr 25 12:34:23 PM PDT 24
Peak memory 214556 kb
Host smart-b9f1d63c-62d8-4026-a390-137974501252
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293764988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.1293764988
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.824381952
Short name T922
Test name
Test status
Simulation time 198669733 ps
CPU time 5.09 seconds
Started Apr 25 12:34:11 PM PDT 24
Finished Apr 25 12:34:18 PM PDT 24
Peak memory 214484 kb
Host smart-a7f8a74f-082e-4cdd-bba4-8f30814870a6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824381952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_shadow_reg_errors_with_csr_rw.824381952
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.1643439768
Short name T952
Test name
Test status
Simulation time 299232784 ps
CPU time 3.45 seconds
Started Apr 25 12:34:18 PM PDT 24
Finished Apr 25 12:34:23 PM PDT 24
Peak memory 214248 kb
Host smart-9178cb1a-f6ae-473f-b14b-d00df3b75435
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643439768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.1643439768
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2342460013
Short name T976
Test name
Test status
Simulation time 60130136 ps
CPU time 2.2 seconds
Started Apr 25 12:34:18 PM PDT 24
Finished Apr 25 12:34:22 PM PDT 24
Peak memory 214256 kb
Host smart-5ca90b2c-620e-4beb-8f09-6a778c826ad7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342460013 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.2342460013
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.3559237156
Short name T1048
Test name
Test status
Simulation time 14450583 ps
CPU time 0.91 seconds
Started Apr 25 12:34:20 PM PDT 24
Finished Apr 25 12:34:24 PM PDT 24
Peak memory 205728 kb
Host smart-f7dc4a0c-aaf4-4f2d-be09-aed5403d59f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559237156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.3559237156
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.1805886745
Short name T1008
Test name
Test status
Simulation time 34152213 ps
CPU time 0.68 seconds
Started Apr 25 12:34:24 PM PDT 24
Finished Apr 25 12:34:27 PM PDT 24
Peak memory 205756 kb
Host smart-12fbc366-8ddf-4ebe-8d52-d07ba50a35f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805886745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.1805886745
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2270162761
Short name T135
Test name
Test status
Simulation time 251615172 ps
CPU time 2.45 seconds
Started Apr 25 12:34:20 PM PDT 24
Finished Apr 25 12:34:24 PM PDT 24
Peak memory 206124 kb
Host smart-aee34ac6-3fc9-45f5-963e-ead01349cf76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270162761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.2270162761
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3976086945
Short name T1015
Test name
Test status
Simulation time 192512235 ps
CPU time 3.87 seconds
Started Apr 25 12:34:16 PM PDT 24
Finished Apr 25 12:34:22 PM PDT 24
Peak memory 214508 kb
Host smart-16840204-d00e-4ee1-a028-7c749619d9c7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976086945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.3976086945
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3581893739
Short name T981
Test name
Test status
Simulation time 77635715 ps
CPU time 3.36 seconds
Started Apr 25 12:34:12 PM PDT 24
Finished Apr 25 12:34:18 PM PDT 24
Peak memory 220632 kb
Host smart-1183b956-da1b-45f9-bcfe-518db36e8c03
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581893739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.3581893739
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.2438618889
Short name T1027
Test name
Test status
Simulation time 48319395 ps
CPU time 1.68 seconds
Started Apr 25 12:34:17 PM PDT 24
Finished Apr 25 12:34:20 PM PDT 24
Peak memory 214212 kb
Host smart-27c16eb9-a088-4984-b66e-ae64a3a3b894
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438618889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.2438618889
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1538984865
Short name T1003
Test name
Test status
Simulation time 51941505 ps
CPU time 2.22 seconds
Started Apr 25 12:34:22 PM PDT 24
Finished Apr 25 12:34:26 PM PDT 24
Peak memory 214356 kb
Host smart-80e2ea28-e1ba-4786-974f-0f074d5d8a0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538984865 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.1538984865
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.2158219207
Short name T1032
Test name
Test status
Simulation time 17787767 ps
CPU time 0.98 seconds
Started Apr 25 12:34:20 PM PDT 24
Finished Apr 25 12:34:23 PM PDT 24
Peak memory 206004 kb
Host smart-1281911b-832e-4cad-8424-037c875165c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158219207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.2158219207
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.2765402749
Short name T1011
Test name
Test status
Simulation time 13487581 ps
CPU time 0.83 seconds
Started Apr 25 12:34:21 PM PDT 24
Finished Apr 25 12:34:24 PM PDT 24
Peak memory 205796 kb
Host smart-708ccdee-8abb-4147-b17e-b50644d6130b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765402749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.2765402749
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.3924933771
Short name T1051
Test name
Test status
Simulation time 122864662 ps
CPU time 2.86 seconds
Started Apr 25 12:34:19 PM PDT 24
Finished Apr 25 12:34:24 PM PDT 24
Peak memory 206152 kb
Host smart-32ed2761-be06-407f-81a7-210f7cb7a04d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924933771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.3924933771
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.3162992002
Short name T118
Test name
Test status
Simulation time 268819537 ps
CPU time 3.31 seconds
Started Apr 25 12:34:24 PM PDT 24
Finished Apr 25 12:34:30 PM PDT 24
Peak memory 214392 kb
Host smart-197e5f9f-b39b-46c6-be07-1a47fdc5c974
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162992002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.3162992002
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.3682974686
Short name T948
Test name
Test status
Simulation time 464202005 ps
CPU time 2.94 seconds
Started Apr 25 12:34:19 PM PDT 24
Finished Apr 25 12:34:24 PM PDT 24
Peak memory 214296 kb
Host smart-f52fb40a-4302-42da-abd8-54f834573720
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682974686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.3682974686
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.94427745
Short name T160
Test name
Test status
Simulation time 1256732682 ps
CPU time 6.45 seconds
Started Apr 25 12:34:18 PM PDT 24
Finished Apr 25 12:34:26 PM PDT 24
Peak memory 214272 kb
Host smart-8874e5f0-0e16-4a18-8e53-2d538d222df9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94427745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err.94427745
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.411775420
Short name T939
Test name
Test status
Simulation time 20450244 ps
CPU time 1.25 seconds
Started Apr 25 12:34:23 PM PDT 24
Finished Apr 25 12:34:27 PM PDT 24
Peak memory 206100 kb
Host smart-47465779-f267-4b5a-9574-8c0de266ef80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411775420 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.411775420
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.2129832929
Short name T171
Test name
Test status
Simulation time 150694828 ps
CPU time 1.16 seconds
Started Apr 25 12:34:24 PM PDT 24
Finished Apr 25 12:34:28 PM PDT 24
Peak memory 205948 kb
Host smart-c8d87783-d7e0-46cf-8186-088b323b8929
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129832929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.2129832929
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.4198556969
Short name T956
Test name
Test status
Simulation time 10737145 ps
CPU time 0.82 seconds
Started Apr 25 12:34:24 PM PDT 24
Finished Apr 25 12:34:27 PM PDT 24
Peak memory 205676 kb
Host smart-7a06dd65-402f-42b4-ac48-be84a5dea45a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198556969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.4198556969
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.4189835831
Short name T140
Test name
Test status
Simulation time 160468920 ps
CPU time 3.69 seconds
Started Apr 25 12:34:22 PM PDT 24
Finished Apr 25 12:34:28 PM PDT 24
Peak memory 206124 kb
Host smart-f3099625-d81b-4bc6-a84f-834955653cbf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189835831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.4189835831
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.180470804
Short name T987
Test name
Test status
Simulation time 1143723389 ps
CPU time 24.89 seconds
Started Apr 25 12:34:19 PM PDT 24
Finished Apr 25 12:34:46 PM PDT 24
Peak memory 216784 kb
Host smart-e86e362c-ed31-4dcc-80db-2e683ad6a335
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180470804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow
_reg_errors.180470804
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.535682450
Short name T1069
Test name
Test status
Simulation time 392469570 ps
CPU time 5.15 seconds
Started Apr 25 12:34:19 PM PDT 24
Finished Apr 25 12:34:26 PM PDT 24
Peak memory 220572 kb
Host smart-8f920844-1971-4be5-ba97-21205a3f66f0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535682450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.k
eymgr_shadow_reg_errors_with_csr_rw.535682450
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.2584293767
Short name T1039
Test name
Test status
Simulation time 1243851125 ps
CPU time 4.12 seconds
Started Apr 25 12:34:21 PM PDT 24
Finished Apr 25 12:34:28 PM PDT 24
Peak memory 214200 kb
Host smart-92f305b1-6946-4afc-845c-3e4e2b98a1e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584293767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.2584293767
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.1711360760
Short name T870
Test name
Test status
Simulation time 20443512 ps
CPU time 0.84 seconds
Started Apr 25 12:52:44 PM PDT 24
Finished Apr 25 12:52:47 PM PDT 24
Peak memory 205708 kb
Host smart-9cae3d11-e6e6-42fa-8849-62d3879cbe1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711360760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.1711360760
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.4068425432
Short name T723
Test name
Test status
Simulation time 716881780 ps
CPU time 3.3 seconds
Started Apr 25 12:52:41 PM PDT 24
Finished Apr 25 12:52:47 PM PDT 24
Peak memory 214132 kb
Host smart-62c814de-1dd7-43f7-860f-0543269116af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4068425432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.4068425432
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.2899199220
Short name T802
Test name
Test status
Simulation time 152195626 ps
CPU time 2.28 seconds
Started Apr 25 12:52:35 PM PDT 24
Finished Apr 25 12:52:38 PM PDT 24
Peak memory 217056 kb
Host smart-4863f6c4-516b-48a2-b538-eabe5801a501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899199220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.2899199220
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.1441880409
Short name T470
Test name
Test status
Simulation time 296942234 ps
CPU time 1.77 seconds
Started Apr 25 12:52:50 PM PDT 24
Finished Apr 25 12:52:53 PM PDT 24
Peak memory 207056 kb
Host smart-8249234b-3607-4a09-b48b-dd705d61b49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441880409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.1441880409
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.1031426945
Short name T239
Test name
Test status
Simulation time 418048389 ps
CPU time 12.35 seconds
Started Apr 25 12:52:42 PM PDT 24
Finished Apr 25 12:52:57 PM PDT 24
Peak memory 222160 kb
Host smart-fa1e3e95-1912-409c-99fa-56a30676b335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031426945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.1031426945
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.2654903787
Short name T734
Test name
Test status
Simulation time 68788802 ps
CPU time 3.66 seconds
Started Apr 25 12:52:44 PM PDT 24
Finished Apr 25 12:52:50 PM PDT 24
Peak memory 215732 kb
Host smart-96b1e464-b8a8-4d43-932a-5ed9be86d29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654903787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.2654903787
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.3774792644
Short name T722
Test name
Test status
Simulation time 82247825 ps
CPU time 3.73 seconds
Started Apr 25 12:52:50 PM PDT 24
Finished Apr 25 12:52:56 PM PDT 24
Peak memory 207428 kb
Host smart-41db642d-b304-4ca2-86bf-0d8074e21d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774792644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.3774792644
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.2935047909
Short name T103
Test name
Test status
Simulation time 3506529160 ps
CPU time 41.28 seconds
Started Apr 25 12:52:42 PM PDT 24
Finished Apr 25 12:53:25 PM PDT 24
Peak memory 243844 kb
Host smart-e74bfc4b-7ab3-4063-b50e-f57dedb81978
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935047909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.2935047909
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.1645736339
Short name T84
Test name
Test status
Simulation time 520107430 ps
CPU time 4.38 seconds
Started Apr 25 12:52:38 PM PDT 24
Finished Apr 25 12:52:44 PM PDT 24
Peak memory 206436 kb
Host smart-af4a02da-7bff-4468-b1a5-ec77b2a506d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645736339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.1645736339
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.1695406472
Short name T180
Test name
Test status
Simulation time 786487245 ps
CPU time 6.17 seconds
Started Apr 25 12:52:45 PM PDT 24
Finished Apr 25 12:52:52 PM PDT 24
Peak memory 208472 kb
Host smart-5ab0443b-0a62-4b30-a8b2-287618965c7d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695406472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.1695406472
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.2468876298
Short name T877
Test name
Test status
Simulation time 508415712 ps
CPU time 3.38 seconds
Started Apr 25 12:52:40 PM PDT 24
Finished Apr 25 12:52:45 PM PDT 24
Peak memory 206596 kb
Host smart-65a26aee-9422-4b61-8840-8276d58437bd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468876298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.2468876298
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.2221790431
Short name T424
Test name
Test status
Simulation time 12956775898 ps
CPU time 27.69 seconds
Started Apr 25 12:52:55 PM PDT 24
Finished Apr 25 12:53:24 PM PDT 24
Peak memory 207960 kb
Host smart-f9da7f57-900e-4f62-a3f6-d58043db9d6d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221790431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.2221790431
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.1317039986
Short name T553
Test name
Test status
Simulation time 48205927 ps
CPU time 2.31 seconds
Started Apr 25 12:52:42 PM PDT 24
Finished Apr 25 12:52:46 PM PDT 24
Peak memory 208484 kb
Host smart-1caa98f5-7b44-44bd-aab4-922a562853d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317039986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.1317039986
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.1200950695
Short name T805
Test name
Test status
Simulation time 56065862 ps
CPU time 2.8 seconds
Started Apr 25 12:52:46 PM PDT 24
Finished Apr 25 12:52:51 PM PDT 24
Peak memory 208036 kb
Host smart-3a1d24d7-f9c2-4427-ae7c-0dec503639a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200950695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.1200950695
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.4200442774
Short name T679
Test name
Test status
Simulation time 1422334305 ps
CPU time 25.26 seconds
Started Apr 25 12:52:50 PM PDT 24
Finished Apr 25 12:53:17 PM PDT 24
Peak memory 215744 kb
Host smart-54ea6685-6b97-4125-b578-7ea36e392cea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200442774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.4200442774
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.359348093
Short name T492
Test name
Test status
Simulation time 80888009 ps
CPU time 3.73 seconds
Started Apr 25 12:52:38 PM PDT 24
Finished Apr 25 12:52:44 PM PDT 24
Peak memory 207424 kb
Host smart-4c7446c0-bb68-46a3-8caa-1c35db8da233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359348093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.359348093
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.3525378591
Short name T655
Test name
Test status
Simulation time 59646158 ps
CPU time 2.45 seconds
Started Apr 25 12:52:50 PM PDT 24
Finished Apr 25 12:52:54 PM PDT 24
Peak memory 209824 kb
Host smart-48900265-550c-42ab-ba0d-41b0f6fb530f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525378591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.3525378591
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.2984031499
Short name T725
Test name
Test status
Simulation time 1524035853 ps
CPU time 66.65 seconds
Started Apr 25 12:52:45 PM PDT 24
Finished Apr 25 12:53:53 PM PDT 24
Peak memory 222528 kb
Host smart-5d2b7fb9-c102-48da-9eb7-b93aeb9d6c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984031499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.2984031499
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.3654426862
Short name T876
Test name
Test status
Simulation time 606644522 ps
CPU time 13.77 seconds
Started Apr 25 12:52:44 PM PDT 24
Finished Apr 25 12:53:00 PM PDT 24
Peak memory 208612 kb
Host smart-88e529c1-ed05-49e2-8889-704559f5c645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654426862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.3654426862
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.844227549
Short name T700
Test name
Test status
Simulation time 529768774 ps
CPU time 4.75 seconds
Started Apr 25 12:52:48 PM PDT 24
Finished Apr 25 12:52:54 PM PDT 24
Peak memory 214048 kb
Host smart-c8139f69-7dfa-4024-8297-f83f8fa0e4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844227549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.844227549
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.1009177826
Short name T257
Test name
Test status
Simulation time 1149959424 ps
CPU time 14.42 seconds
Started Apr 25 12:52:44 PM PDT 24
Finished Apr 25 12:53:00 PM PDT 24
Peak memory 210668 kb
Host smart-778f71d5-6be1-4d54-83de-c81002cf7e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009177826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.1009177826
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.2472312932
Short name T874
Test name
Test status
Simulation time 119305729 ps
CPU time 4.03 seconds
Started Apr 25 12:52:43 PM PDT 24
Finished Apr 25 12:52:48 PM PDT 24
Peak memory 218756 kb
Host smart-ff7c1401-a69c-4688-a2bf-e7aa2eaba91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472312932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.2472312932
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.369518750
Short name T13
Test name
Test status
Simulation time 326226809 ps
CPU time 10.51 seconds
Started Apr 25 12:52:39 PM PDT 24
Finished Apr 25 12:52:52 PM PDT 24
Peak memory 229212 kb
Host smart-36728288-2d4e-4cf5-a94d-1e493237ecee
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369518750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.369518750
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.1109871708
Short name T485
Test name
Test status
Simulation time 358998717 ps
CPU time 4.91 seconds
Started Apr 25 12:52:44 PM PDT 24
Finished Apr 25 12:52:50 PM PDT 24
Peak memory 206460 kb
Host smart-7aa61164-3249-4034-bcdc-58d9c643103b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109871708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.1109871708
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.4259078985
Short name T449
Test name
Test status
Simulation time 1414517598 ps
CPU time 39.2 seconds
Started Apr 25 12:52:39 PM PDT 24
Finished Apr 25 12:53:20 PM PDT 24
Peak memory 207680 kb
Host smart-241c5356-fffd-4122-b7de-50eff1fa3e9c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259078985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.4259078985
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.2390687099
Short name T845
Test name
Test status
Simulation time 127128406 ps
CPU time 2.44 seconds
Started Apr 25 12:52:45 PM PDT 24
Finished Apr 25 12:52:49 PM PDT 24
Peak memory 208468 kb
Host smart-dda3faee-379c-4c53-899a-1cffc66a899f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390687099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.2390687099
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.201263490
Short name T743
Test name
Test status
Simulation time 367866202 ps
CPU time 3.46 seconds
Started Apr 25 12:52:49 PM PDT 24
Finished Apr 25 12:52:54 PM PDT 24
Peak memory 208236 kb
Host smart-4a2003d8-ab9e-433b-9e75-a79c9334f598
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201263490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.201263490
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.4149385986
Short name T478
Test name
Test status
Simulation time 122916503 ps
CPU time 2.83 seconds
Started Apr 25 12:52:53 PM PDT 24
Finished Apr 25 12:52:57 PM PDT 24
Peak memory 206768 kb
Host smart-fc5cbf06-1725-493d-bb63-6949a0bbb793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149385986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.4149385986
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.2926763651
Short name T621
Test name
Test status
Simulation time 882928954 ps
CPU time 3.65 seconds
Started Apr 25 12:52:50 PM PDT 24
Finished Apr 25 12:52:55 PM PDT 24
Peak memory 206364 kb
Host smart-002f0fe8-cb37-47ca-a278-d0996722e88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926763651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.2926763651
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.3726802573
Short name T223
Test name
Test status
Simulation time 2016272244 ps
CPU time 20.94 seconds
Started Apr 25 12:52:34 PM PDT 24
Finished Apr 25 12:52:56 PM PDT 24
Peak memory 214908 kb
Host smart-8e612d89-6d19-4042-afa1-23c29c170b0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726802573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.3726802573
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.2221451891
Short name T894
Test name
Test status
Simulation time 1120064660 ps
CPU time 8.7 seconds
Started Apr 25 12:52:42 PM PDT 24
Finished Apr 25 12:52:52 PM PDT 24
Peak memory 214036 kb
Host smart-4f819366-773b-414d-9e69-9c10840f686e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221451891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.2221451891
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.1756410716
Short name T830
Test name
Test status
Simulation time 85346205 ps
CPU time 3.4 seconds
Started Apr 25 12:52:59 PM PDT 24
Finished Apr 25 12:53:03 PM PDT 24
Peak memory 209752 kb
Host smart-d63e31f0-0961-4e12-a9e0-aa9ad60e4d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756410716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.1756410716
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.3565089248
Short name T645
Test name
Test status
Simulation time 46279880 ps
CPU time 0.83 seconds
Started Apr 25 12:53:08 PM PDT 24
Finished Apr 25 12:53:12 PM PDT 24
Peak memory 205704 kb
Host smart-85b7cf9d-e51f-4695-8713-3f20ce990f34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565089248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.3565089248
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.3766636943
Short name T365
Test name
Test status
Simulation time 3498451317 ps
CPU time 93.2 seconds
Started Apr 25 12:53:28 PM PDT 24
Finished Apr 25 12:55:04 PM PDT 24
Peak memory 215720 kb
Host smart-27575563-a1d3-4f8a-a362-6c77b92d2544
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3766636943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.3766636943
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.3533266125
Short name T648
Test name
Test status
Simulation time 362957719 ps
CPU time 5.88 seconds
Started Apr 25 12:53:11 PM PDT 24
Finished Apr 25 12:53:20 PM PDT 24
Peak memory 209764 kb
Host smart-8a57dc80-d418-4fb8-bb04-a21934e16590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533266125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.3533266125
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.962543580
Short name T668
Test name
Test status
Simulation time 733312019 ps
CPU time 5.07 seconds
Started Apr 25 12:53:11 PM PDT 24
Finished Apr 25 12:53:19 PM PDT 24
Peak memory 213996 kb
Host smart-b33c1c62-4907-4670-ac92-aa9dc43749d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962543580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.962543580
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.3023280472
Short name T817
Test name
Test status
Simulation time 1116201858 ps
CPU time 19.08 seconds
Started Apr 25 12:53:05 PM PDT 24
Finished Apr 25 12:53:26 PM PDT 24
Peak memory 209700 kb
Host smart-57820d4a-5195-43b3-94c4-7ebe1b535a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023280472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.3023280472
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_random.3615796543
Short name T799
Test name
Test status
Simulation time 151963070 ps
CPU time 5.69 seconds
Started Apr 25 12:53:05 PM PDT 24
Finished Apr 25 12:53:12 PM PDT 24
Peak memory 207824 kb
Host smart-0b3b88b9-0d92-4cc7-a426-b826e4e79748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615796543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.3615796543
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.519856781
Short name T274
Test name
Test status
Simulation time 117792758 ps
CPU time 4.62 seconds
Started Apr 25 12:53:07 PM PDT 24
Finished Apr 25 12:53:16 PM PDT 24
Peak memory 208168 kb
Host smart-aec95164-756e-4bc4-bb0c-98043b5d4b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519856781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.519856781
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.4282304480
Short name T808
Test name
Test status
Simulation time 283708911 ps
CPU time 5.75 seconds
Started Apr 25 12:53:07 PM PDT 24
Finished Apr 25 12:53:16 PM PDT 24
Peak memory 208192 kb
Host smart-652636c1-025c-4803-99e9-b80b0a5d7f04
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282304480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.4282304480
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.957143338
Short name T454
Test name
Test status
Simulation time 54886437 ps
CPU time 2.9 seconds
Started Apr 25 12:53:18 PM PDT 24
Finished Apr 25 12:53:23 PM PDT 24
Peak memory 206544 kb
Host smart-94b57e85-ab2c-4df6-8465-d292254941e3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957143338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.957143338
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.2858723503
Short name T279
Test name
Test status
Simulation time 39656781 ps
CPU time 2.67 seconds
Started Apr 25 12:53:06 PM PDT 24
Finished Apr 25 12:53:12 PM PDT 24
Peak memory 208516 kb
Host smart-8b87c00a-fa0a-4dbd-b494-c6ab33ea70dd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858723503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.2858723503
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.1631538289
Short name T657
Test name
Test status
Simulation time 282337311 ps
CPU time 3.89 seconds
Started Apr 25 12:53:13 PM PDT 24
Finished Apr 25 12:53:20 PM PDT 24
Peak memory 207860 kb
Host smart-e54a2dff-7298-4568-9fb8-1c6038134557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631538289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.1631538289
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.2185555569
Short name T388
Test name
Test status
Simulation time 161888168 ps
CPU time 2.86 seconds
Started Apr 25 12:53:21 PM PDT 24
Finished Apr 25 12:53:25 PM PDT 24
Peak memory 208208 kb
Host smart-f10a34c7-ca60-48e2-a55a-00c7711dd02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185555569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.2185555569
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.2875130362
Short name T242
Test name
Test status
Simulation time 153239584 ps
CPU time 4.76 seconds
Started Apr 25 12:53:08 PM PDT 24
Finished Apr 25 12:53:16 PM PDT 24
Peak memory 214032 kb
Host smart-13c6afbf-c546-4380-af5f-1a37cb2cb808
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875130362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.2875130362
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.345355418
Short name T659
Test name
Test status
Simulation time 218148298 ps
CPU time 8.61 seconds
Started Apr 25 12:53:02 PM PDT 24
Finished Apr 25 12:53:12 PM PDT 24
Peak memory 219460 kb
Host smart-25ebf6fb-f60d-431b-99ed-3a71ccd1a54c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345355418 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.345355418
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.4248664188
Short name T519
Test name
Test status
Simulation time 2577704497 ps
CPU time 80.46 seconds
Started Apr 25 12:53:07 PM PDT 24
Finished Apr 25 12:54:31 PM PDT 24
Peak memory 222324 kb
Host smart-2c5ac2f2-6d74-480c-bc86-1756a50329fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248664188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.4248664188
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.371468318
Short name T432
Test name
Test status
Simulation time 40364881 ps
CPU time 0.84 seconds
Started Apr 25 12:53:11 PM PDT 24
Finished Apr 25 12:53:15 PM PDT 24
Peak memory 205704 kb
Host smart-de3e91be-4de0-4193-a577-2eecba9dc831
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371468318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.371468318
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.2924084127
Short name T384
Test name
Test status
Simulation time 84709406 ps
CPU time 3.68 seconds
Started Apr 25 12:53:28 PM PDT 24
Finished Apr 25 12:53:35 PM PDT 24
Peak memory 215180 kb
Host smart-f58b75ef-73bd-4441-bbf9-890f8a407201
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2924084127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.2924084127
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.4247627191
Short name T20
Test name
Test status
Simulation time 84528254 ps
CPU time 2.74 seconds
Started Apr 25 12:53:08 PM PDT 24
Finished Apr 25 12:53:14 PM PDT 24
Peak memory 210140 kb
Host smart-7aa50900-13a0-49b9-bfc2-37b1c69c32ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247627191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.4247627191
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.3266575423
Short name T321
Test name
Test status
Simulation time 2424429667 ps
CPU time 29.15 seconds
Started Apr 25 12:53:11 PM PDT 24
Finished Apr 25 12:53:43 PM PDT 24
Peak memory 214116 kb
Host smart-81afacfa-c0b1-4459-84aa-6697449bdb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266575423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.3266575423
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.4192878588
Short name T91
Test name
Test status
Simulation time 1304730196 ps
CPU time 13.16 seconds
Started Apr 25 12:53:12 PM PDT 24
Finished Apr 25 12:53:29 PM PDT 24
Peak memory 214140 kb
Host smart-42ee74b6-b171-4b86-8aac-830b50353935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192878588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.4192878588
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.1415517297
Short name T203
Test name
Test status
Simulation time 59273586 ps
CPU time 1.56 seconds
Started Apr 25 12:53:15 PM PDT 24
Finished Apr 25 12:53:20 PM PDT 24
Peak memory 205952 kb
Host smart-0d45a231-9ae0-4521-ac89-04340d52c4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415517297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.1415517297
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.3874433038
Short name T401
Test name
Test status
Simulation time 8600784457 ps
CPU time 53.04 seconds
Started Apr 25 12:53:05 PM PDT 24
Finished Apr 25 12:54:01 PM PDT 24
Peak memory 218176 kb
Host smart-71c4782f-ddb0-437c-bdc8-9dbe0954fc3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874433038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.3874433038
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.3624404478
Short name T665
Test name
Test status
Simulation time 754067958 ps
CPU time 8.07 seconds
Started Apr 25 12:53:08 PM PDT 24
Finished Apr 25 12:53:19 PM PDT 24
Peak memory 208180 kb
Host smart-c8ef99f9-38aa-4d84-9f4b-6476c5451c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624404478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.3624404478
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.614022638
Short name T393
Test name
Test status
Simulation time 1133567701 ps
CPU time 2.88 seconds
Started Apr 25 12:53:06 PM PDT 24
Finished Apr 25 12:53:11 PM PDT 24
Peak memory 206524 kb
Host smart-9fcce19d-8ddc-4b64-ab06-149e9951bc95
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614022638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.614022638
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.3367536449
Short name T323
Test name
Test status
Simulation time 206374822 ps
CPU time 5.83 seconds
Started Apr 25 12:53:02 PM PDT 24
Finished Apr 25 12:53:09 PM PDT 24
Peak memory 208388 kb
Host smart-61ff5927-90b0-4aa5-a784-5f82a6357818
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367536449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.3367536449
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.759501331
Short name T499
Test name
Test status
Simulation time 351340487 ps
CPU time 6.63 seconds
Started Apr 25 12:53:04 PM PDT 24
Finished Apr 25 12:53:13 PM PDT 24
Peak memory 208008 kb
Host smart-877c4d0c-6e72-4999-acbe-64b376193c18
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759501331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.759501331
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.1738201969
Short name T358
Test name
Test status
Simulation time 384435186 ps
CPU time 2.86 seconds
Started Apr 25 12:53:11 PM PDT 24
Finished Apr 25 12:53:17 PM PDT 24
Peak memory 208884 kb
Host smart-ce52bbab-5ec3-4332-b371-6eafb3340c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738201969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.1738201969
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.59025540
Short name T842
Test name
Test status
Simulation time 96562425 ps
CPU time 3.37 seconds
Started Apr 25 12:53:05 PM PDT 24
Finished Apr 25 12:53:11 PM PDT 24
Peak memory 208484 kb
Host smart-59372024-1b6e-454d-bfd4-812c032e66f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59025540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.59025540
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.3391781454
Short name T8
Test name
Test status
Simulation time 247837706 ps
CPU time 11.87 seconds
Started Apr 25 12:53:07 PM PDT 24
Finished Apr 25 12:53:22 PM PDT 24
Peak memory 215516 kb
Host smart-2aed12b5-a2a1-472f-a289-8ec72508a5b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391781454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.3391781454
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.3701146547
Short name T17
Test name
Test status
Simulation time 391989511 ps
CPU time 3.92 seconds
Started Apr 25 12:53:14 PM PDT 24
Finished Apr 25 12:53:21 PM PDT 24
Peak memory 214124 kb
Host smart-f0031def-5fcf-467d-9019-3ca6e78c847a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701146547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.3701146547
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.1471202839
Short name T175
Test name
Test status
Simulation time 1140873555 ps
CPU time 19.32 seconds
Started Apr 25 12:53:07 PM PDT 24
Finished Apr 25 12:53:30 PM PDT 24
Peak memory 222332 kb
Host smart-50a4de63-b04b-4280-9c88-613f77f21438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471202839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.1471202839
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.733274682
Short name T661
Test name
Test status
Simulation time 39007411 ps
CPU time 0.87 seconds
Started Apr 25 12:53:15 PM PDT 24
Finished Apr 25 12:53:19 PM PDT 24
Peak memory 205580 kb
Host smart-2185cd7e-3064-48ba-88ac-c5da04326a22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733274682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.733274682
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.927053111
Short name T142
Test name
Test status
Simulation time 302154329 ps
CPU time 8.31 seconds
Started Apr 25 12:53:13 PM PDT 24
Finished Apr 25 12:53:25 PM PDT 24
Peak memory 214196 kb
Host smart-d7c366fa-c01d-4e75-8945-a74be9a07987
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=927053111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.927053111
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.2615156706
Short name T10
Test name
Test status
Simulation time 375533027 ps
CPU time 2.71 seconds
Started Apr 25 12:53:13 PM PDT 24
Finished Apr 25 12:53:19 PM PDT 24
Peak memory 214408 kb
Host smart-fc7f718d-ac2b-4a51-a5b3-98859142bff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615156706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.2615156706
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.1606354671
Short name T396
Test name
Test status
Simulation time 119612426 ps
CPU time 3.38 seconds
Started Apr 25 12:53:15 PM PDT 24
Finished Apr 25 12:53:25 PM PDT 24
Peak memory 209864 kb
Host smart-5564895a-cc75-4bfe-8aac-33251b682b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606354671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.1606354671
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.433904816
Short name T294
Test name
Test status
Simulation time 54600070 ps
CPU time 2.56 seconds
Started Apr 25 12:53:09 PM PDT 24
Finished Apr 25 12:53:15 PM PDT 24
Peak memory 209024 kb
Host smart-cd285bb5-a93d-43f6-bdeb-2e24d63ec372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433904816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.433904816
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.1688141281
Short name T67
Test name
Test status
Simulation time 335125612 ps
CPU time 4.33 seconds
Started Apr 25 12:53:17 PM PDT 24
Finished Apr 25 12:53:23 PM PDT 24
Peak memory 208880 kb
Host smart-f6c21a54-c3d2-446b-9695-d213004429e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688141281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.1688141281
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.488628974
Short name T474
Test name
Test status
Simulation time 6348054142 ps
CPU time 17.77 seconds
Started Apr 25 12:53:35 PM PDT 24
Finished Apr 25 12:53:55 PM PDT 24
Peak memory 222316 kb
Host smart-ae9014a7-6ace-4c3a-beca-e72cd9493a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488628974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.488628974
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.803660764
Short name T548
Test name
Test status
Simulation time 188010054 ps
CPU time 4.07 seconds
Started Apr 25 12:53:27 PM PDT 24
Finished Apr 25 12:53:35 PM PDT 24
Peak memory 208132 kb
Host smart-043624e7-d390-453c-b402-ab8fbbdda436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803660764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.803660764
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.2415004437
Short name T332
Test name
Test status
Simulation time 78920222 ps
CPU time 3.83 seconds
Started Apr 25 12:53:28 PM PDT 24
Finished Apr 25 12:53:35 PM PDT 24
Peak memory 208344 kb
Host smart-dcfaab07-e642-4512-bbf8-33a1142660e9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415004437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.2415004437
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.1014826541
Short name T608
Test name
Test status
Simulation time 695737641 ps
CPU time 15.78 seconds
Started Apr 25 12:53:16 PM PDT 24
Finished Apr 25 12:53:34 PM PDT 24
Peak memory 207528 kb
Host smart-2a1eeec1-e097-48e2-ac18-7c4a7fa66386
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014826541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.1014826541
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.186929400
Short name T397
Test name
Test status
Simulation time 12951018203 ps
CPU time 44.33 seconds
Started Apr 25 12:53:06 PM PDT 24
Finished Apr 25 12:53:54 PM PDT 24
Peak memory 208624 kb
Host smart-77eea5f6-854c-48c7-bf34-8f4b43dab8c0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186929400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.186929400
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.3104135191
Short name T578
Test name
Test status
Simulation time 370828556 ps
CPU time 9.21 seconds
Started Apr 25 12:53:23 PM PDT 24
Finished Apr 25 12:53:34 PM PDT 24
Peak memory 209640 kb
Host smart-e16b54bc-c4a3-4d6f-a793-0c9c1977c38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104135191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.3104135191
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.399513281
Short name T891
Test name
Test status
Simulation time 54857791 ps
CPU time 2.71 seconds
Started Apr 25 12:53:20 PM PDT 24
Finished Apr 25 12:53:24 PM PDT 24
Peak memory 207832 kb
Host smart-dfbafd08-da5d-4eed-aed2-a6d190cd2bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399513281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.399513281
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.626895312
Short name T126
Test name
Test status
Simulation time 764641847 ps
CPU time 16.47 seconds
Started Apr 25 12:53:13 PM PDT 24
Finished Apr 25 12:53:32 PM PDT 24
Peak memory 222376 kb
Host smart-e8b794ac-eac2-4c04-9c12-e7b4d8cd70dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626895312 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.626895312
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.1903044435
Short name T299
Test name
Test status
Simulation time 127624307 ps
CPU time 4.28 seconds
Started Apr 25 12:53:23 PM PDT 24
Finished Apr 25 12:53:28 PM PDT 24
Peak memory 214192 kb
Host smart-963774a6-d4ce-46f7-a2b4-8adeb99d5952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903044435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.1903044435
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.1201621551
Short name T540
Test name
Test status
Simulation time 45209734 ps
CPU time 0.9 seconds
Started Apr 25 12:53:16 PM PDT 24
Finished Apr 25 12:53:19 PM PDT 24
Peak memory 205636 kb
Host smart-e4e99c40-afb0-4b78-a426-4725cf0e879f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201621551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.1201621551
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.3885000573
Short name T386
Test name
Test status
Simulation time 33240221 ps
CPU time 2.4 seconds
Started Apr 25 12:53:19 PM PDT 24
Finished Apr 25 12:53:23 PM PDT 24
Peak memory 213988 kb
Host smart-621fe0fc-1db6-4ac2-b2c3-538683bac0ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3885000573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.3885000573
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.4247944730
Short name T886
Test name
Test status
Simulation time 142236502 ps
CPU time 3.51 seconds
Started Apr 25 12:53:15 PM PDT 24
Finished Apr 25 12:53:21 PM PDT 24
Peak memory 214328 kb
Host smart-739f2d5d-28fa-4e4d-ad7b-2dcae9fc6fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247944730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.4247944730
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.3114440331
Short name T860
Test name
Test status
Simulation time 86976981 ps
CPU time 1.69 seconds
Started Apr 25 12:53:34 PM PDT 24
Finished Apr 25 12:53:38 PM PDT 24
Peak memory 205932 kb
Host smart-1bd5de45-42fb-46e2-855c-e618b0b3e0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114440331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.3114440331
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.1812843074
Short name T28
Test name
Test status
Simulation time 1161711618 ps
CPU time 5.18 seconds
Started Apr 25 12:53:33 PM PDT 24
Finished Apr 25 12:53:40 PM PDT 24
Peak memory 214092 kb
Host smart-24d16fc6-6094-4c7f-b452-2adeb797ce15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812843074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.1812843074
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_random.2025977682
Short name T765
Test name
Test status
Simulation time 69609816 ps
CPU time 3.41 seconds
Started Apr 25 12:53:13 PM PDT 24
Finished Apr 25 12:53:19 PM PDT 24
Peak memory 209160 kb
Host smart-743942cf-18c3-4017-b94e-f388d65bc720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025977682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.2025977682
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.1689657855
Short name T729
Test name
Test status
Simulation time 314280902 ps
CPU time 3.25 seconds
Started Apr 25 12:53:30 PM PDT 24
Finished Apr 25 12:53:36 PM PDT 24
Peak memory 208316 kb
Host smart-b0a68126-9002-407c-8d69-814b04edcb82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689657855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.1689657855
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.2594219830
Short name T508
Test name
Test status
Simulation time 172337283 ps
CPU time 2.8 seconds
Started Apr 25 12:53:10 PM PDT 24
Finished Apr 25 12:53:16 PM PDT 24
Peak memory 206508 kb
Host smart-d012d293-9458-4fa2-8fee-4c6ce1e3eeb3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594219830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.2594219830
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.1515178959
Short name T200
Test name
Test status
Simulation time 98695388 ps
CPU time 4.26 seconds
Started Apr 25 12:53:21 PM PDT 24
Finished Apr 25 12:53:26 PM PDT 24
Peak memory 208272 kb
Host smart-747fe25e-1e32-488e-996f-d7cb6978e2ba
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515178959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.1515178959
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.3998892251
Short name T786
Test name
Test status
Simulation time 133283091 ps
CPU time 3.63 seconds
Started Apr 25 12:53:21 PM PDT 24
Finished Apr 25 12:53:33 PM PDT 24
Peak memory 206568 kb
Host smart-25d16e7e-6034-4811-b9ed-7ae5c7361215
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998892251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.3998892251
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.2757390316
Short name T196
Test name
Test status
Simulation time 74490802 ps
CPU time 1.67 seconds
Started Apr 25 12:53:25 PM PDT 24
Finished Apr 25 12:53:29 PM PDT 24
Peak memory 214100 kb
Host smart-2c58cc7b-c937-455e-b540-e177a0e7934e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757390316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.2757390316
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.4009089828
Short name T430
Test name
Test status
Simulation time 3275449293 ps
CPU time 21.03 seconds
Started Apr 25 12:53:26 PM PDT 24
Finished Apr 25 12:53:50 PM PDT 24
Peak memory 207604 kb
Host smart-83a87869-0ea1-4117-9cb3-c179ec798c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009089828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.4009089828
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.1836024739
Short name T168
Test name
Test status
Simulation time 295051778 ps
CPU time 11.62 seconds
Started Apr 25 12:53:23 PM PDT 24
Finished Apr 25 12:53:36 PM PDT 24
Peak memory 219164 kb
Host smart-02334c06-2caf-444d-9baf-8f144faefa30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836024739 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.1836024739
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.1325880562
Short name T684
Test name
Test status
Simulation time 2442493646 ps
CPU time 79.08 seconds
Started Apr 25 12:53:25 PM PDT 24
Finished Apr 25 12:54:47 PM PDT 24
Peak memory 208104 kb
Host smart-b2a6fb65-59c9-4c4c-9f99-0f27018064db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325880562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.1325880562
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.3511510728
Short name T576
Test name
Test status
Simulation time 131678447 ps
CPU time 3.25 seconds
Started Apr 25 12:53:18 PM PDT 24
Finished Apr 25 12:53:23 PM PDT 24
Peak memory 210224 kb
Host smart-7c342eb6-0aff-4762-a677-d30c853adf00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511510728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.3511510728
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.195955986
Short name T527
Test name
Test status
Simulation time 16508533 ps
CPU time 0.79 seconds
Started Apr 25 12:53:29 PM PDT 24
Finished Apr 25 12:53:33 PM PDT 24
Peak memory 205596 kb
Host smart-82936481-f411-4899-8b4a-4558e5917345
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195955986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.195955986
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.1561497730
Short name T417
Test name
Test status
Simulation time 4815631289 ps
CPU time 127.73 seconds
Started Apr 25 12:53:07 PM PDT 24
Finished Apr 25 12:55:18 PM PDT 24
Peak memory 214204 kb
Host smart-deee55ef-0140-4eaf-92cf-334b0d84eee8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1561497730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.1561497730
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.66428904
Short name T828
Test name
Test status
Simulation time 96371586 ps
CPU time 1.63 seconds
Started Apr 25 12:53:19 PM PDT 24
Finished Apr 25 12:53:22 PM PDT 24
Peak memory 209508 kb
Host smart-1a4e928b-f702-43b7-91b9-ed0e9a3eef8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66428904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.66428904
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.1782009059
Short name T782
Test name
Test status
Simulation time 4071141409 ps
CPU time 9.83 seconds
Started Apr 25 12:53:22 PM PDT 24
Finished Apr 25 12:53:34 PM PDT 24
Peak memory 214152 kb
Host smart-095e61ae-1c28-4cbb-b826-0743028b56d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782009059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.1782009059
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.848308082
Short name T338
Test name
Test status
Simulation time 392670329 ps
CPU time 10.93 seconds
Started Apr 25 12:53:30 PM PDT 24
Finished Apr 25 12:53:44 PM PDT 24
Peak memory 214076 kb
Host smart-f3ca1405-8577-48fe-99d9-31fe1e6f55a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848308082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.848308082
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.2837415142
Short name T52
Test name
Test status
Simulation time 254831099 ps
CPU time 3.4 seconds
Started Apr 25 12:53:29 PM PDT 24
Finished Apr 25 12:53:36 PM PDT 24
Peak memory 208480 kb
Host smart-e45c690d-ee47-47da-89a2-8a7c3039a063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837415142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.2837415142
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.2293963394
Short name T112
Test name
Test status
Simulation time 670002779 ps
CPU time 5.48 seconds
Started Apr 25 12:53:15 PM PDT 24
Finished Apr 25 12:53:23 PM PDT 24
Peak memory 207660 kb
Host smart-c74d385d-6264-420e-a8d3-f38170d002bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293963394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.2293963394
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.2018437211
Short name T605
Test name
Test status
Simulation time 717353164 ps
CPU time 2.81 seconds
Started Apr 25 12:53:36 PM PDT 24
Finished Apr 25 12:53:40 PM PDT 24
Peak memory 207984 kb
Host smart-51367e8a-4cc0-4c4c-b248-8a15885e1ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018437211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.2018437211
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.3670353863
Short name T585
Test name
Test status
Simulation time 304250246 ps
CPU time 5.05 seconds
Started Apr 25 12:53:27 PM PDT 24
Finished Apr 25 12:53:35 PM PDT 24
Peak memory 207664 kb
Host smart-68ca041a-706e-4e95-b386-3ad01ec6c3ec
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670353863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.3670353863
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.838493577
Short name T308
Test name
Test status
Simulation time 941427804 ps
CPU time 25.02 seconds
Started Apr 25 12:53:25 PM PDT 24
Finished Apr 25 12:53:53 PM PDT 24
Peak memory 207772 kb
Host smart-3463bb7f-bfed-4437-b666-6a076b87a8f1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838493577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.838493577
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.881743849
Short name T617
Test name
Test status
Simulation time 313768440 ps
CPU time 3.68 seconds
Started Apr 25 12:53:27 PM PDT 24
Finished Apr 25 12:53:34 PM PDT 24
Peak memory 208196 kb
Host smart-7a06f45e-d00c-4ec7-84e5-d80916353f67
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881743849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.881743849
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.1218785476
Short name T867
Test name
Test status
Simulation time 48801766 ps
CPU time 1.63 seconds
Started Apr 25 12:53:20 PM PDT 24
Finished Apr 25 12:53:23 PM PDT 24
Peak memory 215584 kb
Host smart-8717ece3-5b01-4552-ad39-731bb79ea410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218785476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.1218785476
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.3202960956
Short name T693
Test name
Test status
Simulation time 1348428688 ps
CPU time 3.66 seconds
Started Apr 25 12:53:07 PM PDT 24
Finished Apr 25 12:53:14 PM PDT 24
Peak memory 206852 kb
Host smart-91abfab1-727d-462a-b69f-340793a02696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202960956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.3202960956
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.3082624288
Short name T316
Test name
Test status
Simulation time 1322762001 ps
CPU time 34.88 seconds
Started Apr 25 12:53:27 PM PDT 24
Finished Apr 25 12:54:05 PM PDT 24
Peak memory 214736 kb
Host smart-732327f6-5442-416e-9faa-fdda5c47290f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082624288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.3082624288
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.3354589784
Short name T373
Test name
Test status
Simulation time 211951275 ps
CPU time 3.5 seconds
Started Apr 25 12:53:16 PM PDT 24
Finished Apr 25 12:53:22 PM PDT 24
Peak memory 207000 kb
Host smart-85238055-27d8-4e33-b941-832399cfd34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354589784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.3354589784
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.1527395490
Short name T587
Test name
Test status
Simulation time 295091447 ps
CPU time 3.34 seconds
Started Apr 25 12:53:25 PM PDT 24
Finished Apr 25 12:53:31 PM PDT 24
Peak memory 209912 kb
Host smart-0fcf3f63-1945-43b6-9524-2a9b863cac08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527395490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.1527395490
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.1247506847
Short name T856
Test name
Test status
Simulation time 15466987 ps
CPU time 0.78 seconds
Started Apr 25 12:53:30 PM PDT 24
Finished Apr 25 12:53:33 PM PDT 24
Peak memory 205624 kb
Host smart-2914bf4e-1b56-48c8-8def-6d0b502ca9a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247506847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.1247506847
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.3885213558
Short name T837
Test name
Test status
Simulation time 30439658 ps
CPU time 1.89 seconds
Started Apr 25 12:53:38 PM PDT 24
Finished Apr 25 12:53:41 PM PDT 24
Peak memory 206732 kb
Host smart-79547905-fafe-404b-8ea2-8e505fb86ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885213558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.3885213558
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.2826835590
Short name T716
Test name
Test status
Simulation time 705286289 ps
CPU time 6.2 seconds
Started Apr 25 12:53:26 PM PDT 24
Finished Apr 25 12:53:35 PM PDT 24
Peak memory 214148 kb
Host smart-75d6a92d-ee46-4e99-89a5-a29884b40973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826835590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.2826835590
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.4063984905
Short name T656
Test name
Test status
Simulation time 1589816938 ps
CPU time 23.39 seconds
Started Apr 25 12:53:33 PM PDT 24
Finished Apr 25 12:53:58 PM PDT 24
Peak memory 222292 kb
Host smart-582cbaf3-4379-471a-8493-5b68a7a485e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063984905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.4063984905
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.2960069594
Short name T263
Test name
Test status
Simulation time 1559762258 ps
CPU time 6.68 seconds
Started Apr 25 12:53:26 PM PDT 24
Finished Apr 25 12:53:35 PM PDT 24
Peak memory 214052 kb
Host smart-8bba1427-17d8-4885-9aff-47811a759bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960069594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.2960069594
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.3977094762
Short name T895
Test name
Test status
Simulation time 140611105 ps
CPU time 3.38 seconds
Started Apr 25 12:53:20 PM PDT 24
Finished Apr 25 12:53:25 PM PDT 24
Peak memory 207652 kb
Host smart-f429eb42-3e11-4e5f-acbb-e4e4c8d35033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977094762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.3977094762
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.2051555479
Short name T490
Test name
Test status
Simulation time 239194353 ps
CPU time 5.8 seconds
Started Apr 25 12:53:27 PM PDT 24
Finished Apr 25 12:53:35 PM PDT 24
Peak memory 207640 kb
Host smart-cce72a6b-711c-4422-8629-50adfef40dc2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051555479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.2051555479
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.2285306307
Short name T280
Test name
Test status
Simulation time 247276378 ps
CPU time 6.71 seconds
Started Apr 25 12:53:35 PM PDT 24
Finished Apr 25 12:53:44 PM PDT 24
Peak memory 208540 kb
Host smart-c1bb9cba-01f9-4aee-b419-f8b77620d1f2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285306307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.2285306307
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.1858829411
Short name T462
Test name
Test status
Simulation time 459491353 ps
CPU time 4.28 seconds
Started Apr 25 12:53:24 PM PDT 24
Finished Apr 25 12:53:30 PM PDT 24
Peak memory 208064 kb
Host smart-64aba33a-80be-4c16-9a61-f14adb25d046
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858829411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.1858829411
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.1378242680
Short name T341
Test name
Test status
Simulation time 54399077 ps
CPU time 2.03 seconds
Started Apr 25 12:53:28 PM PDT 24
Finished Apr 25 12:53:33 PM PDT 24
Peak memory 217988 kb
Host smart-b80a7bed-c0b6-47cb-9856-20dde25e68c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378242680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.1378242680
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.3655160824
Short name T130
Test name
Test status
Simulation time 417205650 ps
CPU time 9.04 seconds
Started Apr 25 12:53:28 PM PDT 24
Finished Apr 25 12:53:40 PM PDT 24
Peak memory 208164 kb
Host smart-497f7ce3-b904-4fbe-9bec-6f21e9f8d7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655160824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.3655160824
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.3442331953
Short name T354
Test name
Test status
Simulation time 113936179 ps
CPU time 6.04 seconds
Started Apr 25 12:53:25 PM PDT 24
Finished Apr 25 12:53:33 PM PDT 24
Peak memory 219044 kb
Host smart-6675ebad-bdc4-473d-87ab-a84da357b7dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442331953 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.3442331953
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.867927615
Short name T688
Test name
Test status
Simulation time 439951471 ps
CPU time 5.39 seconds
Started Apr 25 12:53:20 PM PDT 24
Finished Apr 25 12:53:26 PM PDT 24
Peak memory 210164 kb
Host smart-8f4a6aad-7ea2-4394-8ce3-08431558088a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867927615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.867927615
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.1277901762
Short name T376
Test name
Test status
Simulation time 58281368 ps
CPU time 2.27 seconds
Started Apr 25 12:53:19 PM PDT 24
Finished Apr 25 12:53:23 PM PDT 24
Peak memory 209416 kb
Host smart-235f2ca5-078b-46c2-b711-8a726a53735a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277901762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.1277901762
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.1021864391
Short name T840
Test name
Test status
Simulation time 49014725 ps
CPU time 0.74 seconds
Started Apr 25 12:53:32 PM PDT 24
Finished Apr 25 12:53:34 PM PDT 24
Peak memory 205716 kb
Host smart-9ffa8dd7-838f-4919-a243-fa0b89c3c3b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021864391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.1021864391
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.2275853192
Short name T596
Test name
Test status
Simulation time 369345013 ps
CPU time 5.53 seconds
Started Apr 25 12:53:22 PM PDT 24
Finished Apr 25 12:53:29 PM PDT 24
Peak memory 214392 kb
Host smart-3512b8fa-604d-4261-b050-64bc6c18a08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275853192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.2275853192
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.1888674126
Short name T73
Test name
Test status
Simulation time 47018070 ps
CPU time 1.85 seconds
Started Apr 25 12:53:27 PM PDT 24
Finished Apr 25 12:53:32 PM PDT 24
Peak memory 209324 kb
Host smart-405c77ae-bced-4993-bfa1-3638e1dc4f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888674126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.1888674126
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.994924802
Short name T94
Test name
Test status
Simulation time 189663725 ps
CPU time 3.5 seconds
Started Apr 25 12:53:28 PM PDT 24
Finished Apr 25 12:53:35 PM PDT 24
Peak memory 214024 kb
Host smart-ca5ddb21-42a5-4862-8a4a-b137f2407947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994924802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.994924802
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.2851322319
Short name T882
Test name
Test status
Simulation time 164326021 ps
CPU time 4.89 seconds
Started Apr 25 12:53:42 PM PDT 24
Finished Apr 25 12:53:48 PM PDT 24
Peak memory 210756 kb
Host smart-b4d0c97a-4a5b-4d7f-86f6-9f31df3b9206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851322319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.2851322319
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.2450441212
Short name T835
Test name
Test status
Simulation time 93217928 ps
CPU time 3.07 seconds
Started Apr 25 12:53:34 PM PDT 24
Finished Apr 25 12:53:39 PM PDT 24
Peak memory 219492 kb
Host smart-b81d812a-203d-4f4b-b54b-6725649866b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450441212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.2450441212
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.2037114639
Short name T197
Test name
Test status
Simulation time 69918869 ps
CPU time 2.61 seconds
Started Apr 25 12:53:29 PM PDT 24
Finished Apr 25 12:53:39 PM PDT 24
Peak memory 208244 kb
Host smart-1008084a-eeab-4b84-9d74-d5ef1df5135d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037114639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.2037114639
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.1999175538
Short name T843
Test name
Test status
Simulation time 3784947257 ps
CPU time 25.06 seconds
Started Apr 25 12:53:24 PM PDT 24
Finished Apr 25 12:53:51 PM PDT 24
Peak memory 207492 kb
Host smart-a238733d-da4c-4d7c-90e6-20c18e05968d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999175538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.1999175538
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.739160429
Short name T104
Test name
Test status
Simulation time 1003870426 ps
CPU time 7.07 seconds
Started Apr 25 12:53:25 PM PDT 24
Finished Apr 25 12:53:34 PM PDT 24
Peak memory 207880 kb
Host smart-99ba7208-3747-4887-ab66-4707b16a8065
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739160429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.739160429
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.3515502378
Short name T589
Test name
Test status
Simulation time 311491811 ps
CPU time 5.22 seconds
Started Apr 25 12:53:24 PM PDT 24
Finished Apr 25 12:53:31 PM PDT 24
Peak memory 208404 kb
Host smart-bf61eb07-7c7f-420b-a733-07db423e23e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515502378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.3515502378
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.2636212199
Short name T469
Test name
Test status
Simulation time 426777944 ps
CPU time 2.33 seconds
Started Apr 25 12:53:23 PM PDT 24
Finished Apr 25 12:53:26 PM PDT 24
Peak memory 206864 kb
Host smart-4dbd63c1-a601-42fc-8761-3f68bce50a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636212199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.2636212199
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.1735083682
Short name T240
Test name
Test status
Simulation time 6262182592 ps
CPU time 19.81 seconds
Started Apr 25 12:53:25 PM PDT 24
Finished Apr 25 12:53:47 PM PDT 24
Peak memory 222308 kb
Host smart-4a388d5b-16f5-4661-b955-bd14c747f0cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735083682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.1735083682
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.3201411156
Short name T468
Test name
Test status
Simulation time 218651267 ps
CPU time 6.4 seconds
Started Apr 25 12:53:27 PM PDT 24
Finished Apr 25 12:53:37 PM PDT 24
Peak memory 209064 kb
Host smart-dafa73b3-eb5f-4402-9c5b-8986ac726975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201411156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.3201411156
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.561132267
Short name T105
Test name
Test status
Simulation time 288799984 ps
CPU time 2.18 seconds
Started Apr 25 12:53:53 PM PDT 24
Finished Apr 25 12:53:56 PM PDT 24
Peak memory 209456 kb
Host smart-3b92c696-7fde-48e6-bf1f-73031a76a716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561132267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.561132267
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.21166237
Short name T776
Test name
Test status
Simulation time 15118229 ps
CPU time 0.71 seconds
Started Apr 25 12:53:41 PM PDT 24
Finished Apr 25 12:53:43 PM PDT 24
Peak memory 205708 kb
Host smart-e0feb4cb-db82-44f3-892a-808c551665d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21166237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.21166237
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.3944737871
Short name T871
Test name
Test status
Simulation time 21836355 ps
CPU time 1.83 seconds
Started Apr 25 12:53:31 PM PDT 24
Finished Apr 25 12:53:35 PM PDT 24
Peak memory 207380 kb
Host smart-c0c42a8f-9b65-4eae-973c-152a380b21b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944737871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.3944737871
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.913840910
Short name T455
Test name
Test status
Simulation time 156397747 ps
CPU time 3.4 seconds
Started Apr 25 12:53:27 PM PDT 24
Finished Apr 25 12:53:33 PM PDT 24
Peak memory 209540 kb
Host smart-717387f2-3b17-4d8b-a4a6-bbe69108c0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913840910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.913840910
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.3247427112
Short name T186
Test name
Test status
Simulation time 890172861 ps
CPU time 6.72 seconds
Started Apr 25 12:53:34 PM PDT 24
Finished Apr 25 12:53:43 PM PDT 24
Peak memory 209824 kb
Host smart-29d98da8-7014-4b72-a9ec-a564899a941e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247427112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.3247427112
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.2800397635
Short name T643
Test name
Test status
Simulation time 135780742 ps
CPU time 4.5 seconds
Started Apr 25 12:53:15 PM PDT 24
Finished Apr 25 12:53:22 PM PDT 24
Peak memory 206540 kb
Host smart-37499671-b6c6-4adb-99ff-32327189b540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800397635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.2800397635
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.130969530
Short name T689
Test name
Test status
Simulation time 57805862 ps
CPU time 2.31 seconds
Started Apr 25 12:53:24 PM PDT 24
Finished Apr 25 12:53:28 PM PDT 24
Peak memory 206532 kb
Host smart-186948bd-48aa-48a5-aeee-94d110ef21a8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130969530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.130969530
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.1359685598
Short name T433
Test name
Test status
Simulation time 35126291 ps
CPU time 2.38 seconds
Started Apr 25 12:53:55 PM PDT 24
Finished Apr 25 12:53:59 PM PDT 24
Peak memory 206552 kb
Host smart-8256e328-2fc7-4d9f-93c4-848a14b1c62a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359685598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.1359685598
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.1118735834
Short name T667
Test name
Test status
Simulation time 206588913 ps
CPU time 5.78 seconds
Started Apr 25 12:53:28 PM PDT 24
Finished Apr 25 12:53:37 PM PDT 24
Peak memory 208416 kb
Host smart-7028c611-77f0-42ee-b606-d32f398385c2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118735834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.1118735834
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.2347809935
Short name T389
Test name
Test status
Simulation time 32790161 ps
CPU time 1.36 seconds
Started Apr 25 12:53:34 PM PDT 24
Finished Apr 25 12:53:37 PM PDT 24
Peak memory 207476 kb
Host smart-506f824c-4239-4537-98d9-d35737337e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347809935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.2347809935
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.4267427935
Short name T428
Test name
Test status
Simulation time 60340554 ps
CPU time 1.81 seconds
Started Apr 25 12:53:25 PM PDT 24
Finished Apr 25 12:53:30 PM PDT 24
Peak memory 206416 kb
Host smart-96067d5b-784a-4cd0-bb4d-0ed3e914a5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267427935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.4267427935
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.20161484
Short name T494
Test name
Test status
Simulation time 171431541 ps
CPU time 7.16 seconds
Started Apr 25 12:53:25 PM PDT 24
Finished Apr 25 12:53:35 PM PDT 24
Peak memory 222452 kb
Host smart-dfa1223e-9ba4-407e-962c-c7ec3751cd0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20161484 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.20161484
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.599519376
Short name T580
Test name
Test status
Simulation time 415580716 ps
CPU time 3.79 seconds
Started Apr 25 12:53:49 PM PDT 24
Finished Apr 25 12:53:54 PM PDT 24
Peak memory 207356 kb
Host smart-169c1303-c5f1-44ec-b605-7943a58856fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599519376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.599519376
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.208183175
Short name T622
Test name
Test status
Simulation time 215124547 ps
CPU time 2.86 seconds
Started Apr 25 12:53:41 PM PDT 24
Finished Apr 25 12:53:45 PM PDT 24
Peak memory 210160 kb
Host smart-639349bf-1d2c-4367-9209-e666e73b5e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208183175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.208183175
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.1606094055
Short name T611
Test name
Test status
Simulation time 13237593 ps
CPU time 0.83 seconds
Started Apr 25 12:53:27 PM PDT 24
Finished Apr 25 12:53:31 PM PDT 24
Peak memory 205652 kb
Host smart-712df2a0-f77f-41d5-b13a-ef0ce8a69a65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606094055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.1606094055
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.992273787
Short name T385
Test name
Test status
Simulation time 66574134 ps
CPU time 3.18 seconds
Started Apr 25 12:53:55 PM PDT 24
Finished Apr 25 12:54:01 PM PDT 24
Peak memory 214024 kb
Host smart-5bc0577c-02c9-4f76-b740-7ef4f2d566a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=992273787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.992273787
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.2842517416
Short name T726
Test name
Test status
Simulation time 433229637 ps
CPU time 4.95 seconds
Started Apr 25 12:53:24 PM PDT 24
Finished Apr 25 12:53:30 PM PDT 24
Peak memory 207324 kb
Host smart-e86f93c7-8496-4c0f-ac15-4eb5c43e3921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842517416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.2842517416
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.1139735890
Short name T779
Test name
Test status
Simulation time 96613076 ps
CPU time 3.71 seconds
Started Apr 25 12:53:27 PM PDT 24
Finished Apr 25 12:53:34 PM PDT 24
Peak memory 214196 kb
Host smart-7b46f49d-d728-49f2-8282-0de42663bdc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139735890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.1139735890
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.232045343
Short name T311
Test name
Test status
Simulation time 7224567433 ps
CPU time 83.14 seconds
Started Apr 25 12:53:23 PM PDT 24
Finished Apr 25 12:54:48 PM PDT 24
Peak memory 226692 kb
Host smart-1f118407-a4f2-4b7c-8839-49f081f1571f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232045343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.232045343
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.2296397255
Short name T72
Test name
Test status
Simulation time 55652752 ps
CPU time 3.4 seconds
Started Apr 25 12:53:29 PM PDT 24
Finished Apr 25 12:53:40 PM PDT 24
Peak memory 214040 kb
Host smart-24b6bc26-c66b-4fa2-bf0a-29a0688c9ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296397255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.2296397255
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.1351763819
Short name T230
Test name
Test status
Simulation time 169400937 ps
CPU time 3.05 seconds
Started Apr 25 12:53:30 PM PDT 24
Finished Apr 25 12:53:35 PM PDT 24
Peak memory 207460 kb
Host smart-cd59d54d-d2d4-4065-8759-3af92bf81d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351763819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.1351763819
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.3047130338
Short name T609
Test name
Test status
Simulation time 140385526 ps
CPU time 2.74 seconds
Started Apr 25 12:53:38 PM PDT 24
Finished Apr 25 12:53:42 PM PDT 24
Peak memory 208520 kb
Host smart-3af0800d-4dbe-494f-b9eb-251b7218da84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047130338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.3047130338
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.3599620359
Short name T452
Test name
Test status
Simulation time 1296008727 ps
CPU time 21.95 seconds
Started Apr 25 12:53:42 PM PDT 24
Finished Apr 25 12:54:05 PM PDT 24
Peak memory 208392 kb
Host smart-8a979776-38db-4c28-9556-0823877fa197
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599620359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.3599620359
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.653760042
Short name T43
Test name
Test status
Simulation time 68592648 ps
CPU time 2.75 seconds
Started Apr 25 12:53:36 PM PDT 24
Finished Apr 25 12:53:40 PM PDT 24
Peak memory 206504 kb
Host smart-fcb105df-bf71-4195-a1e4-655bfa59ca5e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653760042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.653760042
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.2212559751
Short name T869
Test name
Test status
Simulation time 1072111672 ps
CPU time 3.44 seconds
Started Apr 25 12:53:28 PM PDT 24
Finished Apr 25 12:53:34 PM PDT 24
Peak memory 208300 kb
Host smart-de64a072-2268-4aa7-9df1-4562995cdac7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212559751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.2212559751
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.4041025583
Short name T709
Test name
Test status
Simulation time 52190615 ps
CPU time 2.25 seconds
Started Apr 25 12:53:31 PM PDT 24
Finished Apr 25 12:53:35 PM PDT 24
Peak memory 208308 kb
Host smart-454e09eb-bc85-46e1-85d1-6ff6499e49c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041025583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.4041025583
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.3704291691
Short name T441
Test name
Test status
Simulation time 115827457 ps
CPU time 2.75 seconds
Started Apr 25 12:53:24 PM PDT 24
Finished Apr 25 12:53:29 PM PDT 24
Peak memory 206556 kb
Host smart-14ecabd2-5343-4774-8b32-c5ca2a8d4c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704291691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.3704291691
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.4294336883
Short name T107
Test name
Test status
Simulation time 4742837366 ps
CPU time 28 seconds
Started Apr 25 12:53:49 PM PDT 24
Finished Apr 25 12:54:18 PM PDT 24
Peak memory 214104 kb
Host smart-55dac949-30af-4438-9f86-aca29d3268d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294336883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.4294336883
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.2905310870
Short name T66
Test name
Test status
Simulation time 125266574 ps
CPU time 2.87 seconds
Started Apr 25 12:53:25 PM PDT 24
Finished Apr 25 12:53:31 PM PDT 24
Peak memory 210052 kb
Host smart-6e6068be-b72b-4fda-a97b-4d9aa8e56dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905310870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.2905310870
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.4064648195
Short name T614
Test name
Test status
Simulation time 16963405 ps
CPU time 0.73 seconds
Started Apr 25 12:53:31 PM PDT 24
Finished Apr 25 12:53:34 PM PDT 24
Peak memory 205604 kb
Host smart-6f32ddf3-b5ac-4c03-bc3c-685fef3f4ce0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064648195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.4064648195
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.1211396004
Short name T771
Test name
Test status
Simulation time 82390845 ps
CPU time 3.43 seconds
Started Apr 25 12:53:26 PM PDT 24
Finished Apr 25 12:53:32 PM PDT 24
Peak memory 208724 kb
Host smart-0d32b064-ad7c-47ac-b803-12fa2a9227b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211396004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.1211396004
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.826239410
Short name T675
Test name
Test status
Simulation time 46324667 ps
CPU time 1.73 seconds
Started Apr 25 12:53:30 PM PDT 24
Finished Apr 25 12:53:34 PM PDT 24
Peak memory 207184 kb
Host smart-48c3e15b-e5bf-49b9-92fa-87af378d4db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826239410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.826239410
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.3203921753
Short name T374
Test name
Test status
Simulation time 323988094 ps
CPU time 3.96 seconds
Started Apr 25 12:53:34 PM PDT 24
Finished Apr 25 12:53:40 PM PDT 24
Peak memory 218252 kb
Host smart-01ed2c2c-52bd-4dea-95ea-4659ce556c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203921753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.3203921753
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.3091332019
Short name T355
Test name
Test status
Simulation time 140586018 ps
CPU time 2.88 seconds
Started Apr 25 12:53:27 PM PDT 24
Finished Apr 25 12:53:33 PM PDT 24
Peak memory 210128 kb
Host smart-119f1013-35b0-45ab-8eaa-8314d1158426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091332019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.3091332019
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.1835832706
Short name T531
Test name
Test status
Simulation time 169099720 ps
CPU time 3.24 seconds
Started Apr 25 12:53:33 PM PDT 24
Finished Apr 25 12:53:38 PM PDT 24
Peak memory 207188 kb
Host smart-0cde692a-408d-4992-8b1b-af7ea7f9c67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835832706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.1835832706
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.2200807468
Short name T884
Test name
Test status
Simulation time 146714975 ps
CPU time 7.05 seconds
Started Apr 25 12:53:26 PM PDT 24
Finished Apr 25 12:53:35 PM PDT 24
Peak memory 209948 kb
Host smart-0b630bf5-7065-4d94-a6e7-368327b370b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200807468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.2200807468
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.4271280592
Short name T563
Test name
Test status
Simulation time 92452451 ps
CPU time 2.57 seconds
Started Apr 25 12:53:26 PM PDT 24
Finished Apr 25 12:53:31 PM PDT 24
Peak memory 206508 kb
Host smart-680816fc-fbdf-464b-859e-e0c8f5f4964d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271280592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.4271280592
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.2304620274
Short name T476
Test name
Test status
Simulation time 170280135 ps
CPU time 4.09 seconds
Started Apr 25 12:53:28 PM PDT 24
Finished Apr 25 12:53:35 PM PDT 24
Peak memory 208388 kb
Host smart-f14e5ff3-df4e-4333-a9d7-fc674cabe8db
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304620274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.2304620274
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.3492174238
Short name T534
Test name
Test status
Simulation time 3095304269 ps
CPU time 42.04 seconds
Started Apr 25 12:53:36 PM PDT 24
Finished Apr 25 12:54:20 PM PDT 24
Peak memory 207708 kb
Host smart-05a2f448-24e8-4312-94f4-e543b6e209b0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492174238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.3492174238
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.1754642441
Short name T502
Test name
Test status
Simulation time 264569431 ps
CPU time 7.87 seconds
Started Apr 25 12:53:26 PM PDT 24
Finished Apr 25 12:53:36 PM PDT 24
Peak memory 208604 kb
Host smart-4005d002-755c-47c5-93c5-cd4ce52eb728
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754642441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.1754642441
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.1235055568
Short name T780
Test name
Test status
Simulation time 57387109 ps
CPU time 1.95 seconds
Started Apr 25 12:53:28 PM PDT 24
Finished Apr 25 12:53:33 PM PDT 24
Peak memory 215008 kb
Host smart-95c3acf0-7fa0-4030-917f-d9d9de7a0443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235055568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.1235055568
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.1158436269
Short name T806
Test name
Test status
Simulation time 478551895 ps
CPU time 3.81 seconds
Started Apr 25 12:53:26 PM PDT 24
Finished Apr 25 12:53:33 PM PDT 24
Peak memory 206476 kb
Host smart-0d1ca7ea-071a-417c-ab7b-6c8672b4f168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158436269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.1158436269
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.3675470836
Short name T754
Test name
Test status
Simulation time 456621380 ps
CPU time 4.06 seconds
Started Apr 25 12:53:28 PM PDT 24
Finished Apr 25 12:53:35 PM PDT 24
Peak memory 207844 kb
Host smart-e7007b98-3786-4f14-85f0-e3dbfebb6ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675470836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.3675470836
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.982245570
Short name T697
Test name
Test status
Simulation time 221863933 ps
CPU time 2.57 seconds
Started Apr 25 12:53:27 PM PDT 24
Finished Apr 25 12:53:33 PM PDT 24
Peak memory 209576 kb
Host smart-7c3b6a6f-b707-4c19-8963-4c3595f3ad36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982245570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.982245570
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.3264253227
Short name T96
Test name
Test status
Simulation time 13197635 ps
CPU time 0.73 seconds
Started Apr 25 12:53:01 PM PDT 24
Finished Apr 25 12:53:03 PM PDT 24
Peak memory 205720 kb
Host smart-8699d1a5-114f-47fe-b76d-908901a5fc81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264253227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.3264253227
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.94415816
Short name T297
Test name
Test status
Simulation time 2025047203 ps
CPU time 56.51 seconds
Started Apr 25 12:52:45 PM PDT 24
Finished Apr 25 12:53:43 PM PDT 24
Peak memory 215280 kb
Host smart-b7fc1800-0d47-450d-8414-184ea39d5081
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=94415816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.94415816
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.157994403
Short name T440
Test name
Test status
Simulation time 22672473 ps
CPU time 1.71 seconds
Started Apr 25 12:52:45 PM PDT 24
Finished Apr 25 12:52:48 PM PDT 24
Peak memory 206952 kb
Host smart-829dfb75-40d0-489e-99f7-f0754df9b79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157994403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.157994403
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.1746612023
Short name T760
Test name
Test status
Simulation time 291126096 ps
CPU time 3.77 seconds
Started Apr 25 12:52:48 PM PDT 24
Finished Apr 25 12:52:53 PM PDT 24
Peak memory 208948 kb
Host smart-394d747e-11a8-4153-be4b-1ef0e8d28bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746612023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.1746612023
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.3279692807
Short name T191
Test name
Test status
Simulation time 427780176 ps
CPU time 7.57 seconds
Started Apr 25 12:52:50 PM PDT 24
Finished Apr 25 12:52:59 PM PDT 24
Peak memory 214088 kb
Host smart-85e1e556-3dc3-4b5b-92b2-d67a8af656de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279692807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.3279692807
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.1779124391
Short name T804
Test name
Test status
Simulation time 60809756 ps
CPU time 3.66 seconds
Started Apr 25 12:52:37 PM PDT 24
Finished Apr 25 12:52:43 PM PDT 24
Peak memory 209156 kb
Host smart-b01f2217-6cba-41b3-accd-35d3beb2b9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779124391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.1779124391
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.1638836327
Short name T179
Test name
Test status
Simulation time 1700564045 ps
CPU time 10.29 seconds
Started Apr 25 12:52:42 PM PDT 24
Finished Apr 25 12:52:54 PM PDT 24
Peak memory 208932 kb
Host smart-8a24c6e5-9136-450c-80b6-da9464c7807e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638836327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.1638836327
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.300802393
Short name T14
Test name
Test status
Simulation time 8411183956 ps
CPU time 19.98 seconds
Started Apr 25 12:52:55 PM PDT 24
Finished Apr 25 12:53:17 PM PDT 24
Peak memory 231280 kb
Host smart-b265c780-82df-448f-92d9-11b28353da7e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300802393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.300802393
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.3341300521
Short name T353
Test name
Test status
Simulation time 10043336947 ps
CPU time 55.73 seconds
Started Apr 25 12:52:51 PM PDT 24
Finished Apr 25 12:53:49 PM PDT 24
Peak memory 207768 kb
Host smart-fba0b41e-58a9-4aa2-a4bb-0ae2a636b0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341300521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.3341300521
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.560402968
Short name T720
Test name
Test status
Simulation time 36845098 ps
CPU time 2.41 seconds
Started Apr 25 12:52:47 PM PDT 24
Finished Apr 25 12:52:51 PM PDT 24
Peak memory 208184 kb
Host smart-47adbe71-dc3a-4623-bedd-d513c6347963
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560402968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.560402968
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.3693564755
Short name T628
Test name
Test status
Simulation time 828877087 ps
CPU time 5.61 seconds
Started Apr 25 12:52:47 PM PDT 24
Finished Apr 25 12:52:54 PM PDT 24
Peak memory 208400 kb
Host smart-a00ebc81-615f-4d5d-8e54-344fa387c07e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693564755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.3693564755
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.4112028710
Short name T588
Test name
Test status
Simulation time 276564916 ps
CPU time 4.23 seconds
Started Apr 25 12:52:59 PM PDT 24
Finished Apr 25 12:53:04 PM PDT 24
Peak memory 208168 kb
Host smart-43a0c025-8a4a-45b0-89b2-8937a67f3cbf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112028710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.4112028710
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.1221401784
Short name T823
Test name
Test status
Simulation time 127214625 ps
CPU time 2.2 seconds
Started Apr 25 12:52:58 PM PDT 24
Finished Apr 25 12:53:01 PM PDT 24
Peak memory 209816 kb
Host smart-a33e1db6-f22d-487f-b9b9-093f7c33b132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221401784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.1221401784
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.2217410126
Short name T427
Test name
Test status
Simulation time 776156553 ps
CPU time 8.27 seconds
Started Apr 25 12:52:44 PM PDT 24
Finished Apr 25 12:52:54 PM PDT 24
Peak memory 208380 kb
Host smart-72575811-dfc6-44f9-8a33-52a28228537d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217410126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.2217410126
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.765791437
Short name T647
Test name
Test status
Simulation time 316213384 ps
CPU time 4.43 seconds
Started Apr 25 12:52:52 PM PDT 24
Finished Apr 25 12:52:57 PM PDT 24
Peak memory 214032 kb
Host smart-4544de17-98ac-4a4a-a3b6-a7c579237576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765791437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.765791437
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.3430119977
Short name T456
Test name
Test status
Simulation time 57970415 ps
CPU time 2.47 seconds
Started Apr 25 12:52:48 PM PDT 24
Finished Apr 25 12:52:53 PM PDT 24
Peak memory 210116 kb
Host smart-3da25fd0-0a83-459b-89c7-8e849e8e1281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430119977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.3430119977
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.3204718752
Short name T758
Test name
Test status
Simulation time 28913794 ps
CPU time 0.75 seconds
Started Apr 25 12:53:25 PM PDT 24
Finished Apr 25 12:53:28 PM PDT 24
Peak memory 205716 kb
Host smart-5274e709-5a3e-4e49-b369-6fd0d7e57f3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204718752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.3204718752
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.2768359937
Short name T406
Test name
Test status
Simulation time 78800224 ps
CPU time 4.88 seconds
Started Apr 25 12:53:39 PM PDT 24
Finished Apr 25 12:53:45 PM PDT 24
Peak memory 214120 kb
Host smart-fe0f74a0-9f60-4bfe-b257-dac8df950661
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2768359937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.2768359937
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.2139430220
Short name T29
Test name
Test status
Simulation time 592640925 ps
CPU time 7.58 seconds
Started Apr 25 12:53:58 PM PDT 24
Finished Apr 25 12:54:09 PM PDT 24
Peak memory 222608 kb
Host smart-62e007f3-6c2c-479d-b246-b8911e2eab96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139430220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.2139430220
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.3539751929
Short name T64
Test name
Test status
Simulation time 52862545 ps
CPU time 2.17 seconds
Started Apr 25 12:53:44 PM PDT 24
Finished Apr 25 12:53:47 PM PDT 24
Peak memory 207188 kb
Host smart-6d45c4ee-e004-4d0b-87d9-989bb170cd8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539751929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.3539751929
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.2907379730
Short name T277
Test name
Test status
Simulation time 276074732 ps
CPU time 3.75 seconds
Started Apr 25 12:53:53 PM PDT 24
Finished Apr 25 12:53:59 PM PDT 24
Peak memory 208168 kb
Host smart-4e56e4fb-d0d2-4377-9c00-9c527d43fa6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907379730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.2907379730
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.3155364096
Short name T680
Test name
Test status
Simulation time 165170487 ps
CPU time 5.05 seconds
Started Apr 25 12:53:43 PM PDT 24
Finished Apr 25 12:53:49 PM PDT 24
Peak memory 214208 kb
Host smart-67f6e5d4-e174-49df-af6b-8c58d53db4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155364096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.3155364096
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.1179452253
Short name T635
Test name
Test status
Simulation time 3268826087 ps
CPU time 38.05 seconds
Started Apr 25 12:53:39 PM PDT 24
Finished Apr 25 12:54:18 PM PDT 24
Peak memory 208120 kb
Host smart-6b819f7c-61c9-44ec-9ed6-d23ddb4d18e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179452253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.1179452253
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.604365034
Short name T579
Test name
Test status
Simulation time 142826467 ps
CPU time 2.89 seconds
Started Apr 25 12:53:46 PM PDT 24
Finished Apr 25 12:53:50 PM PDT 24
Peak memory 208388 kb
Host smart-a8cbd196-d310-4856-a617-6dd2a19e764a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604365034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.604365034
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.3175074699
Short name T5
Test name
Test status
Simulation time 89659575 ps
CPU time 1.91 seconds
Started Apr 25 12:53:38 PM PDT 24
Finished Apr 25 12:53:41 PM PDT 24
Peak memory 206440 kb
Host smart-78316976-280c-492d-909d-fe07f2840fff
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175074699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.3175074699
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.3176058121
Short name T606
Test name
Test status
Simulation time 5291690238 ps
CPU time 11.26 seconds
Started Apr 25 12:53:47 PM PDT 24
Finished Apr 25 12:53:59 PM PDT 24
Peak memory 207688 kb
Host smart-b46a5f10-3914-4b26-9d63-ec8f802adb22
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176058121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.3176058121
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.3226746795
Short name T732
Test name
Test status
Simulation time 124422868 ps
CPU time 3.38 seconds
Started Apr 25 12:53:54 PM PDT 24
Finished Apr 25 12:53:59 PM PDT 24
Peak memory 209396 kb
Host smart-1d0b9486-8123-4fc3-a654-3268e542e864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226746795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.3226746795
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.3489431822
Short name T529
Test name
Test status
Simulation time 225590219 ps
CPU time 5.55 seconds
Started Apr 25 12:53:32 PM PDT 24
Finished Apr 25 12:53:40 PM PDT 24
Peak memory 206364 kb
Host smart-706e72ea-df17-4077-921a-8dbc322da60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489431822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.3489431822
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.3698392893
Short name T244
Test name
Test status
Simulation time 1463069407 ps
CPU time 46.1 seconds
Started Apr 25 12:53:50 PM PDT 24
Finished Apr 25 12:54:38 PM PDT 24
Peak memory 216156 kb
Host smart-28cd470a-0788-437e-878e-af19188f0fa0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698392893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.3698392893
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.1949696680
Short name T785
Test name
Test status
Simulation time 1045262780 ps
CPU time 6.39 seconds
Started Apr 25 12:53:42 PM PDT 24
Finished Apr 25 12:53:50 PM PDT 24
Peak memory 218208 kb
Host smart-c5e94d15-aeec-48c4-823a-16d82742ac59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949696680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.1949696680
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.310135722
Short name T521
Test name
Test status
Simulation time 112026112 ps
CPU time 1.91 seconds
Started Apr 25 12:53:29 PM PDT 24
Finished Apr 25 12:53:34 PM PDT 24
Peak memory 209764 kb
Host smart-800850db-23ac-44ba-b02d-2e15b3e043af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310135722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.310135722
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.1748524399
Short name T443
Test name
Test status
Simulation time 21590434 ps
CPU time 1.04 seconds
Started Apr 25 12:53:37 PM PDT 24
Finished Apr 25 12:53:40 PM PDT 24
Peak memory 205836 kb
Host smart-dd87d433-a792-4a68-95a1-95beccf46a92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748524399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.1748524399
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.882287257
Short name T229
Test name
Test status
Simulation time 183385074 ps
CPU time 3.79 seconds
Started Apr 25 12:53:48 PM PDT 24
Finished Apr 25 12:53:54 PM PDT 24
Peak memory 214012 kb
Host smart-09b2355c-7b45-48cd-af39-6be922c50b84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=882287257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.882287257
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.1972875248
Short name T11
Test name
Test status
Simulation time 104254096 ps
CPU time 3.89 seconds
Started Apr 25 12:53:36 PM PDT 24
Finished Apr 25 12:53:41 PM PDT 24
Peak memory 210144 kb
Host smart-5171e66e-a654-4d73-975c-f27d4a508f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972875248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.1972875248
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.2728177183
Short name T270
Test name
Test status
Simulation time 48847551 ps
CPU time 2.84 seconds
Started Apr 25 12:53:30 PM PDT 24
Finished Apr 25 12:53:35 PM PDT 24
Peak memory 206684 kb
Host smart-120b1a1c-d753-47fa-ab7e-c8f74890bf43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728177183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.2728177183
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.59215966
Short name T102
Test name
Test status
Simulation time 263155548 ps
CPU time 2.95 seconds
Started Apr 25 12:53:33 PM PDT 24
Finished Apr 25 12:53:38 PM PDT 24
Peak memory 208164 kb
Host smart-a69d1fc4-5a18-4d70-9fb5-f504ca23dc01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59215966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.59215966
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.3536138374
Short name T544
Test name
Test status
Simulation time 301305400 ps
CPU time 4.03 seconds
Started Apr 25 12:53:42 PM PDT 24
Finished Apr 25 12:53:47 PM PDT 24
Peak memory 222168 kb
Host smart-eae9326d-502e-4ba4-aefe-011a431a60d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536138374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.3536138374
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.430698669
Short name T253
Test name
Test status
Simulation time 301105123 ps
CPU time 3.97 seconds
Started Apr 25 12:53:47 PM PDT 24
Finished Apr 25 12:53:53 PM PDT 24
Peak memory 214008 kb
Host smart-745c2478-1b47-4883-93a2-e8723701d307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430698669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.430698669
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.658775777
Short name T555
Test name
Test status
Simulation time 792489475 ps
CPU time 26.31 seconds
Started Apr 25 12:53:25 PM PDT 24
Finished Apr 25 12:53:54 PM PDT 24
Peak memory 208608 kb
Host smart-b942a6b4-4ca7-49f1-860b-6717ec635185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658775777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.658775777
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.966463730
Short name T18
Test name
Test status
Simulation time 864151028 ps
CPU time 9.39 seconds
Started Apr 25 12:53:46 PM PDT 24
Finished Apr 25 12:53:57 PM PDT 24
Peak memory 208492 kb
Host smart-156047e6-6a5e-4759-9e29-fc09119d9ae7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966463730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.966463730
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.1054168338
Short name T228
Test name
Test status
Simulation time 7739076173 ps
CPU time 55.59 seconds
Started Apr 25 12:53:27 PM PDT 24
Finished Apr 25 12:54:25 PM PDT 24
Peak memory 208632 kb
Host smart-e4bcfd40-c254-48bf-b7d9-b1ba8de1f43c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054168338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.1054168338
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.2056708000
Short name T788
Test name
Test status
Simulation time 277123794 ps
CPU time 3.29 seconds
Started Apr 25 12:53:33 PM PDT 24
Finished Apr 25 12:53:40 PM PDT 24
Peak memory 206484 kb
Host smart-8a571ef8-4cce-48a4-88bb-4a507dd3e558
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056708000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.2056708000
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.914188761
Short name T533
Test name
Test status
Simulation time 29826662 ps
CPU time 2.18 seconds
Started Apr 25 12:53:37 PM PDT 24
Finished Apr 25 12:53:41 PM PDT 24
Peak memory 208800 kb
Host smart-3208374a-1c9c-4043-9a94-0eb941e55cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914188761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.914188761
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.4242577395
Short name T539
Test name
Test status
Simulation time 103441086 ps
CPU time 2.21 seconds
Started Apr 25 12:54:05 PM PDT 24
Finished Apr 25 12:54:11 PM PDT 24
Peak memory 205840 kb
Host smart-ec0ee51b-fb82-43ce-be5c-b8261e45c4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242577395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.4242577395
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.3706904329
Short name T300
Test name
Test status
Simulation time 1520128116 ps
CPU time 52.16 seconds
Started Apr 25 12:53:38 PM PDT 24
Finished Apr 25 12:54:37 PM PDT 24
Peak memory 216944 kb
Host smart-a63dff6e-211d-4864-8352-79d08cf7b0f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706904329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.3706904329
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.1813120364
Short name T260
Test name
Test status
Simulation time 1083749216 ps
CPU time 12.16 seconds
Started Apr 25 12:53:34 PM PDT 24
Finished Apr 25 12:53:49 PM PDT 24
Peak memory 214204 kb
Host smart-cf3d62ae-9e79-43f8-809c-deaaa40d1ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813120364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.1813120364
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.2823349253
Short name T736
Test name
Test status
Simulation time 2251939359 ps
CPU time 25.83 seconds
Started Apr 25 12:53:40 PM PDT 24
Finished Apr 25 12:54:07 PM PDT 24
Peak memory 210144 kb
Host smart-d4429148-2783-44aa-8bb7-195a2f60f0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823349253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.2823349253
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.268546979
Short name T464
Test name
Test status
Simulation time 57543204 ps
CPU time 0.76 seconds
Started Apr 25 12:53:48 PM PDT 24
Finished Apr 25 12:53:51 PM PDT 24
Peak memory 205588 kb
Host smart-ecc2ac7d-51af-46ec-b867-aeadd4debea7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268546979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.268546979
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.2243291000
Short name T408
Test name
Test status
Simulation time 3653237907 ps
CPU time 48.87 seconds
Started Apr 25 12:53:41 PM PDT 24
Finished Apr 25 12:54:31 PM PDT 24
Peak memory 215212 kb
Host smart-a599a64b-b6a2-4c4b-8d66-5e21ad954d9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2243291000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.2243291000
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.399087324
Short name T305
Test name
Test status
Simulation time 38001043 ps
CPU time 2.6 seconds
Started Apr 25 12:53:38 PM PDT 24
Finished Apr 25 12:53:42 PM PDT 24
Peak memory 209572 kb
Host smart-eeedd0b8-3862-4c77-bc49-07256f258ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399087324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.399087324
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.3136525186
Short name T320
Test name
Test status
Simulation time 43106934 ps
CPU time 2.86 seconds
Started Apr 25 12:53:46 PM PDT 24
Finished Apr 25 12:53:50 PM PDT 24
Peak memory 208320 kb
Host smart-1865f279-66f9-461c-9e86-b999c97b3d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136525186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.3136525186
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.2355559408
Short name T692
Test name
Test status
Simulation time 213544127 ps
CPU time 3.88 seconds
Started Apr 25 12:53:50 PM PDT 24
Finished Apr 25 12:53:55 PM PDT 24
Peak memory 222272 kb
Host smart-ed481039-f361-4d0d-a95b-195da6afbc68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355559408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.2355559408
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_sideload.4013669080
Short name T818
Test name
Test status
Simulation time 239750947 ps
CPU time 2.79 seconds
Started Apr 25 12:53:32 PM PDT 24
Finished Apr 25 12:53:37 PM PDT 24
Peak memory 208444 kb
Host smart-5df3e807-8659-45fe-918b-6ea6d4d7e9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013669080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.4013669080
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.2296160826
Short name T724
Test name
Test status
Simulation time 307097910 ps
CPU time 2.81 seconds
Started Apr 25 12:53:56 PM PDT 24
Finished Apr 25 12:54:01 PM PDT 24
Peak memory 206600 kb
Host smart-ace15572-f477-4e5d-bac9-c2fc604882bd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296160826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.2296160826
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.2046906249
Short name T546
Test name
Test status
Simulation time 116112986 ps
CPU time 2.91 seconds
Started Apr 25 12:54:01 PM PDT 24
Finished Apr 25 12:54:09 PM PDT 24
Peak memory 207644 kb
Host smart-f117d91d-0161-4e0f-983f-9cf1114ed7a1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046906249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.2046906249
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.270788036
Short name T809
Test name
Test status
Simulation time 159966239 ps
CPU time 4.47 seconds
Started Apr 25 12:53:40 PM PDT 24
Finished Apr 25 12:53:46 PM PDT 24
Peak memory 207852 kb
Host smart-a481e55d-5532-4c38-a0bb-329774bc89eb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270788036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.270788036
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.3878405463
Short name T615
Test name
Test status
Simulation time 89415617 ps
CPU time 2.34 seconds
Started Apr 25 12:53:57 PM PDT 24
Finished Apr 25 12:54:03 PM PDT 24
Peak memory 209568 kb
Host smart-a322b09e-49c4-4336-b6a2-b79c1fac4075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878405463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.3878405463
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.4255440126
Short name T543
Test name
Test status
Simulation time 78171271 ps
CPU time 1.78 seconds
Started Apr 25 12:53:48 PM PDT 24
Finished Apr 25 12:53:51 PM PDT 24
Peak memory 207076 kb
Host smart-2a7a97e4-fddf-4caa-8a81-ae83618c23cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255440126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.4255440126
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.4161233567
Short name T49
Test name
Test status
Simulation time 1317220185 ps
CPU time 34.03 seconds
Started Apr 25 12:53:50 PM PDT 24
Finished Apr 25 12:54:26 PM PDT 24
Peak memory 221100 kb
Host smart-8d216538-a9b7-44c4-ae35-f46ec1942785
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161233567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.4161233567
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.2605860073
Short name T704
Test name
Test status
Simulation time 46215414 ps
CPU time 3.12 seconds
Started Apr 25 12:53:46 PM PDT 24
Finished Apr 25 12:53:50 PM PDT 24
Peak memory 218328 kb
Host smart-5b6d0101-8bbd-417b-a36d-06967b34b611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605860073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.2605860073
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.4146059061
Short name T162
Test name
Test status
Simulation time 251492440 ps
CPU time 2.71 seconds
Started Apr 25 12:53:59 PM PDT 24
Finished Apr 25 12:54:06 PM PDT 24
Peak memory 209540 kb
Host smart-9eccb77f-daea-449b-90ef-bb0216e60d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146059061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.4146059061
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.2843384824
Short name T551
Test name
Test status
Simulation time 18584457 ps
CPU time 0.72 seconds
Started Apr 25 12:53:39 PM PDT 24
Finished Apr 25 12:53:41 PM PDT 24
Peak memory 205732 kb
Host smart-d310683d-3e14-4461-90b0-504d74e4b999
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843384824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.2843384824
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.2719062146
Short name T248
Test name
Test status
Simulation time 56917207 ps
CPU time 4.12 seconds
Started Apr 25 12:53:51 PM PDT 24
Finished Apr 25 12:53:56 PM PDT 24
Peak memory 214136 kb
Host smart-23b5b192-ec39-4931-85f9-4e0b0f6a5007
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2719062146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.2719062146
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.1492527782
Short name T757
Test name
Test status
Simulation time 105518987 ps
CPU time 3.23 seconds
Started Apr 25 12:53:42 PM PDT 24
Finished Apr 25 12:53:46 PM PDT 24
Peak memory 210344 kb
Host smart-026855e2-d69d-4695-a27d-d5486e5e1ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492527782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.1492527782
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.490220758
Short name T337
Test name
Test status
Simulation time 38616819 ps
CPU time 2.12 seconds
Started Apr 25 12:53:44 PM PDT 24
Finished Apr 25 12:53:48 PM PDT 24
Peak memory 209148 kb
Host smart-d4362332-220c-46fb-b9f1-53e2b1187a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490220758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.490220758
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.3511928205
Short name T510
Test name
Test status
Simulation time 196791543 ps
CPU time 3.61 seconds
Started Apr 25 12:53:50 PM PDT 24
Finished Apr 25 12:53:55 PM PDT 24
Peak memory 208376 kb
Host smart-33e67b45-f352-4ab7-b7c1-09e904d804a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511928205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.3511928205
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.3199034820
Short name T194
Test name
Test status
Simulation time 657593038 ps
CPU time 8.06 seconds
Started Apr 25 12:53:57 PM PDT 24
Finished Apr 25 12:54:08 PM PDT 24
Peak memory 214080 kb
Host smart-2f35bad8-8451-473e-82ac-12d439131f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199034820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.3199034820
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.3981341064
Short name T640
Test name
Test status
Simulation time 57485512 ps
CPU time 2.39 seconds
Started Apr 25 12:54:00 PM PDT 24
Finished Apr 25 12:54:07 PM PDT 24
Peak memory 215084 kb
Host smart-a8fcf81c-6c35-420c-9834-f57a258fe3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981341064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.3981341064
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.2390574335
Short name T523
Test name
Test status
Simulation time 109998180 ps
CPU time 3.39 seconds
Started Apr 25 12:53:49 PM PDT 24
Finished Apr 25 12:53:54 PM PDT 24
Peak memory 206944 kb
Host smart-192cb701-98b7-4ec7-a120-bf344258ff68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390574335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.2390574335
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.2559938025
Short name T742
Test name
Test status
Simulation time 206611779 ps
CPU time 4.62 seconds
Started Apr 25 12:53:59 PM PDT 24
Finished Apr 25 12:54:08 PM PDT 24
Peak memory 206488 kb
Host smart-a9a822b8-4701-4f12-b91c-e00fb3ec279d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559938025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.2559938025
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.179070049
Short name T486
Test name
Test status
Simulation time 166453020 ps
CPU time 2.5 seconds
Started Apr 25 12:53:53 PM PDT 24
Finished Apr 25 12:53:57 PM PDT 24
Peak memory 206460 kb
Host smart-33a90ba9-29b9-40ab-b370-319e1fce3caa
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179070049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.179070049
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.616344514
Short name T438
Test name
Test status
Simulation time 11309550860 ps
CPU time 23.69 seconds
Started Apr 25 12:54:04 PM PDT 24
Finished Apr 25 12:54:31 PM PDT 24
Peak memory 208088 kb
Host smart-6492df77-2b53-4068-8334-b3a470b485a1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616344514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.616344514
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.1452024198
Short name T528
Test name
Test status
Simulation time 597115071 ps
CPU time 5.04 seconds
Started Apr 25 12:53:59 PM PDT 24
Finished Apr 25 12:54:08 PM PDT 24
Peak memory 208272 kb
Host smart-29dc3dab-d92e-4dc3-a9d1-5bb92733a8b3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452024198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.1452024198
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.2588582639
Short name T41
Test name
Test status
Simulation time 840444663 ps
CPU time 3.18 seconds
Started Apr 25 12:53:52 PM PDT 24
Finished Apr 25 12:53:57 PM PDT 24
Peak memory 208724 kb
Host smart-012579dc-dab3-4402-9c22-c2878e65e8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588582639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.2588582639
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.2550529995
Short name T565
Test name
Test status
Simulation time 48611637 ps
CPU time 2.43 seconds
Started Apr 25 12:53:49 PM PDT 24
Finished Apr 25 12:53:53 PM PDT 24
Peak memory 207744 kb
Host smart-2930b187-69bd-408b-8f11-a1cdd6974a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550529995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.2550529995
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.2535192624
Short name T170
Test name
Test status
Simulation time 568133663 ps
CPU time 22.33 seconds
Started Apr 25 12:53:47 PM PDT 24
Finished Apr 25 12:54:10 PM PDT 24
Peak memory 220348 kb
Host smart-ac1a2f1e-a9c8-45f5-bfa0-00cac41885a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535192624 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.2535192624
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.3872976017
Short name T616
Test name
Test status
Simulation time 199671328 ps
CPU time 5.73 seconds
Started Apr 25 12:53:45 PM PDT 24
Finished Apr 25 12:53:52 PM PDT 24
Peak memory 217944 kb
Host smart-e626fcc1-7c27-4ba6-aa66-dccb3f38b176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872976017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.3872976017
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.1357301903
Short name T849
Test name
Test status
Simulation time 82985581 ps
CPU time 2.42 seconds
Started Apr 25 12:53:48 PM PDT 24
Finished Apr 25 12:53:52 PM PDT 24
Peak memory 209720 kb
Host smart-37bdce34-a684-464a-b045-67fe0ace3720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357301903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.1357301903
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.361520555
Short name T436
Test name
Test status
Simulation time 55026133 ps
CPU time 0.79 seconds
Started Apr 25 12:53:57 PM PDT 24
Finished Apr 25 12:54:00 PM PDT 24
Peak memory 205616 kb
Host smart-f2acc260-fce7-4f38-b67a-80798f544fa4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361520555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.361520555
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.2332624014
Short name T749
Test name
Test status
Simulation time 3188767043 ps
CPU time 5.84 seconds
Started Apr 25 12:53:42 PM PDT 24
Finished Apr 25 12:53:49 PM PDT 24
Peak memory 222240 kb
Host smart-3a0700e3-4947-4ea4-8d5e-80e53ccb0a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332624014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.2332624014
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.297873590
Short name T412
Test name
Test status
Simulation time 106140873 ps
CPU time 2.15 seconds
Started Apr 25 12:53:47 PM PDT 24
Finished Apr 25 12:53:50 PM PDT 24
Peak memory 209512 kb
Host smart-80ff871f-dd42-417d-83c0-794069ab8c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297873590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.297873590
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.4260777451
Short name T532
Test name
Test status
Simulation time 100816373 ps
CPU time 4.39 seconds
Started Apr 25 12:53:58 PM PDT 24
Finished Apr 25 12:54:07 PM PDT 24
Peak memory 221000 kb
Host smart-39d9d8df-8906-4fec-9b66-5930cd8dfe65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260777451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.4260777451
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.3570542933
Short name T272
Test name
Test status
Simulation time 2038034668 ps
CPU time 56.19 seconds
Started Apr 25 12:53:44 PM PDT 24
Finished Apr 25 12:54:41 PM PDT 24
Peak memory 225148 kb
Host smart-2b7d54b3-0f7e-4885-b70d-ee5577dea967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570542933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.3570542933
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_random.443585073
Short name T600
Test name
Test status
Simulation time 298288480 ps
CPU time 5.08 seconds
Started Apr 25 12:53:43 PM PDT 24
Finished Apr 25 12:53:50 PM PDT 24
Peak memory 208640 kb
Host smart-5a98e013-28d3-4c65-9077-68bfa1d98c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443585073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.443585073
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.3917481920
Short name T278
Test name
Test status
Simulation time 177998720 ps
CPU time 4.15 seconds
Started Apr 25 12:53:53 PM PDT 24
Finished Apr 25 12:53:59 PM PDT 24
Peak memory 208004 kb
Host smart-18c58b41-e8f3-49b1-b812-17318e3ebda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917481920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.3917481920
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.3669284296
Short name T329
Test name
Test status
Simulation time 299192538 ps
CPU time 4.2 seconds
Started Apr 25 12:54:00 PM PDT 24
Finished Apr 25 12:54:08 PM PDT 24
Peak memory 208360 kb
Host smart-eae8af72-7f11-4f09-9797-047318afdcd4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669284296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.3669284296
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.2353004125
Short name T783
Test name
Test status
Simulation time 179068694 ps
CPU time 5.26 seconds
Started Apr 25 12:53:49 PM PDT 24
Finished Apr 25 12:53:56 PM PDT 24
Peak memory 208216 kb
Host smart-c58b2b2b-6724-4b1c-88cc-7acd8dca5bb7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353004125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.2353004125
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.291160654
Short name T594
Test name
Test status
Simulation time 64425810 ps
CPU time 3.02 seconds
Started Apr 25 12:54:01 PM PDT 24
Finished Apr 25 12:54:09 PM PDT 24
Peak memory 208312 kb
Host smart-d5c01411-7abe-45a2-a93e-722a31b0414c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291160654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.291160654
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.2797381485
Short name T739
Test name
Test status
Simulation time 250093867 ps
CPU time 6.25 seconds
Started Apr 25 12:53:53 PM PDT 24
Finished Apr 25 12:54:01 PM PDT 24
Peak memory 208208 kb
Host smart-63c98b9e-88ca-4b52-9b7e-c92082456a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797381485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.2797381485
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.3401988786
Short name T797
Test name
Test status
Simulation time 754298233 ps
CPU time 19.67 seconds
Started Apr 25 12:53:47 PM PDT 24
Finished Apr 25 12:54:08 PM PDT 24
Peak memory 207604 kb
Host smart-2ef5217a-e50b-4fd5-ad91-a26f80aa43d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401988786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.3401988786
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.2834688289
Short name T213
Test name
Test status
Simulation time 2781258029 ps
CPU time 28.2 seconds
Started Apr 25 12:54:00 PM PDT 24
Finished Apr 25 12:54:33 PM PDT 24
Peak memory 216048 kb
Host smart-0e0af606-d8b7-47b5-9b2e-d33d0748f56b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834688289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.2834688289
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.272508880
Short name T233
Test name
Test status
Simulation time 95497116 ps
CPU time 4 seconds
Started Apr 25 12:53:53 PM PDT 24
Finished Apr 25 12:53:59 PM PDT 24
Peak memory 208980 kb
Host smart-41af70d5-7f40-4344-855f-48bb6848be53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272508880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.272508880
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.1923601667
Short name T572
Test name
Test status
Simulation time 54743009 ps
CPU time 1.91 seconds
Started Apr 25 12:53:47 PM PDT 24
Finished Apr 25 12:53:50 PM PDT 24
Peak memory 209824 kb
Host smart-2c3fa4b8-3abe-4457-a39c-0980337d3779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923601667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.1923601667
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.2656486099
Short name T768
Test name
Test status
Simulation time 30760185 ps
CPU time 0.91 seconds
Started Apr 25 12:53:50 PM PDT 24
Finished Apr 25 12:53:52 PM PDT 24
Peak memory 205860 kb
Host smart-80349a1d-fd6e-4a36-aa9a-7808414ccc56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656486099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.2656486099
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.2938396486
Short name T415
Test name
Test status
Simulation time 18641089679 ps
CPU time 67.79 seconds
Started Apr 25 12:53:58 PM PDT 24
Finished Apr 25 12:55:09 PM PDT 24
Peak memory 217384 kb
Host smart-bccf601f-e911-4f35-8bd9-215fbc335388
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2938396486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.2938396486
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.293331902
Short name T674
Test name
Test status
Simulation time 172073876 ps
CPU time 2.92 seconds
Started Apr 25 12:54:00 PM PDT 24
Finished Apr 25 12:54:08 PM PDT 24
Peak memory 209836 kb
Host smart-d79cfb20-49c7-4c24-8fdb-1c018ade9dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293331902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.293331902
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.2470324778
Short name T535
Test name
Test status
Simulation time 248682167 ps
CPU time 3.02 seconds
Started Apr 25 12:53:56 PM PDT 24
Finished Apr 25 12:54:01 PM PDT 24
Peak memory 209104 kb
Host smart-a3c74ac1-5abb-415a-8137-97949c205f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470324778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.2470324778
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.2648685912
Short name T881
Test name
Test status
Simulation time 203611532 ps
CPU time 5 seconds
Started Apr 25 12:53:52 PM PDT 24
Finished Apr 25 12:53:58 PM PDT 24
Peak memory 209592 kb
Host smart-8051c517-2482-49b4-a993-118df7c134bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648685912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.2648685912
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.1620367498
Short name T855
Test name
Test status
Simulation time 115000669 ps
CPU time 2.55 seconds
Started Apr 25 12:54:00 PM PDT 24
Finished Apr 25 12:54:06 PM PDT 24
Peak memory 209404 kb
Host smart-3e8657ed-c47b-463c-ba5a-24fed7787785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620367498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.1620367498
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.2253623399
Short name T829
Test name
Test status
Simulation time 192030108 ps
CPU time 4.46 seconds
Started Apr 25 12:53:57 PM PDT 24
Finished Apr 25 12:54:04 PM PDT 24
Peak memory 214072 kb
Host smart-fa58c8c1-9598-4dbc-b6f0-0ac16d414ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253623399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.2253623399
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.1784659130
Short name T281
Test name
Test status
Simulation time 2339359846 ps
CPU time 79.21 seconds
Started Apr 25 12:53:53 PM PDT 24
Finished Apr 25 12:55:14 PM PDT 24
Peak memory 222232 kb
Host smart-e8adc593-54b3-4ce5-ad8d-76eb1257bbc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784659130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.1784659130
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.942954178
Short name T663
Test name
Test status
Simulation time 124901686 ps
CPU time 4.32 seconds
Started Apr 25 12:54:00 PM PDT 24
Finished Apr 25 12:54:08 PM PDT 24
Peak memory 208512 kb
Host smart-def2cdcf-f5aa-4762-9674-72b0c0695d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942954178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.942954178
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.343735566
Short name T453
Test name
Test status
Simulation time 147886671 ps
CPU time 3.35 seconds
Started Apr 25 12:54:04 PM PDT 24
Finished Apr 25 12:54:12 PM PDT 24
Peak memory 208248 kb
Host smart-43173daf-9905-47c7-becb-603029698b9a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343735566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.343735566
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.4210694538
Short name T335
Test name
Test status
Simulation time 1998902440 ps
CPU time 4.27 seconds
Started Apr 25 12:53:56 PM PDT 24
Finished Apr 25 12:54:14 PM PDT 24
Peak memory 206600 kb
Host smart-51cea4cb-70b1-40e3-99a1-f2f375266aa8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210694538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.4210694538
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.1050478736
Short name T866
Test name
Test status
Simulation time 94351622 ps
CPU time 3.26 seconds
Started Apr 25 12:54:08 PM PDT 24
Finished Apr 25 12:54:15 PM PDT 24
Peak memory 208304 kb
Host smart-ba73c568-3a03-4893-8c6a-b1382c7f243d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050478736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.1050478736
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.3225565277
Short name T820
Test name
Test status
Simulation time 130286570 ps
CPU time 3.67 seconds
Started Apr 25 12:53:57 PM PDT 24
Finished Apr 25 12:54:04 PM PDT 24
Peak memory 209280 kb
Host smart-a058e824-f30d-4758-96e1-e01e0e969055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225565277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.3225565277
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.4058467198
Short name T402
Test name
Test status
Simulation time 50462619 ps
CPU time 2.8 seconds
Started Apr 25 12:53:51 PM PDT 24
Finished Apr 25 12:53:55 PM PDT 24
Peak memory 206228 kb
Host smart-ba51c1f1-57f9-4867-add5-cb728a5e25cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058467198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.4058467198
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.3548169147
Short name T550
Test name
Test status
Simulation time 107195206 ps
CPU time 4.52 seconds
Started Apr 25 12:54:07 PM PDT 24
Finished Apr 25 12:54:15 PM PDT 24
Peak memory 208452 kb
Host smart-2a654f44-4845-4eaa-9248-55d732b615b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548169147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.3548169147
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.2937770684
Short name T834
Test name
Test status
Simulation time 211941340 ps
CPU time 6.67 seconds
Started Apr 25 12:53:58 PM PDT 24
Finished Apr 25 12:54:09 PM PDT 24
Peak memory 222436 kb
Host smart-c96bc207-7e9d-43cb-bf89-efe6c8442b14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937770684 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.2937770684
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.3865864979
Short name T536
Test name
Test status
Simulation time 153857433 ps
CPU time 4.05 seconds
Started Apr 25 12:53:54 PM PDT 24
Finished Apr 25 12:54:01 PM PDT 24
Peak memory 207200 kb
Host smart-ff6136ab-d500-48a7-8003-a702856b5beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865864979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.3865864979
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.1629879771
Short name T58
Test name
Test status
Simulation time 80775972 ps
CPU time 2.83 seconds
Started Apr 25 12:53:50 PM PDT 24
Finished Apr 25 12:53:55 PM PDT 24
Peak memory 209948 kb
Host smart-64e325f8-8890-455d-a1c4-6248fe58c740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629879771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.1629879771
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.3739217844
Short name T420
Test name
Test status
Simulation time 45154416 ps
CPU time 0.78 seconds
Started Apr 25 12:54:04 PM PDT 24
Finished Apr 25 12:54:08 PM PDT 24
Peak memory 205624 kb
Host smart-18c94442-c076-4864-a9c8-4513469875ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739217844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.3739217844
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.610455418
Short name T243
Test name
Test status
Simulation time 374163467 ps
CPU time 5.71 seconds
Started Apr 25 12:53:59 PM PDT 24
Finished Apr 25 12:54:09 PM PDT 24
Peak memory 214588 kb
Host smart-ce980997-d898-4bed-b889-b94ca47ff7ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=610455418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.610455418
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.290494755
Short name T498
Test name
Test status
Simulation time 295406875 ps
CPU time 3.84 seconds
Started Apr 25 12:53:58 PM PDT 24
Finished Apr 25 12:54:06 PM PDT 24
Peak memory 214308 kb
Host smart-55573905-d5d6-40ab-af88-a5ec2920ba71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290494755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.290494755
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.2178371024
Short name T633
Test name
Test status
Simulation time 944315516 ps
CPU time 13.62 seconds
Started Apr 25 12:53:58 PM PDT 24
Finished Apr 25 12:54:15 PM PDT 24
Peak memory 209744 kb
Host smart-9fb29a77-878c-40d2-8e75-57725ad33ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178371024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.2178371024
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.3590412903
Short name T583
Test name
Test status
Simulation time 723170085 ps
CPU time 10.2 seconds
Started Apr 25 12:53:57 PM PDT 24
Finished Apr 25 12:54:11 PM PDT 24
Peak memory 214124 kb
Host smart-cc87327b-3036-4a8b-8587-2738eee53b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590412903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.3590412903
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.2237701684
Short name T811
Test name
Test status
Simulation time 444317174 ps
CPU time 4.89 seconds
Started Apr 25 12:53:53 PM PDT 24
Finished Apr 25 12:54:00 PM PDT 24
Peak memory 209372 kb
Host smart-3a7d11d7-371d-43b7-97bc-4c5fb91daebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237701684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.2237701684
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.12975535
Short name T266
Test name
Test status
Simulation time 211097776 ps
CPU time 5.18 seconds
Started Apr 25 12:53:57 PM PDT 24
Finished Apr 25 12:54:05 PM PDT 24
Peak memory 216092 kb
Host smart-11b29720-c269-49c9-adf5-12985ceefde8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12975535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.12975535
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.1790608238
Short name T812
Test name
Test status
Simulation time 335756886 ps
CPU time 4.19 seconds
Started Apr 25 12:54:14 PM PDT 24
Finished Apr 25 12:54:22 PM PDT 24
Peak memory 207116 kb
Host smart-18b5c8aa-83b8-4aa1-a9ac-309d7bdb13b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790608238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.1790608238
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.3306139265
Short name T199
Test name
Test status
Simulation time 118137826 ps
CPU time 4.19 seconds
Started Apr 25 12:54:00 PM PDT 24
Finished Apr 25 12:54:09 PM PDT 24
Peak memory 208240 kb
Host smart-96636dc9-c0dc-4c12-98d5-2d8855e332ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306139265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.3306139265
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.3466908630
Short name T745
Test name
Test status
Simulation time 248894260 ps
CPU time 3.33 seconds
Started Apr 25 12:53:45 PM PDT 24
Finished Apr 25 12:53:49 PM PDT 24
Peak memory 208580 kb
Host smart-8bf9418b-1cb7-4880-8313-4b06f096d1a1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466908630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.3466908630
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.1026910924
Short name T873
Test name
Test status
Simulation time 148164365 ps
CPU time 2.36 seconds
Started Apr 25 12:53:52 PM PDT 24
Finished Apr 25 12:53:56 PM PDT 24
Peak memory 206568 kb
Host smart-0ed44fce-e4a9-4a6e-9fe1-53d5c5fa8c2f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026910924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.1026910924
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.3610663615
Short name T701
Test name
Test status
Simulation time 6924475880 ps
CPU time 34.13 seconds
Started Apr 25 12:54:03 PM PDT 24
Finished Apr 25 12:54:41 PM PDT 24
Peak memory 207860 kb
Host smart-6695ecb9-ea6c-4f00-97ba-11056fbeac67
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610663615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.3610663615
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.479739065
Short name T575
Test name
Test status
Simulation time 46309801 ps
CPU time 2.17 seconds
Started Apr 25 12:53:57 PM PDT 24
Finished Apr 25 12:54:02 PM PDT 24
Peak memory 214096 kb
Host smart-5c183325-3e20-4dbb-b99c-86dbdc23ca7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479739065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.479739065
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.124221227
Short name T451
Test name
Test status
Simulation time 23163077 ps
CPU time 1.81 seconds
Started Apr 25 12:53:58 PM PDT 24
Finished Apr 25 12:54:04 PM PDT 24
Peak memory 206432 kb
Host smart-5c81dca6-5491-461a-a0e5-91202ea878a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124221227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.124221227
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.4258091663
Short name T210
Test name
Test status
Simulation time 5605419507 ps
CPU time 128.4 seconds
Started Apr 25 12:53:58 PM PDT 24
Finished Apr 25 12:56:10 PM PDT 24
Peak memory 216104 kb
Host smart-2ae1a7c0-ca9d-408f-a45c-3c505f17129b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258091663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.4258091663
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.2929453787
Short name T816
Test name
Test status
Simulation time 114094603 ps
CPU time 4.37 seconds
Started Apr 25 12:53:54 PM PDT 24
Finished Apr 25 12:54:00 PM PDT 24
Peak memory 207904 kb
Host smart-3840147c-e7af-4c70-926b-031914ed5d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929453787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.2929453787
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.282934964
Short name T507
Test name
Test status
Simulation time 556544172 ps
CPU time 3.44 seconds
Started Apr 25 12:53:55 PM PDT 24
Finished Apr 25 12:54:00 PM PDT 24
Peak memory 210344 kb
Host smart-6e145668-614b-4502-8472-dcc9a4985406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282934964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.282934964
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.1450698275
Short name T487
Test name
Test status
Simulation time 16378034 ps
CPU time 0.8 seconds
Started Apr 25 12:54:08 PM PDT 24
Finished Apr 25 12:54:12 PM PDT 24
Peak memory 205712 kb
Host smart-ab8e6c58-0926-4cea-ab34-52030662cc7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450698275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.1450698275
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.1608936413
Short name T446
Test name
Test status
Simulation time 137402280 ps
CPU time 1.92 seconds
Started Apr 25 12:54:03 PM PDT 24
Finished Apr 25 12:54:09 PM PDT 24
Peak memory 209076 kb
Host smart-cb7759af-279c-432f-8497-33d6d2bb3c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608936413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.1608936413
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.2167025322
Short name T747
Test name
Test status
Simulation time 318151054 ps
CPU time 6.33 seconds
Started Apr 25 12:54:09 PM PDT 24
Finished Apr 25 12:54:18 PM PDT 24
Peak memory 208948 kb
Host smart-b7723653-2ff5-4ba8-a739-2b895869ea46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167025322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.2167025322
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.863156640
Short name T44
Test name
Test status
Simulation time 75782270 ps
CPU time 3.42 seconds
Started Apr 25 12:54:03 PM PDT 24
Finished Apr 25 12:54:11 PM PDT 24
Peak memory 209516 kb
Host smart-d989d5bc-fd09-4fe4-8d5b-b37326776473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863156640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.863156640
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.577251208
Short name T810
Test name
Test status
Simulation time 147565202 ps
CPU time 4.87 seconds
Started Apr 25 12:54:03 PM PDT 24
Finished Apr 25 12:54:12 PM PDT 24
Peak memory 209144 kb
Host smart-7547f8b2-7a9b-455d-8662-7a89205735a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577251208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.577251208
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.901250121
Short name T591
Test name
Test status
Simulation time 787658040 ps
CPU time 3.93 seconds
Started Apr 25 12:54:01 PM PDT 24
Finished Apr 25 12:54:09 PM PDT 24
Peak memory 206424 kb
Host smart-e9a50488-393c-4dd6-856e-302a24e6886a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901250121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.901250121
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.4152609145
Short name T623
Test name
Test status
Simulation time 280335115 ps
CPU time 4.35 seconds
Started Apr 25 12:54:10 PM PDT 24
Finished Apr 25 12:54:18 PM PDT 24
Peak memory 206448 kb
Host smart-1e4ccb87-2e7c-4555-ac21-e025d6700845
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152609145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.4152609145
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.4045263486
Short name T582
Test name
Test status
Simulation time 553313269 ps
CPU time 4.38 seconds
Started Apr 25 12:53:55 PM PDT 24
Finished Apr 25 12:54:01 PM PDT 24
Peak memory 206876 kb
Host smart-e9d98295-35cf-41ff-9e01-74c46b747a8c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045263486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.4045263486
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.4050777046
Short name T612
Test name
Test status
Simulation time 27014684 ps
CPU time 1.8 seconds
Started Apr 25 12:54:16 PM PDT 24
Finished Apr 25 12:54:22 PM PDT 24
Peak memory 206572 kb
Host smart-01e04a93-f645-4dc9-a0de-35f2f73f857d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050777046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.4050777046
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.3463372405
Short name T187
Test name
Test status
Simulation time 99954247 ps
CPU time 2.09 seconds
Started Apr 25 12:54:00 PM PDT 24
Finished Apr 25 12:54:06 PM PDT 24
Peak memory 214060 kb
Host smart-9ae1f69a-d429-402a-97f2-ab7d1d660474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463372405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.3463372405
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.28301211
Short name T787
Test name
Test status
Simulation time 292114054 ps
CPU time 2.47 seconds
Started Apr 25 12:54:00 PM PDT 24
Finished Apr 25 12:54:07 PM PDT 24
Peak memory 206228 kb
Host smart-68227cb4-7d54-4582-85de-05e3f52f2314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28301211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.28301211
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.1991722746
Short name T638
Test name
Test status
Simulation time 73519217 ps
CPU time 2.7 seconds
Started Apr 25 12:54:06 PM PDT 24
Finished Apr 25 12:54:12 PM PDT 24
Peak memory 207856 kb
Host smart-f0152806-c442-4706-9b45-c82937c9d6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991722746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.1991722746
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.755428077
Short name T172
Test name
Test status
Simulation time 150576973 ps
CPU time 2.51 seconds
Started Apr 25 12:54:05 PM PDT 24
Finished Apr 25 12:54:11 PM PDT 24
Peak memory 209748 kb
Host smart-16a23021-6b6d-431c-9c77-6b61b39be0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755428077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.755428077
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.1319632332
Short name T752
Test name
Test status
Simulation time 36216529 ps
CPU time 0.79 seconds
Started Apr 25 12:53:55 PM PDT 24
Finished Apr 25 12:53:58 PM PDT 24
Peak memory 205572 kb
Host smart-8f3eeece-a812-48a6-a5f3-bc7fcd7ff4db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319632332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.1319632332
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.671293688
Short name T22
Test name
Test status
Simulation time 267934351 ps
CPU time 5.53 seconds
Started Apr 25 12:54:00 PM PDT 24
Finished Apr 25 12:54:10 PM PDT 24
Peak memory 222496 kb
Host smart-01b14e96-bb3d-4dd4-8aa7-1fafb4b793c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671293688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.671293688
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.3664009832
Short name T755
Test name
Test status
Simulation time 320345096 ps
CPU time 3.38 seconds
Started Apr 25 12:54:03 PM PDT 24
Finished Apr 25 12:54:10 PM PDT 24
Peak memory 210036 kb
Host smart-2870dbf5-43ae-4a29-8d93-bdf45589e217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664009832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.3664009832
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.1469413920
Short name T110
Test name
Test status
Simulation time 331060910 ps
CPU time 2.28 seconds
Started Apr 25 12:53:48 PM PDT 24
Finished Apr 25 12:53:52 PM PDT 24
Peak memory 208708 kb
Host smart-6f5593fe-47a6-4392-a73d-fdf276f6fba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469413920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.1469413920
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.2153300193
Short name T237
Test name
Test status
Simulation time 4830274970 ps
CPU time 23.33 seconds
Started Apr 25 12:54:21 PM PDT 24
Finished Apr 25 12:54:48 PM PDT 24
Peak memory 222292 kb
Host smart-ab98757c-48a9-4ed3-a28a-d92f7f0243d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153300193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.2153300193
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.1125978937
Short name T6
Test name
Test status
Simulation time 598870176 ps
CPU time 4.25 seconds
Started Apr 25 12:53:59 PM PDT 24
Finished Apr 25 12:54:08 PM PDT 24
Peak memory 215324 kb
Host smart-21a4e4b8-23dd-45ca-85fc-f2f41651d342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125978937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.1125978937
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.371886040
Short name T298
Test name
Test status
Simulation time 395117268 ps
CPU time 4.44 seconds
Started Apr 25 12:53:57 PM PDT 24
Finished Apr 25 12:54:04 PM PDT 24
Peak memory 214048 kb
Host smart-cd230878-6846-40ff-b329-5f5182d43333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371886040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.371886040
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.2786177265
Short name T694
Test name
Test status
Simulation time 823582554 ps
CPU time 6.21 seconds
Started Apr 25 12:54:27 PM PDT 24
Finished Apr 25 12:54:37 PM PDT 24
Peak memory 207132 kb
Host smart-bffc2401-52de-4891-be3d-8daa36d0385d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786177265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.2786177265
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.4234423926
Short name T625
Test name
Test status
Simulation time 210231351 ps
CPU time 4.78 seconds
Started Apr 25 12:54:11 PM PDT 24
Finished Apr 25 12:54:19 PM PDT 24
Peak memory 206608 kb
Host smart-65384da9-e070-45a6-b25c-ccfdc5c28123
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234423926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.4234423926
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.4099817583
Short name T435
Test name
Test status
Simulation time 260861107 ps
CPU time 5.52 seconds
Started Apr 25 12:54:04 PM PDT 24
Finished Apr 25 12:54:13 PM PDT 24
Peak memory 206556 kb
Host smart-33a82432-11c9-41ae-a5fe-c87bf3cd4086
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099817583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.4099817583
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.2689139627
Short name T775
Test name
Test status
Simulation time 7915846051 ps
CPU time 81.23 seconds
Started Apr 25 12:54:11 PM PDT 24
Finished Apr 25 12:55:36 PM PDT 24
Peak memory 208252 kb
Host smart-839b2889-077a-401f-b8f5-727380a8d9fc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689139627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.2689139627
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.3230510108
Short name T472
Test name
Test status
Simulation time 357916462 ps
CPU time 2.46 seconds
Started Apr 25 12:53:54 PM PDT 24
Finished Apr 25 12:53:59 PM PDT 24
Peak memory 208988 kb
Host smart-566b32e3-642b-4821-9344-7caab195635a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230510108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.3230510108
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.2416782097
Short name T1
Test name
Test status
Simulation time 98333790 ps
CPU time 2.62 seconds
Started Apr 25 12:54:17 PM PDT 24
Finished Apr 25 12:54:24 PM PDT 24
Peak memory 207676 kb
Host smart-c7319149-5a13-4830-8121-c6f1d8aa3673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416782097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.2416782097
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.1701401887
Short name T573
Test name
Test status
Simulation time 192407917 ps
CPU time 5.43 seconds
Started Apr 25 12:54:03 PM PDT 24
Finished Apr 25 12:54:12 PM PDT 24
Peak memory 207128 kb
Host smart-40f883d8-3527-4a61-b5fc-b4c24a87c07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701401887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.1701401887
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.2478260769
Short name T158
Test name
Test status
Simulation time 233524749 ps
CPU time 2.8 seconds
Started Apr 25 12:54:02 PM PDT 24
Finished Apr 25 12:54:09 PM PDT 24
Peak memory 209576 kb
Host smart-ae5082b4-086a-45b5-b96e-17faf9c7e956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478260769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.2478260769
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.2189236261
Short name T858
Test name
Test status
Simulation time 67011702 ps
CPU time 0.77 seconds
Started Apr 25 12:53:58 PM PDT 24
Finished Apr 25 12:54:03 PM PDT 24
Peak memory 205692 kb
Host smart-13e7cb65-de80-4b1c-9eea-8df8a50cbcec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189236261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.2189236261
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.457272971
Short name T38
Test name
Test status
Simulation time 404982929 ps
CPU time 3.86 seconds
Started Apr 25 12:54:00 PM PDT 24
Finished Apr 25 12:54:08 PM PDT 24
Peak memory 217976 kb
Host smart-998b3191-6931-493f-a823-7ae014d5a603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457272971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.457272971
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.41021870
Short name T484
Test name
Test status
Simulation time 46454849 ps
CPU time 2.43 seconds
Started Apr 25 12:53:59 PM PDT 24
Finished Apr 25 12:54:06 PM PDT 24
Peak memory 208940 kb
Host smart-4d0e8dd1-e76e-42bc-9e80-8987a05503f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41021870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.41021870
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.2757979388
Short name T681
Test name
Test status
Simulation time 862811243 ps
CPU time 20.7 seconds
Started Apr 25 12:53:59 PM PDT 24
Finished Apr 25 12:54:24 PM PDT 24
Peak memory 214000 kb
Host smart-b74d3a43-9c36-4dab-b52c-3a47b3a5168b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757979388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.2757979388
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.2267748593
Short name T545
Test name
Test status
Simulation time 451564466 ps
CPU time 5.7 seconds
Started Apr 25 12:53:59 PM PDT 24
Finished Apr 25 12:54:09 PM PDT 24
Peak memory 214164 kb
Host smart-8fca4eed-bd12-4e37-b0f6-e0585b58a924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267748593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.2267748593
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.4011083238
Short name T610
Test name
Test status
Simulation time 110490603 ps
CPU time 3.54 seconds
Started Apr 25 12:54:04 PM PDT 24
Finished Apr 25 12:54:11 PM PDT 24
Peak memory 209584 kb
Host smart-f3e20700-467d-4828-ad81-9c678c364feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011083238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.4011083238
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.2276587001
Short name T706
Test name
Test status
Simulation time 51814582 ps
CPU time 3.59 seconds
Started Apr 25 12:53:52 PM PDT 24
Finished Apr 25 12:54:03 PM PDT 24
Peak memory 209860 kb
Host smart-54b50b06-ee61-4754-9f4a-28b078e6430e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276587001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.2276587001
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.3726673128
Short name T595
Test name
Test status
Simulation time 187752845 ps
CPU time 6.07 seconds
Started Apr 25 12:54:04 PM PDT 24
Finished Apr 25 12:54:14 PM PDT 24
Peak memory 207660 kb
Host smart-c8c85026-1ea2-43ca-97c4-b3b5a4a65ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726673128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.3726673128
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.3303785716
Short name T557
Test name
Test status
Simulation time 105357924 ps
CPU time 3.6 seconds
Started Apr 25 12:54:07 PM PDT 24
Finished Apr 25 12:54:14 PM PDT 24
Peak memory 206616 kb
Host smart-3b7a0d13-123e-4d84-93e1-2d310947e382
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303785716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.3303785716
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.235234806
Short name T730
Test name
Test status
Simulation time 369374890 ps
CPU time 7.3 seconds
Started Apr 25 12:54:02 PM PDT 24
Finished Apr 25 12:54:14 PM PDT 24
Peak memory 206488 kb
Host smart-e8d28402-02b4-4b45-b7ff-002633905591
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235234806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.235234806
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.4152332263
Short name T784
Test name
Test status
Simulation time 7015956781 ps
CPU time 45.6 seconds
Started Apr 25 12:54:01 PM PDT 24
Finished Apr 25 12:54:51 PM PDT 24
Peak memory 208120 kb
Host smart-06486d66-a447-4ffe-b1b8-18ab00d90d13
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152332263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.4152332263
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.2699779009
Short name T815
Test name
Test status
Simulation time 166739671 ps
CPU time 2.35 seconds
Started Apr 25 12:54:02 PM PDT 24
Finished Apr 25 12:54:08 PM PDT 24
Peak memory 215468 kb
Host smart-ea2faf24-01c8-489c-a072-9053255dc495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699779009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.2699779009
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.3473727986
Short name T733
Test name
Test status
Simulation time 37882044 ps
CPU time 2.23 seconds
Started Apr 25 12:54:03 PM PDT 24
Finished Apr 25 12:54:09 PM PDT 24
Peak memory 206356 kb
Host smart-88856464-36e0-43f4-83eb-3523ce47c4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473727986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.3473727986
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.554547339
Short name T78
Test name
Test status
Simulation time 701236367 ps
CPU time 10.5 seconds
Started Apr 25 12:54:13 PM PDT 24
Finished Apr 25 12:54:27 PM PDT 24
Peak memory 222008 kb
Host smart-1fa9d7fd-f6a8-4ac6-bc92-4c95534675d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554547339 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.554547339
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.2148869227
Short name T899
Test name
Test status
Simulation time 185767526 ps
CPU time 6.94 seconds
Started Apr 25 12:54:13 PM PDT 24
Finished Apr 25 12:54:23 PM PDT 24
Peak memory 207072 kb
Host smart-3aa33045-3427-4413-83f9-cdccc868b411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148869227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.2148869227
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.1349779591
Short name T450
Test name
Test status
Simulation time 1152199169 ps
CPU time 3.45 seconds
Started Apr 25 12:54:03 PM PDT 24
Finished Apr 25 12:54:11 PM PDT 24
Peak memory 209596 kb
Host smart-429f8c26-4d4d-41a6-a29f-e0af1ab721fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349779591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.1349779591
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.2799583467
Short name T419
Test name
Test status
Simulation time 27313207 ps
CPU time 0.78 seconds
Started Apr 25 12:52:54 PM PDT 24
Finished Apr 25 12:52:56 PM PDT 24
Peak memory 205692 kb
Host smart-3dcb7394-e751-4ea7-9ea1-24c2b99b4b52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799583467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.2799583467
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.3109055080
Short name T131
Test name
Test status
Simulation time 6001159444 ps
CPU time 79.12 seconds
Started Apr 25 12:52:49 PM PDT 24
Finished Apr 25 12:54:10 PM PDT 24
Peak memory 219336 kb
Host smart-aec1fd2d-65e2-4e22-bdf0-dc5aa6966f97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3109055080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.3109055080
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.1492781916
Short name T570
Test name
Test status
Simulation time 720502308 ps
CPU time 5.87 seconds
Started Apr 25 12:52:48 PM PDT 24
Finished Apr 25 12:52:56 PM PDT 24
Peak memory 222596 kb
Host smart-b8d16917-6303-4b2d-9102-080d2f813dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492781916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.1492781916
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.2492793361
Short name T15
Test name
Test status
Simulation time 244984173 ps
CPU time 3 seconds
Started Apr 25 12:52:53 PM PDT 24
Finished Apr 25 12:52:57 PM PDT 24
Peak memory 207152 kb
Host smart-a8877c65-7350-402e-a5e1-ec442a566ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492793361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.2492793361
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.2380467457
Short name T256
Test name
Test status
Simulation time 876588475 ps
CPU time 4.41 seconds
Started Apr 25 12:52:53 PM PDT 24
Finished Apr 25 12:52:59 PM PDT 24
Peak memory 210496 kb
Host smart-d0676bf1-a4dc-4a37-95be-696a3bfd3175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380467457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.2380467457
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.3929872273
Short name T798
Test name
Test status
Simulation time 266306823 ps
CPU time 3.57 seconds
Started Apr 25 12:53:00 PM PDT 24
Finished Apr 25 12:53:05 PM PDT 24
Peak memory 214068 kb
Host smart-e15dd061-1fcb-48f3-aad6-eba9eca25c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929872273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.3929872273
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.3797081219
Short name T336
Test name
Test status
Simulation time 42509408 ps
CPU time 2.72 seconds
Started Apr 25 12:52:45 PM PDT 24
Finished Apr 25 12:52:49 PM PDT 24
Peak memory 207804 kb
Host smart-e85a81b0-b5c7-4a64-b4aa-d77b42935108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797081219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.3797081219
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sideload.3280847907
Short name T109
Test name
Test status
Simulation time 154155309 ps
CPU time 5.03 seconds
Started Apr 25 12:53:01 PM PDT 24
Finished Apr 25 12:53:07 PM PDT 24
Peak memory 208176 kb
Host smart-9f4c12ab-56ea-4e9e-8745-2d9156e262a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280847907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.3280847907
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.2061238493
Short name T649
Test name
Test status
Simulation time 136366708 ps
CPU time 3.46 seconds
Started Apr 25 12:52:59 PM PDT 24
Finished Apr 25 12:53:04 PM PDT 24
Peak memory 208748 kb
Host smart-8cca1fba-8db2-4d0f-b016-db42a1d3179e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061238493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.2061238493
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.1437256314
Short name T398
Test name
Test status
Simulation time 4700030900 ps
CPU time 12.39 seconds
Started Apr 25 12:52:47 PM PDT 24
Finished Apr 25 12:53:01 PM PDT 24
Peak memory 207700 kb
Host smart-9bf2d147-3dd8-4104-88a0-dfea31cff6bc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437256314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.1437256314
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.2043025434
Short name T399
Test name
Test status
Simulation time 155361967 ps
CPU time 3.1 seconds
Started Apr 25 12:52:59 PM PDT 24
Finished Apr 25 12:53:04 PM PDT 24
Peak memory 206408 kb
Host smart-90add955-9237-48dd-b8a8-a3c7d48be692
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043025434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.2043025434
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.3841727051
Short name T690
Test name
Test status
Simulation time 615622603 ps
CPU time 2.54 seconds
Started Apr 25 12:52:57 PM PDT 24
Finished Apr 25 12:53:00 PM PDT 24
Peak memory 209052 kb
Host smart-e9067a7b-7764-4683-bfe4-d5653aa044db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841727051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.3841727051
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.1236051252
Short name T626
Test name
Test status
Simulation time 39411796 ps
CPU time 1.71 seconds
Started Apr 25 12:52:49 PM PDT 24
Finished Apr 25 12:52:52 PM PDT 24
Peak memory 206352 kb
Host smart-9374bbe9-7c03-4c92-b04f-4bc62caefcdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236051252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.1236051252
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.531043956
Short name T216
Test name
Test status
Simulation time 5836621524 ps
CPU time 39.8 seconds
Started Apr 25 12:52:52 PM PDT 24
Finished Apr 25 12:53:33 PM PDT 24
Peak memory 215748 kb
Host smart-e893140b-fbd5-4302-8449-0ea3b023b73f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531043956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.531043956
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.704711600
Short name T101
Test name
Test status
Simulation time 163372562 ps
CPU time 5.6 seconds
Started Apr 25 12:52:50 PM PDT 24
Finished Apr 25 12:52:57 PM PDT 24
Peak memory 222428 kb
Host smart-d8390d15-67a6-4f0f-b221-87df0b0e59fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704711600 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.704711600
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.126463734
Short name T296
Test name
Test status
Simulation time 1231728735 ps
CPU time 24.15 seconds
Started Apr 25 12:52:58 PM PDT 24
Finished Apr 25 12:53:23 PM PDT 24
Peak memory 213996 kb
Host smart-cde6826c-746f-459a-b86c-63e2b53affa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126463734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.126463734
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.3259130823
Short name T75
Test name
Test status
Simulation time 167573290 ps
CPU time 3.41 seconds
Started Apr 25 12:52:48 PM PDT 24
Finished Apr 25 12:52:58 PM PDT 24
Peak memory 210416 kb
Host smart-42c39f0e-4c39-42eb-b74f-08da78b828c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259130823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.3259130823
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.2692978398
Short name T862
Test name
Test status
Simulation time 13343630 ps
CPU time 0.83 seconds
Started Apr 25 12:54:22 PM PDT 24
Finished Apr 25 12:54:26 PM PDT 24
Peak memory 205708 kb
Host smart-bf3a7b0c-0d0d-4c01-aea3-5b2ed3817da5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692978398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.2692978398
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.2693150681
Short name T360
Test name
Test status
Simulation time 154548468 ps
CPU time 8.23 seconds
Started Apr 25 12:54:09 PM PDT 24
Finished Apr 25 12:54:20 PM PDT 24
Peak memory 214128 kb
Host smart-427bed96-75a7-4e8f-94c2-9ab39fff4d33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2693150681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.2693150681
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.2106781578
Short name T83
Test name
Test status
Simulation time 92668910 ps
CPU time 3.94 seconds
Started Apr 25 12:54:09 PM PDT 24
Finished Apr 25 12:54:16 PM PDT 24
Peak memory 214168 kb
Host smart-db508ebf-b5fc-46c7-9852-f8649d80a994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106781578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.2106781578
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.577653212
Short name T92
Test name
Test status
Simulation time 50376019 ps
CPU time 3.27 seconds
Started Apr 25 12:54:15 PM PDT 24
Finished Apr 25 12:54:22 PM PDT 24
Peak memory 208876 kb
Host smart-4f32e73a-e635-4e41-a000-2c8541f0768f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577653212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.577653212
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.3674164262
Short name T286
Test name
Test status
Simulation time 5915211446 ps
CPU time 86.74 seconds
Started Apr 25 12:54:30 PM PDT 24
Finished Apr 25 12:56:00 PM PDT 24
Peak memory 245208 kb
Host smart-212955ab-52ac-405f-849b-ebf2a40577a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674164262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.3674164262
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.692260788
Short name T890
Test name
Test status
Simulation time 1080246911 ps
CPU time 3.25 seconds
Started Apr 25 12:54:15 PM PDT 24
Finished Apr 25 12:54:21 PM PDT 24
Peak memory 209732 kb
Host smart-c6753424-13c0-4953-972b-ba4c395d6c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692260788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.692260788
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.3189695499
Short name T778
Test name
Test status
Simulation time 461559036 ps
CPU time 5.07 seconds
Started Apr 25 12:54:05 PM PDT 24
Finished Apr 25 12:54:13 PM PDT 24
Peak memory 206940 kb
Host smart-a5b7ce01-27f1-42f8-a303-8c0a26a5a4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189695499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.3189695499
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.291312283
Short name T467
Test name
Test status
Simulation time 126660739 ps
CPU time 2.06 seconds
Started Apr 25 12:54:16 PM PDT 24
Finished Apr 25 12:54:22 PM PDT 24
Peak memory 208228 kb
Host smart-a41e2480-3ef9-405b-9480-ab41059f88f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291312283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.291312283
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.3573828328
Short name T471
Test name
Test status
Simulation time 164716576 ps
CPU time 3.25 seconds
Started Apr 25 12:54:01 PM PDT 24
Finished Apr 25 12:54:09 PM PDT 24
Peak memory 208120 kb
Host smart-e0db7636-f370-45e4-8adb-31ed7fb2cfc7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573828328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.3573828328
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.2600501828
Short name T567
Test name
Test status
Simulation time 102243213 ps
CPU time 2.24 seconds
Started Apr 25 12:54:14 PM PDT 24
Finished Apr 25 12:54:20 PM PDT 24
Peak memory 206504 kb
Host smart-2416be19-d5bb-4f57-8bcd-d385b73ca8ac
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600501828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.2600501828
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.3596057696
Short name T552
Test name
Test status
Simulation time 245263363 ps
CPU time 3.23 seconds
Started Apr 25 12:54:13 PM PDT 24
Finished Apr 25 12:54:20 PM PDT 24
Peak memory 208340 kb
Host smart-2218918e-a31b-4d56-8ab0-a821904516db
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596057696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.3596057696
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.4164445147
Short name T741
Test name
Test status
Simulation time 70490336 ps
CPU time 2.59 seconds
Started Apr 25 12:53:55 PM PDT 24
Finished Apr 25 12:54:00 PM PDT 24
Peak memory 209556 kb
Host smart-6aa30e88-dbfc-4af2-a286-188343fc6094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164445147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.4164445147
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.428329753
Short name T509
Test name
Test status
Simulation time 958863978 ps
CPU time 7.24 seconds
Started Apr 25 12:53:58 PM PDT 24
Finished Apr 25 12:54:09 PM PDT 24
Peak memory 207424 kb
Host smart-903b8911-1302-43ea-97b9-03ce5e6b7690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428329753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.428329753
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.2670998663
Short name T174
Test name
Test status
Simulation time 929275422 ps
CPU time 10.05 seconds
Started Apr 25 12:54:16 PM PDT 24
Finished Apr 25 12:54:31 PM PDT 24
Peak memory 215788 kb
Host smart-17f2b1b6-34c9-418d-b3d8-95748bdcac24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670998663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.2670998663
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.2744031874
Short name T852
Test name
Test status
Simulation time 301155820 ps
CPU time 3.95 seconds
Started Apr 25 12:54:18 PM PDT 24
Finished Apr 25 12:54:26 PM PDT 24
Peak memory 207756 kb
Host smart-e78ba9d1-b480-4141-a992-3be8330eb2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744031874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.2744031874
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.2069615806
Short name T574
Test name
Test status
Simulation time 286753564 ps
CPU time 3.36 seconds
Started Apr 25 12:54:14 PM PDT 24
Finished Apr 25 12:54:20 PM PDT 24
Peak memory 209880 kb
Host smart-1745f03b-7a3d-48be-b071-f874d38255c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069615806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.2069615806
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.1543315941
Short name T421
Test name
Test status
Simulation time 14525248 ps
CPU time 0.71 seconds
Started Apr 25 12:54:14 PM PDT 24
Finished Apr 25 12:54:18 PM PDT 24
Peak memory 205632 kb
Host smart-18e03e75-d7be-4c1b-955e-c68d4c1e7c79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543315941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.1543315941
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.3885223353
Short name T134
Test name
Test status
Simulation time 219444492 ps
CPU time 4.28 seconds
Started Apr 25 12:54:13 PM PDT 24
Finished Apr 25 12:54:21 PM PDT 24
Peak memory 214124 kb
Host smart-43e2be3b-8de4-4bec-a93f-5d284df2213a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3885223353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.3885223353
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.4073501568
Short name T838
Test name
Test status
Simulation time 1528351755 ps
CPU time 40.15 seconds
Started Apr 25 12:54:16 PM PDT 24
Finished Apr 25 12:55:01 PM PDT 24
Peak memory 222060 kb
Host smart-9842b908-800c-46b7-a2f8-67d114ca8ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073501568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.4073501568
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.3993838146
Short name T56
Test name
Test status
Simulation time 113351679 ps
CPU time 2.78 seconds
Started Apr 25 12:54:09 PM PDT 24
Finished Apr 25 12:54:15 PM PDT 24
Peak memory 207268 kb
Host smart-0f0650ce-b1a0-4d58-9423-1ccec3b3509e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993838146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.3993838146
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.1515030287
Short name T317
Test name
Test status
Simulation time 366464539 ps
CPU time 8.98 seconds
Started Apr 25 12:54:09 PM PDT 24
Finished Apr 25 12:54:22 PM PDT 24
Peak memory 209312 kb
Host smart-94184ba0-c7a0-417d-b703-2ec887945033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515030287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.1515030287
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.2611266649
Short name T285
Test name
Test status
Simulation time 241987841 ps
CPU time 2.97 seconds
Started Apr 25 12:54:01 PM PDT 24
Finished Apr 25 12:54:08 PM PDT 24
Peak memory 222208 kb
Host smart-52dfc4d8-7f4a-4197-bd9e-f3571e6d450f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611266649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.2611266649
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.3174252311
Short name T395
Test name
Test status
Simulation time 116278982 ps
CPU time 3.72 seconds
Started Apr 25 12:54:13 PM PDT 24
Finished Apr 25 12:54:20 PM PDT 24
Peak memory 218324 kb
Host smart-f98922c9-4209-401f-bbd8-c6febf0d0fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174252311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.3174252311
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.3603370786
Short name T541
Test name
Test status
Simulation time 952742460 ps
CPU time 6.77 seconds
Started Apr 25 12:54:02 PM PDT 24
Finished Apr 25 12:54:13 PM PDT 24
Peak memory 209804 kb
Host smart-cc84eed8-8e46-4389-8cc0-28b6316153bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603370786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.3603370786
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.2992989340
Short name T562
Test name
Test status
Simulation time 310863385 ps
CPU time 2.72 seconds
Started Apr 25 12:54:13 PM PDT 24
Finished Apr 25 12:54:25 PM PDT 24
Peak memory 206356 kb
Host smart-9fed3eb4-ec8f-49be-b290-a714a7b2e722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992989340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.2992989340
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.795500788
Short name T489
Test name
Test status
Simulation time 982965032 ps
CPU time 5.12 seconds
Started Apr 25 12:54:15 PM PDT 24
Finished Apr 25 12:54:24 PM PDT 24
Peak memory 208528 kb
Host smart-045c4935-3ed1-4a14-a67e-bf748cdfd706
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795500788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.795500788
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.3422175102
Short name T753
Test name
Test status
Simulation time 1453701039 ps
CPU time 43.17 seconds
Started Apr 25 12:54:01 PM PDT 24
Finished Apr 25 12:54:49 PM PDT 24
Peak memory 208764 kb
Host smart-a7b70e4f-ef81-49e6-83f1-c35f08b23cb3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422175102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.3422175102
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.814104105
Short name T695
Test name
Test status
Simulation time 366891011 ps
CPU time 4.56 seconds
Started Apr 25 12:54:19 PM PDT 24
Finished Apr 25 12:54:28 PM PDT 24
Peak memory 208536 kb
Host smart-fd28b00d-ef83-414b-ba8c-bd588c37579d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814104105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.814104105
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.1315682649
Short name T2
Test name
Test status
Simulation time 111767233 ps
CPU time 2.19 seconds
Started Apr 25 12:53:54 PM PDT 24
Finished Apr 25 12:53:58 PM PDT 24
Peak memory 207600 kb
Host smart-7cd1f207-c13c-4b41-b2ca-10b73e1fc4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315682649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.1315682649
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.4098357445
Short name T634
Test name
Test status
Simulation time 865117686 ps
CPU time 6.59 seconds
Started Apr 25 12:54:11 PM PDT 24
Finished Apr 25 12:54:22 PM PDT 24
Peak memory 206184 kb
Host smart-f2bb74ba-986f-4675-9d6b-87ec70301f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098357445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.4098357445
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.1410932926
Short name T214
Test name
Test status
Simulation time 694367928 ps
CPU time 34.29 seconds
Started Apr 25 12:53:59 PM PDT 24
Finished Apr 25 12:54:38 PM PDT 24
Peak memory 216256 kb
Host smart-b1869ea3-7c0b-4f59-9df8-5492f24d13e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410932926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.1410932926
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.2032167246
Short name T167
Test name
Test status
Simulation time 938464962 ps
CPU time 9.77 seconds
Started Apr 25 12:54:00 PM PDT 24
Finished Apr 25 12:54:14 PM PDT 24
Peak memory 222408 kb
Host smart-be84065d-2e04-400c-b84a-c22cb45ce42c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032167246 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.2032167246
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.4157058041
Short name T497
Test name
Test status
Simulation time 152550695 ps
CPU time 2.78 seconds
Started Apr 25 12:54:08 PM PDT 24
Finished Apr 25 12:54:14 PM PDT 24
Peak memory 209884 kb
Host smart-66798c03-f6d8-4146-84b3-3555d6933e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157058041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.4157058041
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.2290941884
Short name T766
Test name
Test status
Simulation time 33037544 ps
CPU time 0.71 seconds
Started Apr 25 12:54:29 PM PDT 24
Finished Apr 25 12:54:33 PM PDT 24
Peak memory 205616 kb
Host smart-02daa2e8-27a6-4f3b-8785-b1b5ecce4822
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290941884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.2290941884
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.2120951302
Short name T826
Test name
Test status
Simulation time 4194400571 ps
CPU time 37.32 seconds
Started Apr 25 12:54:07 PM PDT 24
Finished Apr 25 12:54:48 PM PDT 24
Peak memory 214348 kb
Host smart-98991f31-92fd-4e40-bc1e-631eeda7f3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120951302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.2120951302
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.605706466
Short name T284
Test name
Test status
Simulation time 52420105 ps
CPU time 3.34 seconds
Started Apr 25 12:53:55 PM PDT 24
Finished Apr 25 12:54:01 PM PDT 24
Peak memory 210564 kb
Host smart-35bba21b-a176-4670-9670-585326003796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605706466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.605706466
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_random.2880191067
Short name T363
Test name
Test status
Simulation time 213579067 ps
CPU time 3.68 seconds
Started Apr 25 12:54:07 PM PDT 24
Finished Apr 25 12:54:14 PM PDT 24
Peak memory 208928 kb
Host smart-36cca115-9dfd-48bd-93ae-5e66ec8ec597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880191067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.2880191067
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.3145586859
Short name T496
Test name
Test status
Simulation time 753562074 ps
CPU time 4.39 seconds
Started Apr 25 12:53:59 PM PDT 24
Finished Apr 25 12:54:08 PM PDT 24
Peak memory 208064 kb
Host smart-a241a290-6799-42ee-a856-ec815a839c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145586859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.3145586859
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.574834232
Short name T333
Test name
Test status
Simulation time 50910830 ps
CPU time 2.75 seconds
Started Apr 25 12:54:06 PM PDT 24
Finished Apr 25 12:54:13 PM PDT 24
Peak memory 206904 kb
Host smart-9f1ce437-767b-4111-8bec-d28b2d85a6bb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574834232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.574834232
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.1698248760
Short name T686
Test name
Test status
Simulation time 584213590 ps
CPU time 3.17 seconds
Started Apr 25 12:54:14 PM PDT 24
Finished Apr 25 12:54:20 PM PDT 24
Peak memory 206600 kb
Host smart-9b8bf0ba-fee7-40de-a0e4-027e1eb9fb30
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698248760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.1698248760
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.3381574726
Short name T770
Test name
Test status
Simulation time 179684838 ps
CPU time 2.76 seconds
Started Apr 25 12:53:59 PM PDT 24
Finished Apr 25 12:54:06 PM PDT 24
Peak memory 206452 kb
Host smart-00cc8d7f-362d-490a-b1fa-ce3e6b7216e5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381574726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.3381574726
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.1175596852
Short name T800
Test name
Test status
Simulation time 216678937 ps
CPU time 3.37 seconds
Started Apr 25 12:54:11 PM PDT 24
Finished Apr 25 12:54:18 PM PDT 24
Peak memory 214116 kb
Host smart-83132033-7ff7-4bb6-9de9-f8bafa3a1af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175596852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.1175596852
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.3762095073
Short name T511
Test name
Test status
Simulation time 470040632 ps
CPU time 6.38 seconds
Started Apr 25 12:54:18 PM PDT 24
Finished Apr 25 12:54:29 PM PDT 24
Peak memory 207596 kb
Host smart-dc4d5b9c-50cd-48f1-9e84-944823f9cbec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762095073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.3762095073
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.118687999
Short name T677
Test name
Test status
Simulation time 2408194751 ps
CPU time 22.96 seconds
Started Apr 25 12:54:00 PM PDT 24
Finished Apr 25 12:54:28 PM PDT 24
Peak memory 222320 kb
Host smart-ddd5e3a1-7598-4751-9669-52e2bb95ec2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118687999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.118687999
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.1125684666
Short name T577
Test name
Test status
Simulation time 424946212 ps
CPU time 6.27 seconds
Started Apr 25 12:54:05 PM PDT 24
Finished Apr 25 12:54:15 PM PDT 24
Peak memory 207956 kb
Host smart-93005b14-fb78-48be-98bf-501c0c9f2df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125684666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.1125684666
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.876754682
Short name T127
Test name
Test status
Simulation time 93491665 ps
CPU time 3.09 seconds
Started Apr 25 12:54:06 PM PDT 24
Finished Apr 25 12:54:13 PM PDT 24
Peak memory 209544 kb
Host smart-ab55fa0b-bbf7-466e-8b55-2ec464ec1c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876754682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.876754682
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.2771009240
Short name T865
Test name
Test status
Simulation time 54050866 ps
CPU time 0.8 seconds
Started Apr 25 12:54:14 PM PDT 24
Finished Apr 25 12:54:18 PM PDT 24
Peak memory 205696 kb
Host smart-14bdae0d-611c-48f0-8a65-32ee1534e9e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771009240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.2771009240
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.184269755
Short name T232
Test name
Test status
Simulation time 598714913 ps
CPU time 14.93 seconds
Started Apr 25 12:54:16 PM PDT 24
Finished Apr 25 12:54:35 PM PDT 24
Peak memory 214080 kb
Host smart-5d3d9990-90b7-426e-b101-1bf0a069756e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=184269755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.184269755
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.3604685604
Short name T24
Test name
Test status
Simulation time 256106828 ps
CPU time 2.18 seconds
Started Apr 25 12:54:27 PM PDT 24
Finished Apr 25 12:54:33 PM PDT 24
Peak memory 214388 kb
Host smart-30c07537-9aad-4d87-ba7c-6746ae5c004f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604685604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.3604685604
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.312695572
Short name T198
Test name
Test status
Simulation time 718254153 ps
CPU time 4.1 seconds
Started Apr 25 12:54:16 PM PDT 24
Finished Apr 25 12:54:25 PM PDT 24
Peak memory 207984 kb
Host smart-f6234ae0-0d1e-44e1-81a5-f7a24856bb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312695572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.312695572
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.3982162428
Short name T292
Test name
Test status
Simulation time 17423477429 ps
CPU time 57.38 seconds
Started Apr 25 12:54:10 PM PDT 24
Finished Apr 25 12:55:11 PM PDT 24
Peak memory 209444 kb
Host smart-6461b6fa-7deb-4131-a41f-4fe000e58d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982162428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.3982162428
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.580298416
Short name T287
Test name
Test status
Simulation time 739030730 ps
CPU time 20.61 seconds
Started Apr 25 12:54:19 PM PDT 24
Finished Apr 25 12:54:44 PM PDT 24
Peak memory 214164 kb
Host smart-11da36a5-7ff9-4e3a-ad84-e6f98e735410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580298416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.580298416
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.650882756
Short name T632
Test name
Test status
Simulation time 377743628 ps
CPU time 4.38 seconds
Started Apr 25 12:54:27 PM PDT 24
Finished Apr 25 12:54:35 PM PDT 24
Peak memory 219768 kb
Host smart-5ae072d4-37cc-4bd7-8509-e1d4d9dcdb34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650882756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.650882756
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.2606943453
Short name T345
Test name
Test status
Simulation time 214843705 ps
CPU time 6.66 seconds
Started Apr 25 12:54:20 PM PDT 24
Finished Apr 25 12:54:30 PM PDT 24
Peak memory 207128 kb
Host smart-f2300b91-edd3-4093-a76d-b05466adbc1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606943453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.2606943453
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.2361093284
Short name T466
Test name
Test status
Simulation time 764469546 ps
CPU time 14.65 seconds
Started Apr 25 12:54:35 PM PDT 24
Finished Apr 25 12:54:52 PM PDT 24
Peak memory 208212 kb
Host smart-05d16ae7-af26-41e8-b6c6-f57452f5aeaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361093284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.2361093284
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.2606649946
Short name T698
Test name
Test status
Simulation time 889318417 ps
CPU time 35.01 seconds
Started Apr 25 12:54:13 PM PDT 24
Finished Apr 25 12:54:52 PM PDT 24
Peak memory 208532 kb
Host smart-632c0cdc-988d-4099-8cb1-ed63a43f59e0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606649946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.2606649946
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.49878095
Short name T514
Test name
Test status
Simulation time 3557130659 ps
CPU time 6.61 seconds
Started Apr 25 12:54:22 PM PDT 24
Finished Apr 25 12:54:32 PM PDT 24
Peak memory 208504 kb
Host smart-db3fa1c6-e188-42d5-bb40-5b31c0b03f39
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49878095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.49878095
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.2920171145
Short name T295
Test name
Test status
Simulation time 1928892942 ps
CPU time 55.15 seconds
Started Apr 25 12:54:24 PM PDT 24
Finished Apr 25 12:55:23 PM PDT 24
Peak memory 208084 kb
Host smart-bd6dc9a7-b8da-4a1b-b616-33e99568964b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920171145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.2920171145
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.3154389875
Short name T566
Test name
Test status
Simulation time 697410558 ps
CPU time 19 seconds
Started Apr 25 12:54:24 PM PDT 24
Finished Apr 25 12:54:47 PM PDT 24
Peak memory 208256 kb
Host smart-f5ab8f62-0f74-48a2-b5a1-854a9b31cd18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154389875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.3154389875
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.2768019356
Short name T620
Test name
Test status
Simulation time 1706548244 ps
CPU time 8.4 seconds
Started Apr 25 12:54:17 PM PDT 24
Finished Apr 25 12:54:30 PM PDT 24
Peak memory 207504 kb
Host smart-9a906de0-3eb0-41cb-817d-3bfc35acc861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768019356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.2768019356
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.270568106
Short name T176
Test name
Test status
Simulation time 1346478845 ps
CPU time 49.99 seconds
Started Apr 25 12:54:27 PM PDT 24
Finished Apr 25 12:55:20 PM PDT 24
Peak memory 216588 kb
Host smart-5c331536-1e3e-4ee4-9200-ae5dd2250ffb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270568106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.270568106
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.194218196
Short name T559
Test name
Test status
Simulation time 525841627 ps
CPU time 8.28 seconds
Started Apr 25 12:54:37 PM PDT 24
Finished Apr 25 12:54:48 PM PDT 24
Peak memory 218096 kb
Host smart-ce9332bc-3aed-4a73-97d7-103da36fa89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194218196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.194218196
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.1437108330
Short name T480
Test name
Test status
Simulation time 286856910 ps
CPU time 1.58 seconds
Started Apr 25 12:54:17 PM PDT 24
Finished Apr 25 12:54:22 PM PDT 24
Peak memory 209564 kb
Host smart-295588bf-68b9-4614-b79e-038b9aa9b0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437108330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.1437108330
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.3954561143
Short name T97
Test name
Test status
Simulation time 43794872 ps
CPU time 0.76 seconds
Started Apr 25 12:54:22 PM PDT 24
Finished Apr 25 12:54:26 PM PDT 24
Peak memory 205716 kb
Host smart-7c583ba0-b690-4a13-b4f3-3eb20ef8de05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954561143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.3954561143
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.4216184893
Short name T241
Test name
Test status
Simulation time 353280516 ps
CPU time 18.51 seconds
Started Apr 25 12:54:29 PM PDT 24
Finished Apr 25 12:54:52 PM PDT 24
Peak memory 215272 kb
Host smart-7a7d11d0-f3d4-4581-89fd-205bf9cc3d6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4216184893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.4216184893
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.4100276896
Short name T475
Test name
Test status
Simulation time 114714881 ps
CPU time 1.58 seconds
Started Apr 25 12:54:28 PM PDT 24
Finished Apr 25 12:54:33 PM PDT 24
Peak memory 207220 kb
Host smart-58d14994-82a5-4df0-9b8e-35b15a80c292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100276896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.4100276896
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.176093216
Short name T795
Test name
Test status
Simulation time 142428108 ps
CPU time 2.27 seconds
Started Apr 25 12:54:28 PM PDT 24
Finished Apr 25 12:54:34 PM PDT 24
Peak memory 207368 kb
Host smart-940b5632-ff5b-40f0-8b35-53d33e79aa99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176093216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.176093216
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.1125430360
Short name T90
Test name
Test status
Simulation time 64771107 ps
CPU time 3.4 seconds
Started Apr 25 12:54:16 PM PDT 24
Finished Apr 25 12:54:23 PM PDT 24
Peak memory 209228 kb
Host smart-bbcb3972-34f0-458f-8b0b-df2aafcf9722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125430360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.1125430360
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.816359837
Short name T236
Test name
Test status
Simulation time 39093574 ps
CPU time 2.55 seconds
Started Apr 25 12:54:35 PM PDT 24
Finished Apr 25 12:54:40 PM PDT 24
Peak memory 210564 kb
Host smart-d012e2c9-35f7-48ad-a51a-e99941b8e1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816359837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.816359837
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.323212602
Short name T207
Test name
Test status
Simulation time 212499248 ps
CPU time 2.89 seconds
Started Apr 25 12:54:30 PM PDT 24
Finished Apr 25 12:54:36 PM PDT 24
Peak memory 209416 kb
Host smart-ce710fbd-26dc-457a-925f-c81b543dab76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323212602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.323212602
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.2642146909
Short name T653
Test name
Test status
Simulation time 84753612 ps
CPU time 3.17 seconds
Started Apr 25 12:54:37 PM PDT 24
Finished Apr 25 12:54:42 PM PDT 24
Peak memory 218044 kb
Host smart-e39494c5-52c1-4865-9cdc-e39d7eaa38ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642146909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.2642146909
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.2683767781
Short name T814
Test name
Test status
Simulation time 21720952924 ps
CPU time 81.31 seconds
Started Apr 25 12:54:21 PM PDT 24
Finished Apr 25 12:55:46 PM PDT 24
Peak memory 208752 kb
Host smart-cfc4daab-27e1-447a-8140-6057ee5a4757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683767781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.2683767781
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.1916555292
Short name T442
Test name
Test status
Simulation time 51291923 ps
CPU time 1.91 seconds
Started Apr 25 12:54:10 PM PDT 24
Finished Apr 25 12:54:15 PM PDT 24
Peak memory 207252 kb
Host smart-2b953ff0-ff80-4a8a-ac74-ee4f30cd1328
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916555292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.1916555292
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.3524073541
Short name T774
Test name
Test status
Simulation time 91473659 ps
CPU time 1.93 seconds
Started Apr 25 12:54:14 PM PDT 24
Finished Apr 25 12:54:19 PM PDT 24
Peak memory 208112 kb
Host smart-b50c91c3-1f1c-4569-abe3-8bd59dbb6e50
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524073541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.3524073541
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.2764953289
Short name T501
Test name
Test status
Simulation time 608630963 ps
CPU time 5.01 seconds
Started Apr 25 12:54:16 PM PDT 24
Finished Apr 25 12:54:25 PM PDT 24
Peak memory 207424 kb
Host smart-31521e64-28c4-4524-91bd-8b2beeeb7402
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764953289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.2764953289
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.1609050175
Short name T400
Test name
Test status
Simulation time 60240468 ps
CPU time 2.88 seconds
Started Apr 25 12:54:10 PM PDT 24
Finished Apr 25 12:54:16 PM PDT 24
Peak memory 209268 kb
Host smart-ce355594-91b2-4b8b-9f6e-09129f7611e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609050175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.1609050175
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.377029987
Short name T500
Test name
Test status
Simulation time 2771143339 ps
CPU time 3.9 seconds
Started Apr 25 12:54:01 PM PDT 24
Finished Apr 25 12:54:09 PM PDT 24
Peak memory 207624 kb
Host smart-216e855b-5b1b-4290-976a-9ba92e69f2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377029987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.377029987
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.1664836113
Short name T465
Test name
Test status
Simulation time 19989946292 ps
CPU time 94.64 seconds
Started Apr 25 12:54:27 PM PDT 24
Finished Apr 25 12:56:05 PM PDT 24
Peak memory 209024 kb
Host smart-acac6e6c-eae6-4115-a461-9acc2b4fcef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664836113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.1664836113
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.1957140238
Short name T520
Test name
Test status
Simulation time 493674172 ps
CPU time 1.98 seconds
Started Apr 25 12:54:23 PM PDT 24
Finished Apr 25 12:54:29 PM PDT 24
Peak memory 209268 kb
Host smart-db0eb92b-55f9-45a1-ad4b-255869919257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957140238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.1957140238
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.46906430
Short name T504
Test name
Test status
Simulation time 30937006 ps
CPU time 0.72 seconds
Started Apr 25 12:54:31 PM PDT 24
Finished Apr 25 12:54:35 PM PDT 24
Peak memory 205680 kb
Host smart-f75c8d97-c02a-4493-a68b-d46b32b38c3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46906430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.46906430
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.934695537
Short name T731
Test name
Test status
Simulation time 772851855 ps
CPU time 4.33 seconds
Started Apr 25 12:54:17 PM PDT 24
Finished Apr 25 12:54:26 PM PDT 24
Peak memory 215276 kb
Host smart-64c7b0f0-ad31-4631-9406-a7da1f92936c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=934695537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.934695537
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.1446450995
Short name T584
Test name
Test status
Simulation time 186703743 ps
CPU time 2.38 seconds
Started Apr 25 12:54:18 PM PDT 24
Finished Apr 25 12:54:25 PM PDT 24
Peak memory 214136 kb
Host smart-2704941d-11b8-4394-a7d7-bc84d05781dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446450995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.1446450995
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.1248796186
Short name T717
Test name
Test status
Simulation time 1516868363 ps
CPU time 3.48 seconds
Started Apr 25 12:54:10 PM PDT 24
Finished Apr 25 12:54:18 PM PDT 24
Peak memory 210004 kb
Host smart-06a575bd-0c79-4554-92db-0f9eea42f89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248796186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.1248796186
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.4100647723
Short name T639
Test name
Test status
Simulation time 61157605 ps
CPU time 2.32 seconds
Started Apr 25 12:54:43 PM PDT 24
Finished Apr 25 12:54:47 PM PDT 24
Peak memory 208908 kb
Host smart-c5054a1c-0309-4060-9662-acaf32a75785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100647723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.4100647723
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.1362270188
Short name T59
Test name
Test status
Simulation time 70300373 ps
CPU time 2.62 seconds
Started Apr 25 12:54:23 PM PDT 24
Finished Apr 25 12:54:30 PM PDT 24
Peak memory 215672 kb
Host smart-e4cd40da-e5f6-4ef5-a21c-b54c261e0132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362270188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.1362270188
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.735991518
Short name T369
Test name
Test status
Simulation time 140900936 ps
CPU time 3.84 seconds
Started Apr 25 12:54:26 PM PDT 24
Finished Apr 25 12:54:34 PM PDT 24
Peak memory 207580 kb
Host smart-59e0c889-2ced-42f0-b1ce-7e9ecba2f677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735991518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.735991518
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.436000245
Short name T746
Test name
Test status
Simulation time 89080272 ps
CPU time 3.94 seconds
Started Apr 25 12:54:19 PM PDT 24
Finished Apr 25 12:54:27 PM PDT 24
Peak memory 208196 kb
Host smart-c05e4fdb-5a30-43ba-b5d1-ffd1dde743e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436000245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.436000245
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.2378951809
Short name T362
Test name
Test status
Simulation time 362260043 ps
CPU time 4.35 seconds
Started Apr 25 12:54:23 PM PDT 24
Finished Apr 25 12:54:32 PM PDT 24
Peak memory 206516 kb
Host smart-d9b2e4d8-b7c7-44e9-b0a0-f75168569460
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378951809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.2378951809
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.2237753442
Short name T848
Test name
Test status
Simulation time 446737128 ps
CPU time 4.99 seconds
Started Apr 25 12:54:23 PM PDT 24
Finished Apr 25 12:54:33 PM PDT 24
Peak memory 208588 kb
Host smart-ccad63f1-6439-4b3d-9b6e-5ee7f9387c8c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237753442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.2237753442
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.1138910198
Short name T348
Test name
Test status
Simulation time 33318603 ps
CPU time 2.23 seconds
Started Apr 25 12:54:26 PM PDT 24
Finished Apr 25 12:54:32 PM PDT 24
Peak memory 206528 kb
Host smart-3a17fbca-dbf7-4988-bb18-3d15428f2ec2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138910198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.1138910198
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.988832383
Short name T331
Test name
Test status
Simulation time 338776881 ps
CPU time 4.67 seconds
Started Apr 25 12:54:13 PM PDT 24
Finished Apr 25 12:54:21 PM PDT 24
Peak memory 209464 kb
Host smart-b12ecf63-3391-4a63-bcef-d91119601313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988832383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.988832383
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.193895108
Short name T554
Test name
Test status
Simulation time 117492240 ps
CPU time 2.96 seconds
Started Apr 25 12:54:09 PM PDT 24
Finished Apr 25 12:54:15 PM PDT 24
Peak memory 208316 kb
Host smart-c027b26d-65cc-4faa-b0dd-ce8d4f48605f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193895108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.193895108
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.4205486495
Short name T218
Test name
Test status
Simulation time 1368907667 ps
CPU time 48.81 seconds
Started Apr 25 12:54:23 PM PDT 24
Finished Apr 25 12:55:16 PM PDT 24
Peak memory 215412 kb
Host smart-4dcada6e-ee61-4b83-97c1-9a47d654d942
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205486495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.4205486495
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.3677860761
Short name T759
Test name
Test status
Simulation time 389808711 ps
CPU time 8.09 seconds
Started Apr 25 12:54:26 PM PDT 24
Finished Apr 25 12:54:38 PM PDT 24
Peak memory 222468 kb
Host smart-35a24eca-57de-416e-9f3f-7c00728283bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677860761 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.3677860761
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.604810298
Short name T859
Test name
Test status
Simulation time 46225531 ps
CPU time 3.31 seconds
Started Apr 25 12:54:15 PM PDT 24
Finished Apr 25 12:54:21 PM PDT 24
Peak memory 214080 kb
Host smart-98401f50-c7c0-4abc-b975-99a3043578b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604810298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.604810298
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.432365424
Short name T794
Test name
Test status
Simulation time 32597144 ps
CPU time 1.85 seconds
Started Apr 25 12:54:24 PM PDT 24
Finished Apr 25 12:54:34 PM PDT 24
Peak memory 209568 kb
Host smart-f7b963aa-6198-48d9-99bc-6c629a2793da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432365424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.432365424
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.1657853793
Short name T853
Test name
Test status
Simulation time 34868550 ps
CPU time 0.71 seconds
Started Apr 25 12:54:22 PM PDT 24
Finished Apr 25 12:54:27 PM PDT 24
Peak memory 205712 kb
Host smart-2876919f-4230-4e7d-8b88-c180e2a988f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657853793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.1657853793
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.2004274553
Short name T542
Test name
Test status
Simulation time 635026812 ps
CPU time 4.01 seconds
Started Apr 25 12:54:27 PM PDT 24
Finished Apr 25 12:54:35 PM PDT 24
Peak memory 218208 kb
Host smart-f87731c7-d530-46bc-baf9-a9ccb6878f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004274553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.2004274553
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.3653862851
Short name T851
Test name
Test status
Simulation time 437054220 ps
CPU time 4.76 seconds
Started Apr 25 12:54:22 PM PDT 24
Finished Apr 25 12:54:30 PM PDT 24
Peak memory 218032 kb
Host smart-3fed77a7-1392-4ecf-bd3f-ecfcdc268bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653862851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.3653862851
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.255451605
Short name T95
Test name
Test status
Simulation time 130294682 ps
CPU time 2.76 seconds
Started Apr 25 12:54:35 PM PDT 24
Finished Apr 25 12:54:40 PM PDT 24
Peak memory 216872 kb
Host smart-12ba6a3a-ae91-456c-a4da-afc6cc88a602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255451605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.255451605
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.1942594888
Short name T259
Test name
Test status
Simulation time 139612832 ps
CPU time 3.9 seconds
Started Apr 25 12:54:36 PM PDT 24
Finished Apr 25 12:54:42 PM PDT 24
Peak memory 210824 kb
Host smart-96a069e7-39e1-4cac-a197-bfb2b6aa26b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942594888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.1942594888
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.2950427807
Short name T790
Test name
Test status
Simulation time 586269947 ps
CPU time 5.99 seconds
Started Apr 25 12:54:25 PM PDT 24
Finished Apr 25 12:54:35 PM PDT 24
Peak memory 222232 kb
Host smart-20f77d5b-895c-47f2-97e7-9c07d2f2841e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950427807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.2950427807
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.367958603
Short name T488
Test name
Test status
Simulation time 922396350 ps
CPU time 23.61 seconds
Started Apr 25 12:54:16 PM PDT 24
Finished Apr 25 12:54:43 PM PDT 24
Peak memory 218228 kb
Host smart-d250c6d8-0fc3-4284-ba95-71a986b69436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367958603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.367958603
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.3929166841
Short name T627
Test name
Test status
Simulation time 177979696 ps
CPU time 6.47 seconds
Started Apr 25 12:54:20 PM PDT 24
Finished Apr 25 12:54:30 PM PDT 24
Peak memory 208500 kb
Host smart-1f5916a1-e12c-4c27-afcf-2c3855e01997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929166841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.3929166841
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.4070597174
Short name T309
Test name
Test status
Simulation time 218113157 ps
CPU time 6.34 seconds
Started Apr 25 12:54:19 PM PDT 24
Finished Apr 25 12:54:35 PM PDT 24
Peak memory 208008 kb
Host smart-f6c349b8-fc23-4365-b3e1-8319673c302b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070597174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.4070597174
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.259394645
Short name T713
Test name
Test status
Simulation time 69380550 ps
CPU time 3.07 seconds
Started Apr 25 12:54:38 PM PDT 24
Finished Apr 25 12:54:43 PM PDT 24
Peak memory 208500 kb
Host smart-4bd1cc05-2982-4c2e-a799-85ae98c07460
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259394645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.259394645
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.3123323638
Short name T875
Test name
Test status
Simulation time 22904843 ps
CPU time 1.85 seconds
Started Apr 25 12:54:28 PM PDT 24
Finished Apr 25 12:54:34 PM PDT 24
Peak memory 206540 kb
Host smart-888d79e6-3c98-42c6-8e3b-45e7aee39ada
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123323638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.3123323638
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.2623172046
Short name T672
Test name
Test status
Simulation time 155787860 ps
CPU time 4.71 seconds
Started Apr 25 12:54:31 PM PDT 24
Finished Apr 25 12:54:39 PM PDT 24
Peak memory 217916 kb
Host smart-c01a48f2-b4d3-4f80-8307-126c0410734c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623172046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.2623172046
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.1125878723
Short name T189
Test name
Test status
Simulation time 107290062 ps
CPU time 1.8 seconds
Started Apr 25 12:54:21 PM PDT 24
Finished Apr 25 12:54:26 PM PDT 24
Peak memory 206256 kb
Host smart-068e1968-16ba-4d06-b701-69c2e56cec44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125878723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.1125878723
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.1012826965
Short name T250
Test name
Test status
Simulation time 1459163993 ps
CPU time 7.48 seconds
Started Apr 25 12:54:18 PM PDT 24
Finished Apr 25 12:54:30 PM PDT 24
Peak memory 214128 kb
Host smart-cff3ee76-0c2d-452c-9a2a-eb49e02f9cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012826965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.1012826965
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.255804705
Short name T728
Test name
Test status
Simulation time 47310894 ps
CPU time 1.5 seconds
Started Apr 25 12:54:23 PM PDT 24
Finished Apr 25 12:54:29 PM PDT 24
Peak memory 209300 kb
Host smart-ab2d0793-180f-423a-8b41-46306f517913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255804705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.255804705
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.3777980849
Short name T819
Test name
Test status
Simulation time 16247337 ps
CPU time 0.78 seconds
Started Apr 25 12:54:28 PM PDT 24
Finished Apr 25 12:54:32 PM PDT 24
Peak memory 205716 kb
Host smart-ddd6a00a-b4bd-49b1-86e7-5c59f73b1d1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777980849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.3777980849
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.2275443983
Short name T861
Test name
Test status
Simulation time 2280401998 ps
CPU time 46.3 seconds
Started Apr 25 12:54:16 PM PDT 24
Finished Apr 25 12:55:06 PM PDT 24
Peak memory 222280 kb
Host smart-0059189d-887a-435a-bd53-29065b5d891e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2275443983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.2275443983
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.2808638345
Short name T166
Test name
Test status
Simulation time 111622831 ps
CPU time 2.15 seconds
Started Apr 25 12:54:32 PM PDT 24
Finished Apr 25 12:54:37 PM PDT 24
Peak memory 209288 kb
Host smart-08e67c48-361c-41b1-97fa-4bcd0db25feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808638345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.2808638345
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.2636402533
Short name T619
Test name
Test status
Simulation time 37669986 ps
CPU time 2.04 seconds
Started Apr 25 12:54:16 PM PDT 24
Finished Apr 25 12:54:23 PM PDT 24
Peak memory 207008 kb
Host smart-51660165-72ec-4dd8-a236-c94f305cf00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636402533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.2636402533
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.1410448919
Short name T773
Test name
Test status
Simulation time 146643602 ps
CPU time 4.88 seconds
Started Apr 25 12:54:43 PM PDT 24
Finished Apr 25 12:54:49 PM PDT 24
Peak memory 208288 kb
Host smart-66acbfb6-1727-42e2-8673-21338c1af007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410448919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.1410448919
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.2423711116
Short name T53
Test name
Test status
Simulation time 688545833 ps
CPU time 3.59 seconds
Started Apr 25 12:54:24 PM PDT 24
Finished Apr 25 12:54:32 PM PDT 24
Peak memory 219844 kb
Host smart-ca78ec80-6dcf-479d-9f83-bd1cfb960338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423711116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.2423711116
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.1412500279
Short name T796
Test name
Test status
Simulation time 1983665254 ps
CPU time 47.64 seconds
Started Apr 25 12:54:19 PM PDT 24
Finished Apr 25 12:55:11 PM PDT 24
Peak memory 209356 kb
Host smart-fa7dde7d-7cb8-4377-80de-f941a9440179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412500279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.1412500279
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.489051330
Short name T658
Test name
Test status
Simulation time 419623952 ps
CPU time 11.54 seconds
Started Apr 25 12:54:26 PM PDT 24
Finished Apr 25 12:54:42 PM PDT 24
Peak memory 208120 kb
Host smart-b5b346ad-2b36-4b48-b225-fa18487b55d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489051330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.489051330
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.365444368
Short name T676
Test name
Test status
Simulation time 82354863 ps
CPU time 1.83 seconds
Started Apr 25 12:54:26 PM PDT 24
Finished Apr 25 12:54:31 PM PDT 24
Peak memory 206528 kb
Host smart-5173e114-4de2-44f8-9e72-c33812915fed
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365444368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.365444368
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.483890010
Short name T108
Test name
Test status
Simulation time 1985082588 ps
CPU time 57.78 seconds
Started Apr 25 12:54:28 PM PDT 24
Finished Apr 25 12:55:30 PM PDT 24
Peak memory 208240 kb
Host smart-3a93e651-bec4-4db6-a78d-7772bf0c79eb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483890010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.483890010
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.3544154640
Short name T437
Test name
Test status
Simulation time 91038415 ps
CPU time 3.36 seconds
Started Apr 25 12:54:09 PM PDT 24
Finished Apr 25 12:54:15 PM PDT 24
Peak memory 206396 kb
Host smart-36c035cc-dacd-4f40-bebf-fefb49966a2c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544154640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.3544154640
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_smoke.685015901
Short name T827
Test name
Test status
Simulation time 106857537 ps
CPU time 2.64 seconds
Started Apr 25 12:54:13 PM PDT 24
Finished Apr 25 12:54:19 PM PDT 24
Peak memory 206416 kb
Host smart-dd47f091-4dd2-4cba-8a72-8005972ba0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685015901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.685015901
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.1767057943
Short name T185
Test name
Test status
Simulation time 60650096 ps
CPU time 3.73 seconds
Started Apr 25 12:54:36 PM PDT 24
Finished Apr 25 12:54:42 PM PDT 24
Peak memory 218152 kb
Host smart-640bf698-79cc-44e3-bea7-32d31550e718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767057943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.1767057943
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.2229066041
Short name T631
Test name
Test status
Simulation time 1562816802 ps
CPU time 25.77 seconds
Started Apr 25 12:54:29 PM PDT 24
Finished Apr 25 12:54:59 PM PDT 24
Peak memory 210124 kb
Host smart-631a554e-bec9-47cb-815c-fd2e797c4f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229066041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.2229066041
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.3416308713
Short name T678
Test name
Test status
Simulation time 20649130 ps
CPU time 0.88 seconds
Started Apr 25 12:54:36 PM PDT 24
Finished Apr 25 12:54:40 PM PDT 24
Peak memory 205716 kb
Host smart-8f120cc5-5119-4084-a289-9ae7f3cb1bfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416308713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.3416308713
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.2976949482
Short name T413
Test name
Test status
Simulation time 124664078 ps
CPU time 2.68 seconds
Started Apr 25 12:54:25 PM PDT 24
Finished Apr 25 12:54:32 PM PDT 24
Peak memory 214220 kb
Host smart-2d2a57a3-e9d0-44e3-9c9c-66bd89effc40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2976949482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.2976949482
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.4140358315
Short name T221
Test name
Test status
Simulation time 392460240 ps
CPU time 5 seconds
Started Apr 25 12:54:32 PM PDT 24
Finished Apr 25 12:54:40 PM PDT 24
Peak memory 209704 kb
Host smart-00a9b5ab-7f43-46c4-a7cc-66c6fdf64b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140358315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.4140358315
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.3293423477
Short name T51
Test name
Test status
Simulation time 83444741 ps
CPU time 1.66 seconds
Started Apr 25 12:54:33 PM PDT 24
Finished Apr 25 12:54:38 PM PDT 24
Peak memory 207180 kb
Host smart-7c22f113-5142-4a35-b841-452e27560e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293423477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.3293423477
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.281995659
Short name T293
Test name
Test status
Simulation time 168787839 ps
CPU time 4.7 seconds
Started Apr 25 12:54:34 PM PDT 24
Finished Apr 25 12:54:42 PM PDT 24
Peak memory 213956 kb
Host smart-ccf6cb4d-9429-4bbd-83e2-fe66a5b55c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281995659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.281995659
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.1037191715
Short name T312
Test name
Test status
Simulation time 277810707 ps
CPU time 8.2 seconds
Started Apr 25 12:55:06 PM PDT 24
Finished Apr 25 12:55:16 PM PDT 24
Peak memory 222276 kb
Host smart-fb4b7007-9ce8-4006-9619-f8e241e3cfcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037191715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.1037191715
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.2258267624
Short name T569
Test name
Test status
Simulation time 93788439 ps
CPU time 4.74 seconds
Started Apr 25 12:54:25 PM PDT 24
Finished Apr 25 12:54:38 PM PDT 24
Peak memory 216236 kb
Host smart-ae7952ae-2c7f-449d-9328-59a339ad5f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258267624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.2258267624
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.1068928986
Short name T458
Test name
Test status
Simulation time 1061014049 ps
CPU time 25.1 seconds
Started Apr 25 12:54:24 PM PDT 24
Finished Apr 25 12:54:54 PM PDT 24
Peak memory 208652 kb
Host smart-1b81a700-0ee0-4056-9eda-84fb66791b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068928986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.1068928986
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.579590625
Short name T322
Test name
Test status
Simulation time 296825427 ps
CPU time 2.52 seconds
Started Apr 25 12:54:41 PM PDT 24
Finished Apr 25 12:54:45 PM PDT 24
Peak memory 207844 kb
Host smart-251cdb56-51d8-43c8-bc56-1e1bab252ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579590625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.579590625
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.1591516712
Short name T392
Test name
Test status
Simulation time 9452099337 ps
CPU time 50.36 seconds
Started Apr 25 12:54:23 PM PDT 24
Finished Apr 25 12:55:18 PM PDT 24
Peak memory 208900 kb
Host smart-02627a83-0cd3-4f5a-9aea-ecc337b3a95e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591516712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.1591516712
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.1024619166
Short name T339
Test name
Test status
Simulation time 862450719 ps
CPU time 3.74 seconds
Started Apr 25 12:54:43 PM PDT 24
Finished Apr 25 12:54:48 PM PDT 24
Peak memory 208364 kb
Host smart-63b56f6b-6c45-43b0-9e8b-b97f65866cf8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024619166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.1024619166
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.1644863912
Short name T756
Test name
Test status
Simulation time 303670756 ps
CPU time 3.77 seconds
Started Apr 25 12:54:21 PM PDT 24
Finished Apr 25 12:54:28 PM PDT 24
Peak memory 208352 kb
Host smart-d8f757ce-1cdc-408c-991d-4fd173423132
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644863912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.1644863912
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.414440995
Short name T847
Test name
Test status
Simulation time 338411929 ps
CPU time 4.22 seconds
Started Apr 25 12:54:27 PM PDT 24
Finished Apr 25 12:54:35 PM PDT 24
Peak memory 209200 kb
Host smart-af3372bb-72ae-4d56-9ee0-fde95a650f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414440995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.414440995
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.1232015713
Short name T391
Test name
Test status
Simulation time 1815408003 ps
CPU time 11.49 seconds
Started Apr 25 12:54:39 PM PDT 24
Finished Apr 25 12:54:53 PM PDT 24
Peak memory 207792 kb
Host smart-989d0865-8c85-4dea-ab6c-3e066a7989f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232015713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.1232015713
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.1293103293
Short name T315
Test name
Test status
Simulation time 2030811072 ps
CPU time 51.76 seconds
Started Apr 25 12:54:40 PM PDT 24
Finished Apr 25 12:55:33 PM PDT 24
Peak memory 218412 kb
Host smart-56b5f9e5-fca4-4d9c-ab13-c7de7df4512c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293103293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.1293103293
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.4285365187
Short name T549
Test name
Test status
Simulation time 64589868 ps
CPU time 0.97 seconds
Started Apr 25 12:54:24 PM PDT 24
Finished Apr 25 12:54:30 PM PDT 24
Peak memory 205868 kb
Host smart-ad53b9ae-dac6-440e-a244-00dbb7f425ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285365187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.4285365187
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.2602169852
Short name T832
Test name
Test status
Simulation time 62700028 ps
CPU time 4.38 seconds
Started Apr 25 12:54:39 PM PDT 24
Finished Apr 25 12:54:45 PM PDT 24
Peak memory 214600 kb
Host smart-5b129f49-e1b8-44cf-bf7a-eb992c075e40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2602169852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.2602169852
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.2897926586
Short name T846
Test name
Test status
Simulation time 533143425 ps
CPU time 4.64 seconds
Started Apr 25 12:54:16 PM PDT 24
Finished Apr 25 12:54:24 PM PDT 24
Peak memory 209284 kb
Host smart-cbdf9299-5f65-470d-9d3e-e8a6796754ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897926586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.2897926586
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.1479281470
Short name T878
Test name
Test status
Simulation time 380167885 ps
CPU time 4.13 seconds
Started Apr 25 12:54:56 PM PDT 24
Finished Apr 25 12:55:03 PM PDT 24
Peak memory 218068 kb
Host smart-31db72c7-4480-460b-bc6a-9c88f11d4866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479281470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.1479281470
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.3610426568
Short name T624
Test name
Test status
Simulation time 710197470 ps
CPU time 4.97 seconds
Started Apr 25 12:54:34 PM PDT 24
Finished Apr 25 12:54:42 PM PDT 24
Peak memory 214132 kb
Host smart-99bca678-2609-4749-83dc-1ac3c4d3266a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610426568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.3610426568
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.60975761
Short name T710
Test name
Test status
Simulation time 77407918 ps
CPU time 3.3 seconds
Started Apr 25 12:54:17 PM PDT 24
Finished Apr 25 12:54:24 PM PDT 24
Peak memory 218060 kb
Host smart-59a61c88-23a7-427b-8ad6-7f48bbb173ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60975761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.60975761
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.3490319228
Short name T342
Test name
Test status
Simulation time 357936659 ps
CPU time 3.27 seconds
Started Apr 25 12:54:16 PM PDT 24
Finished Apr 25 12:54:23 PM PDT 24
Peak memory 207976 kb
Host smart-a8cccf3a-ecd9-4730-8fe1-b9ae268418ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490319228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.3490319228
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.2243860066
Short name T493
Test name
Test status
Simulation time 23319099 ps
CPU time 1.78 seconds
Started Apr 25 12:54:36 PM PDT 24
Finished Apr 25 12:54:40 PM PDT 24
Peak memory 206496 kb
Host smart-f8362425-3021-4573-a08a-b1f63655fc6e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243860066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.2243860066
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.2769825538
Short name T368
Test name
Test status
Simulation time 7113988085 ps
CPU time 43.53 seconds
Started Apr 25 12:54:24 PM PDT 24
Finished Apr 25 12:55:11 PM PDT 24
Peak memory 207900 kb
Host smart-ba11674b-85c0-4076-9712-89ffd1cc5164
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769825538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.2769825538
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.146169008
Short name T291
Test name
Test status
Simulation time 555704681 ps
CPU time 5.92 seconds
Started Apr 25 12:54:22 PM PDT 24
Finished Apr 25 12:54:32 PM PDT 24
Peak memory 208636 kb
Host smart-651ff687-5a29-4627-b41b-6d8839220ef7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146169008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.146169008
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.4088781061
Short name T673
Test name
Test status
Simulation time 77200282 ps
CPU time 2.28 seconds
Started Apr 25 12:54:48 PM PDT 24
Finished Apr 25 12:54:52 PM PDT 24
Peak memory 209652 kb
Host smart-28981058-70b8-409c-92d5-e97a31ef7dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088781061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.4088781061
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.558089542
Short name T444
Test name
Test status
Simulation time 3178394022 ps
CPU time 47.36 seconds
Started Apr 25 12:54:27 PM PDT 24
Finished Apr 25 12:55:18 PM PDT 24
Peak memory 207884 kb
Host smart-c736e9e8-f2e1-4df9-a30b-b644c5ab1870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558089542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.558089542
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.2811386639
Short name T304
Test name
Test status
Simulation time 2020219350 ps
CPU time 23.48 seconds
Started Apr 25 12:54:29 PM PDT 24
Finished Apr 25 12:54:56 PM PDT 24
Peak memory 214796 kb
Host smart-181b4393-ca06-48c6-a64b-7dad54ce6be6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811386639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.2811386639
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.2231741667
Short name T841
Test name
Test status
Simulation time 2841115089 ps
CPU time 29.72 seconds
Started Apr 25 12:54:28 PM PDT 24
Finished Apr 25 12:55:01 PM PDT 24
Peak memory 209716 kb
Host smart-90def5b0-1682-4fcf-961f-fa042e4d8510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231741667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.2231741667
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.3960368189
Short name T586
Test name
Test status
Simulation time 129835564 ps
CPU time 1.87 seconds
Started Apr 25 12:54:27 PM PDT 24
Finished Apr 25 12:54:33 PM PDT 24
Peak memory 209808 kb
Host smart-f5d27e00-da00-4100-b2f4-0436921455e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960368189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.3960368189
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.2452857343
Short name T821
Test name
Test status
Simulation time 25645167 ps
CPU time 0.9 seconds
Started Apr 25 12:52:54 PM PDT 24
Finished Apr 25 12:52:56 PM PDT 24
Peak memory 205760 kb
Host smart-3e02d902-9efd-427b-8875-230f922ca4c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452857343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.2452857343
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.662223966
Short name T383
Test name
Test status
Simulation time 80543866 ps
CPU time 2.95 seconds
Started Apr 25 12:52:53 PM PDT 24
Finished Apr 25 12:52:58 PM PDT 24
Peak memory 215064 kb
Host smart-a5d5c297-e6df-4761-af6b-a5f95c7bfe19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=662223966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.662223966
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.2631765329
Short name T791
Test name
Test status
Simulation time 268753449 ps
CPU time 6.82 seconds
Started Apr 25 12:52:59 PM PDT 24
Finished Apr 25 12:53:07 PM PDT 24
Peak memory 217196 kb
Host smart-420cb076-185f-499f-b25a-106fa9f9c2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631765329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.2631765329
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.4094034202
Short name T650
Test name
Test status
Simulation time 272281514 ps
CPU time 3.57 seconds
Started Apr 25 12:53:09 PM PDT 24
Finished Apr 25 12:53:15 PM PDT 24
Peak memory 214124 kb
Host smart-321f9091-ddba-43e2-ba2d-3c290f4f24cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094034202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.4094034202
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.1614890629
Short name T319
Test name
Test status
Simulation time 438749145 ps
CPU time 6.96 seconds
Started Apr 25 12:53:01 PM PDT 24
Finished Apr 25 12:53:09 PM PDT 24
Peak memory 209004 kb
Host smart-aa03dc06-91d6-4ea5-9c16-3241db05a386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614890629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.1614890629
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.2266468010
Short name T727
Test name
Test status
Simulation time 379131202 ps
CPU time 3.4 seconds
Started Apr 25 12:53:04 PM PDT 24
Finished Apr 25 12:53:09 PM PDT 24
Peak memory 210532 kb
Host smart-93bd2ed6-3bc2-4d72-a807-70be23517f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266468010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.2266468010
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.2640480969
Short name T212
Test name
Test status
Simulation time 195236531 ps
CPU time 3.44 seconds
Started Apr 25 12:53:01 PM PDT 24
Finished Apr 25 12:53:06 PM PDT 24
Peak memory 222328 kb
Host smart-30f22e86-69bc-460e-83f1-b0f9430cc290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640480969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.2640480969
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.4065190712
Short name T42
Test name
Test status
Simulation time 5518805047 ps
CPU time 51.02 seconds
Started Apr 25 12:53:02 PM PDT 24
Finished Apr 25 12:53:55 PM PDT 24
Peak memory 236848 kb
Host smart-577ec664-aa01-4f9e-965c-23e4821171a5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065190712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.4065190712
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.1432046604
Short name T748
Test name
Test status
Simulation time 73822503 ps
CPU time 3 seconds
Started Apr 25 12:53:02 PM PDT 24
Finished Apr 25 12:53:06 PM PDT 24
Peak memory 206464 kb
Host smart-6130a246-70ad-4e11-9922-3652b843c1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432046604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.1432046604
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.468704619
Short name T461
Test name
Test status
Simulation time 62296784 ps
CPU time 3.03 seconds
Started Apr 25 12:53:05 PM PDT 24
Finished Apr 25 12:53:11 PM PDT 24
Peak memory 208524 kb
Host smart-a54cad2c-d75f-4e2a-b398-254ddd0c2146
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468704619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.468704619
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.1155041469
Short name T685
Test name
Test status
Simulation time 593310439 ps
CPU time 4.97 seconds
Started Apr 25 12:52:51 PM PDT 24
Finished Apr 25 12:52:57 PM PDT 24
Peak memory 208476 kb
Host smart-99681d22-0a5c-4038-ac39-b61704e70295
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155041469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.1155041469
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.578411567
Short name T429
Test name
Test status
Simulation time 555094794 ps
CPU time 4.98 seconds
Started Apr 25 12:52:52 PM PDT 24
Finished Apr 25 12:52:58 PM PDT 24
Peak memory 206564 kb
Host smart-8c4fb20b-acf0-4f39-9f00-c4537b946ceb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578411567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.578411567
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.504383125
Short name T409
Test name
Test status
Simulation time 17902150 ps
CPU time 1.6 seconds
Started Apr 25 12:53:00 PM PDT 24
Finished Apr 25 12:53:03 PM PDT 24
Peak memory 207504 kb
Host smart-35f85d11-fb0b-473e-87e4-41c20f9fe3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504383125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.504383125
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.66528726
Short name T718
Test name
Test status
Simulation time 200208500 ps
CPU time 3.35 seconds
Started Apr 25 12:52:50 PM PDT 24
Finished Apr 25 12:52:55 PM PDT 24
Peak memory 207856 kb
Host smart-3e6a661d-7495-4fd7-ad4b-900b23d64d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66528726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.66528726
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.2827148621
Short name T352
Test name
Test status
Simulation time 399214543 ps
CPU time 12.73 seconds
Started Apr 25 12:52:52 PM PDT 24
Finished Apr 25 12:53:06 PM PDT 24
Peak memory 208460 kb
Host smart-bd8649e9-485a-4aed-b9b1-9c66f3600184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827148621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.2827148621
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.331101742
Short name T380
Test name
Test status
Simulation time 111456226 ps
CPU time 2.09 seconds
Started Apr 25 12:52:59 PM PDT 24
Finished Apr 25 12:53:03 PM PDT 24
Peak memory 209712 kb
Host smart-843a2557-a13c-4e6a-a3ea-4b725a2ca00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331101742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.331101742
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.4122545292
Short name T593
Test name
Test status
Simulation time 14487905 ps
CPU time 0.71 seconds
Started Apr 25 12:54:28 PM PDT 24
Finished Apr 25 12:54:32 PM PDT 24
Peak memory 205600 kb
Host smart-5e9c2396-9bf8-4888-ab4f-d548082f102a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122545292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.4122545292
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.3511349666
Short name T896
Test name
Test status
Simulation time 28529834 ps
CPU time 2.2 seconds
Started Apr 25 12:54:23 PM PDT 24
Finished Apr 25 12:54:30 PM PDT 24
Peak memory 214136 kb
Host smart-28599bd8-162e-48cd-8e19-0edf39e0a481
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3511349666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.3511349666
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.1113587788
Short name T702
Test name
Test status
Simulation time 1413848667 ps
CPU time 6.64 seconds
Started Apr 25 12:54:19 PM PDT 24
Finished Apr 25 12:54:30 PM PDT 24
Peak memory 208808 kb
Host smart-9922db12-0d41-43b4-8e21-ea86ddbb12e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113587788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.1113587788
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.1229006850
Short name T327
Test name
Test status
Simulation time 239597035 ps
CPU time 5.41 seconds
Started Apr 25 12:54:32 PM PDT 24
Finished Apr 25 12:54:41 PM PDT 24
Peak memory 210248 kb
Host smart-a3404e28-281b-44f8-83a3-8bfbd653447d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229006850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.1229006850
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.1539703454
Short name T25
Test name
Test status
Simulation time 297878205 ps
CPU time 7.53 seconds
Started Apr 25 12:54:45 PM PDT 24
Finished Apr 25 12:54:54 PM PDT 24
Peak memory 214092 kb
Host smart-84c406c1-bde2-48b2-89cd-c59753013d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539703454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.1539703454
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.3437062087
Short name T195
Test name
Test status
Simulation time 330092744 ps
CPU time 11.07 seconds
Started Apr 25 12:54:29 PM PDT 24
Finished Apr 25 12:54:43 PM PDT 24
Peak memory 210576 kb
Host smart-7a618a84-1ea9-4286-8efb-681dc301f9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437062087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.3437062087
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.2074276601
Short name T807
Test name
Test status
Simulation time 785325791 ps
CPU time 3.79 seconds
Started Apr 25 12:54:33 PM PDT 24
Finished Apr 25 12:54:40 PM PDT 24
Peak memory 209440 kb
Host smart-912b6050-d10f-45b1-b406-3ab2bd2b9bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074276601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.2074276601
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.926708020
Short name T124
Test name
Test status
Simulation time 470839620 ps
CPU time 9.4 seconds
Started Apr 25 12:54:27 PM PDT 24
Finished Apr 25 12:54:40 PM PDT 24
Peak memory 214064 kb
Host smart-60dc0f75-dd80-49c4-a08a-98ad1c76e88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926708020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.926708020
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.3118973847
Short name T883
Test name
Test status
Simulation time 39575045 ps
CPU time 2.28 seconds
Started Apr 25 12:54:29 PM PDT 24
Finished Apr 25 12:54:34 PM PDT 24
Peak memory 206404 kb
Host smart-094d4629-a683-43cb-85f1-e575e1110777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118973847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.3118973847
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.770389148
Short name T269
Test name
Test status
Simulation time 162991584 ps
CPU time 4.53 seconds
Started Apr 25 12:54:20 PM PDT 24
Finished Apr 25 12:54:28 PM PDT 24
Peak memory 208148 kb
Host smart-cb365699-b862-4684-a359-0424a5c5c879
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770389148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.770389148
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.938477948
Short name T581
Test name
Test status
Simulation time 148834126 ps
CPU time 5.34 seconds
Started Apr 25 12:54:35 PM PDT 24
Finished Apr 25 12:54:43 PM PDT 24
Peak memory 208068 kb
Host smart-7f104625-d60c-4d01-b8e7-e2344e4f19df
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938477948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.938477948
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.2079083128
Short name T530
Test name
Test status
Simulation time 330727199 ps
CPU time 4.8 seconds
Started Apr 25 12:54:31 PM PDT 24
Finished Apr 25 12:54:39 PM PDT 24
Peak memory 208408 kb
Host smart-5fbf3e23-fd4c-40f8-a07d-b95b5fac94db
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079083128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.2079083128
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.3208310826
Short name T265
Test name
Test status
Simulation time 1048800031 ps
CPU time 4 seconds
Started Apr 25 12:54:32 PM PDT 24
Finished Apr 25 12:54:39 PM PDT 24
Peak memory 208600 kb
Host smart-33f1a069-62f7-47bc-b403-2678d46ac256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208310826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.3208310826
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.176441862
Short name T505
Test name
Test status
Simulation time 222863974 ps
CPU time 5.39 seconds
Started Apr 25 12:54:26 PM PDT 24
Finished Apr 25 12:54:35 PM PDT 24
Peak memory 207320 kb
Host smart-2e747dbd-a91d-4735-a898-5ab9bb991259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176441862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.176441862
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.2131349113
Short name T888
Test name
Test status
Simulation time 2319540491 ps
CPU time 57.66 seconds
Started Apr 25 12:54:51 PM PDT 24
Finished Apr 25 12:55:51 PM PDT 24
Peak memory 215812 kb
Host smart-dc89ba84-464a-4b9c-98e3-b5b400b31012
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131349113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.2131349113
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.1194439731
Short name T538
Test name
Test status
Simulation time 64869296 ps
CPU time 1.96 seconds
Started Apr 25 12:54:37 PM PDT 24
Finished Apr 25 12:54:41 PM PDT 24
Peak memory 209672 kb
Host smart-cf047970-4289-43b6-a1e8-7bb15ff69a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194439731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.1194439731
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.3721704979
Short name T654
Test name
Test status
Simulation time 43182152 ps
CPU time 0.85 seconds
Started Apr 25 12:54:36 PM PDT 24
Finished Apr 25 12:54:39 PM PDT 24
Peak memory 205616 kb
Host smart-5373d3ef-fb0c-4531-b90a-ab6319ea16dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721704979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.3721704979
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.3031591467
Short name T387
Test name
Test status
Simulation time 64164280 ps
CPU time 4.29 seconds
Started Apr 25 12:54:25 PM PDT 24
Finished Apr 25 12:54:33 PM PDT 24
Peak memory 215204 kb
Host smart-f2a716d6-2fd6-4e8d-89bd-3169182432d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3031591467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.3031591467
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.289062716
Short name T607
Test name
Test status
Simulation time 865397948 ps
CPU time 3 seconds
Started Apr 25 12:54:47 PM PDT 24
Finished Apr 25 12:54:52 PM PDT 24
Peak memory 214036 kb
Host smart-93a001cc-cf62-4418-8c67-512ffb4972fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289062716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.289062716
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.388838648
Short name T893
Test name
Test status
Simulation time 87840328 ps
CPU time 3.9 seconds
Started Apr 25 12:54:49 PM PDT 24
Finished Apr 25 12:54:55 PM PDT 24
Peak memory 210060 kb
Host smart-84bb0395-37ca-4fcb-ae4c-cded2d801397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388838648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.388838648
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.3004173898
Short name T344
Test name
Test status
Simulation time 438241379 ps
CPU time 8.9 seconds
Started Apr 25 12:54:34 PM PDT 24
Finished Apr 25 12:54:46 PM PDT 24
Peak memory 222216 kb
Host smart-2f60f907-f8db-4edb-9a7a-8a1772024faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004173898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.3004173898
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.2498329056
Short name T273
Test name
Test status
Simulation time 785778584 ps
CPU time 11.89 seconds
Started Apr 25 12:54:32 PM PDT 24
Finished Apr 25 12:54:47 PM PDT 24
Peak memory 214108 kb
Host smart-5f6232a0-de70-4750-94ed-d3d89051c413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498329056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.2498329056
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.2311152053
Short name T340
Test name
Test status
Simulation time 164484021 ps
CPU time 3.39 seconds
Started Apr 25 12:54:57 PM PDT 24
Finished Apr 25 12:55:03 PM PDT 24
Peak memory 219984 kb
Host smart-9d33e11f-7cb1-4396-979c-0006f49dd203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311152053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.2311152053
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.1084916616
Short name T537
Test name
Test status
Simulation time 73133756 ps
CPU time 3.77 seconds
Started Apr 25 12:54:29 PM PDT 24
Finished Apr 25 12:54:36 PM PDT 24
Peak memory 206792 kb
Host smart-20951fa4-2f73-41e4-81b6-2835cf391fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084916616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.1084916616
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.3271520221
Short name T590
Test name
Test status
Simulation time 39548516 ps
CPU time 2.42 seconds
Started Apr 25 12:54:34 PM PDT 24
Finished Apr 25 12:54:40 PM PDT 24
Peak memory 206288 kb
Host smart-4bb340b1-7902-4ff9-a134-46595fb2aea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271520221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.3271520221
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.1980500532
Short name T691
Test name
Test status
Simulation time 99144483 ps
CPU time 2.85 seconds
Started Apr 25 12:54:37 PM PDT 24
Finished Apr 25 12:54:42 PM PDT 24
Peak memory 208132 kb
Host smart-d4ec612d-1ce3-4f18-93d2-035f9a15685f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980500532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.1980500532
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.3571823059
Short name T705
Test name
Test status
Simulation time 451156354 ps
CPU time 3.84 seconds
Started Apr 25 12:54:29 PM PDT 24
Finished Apr 25 12:54:37 PM PDT 24
Peak memory 207968 kb
Host smart-404c0d93-367a-46da-b706-763b8cc75286
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571823059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.3571823059
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.4058911746
Short name T714
Test name
Test status
Simulation time 223599537 ps
CPU time 3.23 seconds
Started Apr 25 12:54:39 PM PDT 24
Finished Apr 25 12:54:44 PM PDT 24
Peak memory 208072 kb
Host smart-1859566a-0fbe-41b8-b806-646b4ba3aec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058911746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.4058911746
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.3519604008
Short name T425
Test name
Test status
Simulation time 326117029 ps
CPU time 5.6 seconds
Started Apr 25 12:54:24 PM PDT 24
Finished Apr 25 12:54:34 PM PDT 24
Peak memory 207876 kb
Host smart-724fe907-dab4-46a4-9f03-e1283c1f31f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519604008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.3519604008
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.2060453765
Short name T351
Test name
Test status
Simulation time 1282640042 ps
CPU time 11.7 seconds
Started Apr 25 12:54:43 PM PDT 24
Finished Apr 25 12:54:56 PM PDT 24
Peak memory 220604 kb
Host smart-977107f8-4570-4131-a2dc-3b4414fe3fe0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060453765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.2060453765
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.3883425995
Short name T249
Test name
Test status
Simulation time 5350688653 ps
CPU time 59.86 seconds
Started Apr 25 12:54:34 PM PDT 24
Finished Apr 25 12:55:37 PM PDT 24
Peak memory 209244 kb
Host smart-4c1f5924-d944-427f-92be-f2bc0e74641b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883425995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.3883425995
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.2477656865
Short name T128
Test name
Test status
Simulation time 1673119983 ps
CPU time 8.47 seconds
Started Apr 25 12:54:43 PM PDT 24
Finished Apr 25 12:54:53 PM PDT 24
Peak memory 210328 kb
Host smart-fa8721b0-25eb-4b8f-85b3-3da1c314c4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477656865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.2477656865
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.1797388390
Short name T491
Test name
Test status
Simulation time 12769083 ps
CPU time 0.77 seconds
Started Apr 25 12:54:32 PM PDT 24
Finished Apr 25 12:54:36 PM PDT 24
Peak memory 205708 kb
Host smart-91728b4d-858d-40d4-8901-52099c267043
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797388390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.1797388390
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.1324706250
Short name T887
Test name
Test status
Simulation time 179816569 ps
CPU time 3.28 seconds
Started Apr 25 12:54:50 PM PDT 24
Finished Apr 25 12:54:56 PM PDT 24
Peak memory 215116 kb
Host smart-6dffe7e8-78c7-4b3f-8229-742ea5285442
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1324706250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.1324706250
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.2347907366
Short name T707
Test name
Test status
Simulation time 90122569 ps
CPU time 3.43 seconds
Started Apr 25 12:54:45 PM PDT 24
Finished Apr 25 12:54:49 PM PDT 24
Peak memory 209432 kb
Host smart-3e69c183-ea82-40f9-9901-22bd49a64724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347907366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.2347907366
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.4250308244
Short name T80
Test name
Test status
Simulation time 42181792 ps
CPU time 2.29 seconds
Started Apr 25 12:54:31 PM PDT 24
Finished Apr 25 12:54:36 PM PDT 24
Peak memory 208908 kb
Host smart-cfb99738-702f-4a35-b367-9f61c328850d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250308244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.4250308244
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.2945830014
Short name T641
Test name
Test status
Simulation time 141659416 ps
CPU time 2.62 seconds
Started Apr 25 12:54:22 PM PDT 24
Finished Apr 25 12:54:28 PM PDT 24
Peak memory 214144 kb
Host smart-786e2e8b-43fa-484e-9e3f-d3dab1e86670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945830014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.2945830014
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.3566249252
Short name T99
Test name
Test status
Simulation time 162578459 ps
CPU time 6.53 seconds
Started Apr 25 12:54:46 PM PDT 24
Finished Apr 25 12:54:55 PM PDT 24
Peak memory 213988 kb
Host smart-09da5b9f-8a91-49eb-87df-e020b0b3cd06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566249252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.3566249252
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.3870467052
Short name T772
Test name
Test status
Simulation time 72573406 ps
CPU time 2.65 seconds
Started Apr 25 12:54:44 PM PDT 24
Finished Apr 25 12:54:48 PM PDT 24
Peak memory 219192 kb
Host smart-8b2d5099-6c0e-41b3-9f7d-5efe342e4b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870467052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.3870467052
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.3534138616
Short name T264
Test name
Test status
Simulation time 833816745 ps
CPU time 25.72 seconds
Started Apr 25 12:54:40 PM PDT 24
Finished Apr 25 12:55:07 PM PDT 24
Peak memory 214116 kb
Host smart-af2d90c2-c0c0-4146-bbe9-ea68f01413c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534138616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.3534138616
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.427623859
Short name T836
Test name
Test status
Simulation time 76893577 ps
CPU time 2.66 seconds
Started Apr 25 12:54:18 PM PDT 24
Finished Apr 25 12:54:25 PM PDT 24
Peak memory 208372 kb
Host smart-1afe7009-7e64-4e96-8053-dfbad6a2ff09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427623859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.427623859
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.2851207791
Short name T324
Test name
Test status
Simulation time 149437059 ps
CPU time 3.47 seconds
Started Apr 25 12:54:47 PM PDT 24
Finished Apr 25 12:54:53 PM PDT 24
Peak memory 208084 kb
Host smart-99fde629-64b5-48e3-8736-1e6f321fb01e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851207791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.2851207791
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.767619961
Short name T683
Test name
Test status
Simulation time 19686102 ps
CPU time 1.83 seconds
Started Apr 25 12:54:51 PM PDT 24
Finished Apr 25 12:54:55 PM PDT 24
Peak memory 206516 kb
Host smart-cbe169d6-e10d-4d5e-8b51-688bda7c8026
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767619961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.767619961
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.315919759
Short name T712
Test name
Test status
Simulation time 894727524 ps
CPU time 7.16 seconds
Started Apr 25 12:54:41 PM PDT 24
Finished Apr 25 12:54:50 PM PDT 24
Peak memory 208324 kb
Host smart-34db8d91-3182-42a9-ad17-ea09fd2ab95b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315919759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.315919759
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.2303457720
Short name T503
Test name
Test status
Simulation time 270685819 ps
CPU time 6.85 seconds
Started Apr 25 12:54:37 PM PDT 24
Finished Apr 25 12:54:46 PM PDT 24
Peak memory 214100 kb
Host smart-16a33d29-4fc3-4bda-8c17-fe475955b02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303457720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.2303457720
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.3109279810
Short name T669
Test name
Test status
Simulation time 907373460 ps
CPU time 5.74 seconds
Started Apr 25 12:54:32 PM PDT 24
Finished Apr 25 12:54:41 PM PDT 24
Peak memory 207804 kb
Host smart-60f3db98-2be1-4ecd-bf46-6a35653c6dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109279810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.3109279810
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.1906765095
Short name T824
Test name
Test status
Simulation time 1700190632 ps
CPU time 46.21 seconds
Started Apr 25 12:54:47 PM PDT 24
Finished Apr 25 12:55:35 PM PDT 24
Peak memory 222252 kb
Host smart-91bb1c14-1dee-4652-8935-c5093c313954
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906765095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.1906765095
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.3085869104
Short name T193
Test name
Test status
Simulation time 362311675 ps
CPU time 9.66 seconds
Started Apr 25 12:54:36 PM PDT 24
Finished Apr 25 12:54:48 PM PDT 24
Peak memory 207968 kb
Host smart-1d0b1cd2-178d-47c3-aac8-1944e815b6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085869104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.3085869104
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.3333767359
Short name T405
Test name
Test status
Simulation time 126942923 ps
CPU time 3.28 seconds
Started Apr 25 12:54:41 PM PDT 24
Finished Apr 25 12:54:46 PM PDT 24
Peak memory 209932 kb
Host smart-cf1d60c3-8804-456b-9a67-516206dd386b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333767359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.3333767359
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.4272764914
Short name T98
Test name
Test status
Simulation time 20162554 ps
CPU time 0.96 seconds
Started Apr 25 12:54:49 PM PDT 24
Finished Apr 25 12:54:52 PM PDT 24
Peak memory 205616 kb
Host smart-3dc24e64-c2fc-4baf-9619-fedc6535f1d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272764914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.4272764914
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.3915111895
Short name T47
Test name
Test status
Simulation time 55535582 ps
CPU time 1.76 seconds
Started Apr 25 12:54:55 PM PDT 24
Finished Apr 25 12:55:00 PM PDT 24
Peak memory 206804 kb
Host smart-a71d4f2c-a11f-4134-ae2c-ddb17e786373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915111895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.3915111895
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.1091144518
Short name T366
Test name
Test status
Simulation time 20171702834 ps
CPU time 58.53 seconds
Started Apr 25 12:54:33 PM PDT 24
Finished Apr 25 12:55:35 PM PDT 24
Peak memory 214180 kb
Host smart-47f75907-bee5-4e15-80a3-ce97f1a66d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091144518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.1091144518
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_random.1503763588
Short name T477
Test name
Test status
Simulation time 1048018768 ps
CPU time 4.71 seconds
Started Apr 25 12:54:37 PM PDT 24
Finished Apr 25 12:54:44 PM PDT 24
Peak memory 218148 kb
Host smart-db7a86a2-0753-4fbc-902d-f8360dd00ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503763588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.1503763588
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.3504718685
Short name T364
Test name
Test status
Simulation time 62440662 ps
CPU time 3.12 seconds
Started Apr 25 12:54:43 PM PDT 24
Finished Apr 25 12:54:48 PM PDT 24
Peak memory 208116 kb
Host smart-b64a9dd8-a4f4-4961-95f9-4c8cd7a8b72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504718685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.3504718685
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.3083462848
Short name T652
Test name
Test status
Simulation time 164900634 ps
CPU time 3.1 seconds
Started Apr 25 12:54:42 PM PDT 24
Finished Apr 25 12:54:46 PM PDT 24
Peak memory 206456 kb
Host smart-c9bb67a1-56d1-4424-93ca-96f272bc817a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083462848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.3083462848
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.1350758105
Short name T822
Test name
Test status
Simulation time 59203724 ps
CPU time 2.73 seconds
Started Apr 25 12:54:42 PM PDT 24
Finished Apr 25 12:54:46 PM PDT 24
Peak memory 208332 kb
Host smart-af6e7501-623f-47e4-b90c-3ae3dff1b9b3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350758105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.1350758105
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.1856236252
Short name T310
Test name
Test status
Simulation time 8066090425 ps
CPU time 73.43 seconds
Started Apr 25 12:54:43 PM PDT 24
Finished Apr 25 12:55:58 PM PDT 24
Peak memory 208424 kb
Host smart-5dcca3b9-8bf9-4459-ab1a-3db59479b8cb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856236252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.1856236252
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.2416954053
Short name T556
Test name
Test status
Simulation time 26698725 ps
CPU time 1.66 seconds
Started Apr 25 12:54:50 PM PDT 24
Finished Apr 25 12:54:54 PM PDT 24
Peak memory 207748 kb
Host smart-a8375b61-d4a5-40d1-84c5-db656f0fe993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416954053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.2416954053
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.1495390670
Short name T434
Test name
Test status
Simulation time 78497979 ps
CPU time 3.32 seconds
Started Apr 25 12:54:43 PM PDT 24
Finished Apr 25 12:54:48 PM PDT 24
Peak memory 208520 kb
Host smart-7f221159-5bbc-436e-a166-a30de592d8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495390670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.1495390670
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.3503871588
Short name T801
Test name
Test status
Simulation time 893130799 ps
CPU time 7.28 seconds
Started Apr 25 12:54:46 PM PDT 24
Finished Apr 25 12:54:54 PM PDT 24
Peak memory 214148 kb
Host smart-36c01a57-084d-4367-8d84-53a42dd81c40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503871588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.3503871588
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.4059050483
Short name T761
Test name
Test status
Simulation time 3275777478 ps
CPU time 22.11 seconds
Started Apr 25 12:54:45 PM PDT 24
Finished Apr 25 12:55:08 PM PDT 24
Peak memory 214172 kb
Host smart-1610869f-d2c6-4447-8b90-e6ce337c1bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059050483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.4059050483
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.2613245393
Short name T154
Test name
Test status
Simulation time 176475236 ps
CPU time 1.56 seconds
Started Apr 25 12:54:49 PM PDT 24
Finished Apr 25 12:54:54 PM PDT 24
Peak memory 209424 kb
Host smart-b399517b-9a03-45ff-aa58-3e85a602ebbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613245393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.2613245393
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.2001115920
Short name T642
Test name
Test status
Simulation time 93350430 ps
CPU time 0.94 seconds
Started Apr 25 12:54:45 PM PDT 24
Finished Apr 25 12:54:47 PM PDT 24
Peak memory 205852 kb
Host smart-8a02b29f-cdcb-47b3-91d8-b10692388bfb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001115920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.2001115920
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.3198035221
Short name T31
Test name
Test status
Simulation time 143350437 ps
CPU time 2.08 seconds
Started Apr 25 12:54:45 PM PDT 24
Finished Apr 25 12:54:49 PM PDT 24
Peak memory 218056 kb
Host smart-c9638c01-fd7b-4ea2-9bf9-f9fd09921e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198035221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.3198035221
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.1693567286
Short name T54
Test name
Test status
Simulation time 72439362 ps
CPU time 2.93 seconds
Started Apr 25 12:54:43 PM PDT 24
Finished Apr 25 12:54:47 PM PDT 24
Peak memory 209368 kb
Host smart-d06c0067-6dcc-4ba6-99e1-f3a17ca856a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693567286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.1693567286
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.2575625818
Short name T111
Test name
Test status
Simulation time 607162428 ps
CPU time 11.43 seconds
Started Apr 25 12:54:29 PM PDT 24
Finished Apr 25 12:54:44 PM PDT 24
Peak memory 214140 kb
Host smart-c6d5a673-6993-450a-8edd-b646a721aec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575625818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.2575625818
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.1108406646
Short name T671
Test name
Test status
Simulation time 349681150 ps
CPU time 4.42 seconds
Started Apr 25 12:54:45 PM PDT 24
Finished Apr 25 12:54:51 PM PDT 24
Peak memory 209284 kb
Host smart-7a49b73c-e797-4e39-956d-6b749890329e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108406646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.1108406646
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.3745205304
Short name T751
Test name
Test status
Simulation time 323785512 ps
CPU time 10.98 seconds
Started Apr 25 12:54:44 PM PDT 24
Finished Apr 25 12:54:56 PM PDT 24
Peak memory 214092 kb
Host smart-0fb39d74-41de-4f13-a860-6f8272c650c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745205304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.3745205304
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.3532972677
Short name T825
Test name
Test status
Simulation time 1217359968 ps
CPU time 18.85 seconds
Started Apr 25 12:54:45 PM PDT 24
Finished Apr 25 12:55:06 PM PDT 24
Peak memory 208132 kb
Host smart-d0e5a1ad-40db-4b33-9227-bad12de94816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532972677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.3532972677
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.659402985
Short name T226
Test name
Test status
Simulation time 72307895 ps
CPU time 2.63 seconds
Started Apr 25 12:54:32 PM PDT 24
Finished Apr 25 12:54:38 PM PDT 24
Peak memory 208472 kb
Host smart-ad61948e-e63d-4a95-9c5d-6cbae14d7112
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659402985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.659402985
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.2476165379
Short name T769
Test name
Test status
Simulation time 962978975 ps
CPU time 7.38 seconds
Started Apr 25 12:54:57 PM PDT 24
Finished Apr 25 12:55:07 PM PDT 24
Peak memory 208568 kb
Host smart-b9b99cbe-69c2-4ead-a514-5f14a72a8a2f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476165379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.2476165379
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.3692823849
Short name T181
Test name
Test status
Simulation time 1846373705 ps
CPU time 4.78 seconds
Started Apr 25 12:54:37 PM PDT 24
Finished Apr 25 12:54:44 PM PDT 24
Peak memory 207452 kb
Host smart-ee703af7-3542-4678-b064-75a48ae2f5e4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692823849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.3692823849
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.3413249701
Short name T857
Test name
Test status
Simulation time 134559741 ps
CPU time 4.09 seconds
Started Apr 25 12:54:39 PM PDT 24
Finished Apr 25 12:54:45 PM PDT 24
Peak memory 208048 kb
Host smart-213e41ae-e706-4c56-a349-58df4356daad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413249701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.3413249701
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.2652985565
Short name T423
Test name
Test status
Simulation time 519162123 ps
CPU time 5.69 seconds
Started Apr 25 12:54:40 PM PDT 24
Finished Apr 25 12:54:47 PM PDT 24
Peak memory 208032 kb
Host smart-4ec8a034-1aa6-47b3-982d-b679fc8f6654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652985565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.2652985565
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.3943055109
Short name T721
Test name
Test status
Simulation time 340036558 ps
CPU time 7.85 seconds
Started Apr 25 12:54:37 PM PDT 24
Finished Apr 25 12:54:47 PM PDT 24
Peak memory 208624 kb
Host smart-ac5151b3-7dff-4c7b-b17d-fba7e6836bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943055109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.3943055109
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.1930378996
Short name T522
Test name
Test status
Simulation time 15756297 ps
CPU time 0.81 seconds
Started Apr 25 12:54:50 PM PDT 24
Finished Apr 25 12:54:54 PM PDT 24
Peak memory 205668 kb
Host smart-13543804-e3ab-4c09-9b2c-f4c0abd535da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930378996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.1930378996
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.1200149653
Short name T234
Test name
Test status
Simulation time 115480373 ps
CPU time 4.4 seconds
Started Apr 25 12:55:00 PM PDT 24
Finished Apr 25 12:55:06 PM PDT 24
Peak memory 215156 kb
Host smart-1ec7e76c-2130-4dc7-9712-999475e9edd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1200149653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.1200149653
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.1782498610
Short name T30
Test name
Test status
Simulation time 363683654 ps
CPU time 2.24 seconds
Started Apr 25 12:54:45 PM PDT 24
Finished Apr 25 12:54:49 PM PDT 24
Peak memory 209532 kb
Host smart-efd0ca5e-97fd-4707-9c58-36a7a563aa95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782498610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.1782498610
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.1229088084
Short name T81
Test name
Test status
Simulation time 662561527 ps
CPU time 3.83 seconds
Started Apr 25 12:54:46 PM PDT 24
Finished Apr 25 12:54:51 PM PDT 24
Peak memory 214104 kb
Host smart-f9776e6a-61a9-430a-93bd-3e4e059a29b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229088084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.1229088084
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.1946767009
Short name T558
Test name
Test status
Simulation time 72979727 ps
CPU time 4.07 seconds
Started Apr 25 12:54:50 PM PDT 24
Finished Apr 25 12:54:57 PM PDT 24
Peak memory 214064 kb
Host smart-16f98e5a-754a-4e82-8172-8affe5559045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946767009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.1946767009
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.1005820833
Short name T371
Test name
Test status
Simulation time 57966400 ps
CPU time 3.66 seconds
Started Apr 25 12:54:57 PM PDT 24
Finished Apr 25 12:55:03 PM PDT 24
Peak memory 222240 kb
Host smart-3312f0de-8c3a-492b-9f13-89b9d8d8d959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005820833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.1005820833
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.1975924636
Short name T460
Test name
Test status
Simulation time 76607501 ps
CPU time 3.77 seconds
Started Apr 25 12:54:58 PM PDT 24
Finished Apr 25 12:55:04 PM PDT 24
Peak memory 214000 kb
Host smart-431ee0b8-26ef-440d-b6f4-b3ae043170fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975924636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.1975924636
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.1293613764
Short name T85
Test name
Test status
Simulation time 261706630 ps
CPU time 3.45 seconds
Started Apr 25 12:54:49 PM PDT 24
Finished Apr 25 12:54:55 PM PDT 24
Peak memory 208596 kb
Host smart-69fafaf3-f823-4aa6-b380-58ddc5024a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293613764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.1293613764
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.3872254799
Short name T231
Test name
Test status
Simulation time 1172447180 ps
CPU time 11.67 seconds
Started Apr 25 12:54:43 PM PDT 24
Finished Apr 25 12:54:57 PM PDT 24
Peak memory 208236 kb
Host smart-04846618-11d0-4b41-81d8-4be3d298655e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872254799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.3872254799
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.1322810476
Short name T359
Test name
Test status
Simulation time 755852575 ps
CPU time 23.23 seconds
Started Apr 25 12:54:38 PM PDT 24
Finished Apr 25 12:55:03 PM PDT 24
Peak memory 208404 kb
Host smart-28d87c3d-82b7-4848-b58f-c9ce3afdbc97
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322810476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.1322810476
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.347401260
Short name T602
Test name
Test status
Simulation time 61498219 ps
CPU time 2.42 seconds
Started Apr 25 12:54:43 PM PDT 24
Finished Apr 25 12:54:47 PM PDT 24
Peak memory 206580 kb
Host smart-c4d68103-5594-4008-86b4-56696da2fbbf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347401260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.347401260
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.3836151159
Short name T613
Test name
Test status
Simulation time 3507743540 ps
CPU time 52.06 seconds
Started Apr 25 12:54:50 PM PDT 24
Finished Apr 25 12:55:45 PM PDT 24
Peak memory 207968 kb
Host smart-1132d970-197b-4b71-b013-6041e564e594
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836151159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.3836151159
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.1582886348
Short name T457
Test name
Test status
Simulation time 175360969 ps
CPU time 4.05 seconds
Started Apr 25 12:54:52 PM PDT 24
Finished Apr 25 12:54:59 PM PDT 24
Peak memory 208688 kb
Host smart-979af304-94a8-49c2-984a-c5481c5f554b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582886348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.1582886348
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.1492480063
Short name T764
Test name
Test status
Simulation time 63661298 ps
CPU time 2.34 seconds
Started Apr 25 12:54:45 PM PDT 24
Finished Apr 25 12:54:49 PM PDT 24
Peak memory 206516 kb
Host smart-6494ffc8-8736-4be3-a04a-ff4907b7888a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492480063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.1492480063
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.2732633693
Short name T687
Test name
Test status
Simulation time 2988634760 ps
CPU time 18.96 seconds
Started Apr 25 12:54:44 PM PDT 24
Finished Apr 25 12:55:05 PM PDT 24
Peak memory 214720 kb
Host smart-89ac2849-ad58-4b5e-acdb-36d821ad1373
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732633693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.2732633693
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.3650929618
Short name T169
Test name
Test status
Simulation time 265030137 ps
CPU time 9.59 seconds
Started Apr 25 12:55:03 PM PDT 24
Finished Apr 25 12:55:15 PM PDT 24
Peak memory 222360 kb
Host smart-d0fcba04-a18f-40a0-96d3-4243add81108
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650929618 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.3650929618
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.531896408
Short name T302
Test name
Test status
Simulation time 641332317 ps
CPU time 5.47 seconds
Started Apr 25 12:54:47 PM PDT 24
Finished Apr 25 12:54:54 PM PDT 24
Peak memory 207600 kb
Host smart-85d63a80-8e8c-40c4-a969-3fbd26201ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531896408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.531896408
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.3062988264
Short name T483
Test name
Test status
Simulation time 115155543 ps
CPU time 2.5 seconds
Started Apr 25 12:54:48 PM PDT 24
Finished Apr 25 12:54:52 PM PDT 24
Peak memory 209404 kb
Host smart-2a596a64-b30f-4ac2-bff4-de5c32385543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062988264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.3062988264
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.4060792821
Short name T599
Test name
Test status
Simulation time 79137896 ps
CPU time 0.96 seconds
Started Apr 25 12:55:11 PM PDT 24
Finished Apr 25 12:55:14 PM PDT 24
Peak memory 205764 kb
Host smart-76161d4b-3375-4118-b106-4599687adcab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060792821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.4060792821
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.1685041010
Short name T132
Test name
Test status
Simulation time 670118188 ps
CPU time 11.69 seconds
Started Apr 25 12:55:13 PM PDT 24
Finished Apr 25 12:55:28 PM PDT 24
Peak memory 214076 kb
Host smart-04499bcd-70eb-4387-b6d2-cc8d534f1f69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1685041010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.1685041010
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.1860423117
Short name T518
Test name
Test status
Simulation time 1607174148 ps
CPU time 10.59 seconds
Started Apr 25 12:54:54 PM PDT 24
Finished Apr 25 12:55:07 PM PDT 24
Peak memory 221248 kb
Host smart-fb487d5d-2caf-40cf-806c-bf3d7ed43e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860423117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.1860423117
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.140313970
Short name T839
Test name
Test status
Simulation time 607949671 ps
CPU time 13.79 seconds
Started Apr 25 12:54:50 PM PDT 24
Finished Apr 25 12:55:07 PM PDT 24
Peak memory 208496 kb
Host smart-a79f89db-f6de-4352-a8f8-07ae0b37af79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140313970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.140313970
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.2569543155
Short name T525
Test name
Test status
Simulation time 323925228 ps
CPU time 9.81 seconds
Started Apr 25 12:55:02 PM PDT 24
Finished Apr 25 12:55:13 PM PDT 24
Peak memory 214008 kb
Host smart-4607af8e-1a6a-41e9-af68-c15eee4b80d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569543155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.2569543155
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.1648309631
Short name T204
Test name
Test status
Simulation time 373881107 ps
CPU time 3.82 seconds
Started Apr 25 12:54:48 PM PDT 24
Finished Apr 25 12:54:54 PM PDT 24
Peak memory 220220 kb
Host smart-d94da62f-797b-4f0a-9a38-6572bce596a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648309631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.1648309631
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.917309221
Short name T251
Test name
Test status
Simulation time 210714418 ps
CPU time 6.53 seconds
Started Apr 25 12:54:47 PM PDT 24
Finished Apr 25 12:54:55 PM PDT 24
Peak memory 214040 kb
Host smart-b120b6fb-eaf0-484c-8460-f91cb3dccd52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917309221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.917309221
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.4254328846
Short name T482
Test name
Test status
Simulation time 1151226479 ps
CPU time 35.75 seconds
Started Apr 25 12:54:59 PM PDT 24
Finished Apr 25 12:55:42 PM PDT 24
Peak memory 208568 kb
Host smart-e2156314-842e-42c2-b0d6-b28c7bcfaf2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254328846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.4254328846
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.1112633506
Short name T777
Test name
Test status
Simulation time 481254812 ps
CPU time 12.81 seconds
Started Apr 25 12:54:56 PM PDT 24
Finished Apr 25 12:55:11 PM PDT 24
Peak memory 207632 kb
Host smart-847db52b-9017-49c7-9ca8-f774d1959b89
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112633506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.1112633506
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.90342707
Short name T651
Test name
Test status
Simulation time 186636116 ps
CPU time 5.87 seconds
Started Apr 25 12:54:49 PM PDT 24
Finished Apr 25 12:54:57 PM PDT 24
Peak memory 207992 kb
Host smart-d198e1ce-3d27-4e81-8301-ba456feddec3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90342707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.90342707
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.2103749338
Short name T750
Test name
Test status
Simulation time 215063023 ps
CPU time 4.09 seconds
Started Apr 25 12:54:46 PM PDT 24
Finished Apr 25 12:54:52 PM PDT 24
Peak memory 208324 kb
Host smart-32f4a87e-1d71-4024-b55e-5397ba1f5786
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103749338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.2103749338
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.4277718389
Short name T715
Test name
Test status
Simulation time 188853444 ps
CPU time 5.27 seconds
Started Apr 25 12:54:34 PM PDT 24
Finished Apr 25 12:54:42 PM PDT 24
Peak memory 209296 kb
Host smart-bc14cd96-9cd5-4dd6-bebe-8af214d64b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277718389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.4277718389
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.2491011385
Short name T699
Test name
Test status
Simulation time 3663224117 ps
CPU time 11.79 seconds
Started Apr 25 12:54:59 PM PDT 24
Finished Apr 25 12:55:13 PM PDT 24
Peak memory 208096 kb
Host smart-01d78c1c-39cd-4c98-bea1-740929a31730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491011385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.2491011385
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.2100422325
Short name T246
Test name
Test status
Simulation time 297870563 ps
CPU time 8.99 seconds
Started Apr 25 12:54:53 PM PDT 24
Finished Apr 25 12:55:05 PM PDT 24
Peak memory 214608 kb
Host smart-bea22296-78ff-4f31-8592-f95320467282
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100422325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.2100422325
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.2110762918
Short name T326
Test name
Test status
Simulation time 875799074 ps
CPU time 10.54 seconds
Started Apr 25 12:55:01 PM PDT 24
Finished Apr 25 12:55:13 PM PDT 24
Peak memory 222324 kb
Host smart-e2853efe-f532-46ce-abf7-5df8f1a3d201
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110762918 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.2110762918
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.1287531799
Short name T182
Test name
Test status
Simulation time 202574071 ps
CPU time 5.02 seconds
Started Apr 25 12:54:43 PM PDT 24
Finished Apr 25 12:54:50 PM PDT 24
Peak memory 214080 kb
Host smart-18c15f7c-94f5-4655-8589-062910a21069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287531799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.1287531799
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.2188630925
Short name T850
Test name
Test status
Simulation time 138018745 ps
CPU time 1.96 seconds
Started Apr 25 12:54:55 PM PDT 24
Finished Apr 25 12:55:00 PM PDT 24
Peak memory 209232 kb
Host smart-fbf956e1-a762-405a-97ac-c76bcb48fc2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188630925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.2188630925
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.3814945917
Short name T431
Test name
Test status
Simulation time 68159997 ps
CPU time 0.76 seconds
Started Apr 25 12:54:59 PM PDT 24
Finished Apr 25 12:55:02 PM PDT 24
Peak memory 205528 kb
Host smart-d6af5fef-96d8-4571-9a43-fadfff4555c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814945917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.3814945917
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.1023189381
Short name T744
Test name
Test status
Simulation time 56007151 ps
CPU time 3.96 seconds
Started Apr 25 12:54:57 PM PDT 24
Finished Apr 25 12:55:03 PM PDT 24
Peak memory 215328 kb
Host smart-9a06326a-230d-4bdd-b338-ba7384232417
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1023189381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.1023189381
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.4023707327
Short name T39
Test name
Test status
Simulation time 552785336 ps
CPU time 5.59 seconds
Started Apr 25 12:55:03 PM PDT 24
Finished Apr 25 12:55:11 PM PDT 24
Peak memory 214056 kb
Host smart-21aceb9d-319b-4321-b615-66ba7f3fbe66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023707327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.4023707327
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.2840411058
Short name T361
Test name
Test status
Simulation time 79595485 ps
CPU time 2.35 seconds
Started Apr 25 12:54:49 PM PDT 24
Finished Apr 25 12:54:54 PM PDT 24
Peak memory 207692 kb
Host smart-f3df2bdb-4e8f-468e-a0f0-6d63b463ebca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840411058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.2840411058
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.538212224
Short name T481
Test name
Test status
Simulation time 236950229 ps
CPU time 6.15 seconds
Started Apr 25 12:54:56 PM PDT 24
Finished Apr 25 12:55:05 PM PDT 24
Peak memory 221096 kb
Host smart-cf5611a4-0ea5-49f2-bfc6-f41ae1e29577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538212224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.538212224
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.1556325309
Short name T271
Test name
Test status
Simulation time 99180988 ps
CPU time 4.07 seconds
Started Apr 25 12:54:50 PM PDT 24
Finished Apr 25 12:54:57 PM PDT 24
Peak memory 214112 kb
Host smart-cc445579-e1f4-4854-8921-2ef98948189c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556325309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.1556325309
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.2222192152
Short name T50
Test name
Test status
Simulation time 250798689 ps
CPU time 2.34 seconds
Started Apr 25 12:54:59 PM PDT 24
Finished Apr 25 12:55:04 PM PDT 24
Peak memory 214024 kb
Host smart-03cc28e4-cc34-4814-a304-15aebe444de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222192152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.2222192152
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.2723894464
Short name T515
Test name
Test status
Simulation time 402551833 ps
CPU time 7.31 seconds
Started Apr 25 12:54:56 PM PDT 24
Finished Apr 25 12:55:06 PM PDT 24
Peak memory 218116 kb
Host smart-c1fa1a95-1dff-44e8-8d83-e7feb60b926f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723894464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.2723894464
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.2435595700
Short name T831
Test name
Test status
Simulation time 61344536 ps
CPU time 3.16 seconds
Started Apr 25 12:54:54 PM PDT 24
Finished Apr 25 12:55:00 PM PDT 24
Peak memory 208248 kb
Host smart-b0e857b4-6b03-4d5d-9e6d-c32ed21dccf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435595700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.2435595700
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.3534054470
Short name T696
Test name
Test status
Simulation time 452918575 ps
CPU time 9.36 seconds
Started Apr 25 12:54:54 PM PDT 24
Finished Apr 25 12:55:06 PM PDT 24
Peak memory 208528 kb
Host smart-d4155973-63b0-4895-9c80-0559e9934463
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534054470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.3534054470
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.4207417922
Short name T592
Test name
Test status
Simulation time 150107507 ps
CPU time 2.25 seconds
Started Apr 25 12:55:14 PM PDT 24
Finished Apr 25 12:55:19 PM PDT 24
Peak memory 206604 kb
Host smart-aca7c4fe-db1a-4122-9873-a2becbc12b75
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207417922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.4207417922
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.3298139800
Short name T445
Test name
Test status
Simulation time 189624466 ps
CPU time 2.82 seconds
Started Apr 25 12:54:53 PM PDT 24
Finished Apr 25 12:54:59 PM PDT 24
Peak memory 208240 kb
Host smart-bb1ffe95-78eb-4e38-82b0-70fc68146b45
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298139800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.3298139800
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.2288880106
Short name T178
Test name
Test status
Simulation time 262710368 ps
CPU time 3.13 seconds
Started Apr 25 12:55:11 PM PDT 24
Finished Apr 25 12:55:17 PM PDT 24
Peak memory 209392 kb
Host smart-fe2100ce-d3da-45ee-95a8-ca1130ecf02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288880106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.2288880106
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.3071360566
Short name T813
Test name
Test status
Simulation time 476739963 ps
CPU time 3.49 seconds
Started Apr 25 12:55:10 PM PDT 24
Finished Apr 25 12:55:14 PM PDT 24
Peak memory 207768 kb
Host smart-c99bf0f3-64b9-4641-b697-4defa7548ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071360566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.3071360566
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.966892608
Short name T129
Test name
Test status
Simulation time 404741327 ps
CPU time 20.41 seconds
Started Apr 25 12:55:03 PM PDT 24
Finished Apr 25 12:55:25 PM PDT 24
Peak memory 222512 kb
Host smart-96c1ae6c-0189-4f57-b432-11d49bafa8ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966892608 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.966892608
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.2913439183
Short name T183
Test name
Test status
Simulation time 255105881 ps
CPU time 7.75 seconds
Started Apr 25 12:54:57 PM PDT 24
Finished Apr 25 12:55:07 PM PDT 24
Peak memory 208272 kb
Host smart-bc1e183b-86c7-4450-8837-eeca6870279d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913439183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.2913439183
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.3131767532
Short name T155
Test name
Test status
Simulation time 149313874 ps
CPU time 2.7 seconds
Started Apr 25 12:54:55 PM PDT 24
Finished Apr 25 12:55:01 PM PDT 24
Peak memory 210044 kb
Host smart-b32b9ba4-7f8d-48ae-af8d-34c268977978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131767532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.3131767532
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.1336003359
Short name T426
Test name
Test status
Simulation time 38219432 ps
CPU time 0.78 seconds
Started Apr 25 12:54:57 PM PDT 24
Finished Apr 25 12:55:00 PM PDT 24
Peak memory 205624 kb
Host smart-f7ed3365-8afd-4821-a112-04c42862a328
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336003359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.1336003359
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.3229340265
Short name T793
Test name
Test status
Simulation time 226680597 ps
CPU time 4.01 seconds
Started Apr 25 12:55:02 PM PDT 24
Finished Apr 25 12:55:08 PM PDT 24
Peak memory 214056 kb
Host smart-0a6a69d8-07fb-44c5-88bc-eb2690e6f0d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3229340265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.3229340265
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.2384335723
Short name T21
Test name
Test status
Simulation time 401538000 ps
CPU time 3.46 seconds
Started Apr 25 12:54:55 PM PDT 24
Finished Apr 25 12:55:01 PM PDT 24
Peak memory 215516 kb
Host smart-5a5abc5c-941a-47d0-8c6f-1105211c4866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384335723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.2384335723
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.1458639473
Short name T76
Test name
Test status
Simulation time 171771278 ps
CPU time 2.53 seconds
Started Apr 25 12:54:51 PM PDT 24
Finished Apr 25 12:54:56 PM PDT 24
Peak memory 207580 kb
Host smart-150e73d9-e3d5-4cc8-a514-60dfa871f9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458639473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.1458639473
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.1287165351
Short name T516
Test name
Test status
Simulation time 185927744 ps
CPU time 3.99 seconds
Started Apr 25 12:54:54 PM PDT 24
Finished Apr 25 12:55:01 PM PDT 24
Peak memory 214120 kb
Host smart-a2b23279-e1bd-4368-b035-8ead239f4d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287165351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.1287165351
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.4100591805
Short name T568
Test name
Test status
Simulation time 128923500 ps
CPU time 3.4 seconds
Started Apr 25 12:54:53 PM PDT 24
Finished Apr 25 12:55:00 PM PDT 24
Peak memory 214132 kb
Host smart-8a407b8a-f762-44e4-a21a-3395ec7320f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100591805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.4100591805
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.3620144575
Short name T513
Test name
Test status
Simulation time 243925164 ps
CPU time 7.98 seconds
Started Apr 25 12:54:58 PM PDT 24
Finished Apr 25 12:55:09 PM PDT 24
Peak memory 222216 kb
Host smart-f27404e1-6c42-41e3-a82b-7778f6b44585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620144575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.3620144575
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.2632229627
Short name T350
Test name
Test status
Simulation time 407166490 ps
CPU time 8.05 seconds
Started Apr 25 12:55:01 PM PDT 24
Finished Apr 25 12:55:11 PM PDT 24
Peak memory 208140 kb
Host smart-fa2b0486-fc46-413f-af5a-23b71151e0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632229627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.2632229627
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.1455925621
Short name T880
Test name
Test status
Simulation time 97623216 ps
CPU time 2.67 seconds
Started Apr 25 12:54:51 PM PDT 24
Finished Apr 25 12:54:57 PM PDT 24
Peak memory 206544 kb
Host smart-9b8b4df4-4adc-4c9d-969a-f11b89c37f15
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455925621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.1455925621
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.2961912218
Short name T394
Test name
Test status
Simulation time 32094567 ps
CPU time 2.29 seconds
Started Apr 25 12:54:51 PM PDT 24
Finished Apr 25 12:54:56 PM PDT 24
Peak memory 206400 kb
Host smart-bbb086cc-8076-4955-8afa-7ad9246e759f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961912218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.2961912218
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.3124812756
Short name T767
Test name
Test status
Simulation time 340696135 ps
CPU time 13.13 seconds
Started Apr 25 12:54:51 PM PDT 24
Finished Apr 25 12:55:07 PM PDT 24
Peak memory 208196 kb
Host smart-01d751db-6181-4299-982e-05ad2bf88105
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124812756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.3124812756
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.1174221499
Short name T357
Test name
Test status
Simulation time 206673488 ps
CPU time 3.39 seconds
Started Apr 25 12:54:58 PM PDT 24
Finished Apr 25 12:55:04 PM PDT 24
Peak memory 214028 kb
Host smart-a1fe3f4a-6215-4471-956c-5c4d0698c549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174221499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.1174221499
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.615490572
Short name T3
Test name
Test status
Simulation time 563222230 ps
CPU time 4.65 seconds
Started Apr 25 12:54:51 PM PDT 24
Finished Apr 25 12:54:59 PM PDT 24
Peak memory 206304 kb
Host smart-22b94231-3d35-4262-9332-f0082d8bd592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615490572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.615490572
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.3427898791
Short name T879
Test name
Test status
Simulation time 208352119 ps
CPU time 4.77 seconds
Started Apr 25 12:54:55 PM PDT 24
Finished Apr 25 12:55:03 PM PDT 24
Peak memory 218104 kb
Host smart-55c80a08-4163-4c19-94e3-41c4d092229f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427898791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.3427898791
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.2156919855
Short name T459
Test name
Test status
Simulation time 50936294 ps
CPU time 2.49 seconds
Started Apr 25 12:54:47 PM PDT 24
Finished Apr 25 12:54:52 PM PDT 24
Peak memory 209768 kb
Host smart-b4ba75af-fcab-41b8-9a59-4ab3c3d9d755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156919855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.2156919855
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.556413334
Short name T762
Test name
Test status
Simulation time 35101929 ps
CPU time 0.77 seconds
Started Apr 25 12:55:16 PM PDT 24
Finished Apr 25 12:55:20 PM PDT 24
Peak memory 205704 kb
Host smart-d1a49b20-aee0-4866-96c6-b7e3a3a9c12d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556413334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.556413334
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.2617773503
Short name T670
Test name
Test status
Simulation time 482829476 ps
CPU time 5.83 seconds
Started Apr 25 12:55:12 PM PDT 24
Finished Apr 25 12:55:21 PM PDT 24
Peak memory 210180 kb
Host smart-72c673a3-3fe5-4c23-b99c-59180e1ddf3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617773503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.2617773503
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.2190931805
Short name T79
Test name
Test status
Simulation time 504073394 ps
CPU time 11.42 seconds
Started Apr 25 12:54:53 PM PDT 24
Finished Apr 25 12:55:08 PM PDT 24
Peak memory 209488 kb
Host smart-56ceb5d3-7ec6-4ebb-bb92-c56aad75d367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190931805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.2190931805
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.1112582485
Short name T864
Test name
Test status
Simulation time 142230379 ps
CPU time 4.6 seconds
Started Apr 25 12:55:02 PM PDT 24
Finished Apr 25 12:55:09 PM PDT 24
Peak memory 222296 kb
Host smart-c3d79003-a09d-484a-9524-ed5f11edce9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112582485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.1112582485
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.1856683566
Short name T660
Test name
Test status
Simulation time 101246649 ps
CPU time 3.31 seconds
Started Apr 25 12:55:04 PM PDT 24
Finished Apr 25 12:55:10 PM PDT 24
Peak memory 215068 kb
Host smart-ce0b50ee-cef8-48d6-a187-b71b2e31a743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856683566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.1856683566
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.613156405
Short name T526
Test name
Test status
Simulation time 4025742230 ps
CPU time 54.26 seconds
Started Apr 25 12:54:50 PM PDT 24
Finished Apr 25 12:55:47 PM PDT 24
Peak memory 208520 kb
Host smart-ae6bddbb-3561-4398-8370-aed6ffe2b306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613156405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.613156405
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.2050550855
Short name T740
Test name
Test status
Simulation time 37059594 ps
CPU time 2.37 seconds
Started Apr 25 12:54:54 PM PDT 24
Finished Apr 25 12:55:00 PM PDT 24
Peak memory 208276 kb
Host smart-c8df79f0-fc35-4561-b1e8-3012ba8bebef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050550855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.2050550855
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.3264708366
Short name T275
Test name
Test status
Simulation time 235558594 ps
CPU time 2.97 seconds
Started Apr 25 12:54:58 PM PDT 24
Finished Apr 25 12:55:03 PM PDT 24
Peak memory 208452 kb
Host smart-ab19eea8-f2bb-47c6-a857-03f5f4103b87
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264708366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.3264708366
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.2791193320
Short name T247
Test name
Test status
Simulation time 91906693 ps
CPU time 2.59 seconds
Started Apr 25 12:54:53 PM PDT 24
Finished Apr 25 12:54:59 PM PDT 24
Peak memory 208516 kb
Host smart-45e0aa9b-f257-40d4-a046-ab69aac3489d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791193320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.2791193320
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.4058664696
Short name T781
Test name
Test status
Simulation time 100439618 ps
CPU time 2.04 seconds
Started Apr 25 12:55:02 PM PDT 24
Finished Apr 25 12:55:06 PM PDT 24
Peak memory 208248 kb
Host smart-5044b888-1a46-4925-9643-aa2c6ca1a727
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058664696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.4058664696
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.453709597
Short name T347
Test name
Test status
Simulation time 140234322 ps
CPU time 3.06 seconds
Started Apr 25 12:55:04 PM PDT 24
Finished Apr 25 12:55:10 PM PDT 24
Peak memory 218024 kb
Host smart-57586ef1-9500-4c4c-acd9-47eaba940d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453709597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.453709597
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.3553634088
Short name T636
Test name
Test status
Simulation time 63963798 ps
CPU time 2.28 seconds
Started Apr 25 12:54:54 PM PDT 24
Finished Apr 25 12:54:59 PM PDT 24
Peak memory 206716 kb
Host smart-a347aa03-8d0b-405d-81f5-fa0ee0b612c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553634088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.3553634088
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.4084719493
Short name T763
Test name
Test status
Simulation time 5546089880 ps
CPU time 102.88 seconds
Started Apr 25 12:55:23 PM PDT 24
Finished Apr 25 12:57:08 PM PDT 24
Peak memory 214096 kb
Host smart-10f265c2-57b8-4391-a4fe-e00ccaf45383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084719493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.4084719493
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.2170314549
Short name T404
Test name
Test status
Simulation time 1133084151 ps
CPU time 10.58 seconds
Started Apr 25 12:55:00 PM PDT 24
Finished Apr 25 12:55:13 PM PDT 24
Peak memory 210808 kb
Host smart-09c47a71-b8ca-47a5-9986-65460df6070f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170314549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.2170314549
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.1730853014
Short name T422
Test name
Test status
Simulation time 59961969 ps
CPU time 0.79 seconds
Started Apr 25 12:53:19 PM PDT 24
Finished Apr 25 12:53:22 PM PDT 24
Peak memory 205712 kb
Host smart-ca83e92b-787d-442f-a462-84af9dcb80bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730853014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.1730853014
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.1364702252
Short name T719
Test name
Test status
Simulation time 155023801 ps
CPU time 9.03 seconds
Started Apr 25 12:52:59 PM PDT 24
Finished Apr 25 12:53:10 PM PDT 24
Peak memory 214480 kb
Host smart-4766c9f3-ee93-4ec0-b040-ceac97622863
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1364702252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.1364702252
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.16209879
Short name T737
Test name
Test status
Simulation time 1165321100 ps
CPU time 23.83 seconds
Started Apr 25 12:53:08 PM PDT 24
Finished Apr 25 12:53:35 PM PDT 24
Peak memory 218936 kb
Host smart-52e6d429-cad7-47c4-8690-c58064e7dde3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16209879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.16209879
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.1780774042
Short name T63
Test name
Test status
Simulation time 278080350 ps
CPU time 6.32 seconds
Started Apr 25 12:53:06 PM PDT 24
Finished Apr 25 12:53:15 PM PDT 24
Peak memory 209644 kb
Host smart-984494b0-8ff3-44bb-a6e6-cddb87eed5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780774042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.1780774042
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.1756700385
Short name T889
Test name
Test status
Simulation time 186135708 ps
CPU time 4.06 seconds
Started Apr 25 12:53:03 PM PDT 24
Finished Apr 25 12:53:08 PM PDT 24
Peak memory 208492 kb
Host smart-488ca0e3-0509-46c8-8f6b-d39511d138c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756700385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.1756700385
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.1988733303
Short name T202
Test name
Test status
Simulation time 106439739 ps
CPU time 5.79 seconds
Started Apr 25 12:53:08 PM PDT 24
Finished Apr 25 12:53:17 PM PDT 24
Peak memory 220248 kb
Host smart-c41ba158-98a9-4ed6-9dc5-e61fe9a901c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988733303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.1988733303
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.283503968
Short name T618
Test name
Test status
Simulation time 94809594 ps
CPU time 4.7 seconds
Started Apr 25 12:53:04 PM PDT 24
Finished Apr 25 12:53:11 PM PDT 24
Peak memory 208372 kb
Host smart-30ac051b-baa0-45e7-9c24-2427130e281d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283503968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.283503968
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.2865710187
Short name T192
Test name
Test status
Simulation time 66062373 ps
CPU time 3.1 seconds
Started Apr 25 12:53:07 PM PDT 24
Finished Apr 25 12:53:18 PM PDT 24
Peak memory 208180 kb
Host smart-ccd71b1e-f16a-4826-87d9-c678a33b5318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865710187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.2865710187
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.471768023
Short name T892
Test name
Test status
Simulation time 85759176 ps
CPU time 2.93 seconds
Started Apr 25 12:52:54 PM PDT 24
Finished Apr 25 12:52:58 PM PDT 24
Peak memory 207048 kb
Host smart-a83cd189-de5d-492e-bb8a-b115b5932a43
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471768023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.471768023
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.2610623302
Short name T447
Test name
Test status
Simulation time 156438423 ps
CPU time 2.4 seconds
Started Apr 25 12:52:50 PM PDT 24
Finished Apr 25 12:52:55 PM PDT 24
Peak memory 206420 kb
Host smart-a4440e8d-68ad-49f6-80a9-1122f4941331
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610623302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.2610623302
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.3676612853
Short name T664
Test name
Test status
Simulation time 51817467 ps
CPU time 2.93 seconds
Started Apr 25 12:53:10 PM PDT 24
Finished Apr 25 12:53:16 PM PDT 24
Peak memory 206492 kb
Host smart-81a94b79-9036-4574-a55a-bffe7ee07148
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676612853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.3676612853
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.3190452432
Short name T603
Test name
Test status
Simulation time 134592085 ps
CPU time 1.89 seconds
Started Apr 25 12:53:03 PM PDT 24
Finished Apr 25 12:53:05 PM PDT 24
Peak memory 208760 kb
Host smart-42e91d47-0d15-440d-9026-49b8b32c4354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190452432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.3190452432
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.1377947293
Short name T473
Test name
Test status
Simulation time 159055450 ps
CPU time 2.31 seconds
Started Apr 25 12:53:04 PM PDT 24
Finished Apr 25 12:53:08 PM PDT 24
Peak memory 206528 kb
Host smart-3f9a2acd-1be1-4802-8731-012a8a35a8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377947293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.1377947293
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.1138551795
Short name T307
Test name
Test status
Simulation time 1136223994 ps
CPU time 43.87 seconds
Started Apr 25 12:53:21 PM PDT 24
Finished Apr 25 12:54:06 PM PDT 24
Peak memory 215004 kb
Host smart-69f143f0-649d-45b5-aeee-2bd1e65d619c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138551795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.1138551795
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.1609031266
Short name T735
Test name
Test status
Simulation time 5092123187 ps
CPU time 27.16 seconds
Started Apr 25 12:52:47 PM PDT 24
Finished Apr 25 12:53:16 PM PDT 24
Peak memory 214108 kb
Host smart-99b23d93-172b-48c1-8297-a777a3aae674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609031266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.1609031266
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.1881376813
Short name T738
Test name
Test status
Simulation time 10790248 ps
CPU time 0.8 seconds
Started Apr 25 12:53:51 PM PDT 24
Finished Apr 25 12:53:53 PM PDT 24
Peak memory 205380 kb
Host smart-f73f13d1-f7c5-449e-9cdf-06456178ed30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881376813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.1881376813
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.3889038124
Short name T407
Test name
Test status
Simulation time 229989311 ps
CPU time 6.04 seconds
Started Apr 25 12:53:59 PM PDT 24
Finished Apr 25 12:54:09 PM PDT 24
Peak memory 213948 kb
Host smart-76161c1b-0cda-4305-b792-b3fa15c8897e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3889038124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.3889038124
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.54565955
Short name T854
Test name
Test status
Simulation time 179267629 ps
CPU time 4.78 seconds
Started Apr 25 12:53:01 PM PDT 24
Finished Apr 25 12:53:07 PM PDT 24
Peak memory 207472 kb
Host smart-d3cf25f0-c567-48eb-abe8-b58e12b9a39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54565955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.54565955
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.149045802
Short name T403
Test name
Test status
Simulation time 826114619 ps
CPU time 6.52 seconds
Started Apr 25 12:52:55 PM PDT 24
Finished Apr 25 12:53:03 PM PDT 24
Peak memory 208840 kb
Host smart-32ec6467-ccca-4847-8afd-eae579b10bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149045802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.149045802
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.954978918
Short name T86
Test name
Test status
Simulation time 61304167 ps
CPU time 2.43 seconds
Started Apr 25 12:53:05 PM PDT 24
Finished Apr 25 12:53:11 PM PDT 24
Peak memory 219056 kb
Host smart-ab4fe652-a9ec-40ab-bd58-b06a0c963dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954978918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.954978918
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.1136767598
Short name T314
Test name
Test status
Simulation time 527793587 ps
CPU time 13.9 seconds
Started Apr 25 12:53:03 PM PDT 24
Finished Apr 25 12:53:19 PM PDT 24
Peak memory 211272 kb
Host smart-0680db52-f16c-4905-901f-27d11cbfb528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136767598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.1136767598
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.1287557057
Short name T19
Test name
Test status
Simulation time 168183840 ps
CPU time 2.41 seconds
Started Apr 25 12:52:59 PM PDT 24
Finished Apr 25 12:53:03 PM PDT 24
Peak memory 222336 kb
Host smart-071622c9-7f56-4d2b-b1ab-b885b93a2cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287557057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.1287557057
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.3068504361
Short name T245
Test name
Test status
Simulation time 441757900 ps
CPU time 4.69 seconds
Started Apr 25 12:53:51 PM PDT 24
Finished Apr 25 12:53:57 PM PDT 24
Peak memory 217888 kb
Host smart-38d735aa-5622-4174-9206-1d557ad80f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068504361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.3068504361
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.4115346941
Short name T288
Test name
Test status
Simulation time 26831491 ps
CPU time 2.06 seconds
Started Apr 25 12:53:04 PM PDT 24
Finished Apr 25 12:53:08 PM PDT 24
Peak memory 207928 kb
Host smart-24a1b4d9-6cad-4f21-963b-eec06f0d9ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115346941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.4115346941
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.4209745893
Short name T479
Test name
Test status
Simulation time 215797734 ps
CPU time 3.67 seconds
Started Apr 25 12:53:06 PM PDT 24
Finished Apr 25 12:53:13 PM PDT 24
Peak memory 208468 kb
Host smart-e8aafc5c-2fd0-415f-8825-a4bf0b1102e7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209745893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.4209745893
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.1732189386
Short name T571
Test name
Test status
Simulation time 198374918 ps
CPU time 4.42 seconds
Started Apr 25 12:53:06 PM PDT 24
Finished Apr 25 12:53:13 PM PDT 24
Peak memory 206500 kb
Host smart-9d9b6f63-3fe7-4cf0-81f7-849b681a39fa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732189386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.1732189386
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.593429746
Short name T872
Test name
Test status
Simulation time 90311047 ps
CPU time 2.67 seconds
Started Apr 25 12:53:07 PM PDT 24
Finished Apr 25 12:53:18 PM PDT 24
Peak memory 206436 kb
Host smart-0bb4f3a6-a253-444b-8d9d-f1a72fc3d001
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593429746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.593429746
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.2979915575
Short name T863
Test name
Test status
Simulation time 54033523 ps
CPU time 2.14 seconds
Started Apr 25 12:52:57 PM PDT 24
Finished Apr 25 12:53:00 PM PDT 24
Peak memory 215300 kb
Host smart-4db364d8-a4b9-4efb-8981-4218fc67e0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979915575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.2979915575
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.515120629
Short name T495
Test name
Test status
Simulation time 94892210 ps
CPU time 3.09 seconds
Started Apr 25 12:53:21 PM PDT 24
Finished Apr 25 12:53:25 PM PDT 24
Peak memory 207472 kb
Host smart-64ac92ce-202b-49ee-80bc-53a2ff2591a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515120629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.515120629
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.3973064532
Short name T82
Test name
Test status
Simulation time 2036417909 ps
CPU time 27.43 seconds
Started Apr 25 12:52:56 PM PDT 24
Finished Apr 25 12:53:25 PM PDT 24
Peak memory 222276 kb
Host smart-015462ce-d26b-4347-b4f5-8951e72d10f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973064532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.3973064532
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.1784607900
Short name T646
Test name
Test status
Simulation time 91095710 ps
CPU time 3.56 seconds
Started Apr 25 12:53:03 PM PDT 24
Finished Apr 25 12:53:08 PM PDT 24
Peak memory 207420 kb
Host smart-89311ca2-9dbc-4f4c-a4d7-385b9582bcec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784607900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.1784607900
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.1110953660
Short name T547
Test name
Test status
Simulation time 36165186 ps
CPU time 0.82 seconds
Started Apr 25 12:53:12 PM PDT 24
Finished Apr 25 12:53:16 PM PDT 24
Peak memory 205616 kb
Host smart-19e282c3-b16e-4fe2-b82c-05ff7eb6f71c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110953660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.1110953660
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.3710220833
Short name T708
Test name
Test status
Simulation time 194746680 ps
CPU time 6.12 seconds
Started Apr 25 12:53:06 PM PDT 24
Finished Apr 25 12:53:16 PM PDT 24
Peak memory 210168 kb
Host smart-836a5e63-c6c5-4a64-b86a-8b2e8470d5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710220833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.3710220833
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.3739027186
Short name T637
Test name
Test status
Simulation time 98547635 ps
CPU time 2.49 seconds
Started Apr 25 12:53:10 PM PDT 24
Finished Apr 25 12:53:16 PM PDT 24
Peak memory 209540 kb
Host smart-17ebd313-dd49-4a9f-bade-d3417f2ed516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739027186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.3739027186
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.18515900
Short name T70
Test name
Test status
Simulation time 116506917 ps
CPU time 4.48 seconds
Started Apr 25 12:53:08 PM PDT 24
Finished Apr 25 12:53:15 PM PDT 24
Peak memory 222276 kb
Host smart-facac6ad-a958-4c6e-84c6-91f8d2cc0bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18515900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.18515900
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.3056904117
Short name T262
Test name
Test status
Simulation time 2405319738 ps
CPU time 7.81 seconds
Started Apr 25 12:53:50 PM PDT 24
Finished Apr 25 12:54:05 PM PDT 24
Peak memory 213772 kb
Host smart-1b4035a5-f0a2-4548-ab1d-4067d004ba10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056904117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.3056904117
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.3007622867
Short name T343
Test name
Test status
Simulation time 148319859 ps
CPU time 3.49 seconds
Started Apr 25 12:53:04 PM PDT 24
Finished Apr 25 12:53:09 PM PDT 24
Peak memory 208236 kb
Host smart-d6e4d3e9-9fc1-43b8-ba60-19057fe191c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007622867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.3007622867
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.595876020
Short name T448
Test name
Test status
Simulation time 469975455 ps
CPU time 6.72 seconds
Started Apr 25 12:53:07 PM PDT 24
Finished Apr 25 12:53:17 PM PDT 24
Peak memory 207792 kb
Host smart-7adb7a3b-9bcc-4e7b-8c6f-86f9db5db4ad
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595876020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.595876020
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.458014733
Short name T597
Test name
Test status
Simulation time 84276052 ps
CPU time 3.65 seconds
Started Apr 25 12:53:03 PM PDT 24
Finished Apr 25 12:53:09 PM PDT 24
Peak memory 208284 kb
Host smart-d8d202f5-6020-4b0c-86f5-c3e277cedfb2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458014733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.458014733
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.3563011467
Short name T644
Test name
Test status
Simulation time 245561181 ps
CPU time 5.39 seconds
Started Apr 25 12:53:03 PM PDT 24
Finished Apr 25 12:53:09 PM PDT 24
Peak memory 207784 kb
Host smart-18fcb504-96f6-41a0-bc9a-d20ad3fe6ea0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563011467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.3563011467
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.754610835
Short name T328
Test name
Test status
Simulation time 94050518 ps
CPU time 3.43 seconds
Started Apr 25 12:53:05 PM PDT 24
Finished Apr 25 12:53:11 PM PDT 24
Peak memory 208832 kb
Host smart-dd16f606-3722-4400-b894-8fb7ae8ac48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754610835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.754610835
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.2941951897
Short name T789
Test name
Test status
Simulation time 148096762 ps
CPU time 2.28 seconds
Started Apr 25 12:53:04 PM PDT 24
Finished Apr 25 12:53:09 PM PDT 24
Peak memory 206632 kb
Host smart-99280d02-8dc4-4d53-8a76-9ef9906aa14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941951897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.2941951897
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.3798347864
Short name T833
Test name
Test status
Simulation time 2193918798 ps
CPU time 57.06 seconds
Started Apr 25 12:52:55 PM PDT 24
Finished Apr 25 12:53:53 PM PDT 24
Peak memory 215988 kb
Host smart-e6237b66-8851-4115-b10b-555de9ecc25c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798347864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.3798347864
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.3311468142
Short name T303
Test name
Test status
Simulation time 441393696 ps
CPU time 12.35 seconds
Started Apr 25 12:53:13 PM PDT 24
Finished Apr 25 12:53:28 PM PDT 24
Peak memory 214016 kb
Host smart-4c22d4f4-a3c8-467e-8813-0b8e80f6cd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311468142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.3311468142
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.186292737
Short name T666
Test name
Test status
Simulation time 36960262 ps
CPU time 1.91 seconds
Started Apr 25 12:53:00 PM PDT 24
Finished Apr 25 12:53:04 PM PDT 24
Peak memory 209672 kb
Host smart-d9b53478-6519-4e00-aed5-d1bc277bc5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186292737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.186292737
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.2289314734
Short name T512
Test name
Test status
Simulation time 49684785 ps
CPU time 0.75 seconds
Started Apr 25 12:53:08 PM PDT 24
Finished Apr 25 12:53:12 PM PDT 24
Peak memory 205696 kb
Host smart-26992b93-c9be-4fe3-8abc-0b834f03c027
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289314734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.2289314734
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.3579657694
Short name T414
Test name
Test status
Simulation time 256176121 ps
CPU time 6.99 seconds
Started Apr 25 12:54:00 PM PDT 24
Finished Apr 25 12:54:11 PM PDT 24
Peak memory 213940 kb
Host smart-9e8e40af-5dff-4025-82de-62112e4ae30b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3579657694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.3579657694
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.933401122
Short name T209
Test name
Test status
Simulation time 2128420659 ps
CPU time 15.25 seconds
Started Apr 25 12:53:04 PM PDT 24
Finished Apr 25 12:53:21 PM PDT 24
Peak memory 219300 kb
Host smart-7e2168b3-6c9f-40c1-8ecd-63644866654c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933401122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.933401122
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.2934378666
Short name T254
Test name
Test status
Simulation time 243054216 ps
CPU time 7.06 seconds
Started Apr 25 12:53:00 PM PDT 24
Finished Apr 25 12:53:09 PM PDT 24
Peak memory 209212 kb
Host smart-13e80008-84e4-4e6d-9203-af43e9d1a208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934378666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.2934378666
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.1719886266
Short name T26
Test name
Test status
Simulation time 857870074 ps
CPU time 7.31 seconds
Started Apr 25 12:53:51 PM PDT 24
Finished Apr 25 12:53:59 PM PDT 24
Peak memory 220196 kb
Host smart-f5dc70bd-e8d5-4703-9777-32eadf52e007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719886266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.1719886266
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.1605604321
Short name T106
Test name
Test status
Simulation time 118009144 ps
CPU time 3.67 seconds
Started Apr 25 12:53:10 PM PDT 24
Finished Apr 25 12:53:17 PM PDT 24
Peak memory 214080 kb
Host smart-88155f5f-5252-410d-8862-ba671623ecf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605604321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.1605604321
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.2343674036
Short name T184
Test name
Test status
Simulation time 209037046 ps
CPU time 3.39 seconds
Started Apr 25 12:53:10 PM PDT 24
Finished Apr 25 12:53:16 PM PDT 24
Peak memory 207916 kb
Host smart-4fbb6954-77f6-4cf0-abba-cd7b032f078d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343674036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.2343674036
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.1084076780
Short name T898
Test name
Test status
Simulation time 80956919 ps
CPU time 3 seconds
Started Apr 25 12:53:04 PM PDT 24
Finished Apr 25 12:53:08 PM PDT 24
Peak memory 205984 kb
Host smart-f2f24f42-4e8e-4b47-b9eb-d03913b59238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084076780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.1084076780
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.119039185
Short name T803
Test name
Test status
Simulation time 270943213 ps
CPU time 4.56 seconds
Started Apr 25 12:53:00 PM PDT 24
Finished Apr 25 12:53:06 PM PDT 24
Peak memory 208708 kb
Host smart-5d852aad-a34d-4d0d-b06d-de392d415db2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119039185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.119039185
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.1133957477
Short name T682
Test name
Test status
Simulation time 1681697250 ps
CPU time 40.16 seconds
Started Apr 25 12:52:57 PM PDT 24
Finished Apr 25 12:53:38 PM PDT 24
Peak memory 207736 kb
Host smart-538bf2f1-9e9d-4499-ba0e-419925adcc7c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133957477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.1133957477
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.1780492892
Short name T601
Test name
Test status
Simulation time 64199426 ps
CPU time 2.29 seconds
Started Apr 25 12:53:01 PM PDT 24
Finished Apr 25 12:53:04 PM PDT 24
Peak memory 206608 kb
Host smart-32d782f3-5e66-49db-8374-2cd07b38aea1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780492892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.1780492892
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.2647555419
Short name T560
Test name
Test status
Simulation time 244161547 ps
CPU time 1.75 seconds
Started Apr 25 12:52:59 PM PDT 24
Finished Apr 25 12:53:01 PM PDT 24
Peak memory 206844 kb
Host smart-09f52e31-5a8c-4360-8790-85d258e59609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647555419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.2647555419
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.1842320148
Short name T439
Test name
Test status
Simulation time 3711908629 ps
CPU time 24.18 seconds
Started Apr 25 12:52:57 PM PDT 24
Finished Apr 25 12:53:22 PM PDT 24
Peak memory 207724 kb
Host smart-8d5166f3-5921-4628-9d19-ff9a8b2dd3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842320148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.1842320148
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.446380860
Short name T289
Test name
Test status
Simulation time 694862049 ps
CPU time 9.66 seconds
Started Apr 25 12:54:00 PM PDT 24
Finished Apr 25 12:54:14 PM PDT 24
Peak memory 214968 kb
Host smart-96a26ffb-40ef-45dc-a80a-006c1a7c2a62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446380860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.446380860
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.2423980852
Short name T662
Test name
Test status
Simulation time 1545470781 ps
CPU time 10.81 seconds
Started Apr 25 12:53:05 PM PDT 24
Finished Apr 25 12:53:18 PM PDT 24
Peak memory 206700 kb
Host smart-c19fedd9-8901-4116-b307-5f4b03cc46be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423980852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.2423980852
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.285998533
Short name T561
Test name
Test status
Simulation time 361689388 ps
CPU time 2.43 seconds
Started Apr 25 12:53:05 PM PDT 24
Finished Apr 25 12:53:10 PM PDT 24
Peak memory 210092 kb
Host smart-2cd8baa1-e217-4256-a2ce-f6a9d842532d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285998533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.285998533
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.3747695497
Short name T604
Test name
Test status
Simulation time 12295109 ps
CPU time 0.72 seconds
Started Apr 25 12:53:18 PM PDT 24
Finished Apr 25 12:53:21 PM PDT 24
Peak memory 205696 kb
Host smart-ad3a130b-b65a-440e-9f5c-b2999e587736
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747695497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.3747695497
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.932905285
Short name T411
Test name
Test status
Simulation time 2806295809 ps
CPU time 49.41 seconds
Started Apr 25 12:53:07 PM PDT 24
Finished Apr 25 12:54:00 PM PDT 24
Peak memory 214200 kb
Host smart-ef5c1dd8-6071-41bb-8333-e78db832ff6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=932905285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.932905285
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.2002945812
Short name T897
Test name
Test status
Simulation time 67197301 ps
CPU time 3.67 seconds
Started Apr 25 12:53:09 PM PDT 24
Finished Apr 25 12:53:16 PM PDT 24
Peak memory 221640 kb
Host smart-b8aac03e-1362-4c0d-9281-b00d939e3f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002945812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.2002945812
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.3714728465
Short name T868
Test name
Test status
Simulation time 34981677 ps
CPU time 2.29 seconds
Started Apr 25 12:53:04 PM PDT 24
Finished Apr 25 12:53:08 PM PDT 24
Peak memory 209752 kb
Host smart-5ea9f42c-5011-44d2-a8ba-71ceeb8f3d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714728465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.3714728465
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.284796393
Short name T276
Test name
Test status
Simulation time 559653518 ps
CPU time 7.15 seconds
Started Apr 25 12:53:06 PM PDT 24
Finished Apr 25 12:53:17 PM PDT 24
Peak memory 220628 kb
Host smart-e3350244-0a94-4f91-bf26-6a226fc794ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284796393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.284796393
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.441807621
Short name T564
Test name
Test status
Simulation time 179899384 ps
CPU time 7.54 seconds
Started Apr 25 12:53:14 PM PDT 24
Finished Apr 25 12:53:24 PM PDT 24
Peak memory 209656 kb
Host smart-887b84a1-ee12-40b4-9b95-2a5b18db4229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441807621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.441807621
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.1515415358
Short name T629
Test name
Test status
Simulation time 33706148 ps
CPU time 2.43 seconds
Started Apr 25 12:53:04 PM PDT 24
Finished Apr 25 12:53:08 PM PDT 24
Peak memory 207236 kb
Host smart-d5c82545-940d-425a-a1ca-b53ee351efb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515415358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.1515415358
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.1309948388
Short name T598
Test name
Test status
Simulation time 84462583 ps
CPU time 4.37 seconds
Started Apr 25 12:53:19 PM PDT 24
Finished Apr 25 12:53:24 PM PDT 24
Peak memory 209880 kb
Host smart-1d779337-abf7-4a73-98be-96c7918f5338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309948388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.1309948388
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.1445403661
Short name T282
Test name
Test status
Simulation time 102412047 ps
CPU time 2.17 seconds
Started Apr 25 12:53:11 PM PDT 24
Finished Apr 25 12:53:16 PM PDT 24
Peak memory 208212 kb
Host smart-9edd71e5-1746-4ed1-98d2-6421d5e58ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445403661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.1445403661
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.654874622
Short name T524
Test name
Test status
Simulation time 81335943 ps
CPU time 3.39 seconds
Started Apr 25 12:53:25 PM PDT 24
Finished Apr 25 12:53:30 PM PDT 24
Peak memory 208368 kb
Host smart-a006558f-740a-4375-a10f-476d639a03f0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654874622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.654874622
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.2274716428
Short name T463
Test name
Test status
Simulation time 168948540 ps
CPU time 2.65 seconds
Started Apr 25 12:53:08 PM PDT 24
Finished Apr 25 12:53:14 PM PDT 24
Peak memory 206440 kb
Host smart-4d328340-7bac-4075-b594-f513b014f5d7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274716428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.2274716428
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.2456842705
Short name T517
Test name
Test status
Simulation time 875085386 ps
CPU time 5.15 seconds
Started Apr 25 12:53:01 PM PDT 24
Finished Apr 25 12:53:08 PM PDT 24
Peak memory 208212 kb
Host smart-f95c99ac-a635-411f-bca6-bbbbd8532968
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456842705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.2456842705
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.1575734191
Short name T711
Test name
Test status
Simulation time 66927716 ps
CPU time 1.5 seconds
Started Apr 25 12:53:21 PM PDT 24
Finished Apr 25 12:53:24 PM PDT 24
Peak memory 207036 kb
Host smart-59c3079f-1f5d-4250-8566-6e4e22b5f577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575734191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.1575734191
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.1701719896
Short name T885
Test name
Test status
Simulation time 400730200 ps
CPU time 2.24 seconds
Started Apr 25 12:53:49 PM PDT 24
Finished Apr 25 12:53:52 PM PDT 24
Peak memory 207552 kb
Host smart-5a235772-748a-4360-8da9-57bceb9e533d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701719896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.1701719896
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.2616686840
Short name T630
Test name
Test status
Simulation time 146131545 ps
CPU time 4.57 seconds
Started Apr 25 12:53:06 PM PDT 24
Finished Apr 25 12:53:22 PM PDT 24
Peak memory 208836 kb
Host smart-28d19861-6765-4fee-a077-23e647167868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616686840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.2616686840
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.3487460296
Short name T173
Test name
Test status
Simulation time 107593853 ps
CPU time 3.81 seconds
Started Apr 25 12:53:09 PM PDT 24
Finished Apr 25 12:53:16 PM PDT 24
Peak memory 209620 kb
Host smart-c64345bc-3cd6-45cd-bc7a-5859c70396f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487460296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.3487460296
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%