Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.84	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	73	257	77.88

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	54	226	80.71	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4619

1

T2

2

T3

2

T14

1

auto[1]

493

1

T18

3

T77

4

T220

4

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4619

1

T2

2

T3

2

T14

1

auto[1]

493

1

T18

3

T77

4

T220

4

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4602

1

T2

2

T3

2

T14

1

auto[1]

510

1

T17

4

T18

2

T30

1

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4602

1

T2

2

T3

2

T14

1

auto[1]

510

1

T17

4

T18

2

T30

1

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	421	1			T18	3		T76	2		T32	1
auto[OpGenId]	1063	1			T18	6		T101	1		T75	2
auto[OpGenSwOut]	1042	1			T2	2		T18	10		T30	1
auto[OpGenHwOut]	2518	1			T3	2		T14	1		T16	1
auto[OpDisable]	68	1			T39	1		T41	2		T48	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	421	1			T18	3		T76	2		T32	1
auto[OpGenId]	1063	1			T18	6		T101	1		T75	2
auto[OpGenSwOut]	1042	1			T2	2		T18	10		T30	1
auto[OpGenHwOut]	2518	1			T3	2		T14	1		T16	1
auto[OpDisable]	68	1			T39	1		T41	2		T48	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4499

1

T2

2

T3

2

T14

1

auto[1]

613

1

T18

4

T74

4

T101

2

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4499

1

T2

2

T3

2

T14

1

auto[1]

613

1

T18

4

T74

4

T101

2

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4818

1

T2

2

T3

2

T14

1

auto[1]

294

1

T76

5

T118

3

T119

12

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1721	1			T2	1		T3	1		T14	1
auto[1]	687	1			T3	1		T17	2		T30	1
auto[2]	726	1			T17	1		T18	3		T74	2
auto[3]	644	1			T2	1		T17	3		T18	3
auto[4]	333	1			T18	1		T75	1		T77	1
auto[5]	343	1			T17	2		T18	2		T220	1
auto[6]	329	1			T18	3		T74	1		T101	1
auto[7]	329	1			T74	1		T220	1		T41	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1334	1			T17	2		T18	6		T74	2
clear_one[1]	687	1			T3	1		T17	2		T30	1
clear_one[2]	726	1			T17	1		T18	3		T74	2
clear_one[3]	644	1			T2	1		T17	3		T18	3
clear_none	1721	1			T2	1		T3	1		T14	1

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	921	1			T2	2		T17	1		T18	8
auto[StInit]	738	1			T3	2		T14	1		T16	1
auto[StCreatorRootKey]	573	1			T17	1		T18	3		T74	1
auto[StOwnerIntKey]	497	1			T17	1		T18	1		T74	1
auto[StOwnerKey]	462	1			T17	1		T18	3		T30	1
auto[StDisabled]	1759	1			T17	4		T18	6		T74	4
auto[StInvalid]	162	1			T25	5		T31	2		T24	2

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	921	1			T2	2		T17	1		T18	8
auto[StInit]	738	1			T3	2		T14	1		T16	1
auto[StCreatorRootKey]	573	1			T17	1		T18	3		T74	1
auto[StOwnerIntKey]	497	1			T17	1		T18	1		T74	1
auto[StOwnerKey]	462	1			T17	1		T18	3		T30	1
auto[StDisabled]	1759	1			T17	4		T18	6		T74	4
auto[StInvalid]	162	1			T25	5		T31	2		T24	2

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	54	226	80.71	54

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[2]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	2
[auto[1] - auto[2]]	[auto[StReset]]	[auto[OpDisable]]	--	--	2
[auto[1] - auto[2]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	8
[auto[1] - auto[2]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2
[auto[3]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[3]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[4]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[4]]	[auto[StInvalid]]	[auto[OpGenHwOut] , auto[OpDisable]]	--	--	2
[auto[5]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[5]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[5]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[6]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	3	1			T245	1		T246	1		T247	1
auto[0]	auto[StReset]	auto[OpGenId]	138	1			T18	1		T207	1		T42	2
auto[0]	auto[StReset]	auto[OpGenSwOut]	136	1			T2	1		T18	1		T75	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	268	1			T17	1		T18	2		T74	1
auto[0]	auto[StInit]	auto[OpAdvance]	40	1			T32	1		T209	1		T216	1
auto[0]	auto[StInit]	auto[OpGenId]	102	1			T18	2		T42	1		T5	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	98	1			T18	1		T30	1		T76	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	190	1			T3	1		T14	1		T16	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	23	1			T35	1		T118	1		T248	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	53	1			T36	3		T249	1		T125	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	44	1			T18	1		T41	1		T48	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	67	1			T18	1		T74	1		T101	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	8	1			T42	1		T250	1		T251	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	27	1			T252	1		T253	1		T254	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	31	1			T217	1		T51	2		T59	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	56	1			T101	1		T218	1		T255	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	11	1			T18	1		T78	1		T118	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	15	1			T39	1		T42	2		T216	2
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	14	1			T41	1		T5	1		T223	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	44	1			T18	1		T41	1		T42	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	29	1			T118	1		T140	1		T36	1
auto[0]	auto[StDisabled]	auto[OpGenId]	52	1			T204	1		T211	1		T206	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	45	1			T75	1		T41	1		T42	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	165	1			T18	1		T74	2		T220	2
auto[0]	auto[StDisabled]	auto[OpDisable]	14	1			T41	2		T256	1		T257	2
auto[0]	auto[StInvalid]	auto[OpAdvance]	12	1			T81	1		T88	1		T258	1
auto[0]	auto[StInvalid]	auto[OpGenId]	14	1			T81	2		T208	2		T95	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	14	1			T86	1		T208	1		T80	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T25	1		T84	1		T47	1
auto[1]	auto[StReset]	auto[OpGenId]	8	1			T126	1		T63	1		T259	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	16	1			T133	1		T260	1		T257	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	49	1			T49	1		T224	1		T5	1
auto[1]	auto[StInit]	auto[OpAdvance]	9	1			T35	1		T5	1		T82	1
auto[1]	auto[StInit]	auto[OpGenId]	15	1			T100	2		T5	1		T50	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	15	1			T23	1		T87	1		T37	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	18	1			T3	1		T261	1		T262	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T140	2		T263	1		T62	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	19	1			T75	1		T42	1		T36	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	17	1			T42	1		T51	1		T130	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	45	1			T17	1		T220	1		T255	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	11	1			T207	1		T119	1		T140	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	11	1			T51	1		T127	1		T264	2
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	15	1			T256	1		T37	1		T260	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	36	1			T77	1		T265	1		T266	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T150	1		T215	1		T267	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	17	1			T42	1		T119	1		T268	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	11	1			T119	2		T49	1		T5	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	40	1			T30	1		T221	1		T224	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	26	1			T118	1		T36	1		T37	3
auto[1]	auto[StDisabled]	auto[OpGenId]	51	1			T211	1		T5	1		T215	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	51	1			T42	1		T119	1		T49	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	154	1			T17	1		T77	1		T218	2
auto[1]	auto[StDisabled]	auto[OpDisable]	14	1			T48	1		T42	1		T269	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	4	1			T96	1		T270	1		T271	1
auto[1]	auto[StInvalid]	auto[OpGenId]	6	1			T84	1		T88	1		T272	2
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T79	1		T88	1		T273	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T274	1		T275	1		T276	1
auto[2]	auto[StReset]	auto[OpGenId]	21	1			T204	1		T254	1		T195	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	14	1			T49	1		T277	1		T52	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	32	1			T77	1		T5	1		T278	2
auto[2]	auto[StInit]	auto[OpAdvance]	9	1			T150	1		T80	1		T279	1
auto[2]	auto[StInit]	auto[OpGenId]	14	1			T23	1		T38	1		T280	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	18	1			T37	1		T85	1		T277	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	39	1			T74	1		T75	1		T204	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	10	1			T42	1		T27	1		T140	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	16	1			T281	1		T282	2		T201	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	13	1			T76	1		T283	1		T267	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	48	1			T76	1		T119	2		T266	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	10	1			T150	1		T219	1		T213	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	13	1			T42	1		T118	1		T284	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	18	1			T78	1		T42	1		T49	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	43	1			T17	1		T285	1		T278	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	9	1			T284	1		T70	1		T286	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	15	1			T49	1		T287	1		T288	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T254	1		T289	1		T106	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	44	1			T220	1		T218	1		T290	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	24	1			T18	2		T42	2		T209	1
auto[2]	auto[StDisabled]	auto[OpGenId]	59	1			T18	1		T75	1		T39	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	59	1			T75	1		T42	2		T131	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	161	1			T74	1		T204	1		T221	1
auto[2]	auto[StDisabled]	auto[OpDisable]	7	1			T50	1		T291	1		T292	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	5	1			T96	1		T293	1		T294	1
auto[2]	auto[StInvalid]	auto[OpGenId]	7	1			T25	1		T295	1		T296	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T31	1		T84	1		T294	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T79	1		T80	1		T96	1
auto[3]	auto[StReset]	auto[OpAdvance]	1	1			T297	1		-	-		-	-
auto[3]	auto[StReset]	auto[OpGenId]	16	1			T140	1		T36	1		T37	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	23	1			T2	1		T18	1		T75	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	46	1			T77	1		T5	1		T290	1
auto[3]	auto[StInit]	auto[OpAdvance]	4	1			T298	1		T299	1		T300	1
auto[3]	auto[StInit]	auto[OpGenId]	8	1			T213	1		T269	1		T235	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	19	1			T42	1		T23	1		T87	2
auto[3]	auto[StInit]	auto[OpGenHwOut]	28	1			T17	1		T77	1		T211	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T301	1		T297	2		T302	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	18	1			T42	1		T100	1		T219	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	13	1			T303	1		T127	1		T130	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	36	1			T221	1		T42	1		T223	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T127	1		T304	1		T264	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T119	1		T131	1		T297	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	12	1			T119	2		T5	1		T36	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	38	1			T74	1		T75	1		T220	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T57	1		T62	1		T305	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	18	1			T217	1		T36	1		T260	2
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	11	1			T306	1		T307	1		T229	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	43	1			T17	1		T77	1		T222	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	21	1			T139	1		T308	1		T262	1
auto[3]	auto[StDisabled]	auto[OpGenId]	41	1			T42	1		T5	1		T51	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	55	1			T18	2		T139	1		T309	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	144	1			T17	1		T77	2		T221	1
auto[3]	auto[StDisabled]	auto[OpDisable]	7	1			T264	1		T202	1		T310	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	3	1			T311	1		T312	1		T294	1
auto[3]	auto[StInvalid]	auto[OpGenId]	9	1			T25	1		T80	1		T96	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T25	1		T24	1		T47	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T295	1		T313	1		T314	1
auto[4]	auto[StReset]	auto[OpGenId]	12	1			T201	1		T257	1		T202	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	10	1			T75	1		T204	1		T256	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	22	1			T213	1		T315	1		T199	1
auto[4]	auto[StInit]	auto[OpAdvance]	1	1			T68	1		-	-		-	-
auto[4]	auto[StInit]	auto[OpGenId]	5	1			T316	1		T317	1		T232	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	10	1			T42	1		T318	1		T319	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	15	1			T197	1		T199	1		T85	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T320	1		T108	1		T321	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T18	1		T56	1		T322	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	4	1			T211	1		T63	1		T186	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	18	1			T42	1		T224	1		T51	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T301	1		T323	1		T247	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	9	1			T214	1		T260	1		T324	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T248	1		T209	1		T129	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	24	1			T222	1		T224	1		T325	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T326	1		T327	1		-	-
auto[4]	auto[StOwnerKey]	auto[OpGenId]	6	1			T328	1		T329	1		T330	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T212	3		T36	1		T127	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	18	1			T325	1		T285	1		T199	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	21	1			T207	1		T5	1		T212	5
auto[4]	auto[StDisabled]	auto[OpGenId]	22	1			T118	1		T219	1		T223	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	22	1			T212	1		T36	1		T195	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	65	1			T77	1		T218	1		T118	1
auto[4]	auto[StDisabled]	auto[OpDisable]	9	1			T39	1		T42	1		T283	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	2	1			T47	1		T88	1		-	-
auto[4]	auto[StInvalid]	auto[OpGenId]	2	1			T208	1		T311	1		-	-
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	2	1			T271	1		T331	1		-	-
auto[5]	auto[StReset]	auto[OpGenId]	8	1			T18	1		T36	1		T127	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	7	1			T35	1		T84	1		T37	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	18	1			T211	1		T261	2		T95	1
auto[5]	auto[StInit]	auto[OpAdvance]	4	1			T5	1		T87	1		T94	1
auto[5]	auto[StInit]	auto[OpGenId]	3	1			T277	1		T332	1		T333	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	5	1			T53	1		T334	1		T240	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	14	1			T315	1		T335	1		T201	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T213	1		T336	1		T337	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	6	1			T87	1		T338	1		T229	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	4	1			T113	1		T339	1		T329	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	20	1			T218	1		T51	1		T340	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T262	1		T332	1		T337	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T339	1		T38	1		T341	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	2	1			T49	1		T342	1		-	-
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	18	1			T339	1		T315	1		T343	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T284	1		T52	1		T344	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	10	1			T41	1		T219	1		T37	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T18	1		T332	1		T345	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	24	1			T346	1		T347	1		T348	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	16	1			T207	1		T139	1		T253	2
auto[5]	auto[StDisabled]	auto[OpGenId]	31	1			T42	1		T217	1		T49	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	24	1			T42	1		T209	1		T213	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	77	1			T17	2		T220	1		T221	1
auto[5]	auto[StDisabled]	auto[OpDisable]	8	1			T37	1		T260	1		T53	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	1	1			T86	1		-	-		-	-
auto[5]	auto[StInvalid]	auto[OpGenId]	4	1			T95	1		T349	1		T313	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T258	1		T350	1		T314	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T86	1		T95	1		T96	1
auto[6]	auto[StReset]	auto[OpAdvance]	1	1			T351	1		-	-		-	-
auto[6]	auto[StReset]	auto[OpGenId]	9	1			T84	1		T36	1		T6	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	12	1			T18	2		T211	1		T50	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	14	1			T77	1		T50	1		T113	1
auto[6]	auto[StInit]	auto[OpAdvance]	2	1			T202	1		T352	1		-	-
auto[6]	auto[StInit]	auto[OpGenId]	5	1			T262	1		T353	1		T63	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	9	1			T23	1		T27	1		T89	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	5	1			T224	1		T354	1		T355	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T76	1		T139	1		T36	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	10	1			T131	1		T251	1		T347	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T139	1		T356	1		T202	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	19	1			T222	1		T346	1		T70	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T36	1		T37	1		T243	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	9	1			T139	1		T50	1		T283	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	10	1			T18	1		T36	1		T357	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	18	1			T199	1		T357	1		T358	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T359	1		T360	1		-	-
auto[6]	auto[StOwnerKey]	auto[OpGenId]	8	1			T101	1		T76	1		T51	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	4	1			T126	1		T361	1		T362	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	19	1			T74	1		T139	3		T265	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	12	1			T76	1		T254	1		T287	1
auto[6]	auto[StDisabled]	auto[OpGenId]	24	1			T150	1		T5	2		T36	2
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	28	1			T76	1		T150	2		T131	2
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	72	1			T76	1		T150	1		T255	2
auto[6]	auto[StDisabled]	auto[OpDisable]	6	1			T213	1		T264	1		T66	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	3	1			T31	1		T293	1		T312	1
auto[6]	auto[StInvalid]	auto[OpGenId]	4	1			T274	1		T349	1		T311	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T81	1		T296	2		-	-
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T25	1		T79	1		T294	1
auto[7]	auto[StReset]	auto[OpGenId]	10	1			T228	1		T353	1		T202	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	6	1			T211	1		T5	1		T262	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	21	1			T100	2		T37	1		T315	1
auto[7]	auto[StInit]	auto[OpAdvance]	4	1			T363	1		T364	1		T246	2
auto[7]	auto[StInit]	auto[OpGenId]	6	1			T51	1		T82	1		T94	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	8	1			T49	1		T36	1		T260	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	16	1			T195	1		T6	1		T229	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T287	1		T317	1		T365	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T284	1		T36	1		T262	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	3	1			T264	1		T366	1		T367	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	17	1			T49	1		T318	1		T368	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T339	1		T304	1		T359	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	10	1			T195	1		T263	1		T231	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	3	1			T223	1		T201	1		T359	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	24	1			T41	1		T5	1		T369	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	1	1			T370	1		-	-		-	-
auto[7]	auto[StOwnerKey]	auto[OpGenId]	5	1			T308	1		T236	1		T359	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T339	1		T36	1		T371	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	19	1			T248	1		T266	1		T280	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	10	1			T214	1		T140	1		T92	1
auto[7]	auto[StDisabled]	auto[OpGenId]	30	1			T42	1		T100	1		T59	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	27	1			T42	2		T252	2		T372	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	73	1			T74	1		T220	1		T78	1
auto[7]	auto[StDisabled]	auto[OpDisable]	3	1			T178	1		T373	1		T374	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	3	1			T24	1		T294	1		T375	1
auto[7]	auto[StInvalid]	auto[OpGenId]	2	1			T80	1		T376	1		-	-
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T258	1		T295	1		T350	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	1	1			T86	1		-	-		-	-

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1334

1

T17

2

T18

6

T74

2

clear_one[1]

auto[0]

auto[0]

auto[0]

388

1

T3

1

T75

1

T77

2

clear_one[1]

auto[0]

auto[0]

auto[1]

130

1

T48

1

T218

2

T118

1

clear_one[1]

auto[0]

auto[1]

auto[0]

113

1

T17

2

T30

1

T42

1

clear_one[1]

auto[0]

auto[1]

auto[1]

56

1

T131

1

T252

1

T51

1

clear_one[2]

auto[0]

auto[0]

auto[0]

415

1

T17

1

T18

1

T74

1

clear_one[2]

auto[0]

auto[0]

auto[1]

143

1

T74

1

T39

1

T78

1

clear_one[2]

auto[1]

auto[0]

auto[0]

119

1

T220

1

T221

1

T42

1

clear_one[2]

auto[1]

auto[0]

auto[1]

49

1

T18

2

T204

1

T42

1

clear_one[3]

auto[0]

auto[0]

auto[0]

388

1

T2

1

T17

1

T18

2

clear_one[3]

auto[0]

auto[1]

auto[0]

116

1

T17

2

T222

1

T42

1

clear_one[3]

auto[1]

auto[0]

auto[0]

103

1

T18

1

T77

3

T220

1

clear_one[3]

auto[1]

auto[1]

auto[0]

37

1

T42

1

T216

1

T256

1

clear_none

auto[0]

auto[0]

auto[0]

1240

1

T2

1

T3

1

T14

1

clear_none

auto[0]

auto[0]

auto[1]

155

1

T18

1

T74

3

T41

3

clear_none

auto[0]

auto[1]

auto[0]

112

1

T18

1

T204

1

T42

1

clear_none

auto[0]

auto[1]

auto[1]

29

1

T18

1

T101

2

T41

1

clear_none

auto[1]

auto[0]

auto[0]

102

1

T77

1

T220

2

T221

1

clear_none

auto[1]

auto[0]

auto[1]

36

1

T48

1

T309

1

T36

2

clear_none

auto[1]

auto[1]

auto[0]

32

1

T204

1

T42

1

T5

1

clear_none

auto[1]

auto[1]

auto[1]

15

1

T252

1

T51

1

T140

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1244	1			T17	2		T18	6		T74	2
clear_all	auto[1]	90	1			T76	4		T118	2		T150	3
clear_one[1]	auto[0]	629	1			T3	1		T17	2		T30	1
clear_one[1]	auto[1]	58	1			T119	6		T139	1		T216	1
clear_one[2]	auto[0]	685	1			T17	1		T18	3		T74	2
clear_one[2]	auto[1]	41	1			T76	1		T119	1		T150	1
clear_one[3]	auto[0]	614	1			T2	1		T17	3		T18	3
clear_one[3]	auto[1]	30	1			T119	5		T139	1		T326	2
clear_none	auto[0]	1646	1			T2	1		T3	1		T14	1
clear_none	auto[1]	75	1			T118	1		T139	1		T216	3