SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
43.16 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 20 | 0 | 20 | 100.00 |
Crosses | 360 | 216 | 144 | 40.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cdi_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 0 | |
dest_cp | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
op_cp | 5 | 0 | 5 | 100.00 | 100 | 1 | 1 | 0 | |
op_status_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 0 | |
state_cp | 7 | 0 | 7 | 100.00 | 100 | 1 | 1 | 0 |
CROSS | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | PRINT MISSING | COMMENT |
op_x_state_cross | 280 | 168 | 112 | 40.00 | 100 | 1 | 1 | 0 | |
op_x_status_cross | 80 | 48 | 32 | 40.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[Sealing] | 10918 | 1 | T1 | 6 | T2 | 6 | T3 | 14 | ||||
auto[Attestation] | 8055 | 1 | T1 | 4 | T3 | 9 | T13 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[None] | 2756 | 1 | T1 | 1 | T2 | 1 | T3 | 8 | ||||
auto[Aes] | 3360 | 1 | T3 | 4 | T14 | 1 | T15 | 1 | ||||
auto[Kmac] | 3375 | 1 | T2 | 1 | T3 | 2 | T13 | 1 | ||||
auto[Otbn] | 3449 | 1 | T1 | 4 | T2 | 3 | T3 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 5 | 0 | 5 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[OpAdvance] | 7765 | 1 | T1 | 3 | T2 | 1 | T3 | 8 | ||||
auto[OpGenId] | 6033 | 1 | T1 | 5 | T2 | 1 | T3 | 7 | ||||
auto[OpGenSwOut] | 5853 | 1 | T1 | 2 | T2 | 3 | T3 | 8 | ||||
auto[OpGenHwOut] | 7087 | 1 | T1 | 3 | T2 | 2 | T3 | 8 | ||||
auto[OpDisable] | 130 | 1 | T14 | 1 | T18 | 2 | T39 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | STATUS |
auto[OpIdle] | 0 | Excluded |
auto[OpWip] | 0 | Excluded |
illegal | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[OpDoneSuccess] | 10116 | 1 | T1 | 8 | T2 | 1 | T3 | 1 | ||||
auto[OpDoneFail] | 16752 | 1 | T1 | 5 | T2 | 6 | T3 | 30 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 7 | 0 | 7 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[StReset] | 6064 | 1 | T1 | 3 | T2 | 7 | T3 | 1 | ||||
auto[StInit] | 4307 | 1 | T1 | 4 | T3 | 30 | T13 | 2 | ||||
auto[StCreatorRootKey] | 2996 | 1 | T1 | 3 | T13 | 2 | T15 | 2 | ||||
auto[StOwnerIntKey] | 2629 | 1 | T1 | 3 | T13 | 2 | T15 | 2 | ||||
auto[StOwnerKey] | 2371 | 1 | T13 | 2 | T15 | 2 | T17 | 2 | ||||
auto[StDisabled] | 7509 | 1 | T13 | 7 | T14 | 5 | T15 | 7 | ||||
auto[StInvalid] | 992 | 1 | T25 | 16 | T31 | 24 | T24 | 22 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 280 | 168 | 112 | 40.00 | 168 |
op_cp | cdi_cp | dest_cp | state_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[OpAdvance] , auto[OpGenId]] | * | * | * | -- | -- | 112 | |
[auto[OpDisable]] | * | * | * | -- | -- | 56 |
op_cp | cdi_cp | dest_cp | state_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[OpGenSwOut] | auto[Sealing] | auto[None] | auto[StReset] | 253 | 1 | T18 | 4 | T75 | 1 | T204 | 1 | ||||
auto[OpGenSwOut] | auto[Sealing] | auto[None] | auto[StInit] | 140 | 1 | T3 | 2 | T25 | 1 | T205 | 1 | ||||
auto[OpGenSwOut] | auto[Sealing] | auto[None] | auto[StCreatorRootKey] | 75 | 1 | T18 | 1 | T42 | 1 | T139 | 1 | ||||
auto[OpGenSwOut] | auto[Sealing] | auto[None] | auto[StOwnerIntKey] | 64 | 1 | T18 | 1 | T42 | 1 | T5 | 1 | ||||
auto[OpGenSwOut] | auto[Sealing] | auto[None] | auto[StOwnerKey] | 60 | 1 | T18 | 1 | T42 | 3 | T206 | 1 | ||||
auto[OpGenSwOut] | auto[Sealing] | auto[None] | auto[StDisabled] | 198 | 1 | T76 | 1 | T207 | 1 | T42 | 3 | ||||
auto[OpGenSwOut] | auto[Sealing] | auto[None] | auto[StInvalid] | 29 | 1 | T31 | 3 | T84 | 1 | T208 | 1 | ||||
auto[OpGenSwOut] | auto[Sealing] | auto[Aes] | auto[StReset] | 287 | 1 | T18 | 2 | T204 | 2 | T207 | 1 | ||||
auto[OpGenSwOut] | auto[Sealing] | auto[Aes] | auto[StInit] | 132 | 1 | T76 | 1 | T48 | 1 | T42 | 2 | ||||
auto[OpGenSwOut] | auto[Sealing] | auto[Aes] | auto[StCreatorRootKey] | 70 | 1 | T15 | 1 | T18 | 1 | T30 | 1 | ||||
auto[OpGenSwOut] | auto[Sealing] | auto[Aes] | auto[StOwnerIntKey] | 56 | 1 | T25 | 1 | T41 | 1 | T27 | 1 | ||||
auto[OpGenSwOut] | auto[Sealing] | auto[Aes] | auto[StOwnerKey] | 50 | 1 | T209 | 1 | T113 | 1 | T210 | 1 | ||||
auto[OpGenSwOut] | auto[Sealing] | auto[Aes] | auto[StDisabled] | 208 | 1 | T18 | 4 | T19 | 1 | T76 | 1 | ||||
auto[OpGenSwOut] | auto[Sealing] | auto[Aes] | auto[StInvalid] | 39 | 1 | T25 | 1 | T24 | 1 | T79 | 1 | ||||
auto[OpGenSwOut] | auto[Sealing] | auto[Kmac] | auto[StReset] | 295 | 1 | T2 | 1 | T18 | 3 | T75 | 2 | ||||
auto[OpGenSwOut] | auto[Sealing] | auto[Kmac] | auto[StInit] | 110 | 1 | T3 | 1 | T18 | 1 | T101 | 1 | ||||
auto[OpGenSwOut] | auto[Sealing] | auto[Kmac] | auto[StCreatorRootKey] | 82 | 1 | T211 | 1 | T49 | 1 | T133 | 1 | ||||
auto[OpGenSwOut] | auto[Sealing] | auto[Kmac] | auto[StOwnerIntKey] | 65 | 1 | T18 | 3 | T76 | 1 | T39 | 1 | ||||
auto[OpGenSwOut] | auto[Sealing] | auto[Kmac] | auto[StOwnerKey] | 60 | 1 | T13 | 1 | T18 | 2 | T41 | 2 | ||||
auto[OpGenSwOut] | auto[Sealing] | auto[Kmac] | auto[StDisabled] | 197 | 1 | T18 | 1 | T75 | 1 | T41 | 1 | ||||
auto[OpGenSwOut] | auto[Sealing] | auto[Kmac] | auto[StInvalid] | 25 | 1 | T31 | 1 | T79 | 1 | T86 | 1 | ||||
auto[OpGenSwOut] | auto[Sealing] | auto[Otbn] | auto[StReset] | 295 | 1 | T2 | 2 | T18 | 6 | T75 | 2 | ||||
auto[OpGenSwOut] | auto[Sealing] | auto[Otbn] | auto[StInit] | 103 | 1 | T18 | 3 | T42 | 1 | T119 | 1 | ||||
auto[OpGenSwOut] | auto[Sealing] | auto[Otbn] | auto[StCreatorRootKey] | 75 | 1 | T13 | 1 | T207 | 1 | T206 | 1 | ||||
auto[OpGenSwOut] | auto[Sealing] | auto[Otbn] | auto[StOwnerIntKey] | 64 | 1 | T1 | 1 | T35 | 1 | T48 | 1 | ||||
auto[OpGenSwOut] | auto[Sealing] | auto[Otbn] | auto[StOwnerKey] | 56 | 1 | T5 | 4 | T212 | 1 | T51 | 1 | ||||
auto[OpGenSwOut] | auto[Sealing] | auto[Otbn] | auto[StDisabled] | 191 | 1 | T18 | 9 | T205 | 2 | T41 | 1 | ||||
auto[OpGenSwOut] | auto[Sealing] | auto[Otbn] | auto[StInvalid] | 21 | 1 | T81 | 2 | T208 | 1 | T80 | 1 | ||||
auto[OpGenSwOut] | auto[Attestation] | auto[None] | auto[StReset] | 84 | 1 | T18 | 3 | T51 | 1 | T59 | 1 | ||||
auto[OpGenSwOut] | auto[Attestation] | auto[None] | auto[StInit] | 116 | 1 | T3 | 1 | T16 | 1 | T30 | 1 | ||||
auto[OpGenSwOut] | auto[Attestation] | auto[None] | auto[StCreatorRootKey] | 68 | 1 | T18 | 1 | T101 | 1 | T41 | 1 | ||||
auto[OpGenSwOut] | auto[Attestation] | auto[None] | auto[StOwnerIntKey] | 64 | 1 | T42 | 1 | T213 | 1 | T36 | 3 | ||||
auto[OpGenSwOut] | auto[Attestation] | auto[None] | auto[StOwnerKey] | 61 | 1 | T42 | 2 | T5 | 1 | T214 | 1 | ||||
auto[OpGenSwOut] | auto[Attestation] | auto[None] | auto[StDisabled] | 211 | 1 | T13 | 2 | T15 | 1 | T18 | 2 | ||||
auto[OpGenSwOut] | auto[Attestation] | auto[None] | auto[StInvalid] | 32 | 1 | T31 | 2 | T79 | 2 | T84 | 1 | ||||
auto[OpGenSwOut] | auto[Attestation] | auto[Aes] | auto[StReset] | 79 | 1 | T42 | 2 | T100 | 4 | T51 | 1 | ||||
auto[OpGenSwOut] | auto[Attestation] | auto[Aes] | auto[StInit] | 129 | 1 | T3 | 1 | T41 | 3 | T42 | 2 | ||||
auto[OpGenSwOut] | auto[Attestation] | auto[Aes] | auto[StCreatorRootKey] | 65 | 1 | T18 | 1 | T76 | 1 | T207 | 1 | ||||
auto[OpGenSwOut] | auto[Attestation] | auto[Aes] | auto[StOwnerIntKey] | 54 | 1 | T18 | 1 | T139 | 1 | T215 | 1 | ||||
auto[OpGenSwOut] | auto[Attestation] | auto[Aes] | auto[StOwnerKey] | 61 | 1 | T207 | 1 | T41 | 1 | T42 | 1 | ||||
auto[OpGenSwOut] | auto[Attestation] | auto[Aes] | auto[StDisabled] | 218 | 1 | T18 | 1 | T75 | 1 | T41 | 1 | ||||
auto[OpGenSwOut] | auto[Attestation] | auto[Aes] | auto[StInvalid] | 30 | 1 | T31 | 1 | T24 | 2 | T84 | 1 | ||||
auto[OpGenSwOut] | auto[Attestation] | auto[Kmac] | auto[StReset] | 73 | 1 | T42 | 2 | T5 | 2 | T51 | 1 | ||||
auto[OpGenSwOut] | auto[Attestation] | auto[Kmac] | auto[StInit] | 123 | 1 | T3 | 1 | T18 | 1 | T41 | 2 | ||||
auto[OpGenSwOut] | auto[Attestation] | auto[Kmac] | auto[StCreatorRootKey] | 75 | 1 | T41 | 1 | T48 | 1 | T42 | 1 | ||||
auto[OpGenSwOut] | auto[Attestation] | auto[Kmac] | auto[StOwnerIntKey] | 57 | 1 | T101 | 1 | T4 | 1 | T41 | 1 | ||||
auto[OpGenSwOut] | auto[Attestation] | auto[Kmac] | auto[StOwnerKey] | 61 | 1 | T30 | 1 | T42 | 1 | T132 | 1 | ||||
auto[OpGenSwOut] | auto[Attestation] | auto[Kmac] | auto[StDisabled] | 196 | 1 | T18 | 1 | T76 | 2 | T42 | 2 | ||||
auto[OpGenSwOut] | auto[Attestation] | auto[Kmac] | auto[StInvalid] | 27 | 1 | T25 | 1 | T31 | 1 | T24 | 1 | ||||
auto[OpGenSwOut] | auto[Attestation] | auto[Otbn] | auto[StReset] | 97 | 1 | T42 | 2 | T100 | 3 | T5 | 4 | ||||
auto[OpGenSwOut] | auto[Attestation] | auto[Otbn] | auto[StInit] | 114 | 1 | T3 | 2 | T42 | 3 | T150 | 1 | ||||
auto[OpGenSwOut] | auto[Attestation] | auto[Otbn] | auto[StCreatorRootKey] | 83 | 1 | T1 | 1 | T207 | 1 | T41 | 2 | ||||
auto[OpGenSwOut] | auto[Attestation] | auto[Otbn] | auto[StOwnerIntKey] | 78 | 1 | T101 | 1 | T78 | 1 | T42 | 1 | ||||
auto[OpGenSwOut] | auto[Attestation] | auto[Otbn] | auto[StOwnerKey] | 60 | 1 | T15 | 1 | T18 | 1 | T205 | 1 | ||||
auto[OpGenSwOut] | auto[Attestation] | auto[Otbn] | auto[StDisabled] | 204 | 1 | T13 | 1 | T18 | 1 | T76 | 1 | ||||
auto[OpGenSwOut] | auto[Attestation] | auto[Otbn] | auto[StInvalid] | 33 | 1 | T25 | 2 | T79 | 1 | T84 | 1 | ||||
auto[OpGenHwOut] | auto[Sealing] | auto[None] | auto[StReset] | 265 | 1 | T2 | 1 | T18 | 6 | T75 | 2 | ||||
auto[OpGenHwOut] | auto[Sealing] | auto[None] | auto[StInit] | 114 | 1 | T3 | 4 | T25 | 1 | T44 | 1 | ||||
auto[OpGenHwOut] | auto[Sealing] | auto[None] | auto[StCreatorRootKey] | 62 | 1 | T30 | 1 | T76 | 1 | T39 | 1 | ||||
auto[OpGenHwOut] | auto[Sealing] | auto[None] | auto[StOwnerIntKey] | 62 | 1 | T42 | 3 | T51 | 1 | T216 | 1 | ||||
auto[OpGenHwOut] | auto[Sealing] | auto[None] | auto[StOwnerKey] | 50 | 1 | T18 | 1 | T30 | 1 | T42 | 1 | ||||
auto[OpGenHwOut] | auto[Sealing] | auto[None] | auto[StDisabled] | 167 | 1 | T18 | 3 | T42 | 1 | T217 | 1 | ||||
auto[OpGenHwOut] | auto[Sealing] | auto[None] | auto[StInvalid] | 39 | 1 | T31 | 2 | T24 | 2 | T79 | 2 | ||||
auto[OpGenHwOut] | auto[Sealing] | auto[Aes] | auto[StReset] | 430 | 1 | T16 | 1 | T18 | 2 | T77 | 12 | ||||
auto[OpGenHwOut] | auto[Sealing] | auto[Aes] | auto[StInit] | 119 | 1 | T3 | 2 | T18 | 1 | T77 | 1 | ||||
auto[OpGenHwOut] | auto[Sealing] | auto[Aes] | auto[StCreatorRootKey] | 92 | 1 | T18 | 1 | T42 | 1 | T100 | 1 | ||||
auto[OpGenHwOut] | auto[Sealing] | auto[Aes] | auto[StOwnerIntKey] | 94 | 1 | T25 | 1 | T48 | 1 | T112 | 1 | ||||
auto[OpGenHwOut] | auto[Sealing] | auto[Aes] | auto[StOwnerKey] | 85 | 1 | T30 | 1 | T101 | 1 | T77 | 1 | ||||
auto[OpGenHwOut] | auto[Sealing] | auto[Aes] | auto[StDisabled] | 254 | 1 | T18 | 2 | T76 | 1 | T77 | 4 | ||||
auto[OpGenHwOut] | auto[Sealing] | auto[Aes] | auto[StInvalid] | 31 | 1 | T31 | 1 | T79 | 1 | T84 | 1 | ||||
auto[OpGenHwOut] | auto[Sealing] | auto[Kmac] | auto[StReset] | 468 | 1 | T16 | 1 | T17 | 4 | T75 | 1 | ||||
auto[OpGenHwOut] | auto[Sealing] | auto[Kmac] | auto[StInit] | 133 | 1 | T75 | 1 | T76 | 1 | T39 | 1 | ||||
auto[OpGenHwOut] | auto[Sealing] | auto[Kmac] | auto[StCreatorRootKey] | 110 | 1 | T18 | 2 | T204 | 1 | T42 | 2 | ||||
auto[OpGenHwOut] | auto[Sealing] | auto[Kmac] | auto[StOwnerIntKey] | 92 | 1 | T17 | 1 | T4 | 1 | T42 | 1 | ||||
auto[OpGenHwOut] | auto[Sealing] | auto[Kmac] | auto[StOwnerKey] | 95 | 1 | T17 | 1 | T30 | 1 | T41 | 1 | ||||
auto[OpGenHwOut] | auto[Sealing] | auto[Kmac] | auto[StDisabled] | 263 | 1 | T14 | 1 | T17 | 3 | T18 | 1 | ||||
auto[OpGenHwOut] | auto[Sealing] | auto[Kmac] | auto[StInvalid] | 25 | 1 | T25 | 2 | T31 | 2 | T86 | 4 | ||||
auto[OpGenHwOut] | auto[Sealing] | auto[Otbn] | auto[StReset] | 445 | 1 | T1 | 1 | T2 | 1 | T18 | 4 | ||||
auto[OpGenHwOut] | auto[Sealing] | auto[Otbn] | auto[StInit] | 135 | 1 | T204 | 1 | T42 | 1 | T218 | 1 | ||||
auto[OpGenHwOut] | auto[Sealing] | auto[Otbn] | auto[StCreatorRootKey] | 115 | 1 | T18 | 1 | T74 | 1 | T101 | 1 | ||||
auto[OpGenHwOut] | auto[Sealing] | auto[Otbn] | auto[StOwnerIntKey] | 90 | 1 | T1 | 1 | T74 | 1 | T41 | 1 | ||||
auto[OpGenHwOut] | auto[Sealing] | auto[Otbn] | auto[StOwnerKey] | 82 | 1 | T30 | 2 | T74 | 1 | T41 | 1 | ||||
auto[OpGenHwOut] | auto[Sealing] | auto[Otbn] | auto[StDisabled] | 262 | 1 | T18 | 1 | T74 | 2 | T39 | 1 | ||||
auto[OpGenHwOut] | auto[Sealing] | auto[Otbn] | auto[StInvalid] | 32 | 1 | T84 | 1 | T47 | 1 | T96 | 2 | ||||
auto[OpGenHwOut] | auto[Attestation] | auto[None] | auto[StReset] | 58 | 1 | T18 | 2 | T42 | 4 | T100 | 1 | ||||
auto[OpGenHwOut] | auto[Attestation] | auto[None] | auto[StInit] | 119 | 1 | T1 | 1 | T3 | 1 | T14 | 1 | ||||
auto[OpGenHwOut] | auto[Attestation] | auto[None] | auto[StCreatorRootKey] | 63 | 1 | T76 | 1 | T78 | 1 | T49 | 1 | ||||
auto[OpGenHwOut] | auto[Attestation] | auto[None] | auto[StOwnerIntKey] | 65 | 1 | T101 | 1 | T75 | 1 | T27 | 1 | ||||
auto[OpGenHwOut] | auto[Attestation] | auto[None] | auto[StOwnerKey] | 49 | 1 | T42 | 1 | T209 | 1 | T219 | 1 | ||||
auto[OpGenHwOut] | auto[Attestation] | auto[None] | auto[StDisabled] | 149 | 1 | T18 | 2 | T207 | 1 | T42 | 3 | ||||
auto[OpGenHwOut] | auto[Attestation] | auto[None] | auto[StInvalid] | 39 | 1 | T24 | 2 | T79 | 1 | T84 | 1 | ||||
auto[OpGenHwOut] | auto[Attestation] | auto[Aes] | auto[StReset] | 44 | 1 | T18 | 1 | T5 | 1 | T113 | 1 | ||||
auto[OpGenHwOut] | auto[Attestation] | auto[Aes] | auto[StInit] | 137 | 1 | T3 | 1 | T220 | 1 | T41 | 1 | ||||
auto[OpGenHwOut] | auto[Attestation] | auto[Aes] | auto[StCreatorRootKey] | 115 | 1 | T77 | 1 | T220 | 1 | T221 | 1 | ||||
auto[OpGenHwOut] | auto[Attestation] | auto[Aes] | auto[StOwnerIntKey] | 87 | 1 | T18 | 1 | T77 | 1 | T220 | 1 | ||||
auto[OpGenHwOut] | auto[Attestation] | auto[Aes] | auto[StOwnerKey] | 87 | 1 | T30 | 1 | T220 | 1 | T221 | 1 | ||||
auto[OpGenHwOut] | auto[Attestation] | auto[Aes] | auto[StDisabled] | 275 | 1 | T14 | 1 | T18 | 1 | T76 | 2 | ||||
auto[OpGenHwOut] | auto[Attestation] | auto[Aes] | auto[StInvalid] | 32 | 1 | T24 | 1 | T79 | 1 | T86 | 3 | ||||
auto[OpGenHwOut] | auto[Attestation] | auto[Kmac] | auto[StReset] | 63 | 1 | T42 | 1 | T100 | 2 | T5 | 2 | ||||
auto[OpGenHwOut] | auto[Attestation] | auto[Kmac] | auto[StInit] | 128 | 1 | T16 | 1 | T17 | 1 | T222 | 1 | ||||
auto[OpGenHwOut] | auto[Attestation] | auto[Kmac] | auto[StCreatorRootKey] | 105 | 1 | T17 | 1 | T18 | 1 | T30 | 1 | ||||
auto[OpGenHwOut] | auto[Attestation] | auto[Kmac] | auto[StOwnerIntKey] | 93 | 1 | T222 | 1 | T42 | 1 | T49 | 1 | ||||
auto[OpGenHwOut] | auto[Attestation] | auto[Kmac] | auto[StOwnerKey] | 73 | 1 | T101 | 1 | T41 | 1 | T42 | 2 | ||||
auto[OpGenHwOut] | auto[Attestation] | auto[Kmac] | auto[StDisabled] | 256 | 1 | T17 | 1 | T18 | 1 | T76 | 1 | ||||
auto[OpGenHwOut] | auto[Attestation] | auto[Kmac] | auto[StInvalid] | 25 | 1 | T25 | 1 | T24 | 1 | T86 | 1 | ||||
auto[OpGenHwOut] | auto[Attestation] | auto[Otbn] | auto[StReset] | 79 | 1 | T42 | 1 | T100 | 2 | T5 | 5 | ||||
auto[OpGenHwOut] | auto[Attestation] | auto[Otbn] | auto[StInit] | 132 | 1 | T74 | 1 | T41 | 1 | T42 | 1 | ||||
auto[OpGenHwOut] | auto[Attestation] | auto[Otbn] | auto[StCreatorRootKey] | 92 | 1 | T78 | 2 | T223 | 1 | T51 | 1 | ||||
auto[OpGenHwOut] | auto[Attestation] | auto[Otbn] | auto[StOwnerIntKey] | 102 | 1 | T18 | 2 | T35 | 1 | T41 | 1 | ||||
auto[OpGenHwOut] | auto[Attestation] | auto[Otbn] | auto[StOwnerKey] | 97 | 1 | T218 | 1 | T224 | 1 | T131 | 1 | ||||
auto[OpGenHwOut] | auto[Attestation] | auto[Otbn] | auto[StDisabled] | 291 | 1 | T14 | 1 | T18 | 1 | T74 | 2 | ||||
auto[OpGenHwOut] | auto[Attestation] | auto[Otbn] | auto[StInvalid] | 21 | 1 | T25 | 1 | T86 | 2 | T47 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins | 80 | 48 | 32 | 40.00 | 48 |
op_cp | cdi_cp | dest_cp | op_status_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[OpAdvance] , auto[OpGenId]] | * | * | * | -- | -- | 32 | |
[auto[OpDisable]] | * | * | * | -- | -- | 16 |
op_cp | cdi_cp | dest_cp | op_status_cp | COUNT | STATUS | |
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]] | [auto[Sealing] , auto[Attestation]] | [auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]] | [auto[OpIdle] , auto[OpWip]] | -- | Excluded | (80 bins) |
op_cp | cdi_cp | dest_cp | op_status_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[OpGenSwOut] | auto[Sealing] | auto[None] | auto[OpDoneSuccess] | 181 | 1 | T18 | 3 | T42 | 5 | T206 | 1 | ||||
auto[OpGenSwOut] | auto[Sealing] | auto[None] | auto[OpDoneFail] | 638 | 1 | T3 | 2 | T18 | 4 | T75 | 1 | ||||
auto[OpGenSwOut] | auto[Sealing] | auto[Aes] | auto[OpDoneSuccess] | 158 | 1 | T15 | 1 | T18 | 1 | T30 | 1 | ||||
auto[OpGenSwOut] | auto[Sealing] | auto[Aes] | auto[OpDoneFail] | 684 | 1 | T18 | 6 | T19 | 1 | T76 | 2 | ||||
auto[OpGenSwOut] | auto[Sealing] | auto[Kmac] | auto[OpDoneSuccess] | 196 | 1 | T13 | 1 | T18 | 5 | T76 | 1 | ||||
auto[OpGenSwOut] | auto[Sealing] | auto[Kmac] | auto[OpDoneFail] | 638 | 1 | T2 | 1 | T3 | 1 | T18 | 5 | ||||
auto[OpGenSwOut] | auto[Sealing] | auto[Otbn] | auto[OpDoneSuccess] | 184 | 1 | T1 | 1 | T13 | 1 | T35 | 1 | ||||
auto[OpGenSwOut] | auto[Sealing] | auto[Otbn] | auto[OpDoneFail] | 621 | 1 | T2 | 2 | T18 | 18 | T75 | 2 | ||||
auto[OpGenSwOut] | auto[Attestation] | auto[None] | auto[OpDoneSuccess] | 185 | 1 | T18 | 1 | T101 | 1 | T41 | 1 | ||||
auto[OpGenSwOut] | auto[Attestation] | auto[None] | auto[OpDoneFail] | 451 | 1 | T3 | 1 | T13 | 2 | T15 | 1 | ||||
auto[OpGenSwOut] | auto[Attestation] | auto[Aes] | auto[OpDoneSuccess] | 167 | 1 | T18 | 1 | T76 | 1 | T207 | 1 | ||||
auto[OpGenSwOut] | auto[Attestation] | auto[Aes] | auto[OpDoneFail] | 469 | 1 | T3 | 1 | T18 | 2 | T75 | 1 | ||||
auto[OpGenSwOut] | auto[Attestation] | auto[Kmac] | auto[OpDoneSuccess] | 176 | 1 | T30 | 1 | T101 | 1 | T4 | 1 | ||||
auto[OpGenSwOut] | auto[Attestation] | auto[Kmac] | auto[OpDoneFail] | 436 | 1 | T3 | 1 | T18 | 2 | T76 | 2 | ||||
auto[OpGenSwOut] | auto[Attestation] | auto[Otbn] | auto[OpDoneSuccess] | 205 | 1 | T1 | 1 | T15 | 1 | T18 | 1 | ||||
auto[OpGenSwOut] | auto[Attestation] | auto[Otbn] | auto[OpDoneFail] | 464 | 1 | T3 | 2 | T13 | 1 | T18 | 1 | ||||
auto[OpGenHwOut] | auto[Sealing] | auto[None] | auto[OpDoneSuccess] | 162 | 1 | T18 | 1 | T30 | 2 | T76 | 1 | ||||
auto[OpGenHwOut] | auto[Sealing] | auto[None] | auto[OpDoneFail] | 597 | 1 | T2 | 1 | T3 | 4 | T18 | 9 | ||||
auto[OpGenHwOut] | auto[Sealing] | auto[Aes] | auto[OpDoneSuccess] | 257 | 1 | T30 | 1 | T101 | 1 | T25 | 1 | ||||
auto[OpGenHwOut] | auto[Sealing] | auto[Aes] | auto[OpDoneFail] | 848 | 1 | T3 | 2 | T16 | 1 | T18 | 6 | ||||
auto[OpGenHwOut] | auto[Sealing] | auto[Kmac] | auto[OpDoneSuccess] | 285 | 1 | T17 | 2 | T18 | 2 | T30 | 1 | ||||
auto[OpGenHwOut] | auto[Sealing] | auto[Kmac] | auto[OpDoneFail] | 901 | 1 | T14 | 1 | T16 | 1 | T17 | 7 | ||||
auto[OpGenHwOut] | auto[Sealing] | auto[Otbn] | auto[OpDoneSuccess] | 271 | 1 | T1 | 1 | T18 | 1 | T30 | 2 | ||||
auto[OpGenHwOut] | auto[Sealing] | auto[Otbn] | auto[OpDoneFail] | 890 | 1 | T1 | 1 | T2 | 1 | T18 | 5 | ||||
auto[OpGenHwOut] | auto[Attestation] | auto[None] | auto[OpDoneSuccess] | 159 | 1 | T101 | 1 | T75 | 1 | T76 | 1 | ||||
auto[OpGenHwOut] | auto[Attestation] | auto[None] | auto[OpDoneFail] | 383 | 1 | T1 | 1 | T3 | 1 | T14 | 1 | ||||
auto[OpGenHwOut] | auto[Attestation] | auto[Aes] | auto[OpDoneSuccess] | 280 | 1 | T18 | 1 | T30 | 1 | T77 | 2 | ||||
auto[OpGenHwOut] | auto[Attestation] | auto[Aes] | auto[OpDoneFail] | 497 | 1 | T3 | 1 | T14 | 1 | T18 | 2 | ||||
auto[OpGenHwOut] | auto[Attestation] | auto[Kmac] | auto[OpDoneSuccess] | 259 | 1 | T17 | 1 | T18 | 1 | T30 | 1 | ||||
auto[OpGenHwOut] | auto[Attestation] | auto[Kmac] | auto[OpDoneFail] | 484 | 1 | T16 | 1 | T17 | 2 | T18 | 1 | ||||
auto[OpGenHwOut] | auto[Attestation] | auto[Otbn] | auto[OpDoneSuccess] | 273 | 1 | T18 | 1 | T35 | 1 | T41 | 1 | ||||
auto[OpGenHwOut] | auto[Attestation] | auto[Otbn] | auto[OpDoneFail] | 541 | 1 | T14 | 1 | T18 | 2 | T74 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |