Unified Coverage Report :: Group Instance : attest_sw_binding_2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30798

1

T1

15

T2

7

T3

36

auto[1]

273

1

T76

8

T118

3

T119

9

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	30804	1			T1	15		T2	7		T3	36
auto[134217728:268435455]	9	1			T119	1		T253	1		T284	1
auto[268435456:402653183]	15	1			T76	2		T139	1		T395	1
auto[402653184:536870911]	14	1			T119	1		T139	1		T253	1
auto[536870912:671088639]	6	1			T119	1		T139	1		T141	1
auto[671088640:805306367]	8	1			T249	1		T396	2		T397	1
auto[805306368:939524095]	8	1			T119	1		T357	1		T326	1
auto[939524096:1073741823]	8	1			T139	1		T253	1		T339	1
auto[1073741824:1207959551]	10	1			T212	1		T284	1		T141	1
auto[1207959552:1342177279]	5	1			T339	1		T282	1		T301	3
auto[1342177280:1476395007]	12	1			T139	1		T216	1		T282	2
auto[1476395008:1610612735]	11	1			T216	2		T141	1		T357	1
auto[1610612736:1744830463]	8	1			T118	1		T139	1		T357	1
auto[1744830464:1879048191]	12	1			T119	2		T139	1		T212	1
auto[1879048192:2013265919]	5	1			T304	1		T396	1		T397	1
auto[2013265920:2147483647]	6	1			T118	1		T212	2		T253	1
auto[2147483648:2281701375]	10	1			T139	1		T212	1		T284	1
auto[2281701376:2415919103]	5	1			T139	1		T398	1		T399	2
auto[2415919104:2550136831]	7	1			T119	1		T212	1		T140	1
auto[2550136832:2684354559]	9	1			T76	2		T119	2		T357	1
auto[2684354560:2818572287]	8	1			T284	1		T249	1		T297	1
auto[2818572288:2952790015]	9	1			T76	1		T396	2		T399	1
auto[2952790016:3087007743]	9	1			T76	1		T212	1		T326	1
auto[3087007744:3221225471]	4	1			T216	1		T70	1		T304	1
auto[3221225472:3355443199]	6	1			T212	1		T216	1		T381	1
auto[3355443200:3489660927]	10	1			T212	2		T249	1		T396	1
auto[3489660928:3623878655]	13	1			T76	1		T139	2		T249	1
auto[3623878656:3758096383]	6	1			T139	1		T253	1		T141	1
auto[3758096384:3892314111]	10	1			T357	1		T326	1		T400	1
auto[3892314112:4026531839]	8	1			T76	1		T140	1		T357	1
auto[4026531840:4160749567]	4	1			T139	2		T357	1		T397	1
auto[4160749568:4294967295]	12	1			T118	1		T150	1		T139	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	30798	1			T1	15		T2	7		T3	36
auto[0:134217727]	auto[1]	6	1			T282	1		T397	1		T398	1
auto[134217728:268435455]	auto[1]	9	1			T119	1		T253	1		T284	1
auto[268435456:402653183]	auto[1]	15	1			T76	2		T139	1		T395	1
auto[402653184:536870911]	auto[1]	14	1			T119	1		T139	1		T253	1
auto[536870912:671088639]	auto[1]	6	1			T119	1		T139	1		T141	1
auto[671088640:805306367]	auto[1]	8	1			T249	1		T396	2		T397	1
auto[805306368:939524095]	auto[1]	8	1			T119	1		T357	1		T326	1
auto[939524096:1073741823]	auto[1]	8	1			T139	1		T253	1		T339	1
auto[1073741824:1207959551]	auto[1]	10	1			T212	1		T284	1		T141	1
auto[1207959552:1342177279]	auto[1]	5	1			T339	1		T282	1		T301	3
auto[1342177280:1476395007]	auto[1]	12	1			T139	1		T216	1		T282	2
auto[1476395008:1610612735]	auto[1]	11	1			T216	2		T141	1		T357	1
auto[1610612736:1744830463]	auto[1]	8	1			T118	1		T139	1		T357	1
auto[1744830464:1879048191]	auto[1]	12	1			T119	2		T139	1		T212	1
auto[1879048192:2013265919]	auto[1]	5	1			T304	1		T396	1		T397	1
auto[2013265920:2147483647]	auto[1]	6	1			T118	1		T212	2		T253	1
auto[2147483648:2281701375]	auto[1]	10	1			T139	1		T212	1		T284	1
auto[2281701376:2415919103]	auto[1]	5	1			T139	1		T398	1		T399	2
auto[2415919104:2550136831]	auto[1]	7	1			T119	1		T212	1		T140	1
auto[2550136832:2684354559]	auto[1]	9	1			T76	2		T119	2		T357	1
auto[2684354560:2818572287]	auto[1]	8	1			T284	1		T249	1		T297	1
auto[2818572288:2952790015]	auto[1]	9	1			T76	1		T396	2		T399	1
auto[2952790016:3087007743]	auto[1]	9	1			T76	1		T212	1		T326	1
auto[3087007744:3221225471]	auto[1]	4	1			T216	1		T70	1		T304	1
auto[3221225472:3355443199]	auto[1]	6	1			T212	1		T216	1		T381	1
auto[3355443200:3489660927]	auto[1]	10	1			T212	2		T249	1		T396	1
auto[3489660928:3623878655]	auto[1]	13	1			T76	1		T139	2		T249	1
auto[3623878656:3758096383]	auto[1]	6	1			T139	1		T253	1		T141	1
auto[3758096384:3892314111]	auto[1]	10	1			T357	1		T326	1		T400	1
auto[3892314112:4026531839]	auto[1]	8	1			T76	1		T140	1		T357	1
auto[4026531840:4160749567]	auto[1]	4	1			T139	2		T357	1		T397	1
auto[4160749568:4294967295]	auto[1]	12	1			T118	1		T150	1		T139	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2737

1

T2

1

T3

6

T14

1

auto[1]

273

1

T76

6

T118

5

T119

10

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	110	1			T35	1		T60	1		T139	1
auto[134217728:268435455]	97	1			T3	1		T76	1		T41	1
auto[268435456:402653183]	89	1			T44	1		T42	1		T131	1
auto[402653184:536870911]	87	1			T25	1		T42	1		T119	1
auto[536870912:671088639]	89	1			T401	1		T23	1		T27	1
auto[671088640:805306367]	89	1			T16	1		T25	1		T41	2
auto[805306368:939524095]	98	1			T3	1		T41	1		T118	1
auto[939524096:1073741823]	102	1			T76	1		T214	1		T219	1
auto[1073741824:1207959551]	96	1			T18	1		T139	1		T209	1
auto[1207959552:1342177279]	89	1			T3	1		T18	1		T41	1
auto[1342177280:1476395007]	86	1			T31	1		T206	1		T5	3
auto[1476395008:1610612735]	87	1			T3	1		T76	1		T118	1
auto[1610612736:1744830463]	83	1			T2	1		T207	1		T42	1
auto[1744830464:1879048191]	96	1			T41	1		T48	1		T119	1
auto[1879048192:2013265919]	75	1			T14	1		T25	1		T207	1
auto[2013265920:2147483647]	104	1			T41	1		T119	1		T31	1
auto[2147483648:2281701375]	89	1			T101	1		T76	1		T31	1
auto[2281701376:2415919103]	97	1			T3	1		T18	1		T42	1
auto[2415919104:2550136831]	107	1			T18	1		T39	1		T42	1
auto[2550136832:2684354559]	97	1			T16	1		T41	1		T42	1
auto[2684354560:2818572287]	83	1			T3	1		T76	1		T42	2
auto[2818572288:2952790015]	91	1			T30	1		T76	1		T44	1
auto[2952790016:3087007743]	101	1			T25	1		T42	1		T49	1
auto[3087007744:3221225471]	102	1			T18	1		T76	1		T207	2
auto[3221225472:3355443199]	92	1			T76	2		T23	2		T49	3
auto[3355443200:3489660927]	84	1			T101	1		T39	1		T118	1
auto[3489660928:3623878655]	114	1			T32	1		T78	1		T42	1
auto[3623878656:3758096383]	98	1			T18	2		T76	1		T35	1
auto[3758096384:3892314111]	87	1			T76	1		T25	1		T4	1
auto[3892314112:4026531839]	100	1			T30	1		T207	1		T42	2
auto[4026531840:4160749567]	89	1			T18	1		T119	1		T31	1
auto[4160749568:4294967295]	102	1			T18	1		T76	1		T207	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	1	63	98.44	1

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[3355443200:3489660927]]	[auto[1]]	0	1	1

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	102	1			T35	1		T60	1		T51	1
auto[0:134217727]	auto[1]	8	1			T139	1		T284	1		T357	1
auto[134217728:268435455]	auto[0]	88	1			T3	1		T41	1		T401	1
auto[134217728:268435455]	auto[1]	9	1			T76	1		T139	1		T140	1
auto[268435456:402653183]	auto[0]	80	1			T44	1		T42	1		T131	1
auto[268435456:402653183]	auto[1]	9	1			T326	1		T395	1		T332	1
auto[402653184:536870911]	auto[0]	73	1			T25	1		T42	1		T100	1
auto[402653184:536870911]	auto[1]	14	1			T119	1		T139	2		T212	1
auto[536870912:671088639]	auto[0]	82	1			T401	1		T23	1		T27	1
auto[536870912:671088639]	auto[1]	7	1			T140	2		T396	2		T397	1
auto[671088640:805306367]	auto[0]	82	1			T16	1		T25	1		T41	2
auto[671088640:805306367]	auto[1]	7	1			T119	1		T212	2		T396	1
auto[805306368:939524095]	auto[0]	86	1			T3	1		T41	1		T119	1
auto[805306368:939524095]	auto[1]	12	1			T118	1		T119	1		T139	1
auto[939524096:1073741823]	auto[0]	97	1			T76	1		T214	1		T219	1
auto[939524096:1073741823]	auto[1]	5	1			T212	1		T326	1		T360	1
auto[1073741824:1207959551]	auto[0]	82	1			T18	1		T139	1		T209	1
auto[1073741824:1207959551]	auto[1]	14	1			T212	1		T249	1		T282	1
auto[1207959552:1342177279]	auto[0]	83	1			T3	1		T18	1		T41	1
auto[1207959552:1342177279]	auto[1]	6	1			T119	1		T282	1		T357	1
auto[1342177280:1476395007]	auto[0]	82	1			T31	1		T206	1		T5	3
auto[1342177280:1476395007]	auto[1]	4	1			T253	1		T381	1		T402	1
auto[1476395008:1610612735]	auto[0]	75	1			T3	1		T76	1		T31	1
auto[1476395008:1610612735]	auto[1]	12	1			T118	1		T339	1		T249	1
auto[1610612736:1744830463]	auto[0]	76	1			T2	1		T207	1		T42	1
auto[1610612736:1744830463]	auto[1]	7	1			T253	1		T282	1		T304	1
auto[1744830464:1879048191]	auto[0]	87	1			T41	1		T48	1		T139	1
auto[1744830464:1879048191]	auto[1]	9	1			T119	1		T212	2		T400	1
auto[1879048192:2013265919]	auto[0]	63	1			T14	1		T25	1		T207	1
auto[1879048192:2013265919]	auto[1]	12	1			T119	1		T249	1		T141	1
auto[2013265920:2147483647]	auto[0]	98	1			T41	1		T31	1		T100	1
auto[2013265920:2147483647]	auto[1]	6	1			T119	1		T284	1		T249	1
auto[2147483648:2281701375]	auto[0]	80	1			T101	1		T31	1		T49	1
auto[2147483648:2281701375]	auto[1]	9	1			T76	1		T212	1		T357	1
auto[2281701376:2415919103]	auto[0]	90	1			T3	1		T18	1		T42	1
auto[2281701376:2415919103]	auto[1]	7	1			T140	1		T357	1		T397	1
auto[2415919104:2550136831]	auto[0]	98	1			T18	1		T39	1		T42	1
auto[2415919104:2550136831]	auto[1]	9	1			T118	1		T139	1		T212	1
auto[2550136832:2684354559]	auto[0]	87	1			T16	1		T41	1		T42	1
auto[2550136832:2684354559]	auto[1]	10	1			T118	1		T139	2		T140	1
auto[2684354560:2818572287]	auto[0]	75	1			T3	1		T76	1		T42	2
auto[2684354560:2818572287]	auto[1]	8	1			T150	1		T339	1		T70	1
auto[2818572288:2952790015]	auto[0]	83	1			T30	1		T76	1		T44	1
auto[2818572288:2952790015]	auto[1]	8	1			T119	1		T139	1		T140	1
auto[2952790016:3087007743]	auto[0]	94	1			T25	1		T42	1		T49	1
auto[2952790016:3087007743]	auto[1]	7	1			T339	1		T141	1		T357	1
auto[3087007744:3221225471]	auto[0]	88	1			T18	1		T207	2		T41	1
auto[3087007744:3221225471]	auto[1]	14	1			T76	1		T119	1		T253	1
auto[3221225472:3355443199]	auto[0]	81	1			T76	2		T23	2		T49	3
auto[3221225472:3355443199]	auto[1]	11	1			T139	1		T253	1		T339	1
auto[3355443200:3489660927]	auto[0]	84	1			T101	1		T39	1		T118	1
auto[3489660928:3623878655]	auto[0]	107	1			T32	1		T78	1		T42	1
auto[3489660928:3623878655]	auto[1]	7	1			T141	1		T400	1		T395	1
auto[3623878656:3758096383]	auto[0]	86	1			T18	2		T35	1		T207	1
auto[3623878656:3758096383]	auto[1]	12	1			T76	1		T118	1		T139	1
auto[3758096384:3892314111]	auto[0]	76	1			T25	1		T4	1		T42	1
auto[3758096384:3892314111]	auto[1]	11	1			T76	1		T339	1		T249	1
auto[3892314112:4026531839]	auto[0]	95	1			T30	1		T207	1		T42	2
auto[3892314112:4026531839]	auto[1]	5	1			T359	1		T403	1		T247	1
auto[4026531840:4160749567]	auto[0]	83	1			T18	1		T31	1		T23	1
auto[4026531840:4160749567]	auto[1]	6	1			T119	1		T216	1		T70	1
auto[4160749568:4294967295]	auto[0]	94	1			T18	1		T207	1		T41	1
auto[4160749568:4294967295]	auto[1]	8	1			T76	1		T284	1		T282	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1511

1

T3

4

T14

1

T16

2

auto[1]

1604

1

T2

2

T3

2

T30

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	91	1			T16	1		T39	1		T207	1
auto[134217728:268435455]	94	1			T4	1		T207	1		T31	1
auto[268435456:402653183]	95	1			T14	1		T41	1		T42	1
auto[402653184:536870911]	93	1			T18	1		T39	1		T150	1
auto[536870912:671088639]	90	1			T3	1		T18	1		T76	1
auto[671088640:805306367]	82	1			T42	1		T150	1		T49	1
auto[805306368:939524095]	96	1			T2	1		T18	2		T25	1
auto[939524096:1073741823]	100	1			T3	1		T42	2		T100	1
auto[1073741824:1207959551]	98	1			T3	1		T44	1		T78	1
auto[1207959552:1342177279]	109	1			T76	2		T41	2		T42	4
auto[1342177280:1476395007]	83	1			T118	1		T150	1		T49	2
auto[1476395008:1610612735]	103	1			T42	2		T118	1		T31	1
auto[1610612736:1744830463]	100	1			T25	1		T35	1		T41	1
auto[1744830464:1879048191]	95	1			T25	1		T32	1		T41	1
auto[1879048192:2013265919]	103	1			T101	1		T25	1		T35	1
auto[2013265920:2147483647]	96	1			T18	1		T35	1		T207	1
auto[2147483648:2281701375]	95	1			T3	1		T18	2		T207	1
auto[2281701376:2415919103]	104	1			T2	1		T16	1		T31	1
auto[2415919104:2550136831]	102	1			T49	1		T100	1		T24	1
auto[2550136832:2684354559]	94	1			T3	1		T41	1		T42	1
auto[2684354560:2818572287]	105	1			T18	1		T30	1		T42	3
auto[2818572288:2952790015]	108	1			T18	1		T41	1		T42	1
auto[2952790016:3087007743]	109	1			T18	1		T119	1		T5	2
auto[3087007744:3221225471]	84	1			T207	1		T41	1		T42	2
auto[3221225472:3355443199]	87	1			T3	1		T18	1		T76	2
auto[3355443200:3489660927]	105	1			T35	1		T42	2		T31	1
auto[3489660928:3623878655]	85	1			T42	1		T100	1		T5	1
auto[3623878656:3758096383]	98	1			T25	1		T35	1		T42	1
auto[3758096384:3892314111]	90	1			T76	1		T41	1		T42	2
auto[3892314112:4026531839]	108	1			T18	2		T30	1		T44	1
auto[4026531840:4160749567]	117	1			T44	1		T41	1		T42	2
auto[4160749568:4294967295]	96	1			T101	1		T207	1		T41	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	46	1			T16	1		T100	2		T5	1
auto[0:134217727]	auto[1]	45	1			T39	1		T207	1		T48	1
auto[134217728:268435455]	auto[0]	45	1			T31	1		T219	1		T89	1
auto[134217728:268435455]	auto[1]	49	1			T4	1		T207	1		T49	1
auto[268435456:402653183]	auto[0]	56	1			T14	1		T79	1		T209	1
auto[268435456:402653183]	auto[1]	39	1			T41	1		T42	1		T5	1
auto[402653184:536870911]	auto[0]	52	1			T18	1		T131	1		T5	1
auto[402653184:536870911]	auto[1]	41	1			T39	1		T150	1		T36	1
auto[536870912:671088639]	auto[0]	43	1			T3	1		T18	1		T76	1
auto[536870912:671088639]	auto[1]	47	1			T44	1		T35	1		T252	1
auto[671088640:805306367]	auto[0]	38	1			T42	1		T150	1		T5	1
auto[671088640:805306367]	auto[1]	44	1			T49	1		T51	1		T113	1
auto[805306368:939524095]	auto[0]	56	1			T18	2		T25	1		T50	1
auto[805306368:939524095]	auto[1]	40	1			T2	1		T44	1		T24	1
auto[939524096:1073741823]	auto[0]	51	1			T3	1		T42	2		T100	1
auto[939524096:1073741823]	auto[1]	49	1			T131	1		T139	1		T253	1
auto[1073741824:1207959551]	auto[0]	42	1			T3	1		T44	1		T78	1
auto[1073741824:1207959551]	auto[1]	56	1			T401	1		T27	1		T5	1
auto[1207959552:1342177279]	auto[0]	55	1			T41	1		T42	1		T23	1
auto[1207959552:1342177279]	auto[1]	54	1			T76	2		T41	1		T42	3
auto[1342177280:1476395007]	auto[0]	37	1			T118	1		T49	1		T89	1
auto[1342177280:1476395007]	auto[1]	46	1			T150	1		T49	1		T100	1
auto[1476395008:1610612735]	auto[0]	57	1			T42	1		T100	1		T215	1
auto[1476395008:1610612735]	auto[1]	46	1			T42	1		T118	1		T31	1
auto[1610612736:1744830463]	auto[0]	46	1			T89	2		T213	1		T309	1
auto[1610612736:1744830463]	auto[1]	54	1			T25	1		T35	1		T41	1
auto[1744830464:1879048191]	auto[0]	39	1			T25	1		T42	1		T5	1
auto[1744830464:1879048191]	auto[1]	56	1			T32	1		T41	1		T213	1
auto[1879048192:2013265919]	auto[0]	45	1			T35	1		T5	1		T213	1
auto[1879048192:2013265919]	auto[1]	58	1			T101	1		T25	1		T42	1
auto[2013265920:2147483647]	auto[0]	39	1			T18	1		T42	1		T213	1
auto[2013265920:2147483647]	auto[1]	57	1			T35	1		T207	1		T206	1
auto[2147483648:2281701375]	auto[0]	54	1			T3	1		T18	2		T207	1
auto[2147483648:2281701375]	auto[1]	41	1			T41	2		T23	1		T100	1
auto[2281701376:2415919103]	auto[0]	54	1			T16	1		T31	1		T5	2
auto[2281701376:2415919103]	auto[1]	50	1			T2	1		T131	1		T216	1
auto[2415919104:2550136831]	auto[0]	44	1			T49	1		T100	1		T24	1
auto[2415919104:2550136831]	auto[1]	58	1			T219	1		T51	1		T208	1
auto[2550136832:2684354559]	auto[0]	46	1			T41	1		T100	1		T24	1
auto[2550136832:2684354559]	auto[1]	48	1			T3	1		T42	1		T49	1
auto[2684354560:2818572287]	auto[0]	52	1			T18	1		T42	2		T27	1
auto[2684354560:2818572287]	auto[1]	53	1			T30	1		T42	1		T100	1
auto[2818572288:2952790015]	auto[0]	48	1			T18	1		T41	1		T5	3
auto[2818572288:2952790015]	auto[1]	60	1			T42	1		T213	1		T57	1
auto[2952790016:3087007743]	auto[0]	54	1			T18	1		T51	2		T84	1
auto[2952790016:3087007743]	auto[1]	55	1			T119	1		T5	2		T214	1
auto[3087007744:3221225471]	auto[0]	34	1			T42	1		T31	1		T100	1
auto[3087007744:3221225471]	auto[1]	50	1			T207	1		T41	1		T42	1
auto[3221225472:3355443199]	auto[0]	44	1			T18	1		T76	2		T207	1
auto[3221225472:3355443199]	auto[1]	43	1			T3	1		T42	1		T5	1
auto[3355443200:3489660927]	auto[0]	55	1			T31	1		T23	1		T5	1
auto[3355443200:3489660927]	auto[1]	50	1			T35	1		T42	2		T5	1
auto[3489660928:3623878655]	auto[0]	40	1			T42	1		T79	1		T209	1
auto[3489660928:3623878655]	auto[1]	45	1			T100	1		T5	1		T47	1
auto[3623878656:3758096383]	auto[0]	47	1			T25	1		T35	1		T401	1
auto[3623878656:3758096383]	auto[1]	51	1			T42	1		T5	1		T214	1
auto[3758096384:3892314111]	auto[0]	35	1			T76	1		T42	1		T27	1
auto[3758096384:3892314111]	auto[1]	55	1			T41	1		T42	1		T5	1
auto[3892314112:4026531839]	auto[0]	56	1			T18	2		T30	1		T44	1
auto[3892314112:4026531839]	auto[1]	52	1			T78	1		T60	1		T213	1
auto[4026531840:4160749567]	auto[0]	56	1			T42	1		T49	1		T100	1
auto[4026531840:4160749567]	auto[1]	61	1			T44	1		T41	1		T42	1
auto[4160749568:4294967295]	auto[0]	45	1			T101	1		T207	1		T41	1
auto[4160749568:4294967295]	auto[1]	51	1			T49	1		T206	1		T5	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1511

1

T3

3

T14

1

T16

2

auto[1]

1604

1

T2

2

T3

3

T18

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	93	1			T18	1		T39	1		T48	1
auto[134217728:268435455]	95	1			T18	1		T44	1		T42	3
auto[268435456:402653183]	93	1			T16	1		T76	1		T35	1
auto[402653184:536870911]	99	1			T101	1		T207	1		T42	3
auto[536870912:671088639]	88	1			T3	2		T18	1		T207	1
auto[671088640:805306367]	97	1			T18	1		T35	1		T206	1
auto[805306368:939524095]	85	1			T41	1		T42	1		T119	1
auto[939524096:1073741823]	98	1			T18	1		T76	1		T44	1
auto[1073741824:1207959551]	99	1			T101	1		T25	1		T35	1
auto[1207959552:1342177279]	110	1			T41	1		T78	1		T42	2
auto[1342177280:1476395007]	99	1			T18	1		T207	1		T42	2
auto[1476395008:1610612735]	92	1			T78	1		T42	3		T131	1
auto[1610612736:1744830463]	104	1			T4	1		T42	2		T150	1
auto[1744830464:1879048191]	97	1			T42	2		T150	1		T31	1
auto[1879048192:2013265919]	111	1			T3	1		T76	1		T42	1
auto[2013265920:2147483647]	114	1			T16	1		T76	1		T207	1
auto[2147483648:2281701375]	92	1			T2	1		T18	1		T44	1
auto[2281701376:2415919103]	98	1			T42	2		T401	1		T119	1
auto[2415919104:2550136831]	100	1			T30	1		T25	1		T150	1
auto[2550136832:2684354559]	92	1			T18	1		T76	2		T42	1
auto[2684354560:2818572287]	80	1			T23	2		T49	1		T100	1
auto[2818572288:2952790015]	103	1			T25	1		T44	1		T100	1
auto[2952790016:3087007743]	100	1			T3	1		T32	1		T42	1
auto[3087007744:3221225471]	93	1			T3	1		T18	1		T25	1
auto[3221225472:3355443199]	102	1			T2	1		T207	1		T42	1
auto[3355443200:3489660927]	94	1			T18	1		T41	2		T42	2
auto[3489660928:3623878655]	83	1			T30	1		T42	1		T49	1
auto[3623878656:3758096383]	104	1			T18	1		T35	1		T42	1
auto[3758096384:3892314111]	95	1			T41	1		T5	1		T24	1
auto[3892314112:4026531839]	104	1			T3	1		T207	1		T100	1
auto[4026531840:4160749567]	102	1			T14	1		T18	1		T25	1
auto[4160749568:4294967295]	99	1			T18	1		T39	1		T41	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	45	1			T18	1		T42	1		T31	1
auto[0:134217727]	auto[1]	48	1			T39	1		T48	1		T5	1
auto[134217728:268435455]	auto[0]	53	1			T18	1		T42	2		T84	1
auto[134217728:268435455]	auto[1]	42	1			T44	1		T42	1		T5	1
auto[268435456:402653183]	auto[0]	43	1			T16	1		T5	1		T24	1
auto[268435456:402653183]	auto[1]	50	1			T76	1		T35	1		T41	3
auto[402653184:536870911]	auto[0]	51	1			T101	1		T207	1		T42	1
auto[402653184:536870911]	auto[1]	48	1			T42	2		T372	1		T36	1
auto[536870912:671088639]	auto[0]	39	1			T3	1		T118	1		T31	1
auto[536870912:671088639]	auto[1]	49	1			T3	1		T18	1		T207	1
auto[671088640:805306367]	auto[0]	46	1			T18	1		T206	1		T100	1
auto[671088640:805306367]	auto[1]	51	1			T35	1		T139	1		T51	2
auto[805306368:939524095]	auto[0]	37	1			T49	1		T372	1		T37	1
auto[805306368:939524095]	auto[1]	48	1			T41	1		T42	1		T119	1
auto[939524096:1073741823]	auto[0]	57	1			T76	1		T44	1		T42	1
auto[939524096:1073741823]	auto[1]	41	1			T18	1		T35	1		T41	1
auto[1073741824:1207959551]	auto[0]	45	1			T35	1		T100	1		T51	1
auto[1073741824:1207959551]	auto[1]	54	1			T101	1		T25	1		T207	1
auto[1207959552:1342177279]	auto[0]	46	1			T100	1		T133	1		T51	1
auto[1207959552:1342177279]	auto[1]	64	1			T41	1		T78	1		T42	2
auto[1342177280:1476395007]	auto[0]	53	1			T18	1		T207	1		T42	1
auto[1342177280:1476395007]	auto[1]	46	1			T42	1		T5	1		T268	1
auto[1476395008:1610612735]	auto[0]	53	1			T42	1		T131	1		T43	1
auto[1476395008:1610612735]	auto[1]	39	1			T78	1		T42	2		T253	1
auto[1610612736:1744830463]	auto[0]	47	1			T42	1		T150	1		T5	1
auto[1610612736:1744830463]	auto[1]	57	1			T4	1		T42	1		T31	1
auto[1744830464:1879048191]	auto[0]	54	1			T42	1		T31	1		T43	1
auto[1744830464:1879048191]	auto[1]	43	1			T42	1		T150	1		T49	1
auto[1879048192:2013265919]	auto[0]	55	1			T3	1		T42	1		T79	1
auto[1879048192:2013265919]	auto[1]	56	1			T76	1		T131	1		T5	1
auto[2013265920:2147483647]	auto[0]	51	1			T16	1		T207	1		T41	1
auto[2013265920:2147483647]	auto[1]	63	1			T76	1		T100	1		T131	1
auto[2147483648:2281701375]	auto[0]	44	1			T18	1		T5	1		T79	1
auto[2147483648:2281701375]	auto[1]	48	1			T2	1		T44	1		T35	1
auto[2281701376:2415919103]	auto[0]	47	1			T42	1		T119	1		T5	2
auto[2281701376:2415919103]	auto[1]	51	1			T42	1		T401	1		T213	1
auto[2415919104:2550136831]	auto[0]	57	1			T30	1		T150	1		T49	1
auto[2415919104:2550136831]	auto[1]	43	1			T25	1		T5	1		T60	1
auto[2550136832:2684354559]	auto[0]	50	1			T18	1		T76	2		T42	1
auto[2550136832:2684354559]	auto[1]	42	1			T31	1		T100	1		T139	1
auto[2684354560:2818572287]	auto[0]	37	1			T23	2		T100	1		T51	1
auto[2684354560:2818572287]	auto[1]	43	1			T49	1		T5	1		T51	1
auto[2818572288:2952790015]	auto[0]	52	1			T25	1		T131	1		T5	2
auto[2818572288:2952790015]	auto[1]	51	1			T44	1		T100	1		T5	1
auto[2952790016:3087007743]	auto[0]	51	1			T3	1		T219	2		T89	1
auto[2952790016:3087007743]	auto[1]	49	1			T32	1		T42	1		T118	1
auto[3087007744:3221225471]	auto[0]	40	1			T25	1		T44	1		T49	1
auto[3087007744:3221225471]	auto[1]	53	1			T3	1		T18	1		T41	1
auto[3221225472:3355443199]	auto[0]	45	1			T100	1		T5	1		T86	1
auto[3221225472:3355443199]	auto[1]	57	1			T2	1		T207	1		T42	1
auto[3355443200:3489660927]	auto[0]	42	1			T18	1		T100	1		T24	1
auto[3355443200:3489660927]	auto[1]	52	1			T41	2		T42	2		T5	2
auto[3489660928:3623878655]	auto[0]	33	1			T30	1		T100	1		T5	1
auto[3489660928:3623878655]	auto[1]	50	1			T42	1		T49	1		T5	1
auto[3623878656:3758096383]	auto[0]	52	1			T18	1		T35	1		T213	2
auto[3623878656:3758096383]	auto[1]	52	1			T42	1		T206	1		T5	2
auto[3758096384:3892314111]	auto[0]	41	1			T24	1		T43	1		T213	2
auto[3758096384:3892314111]	auto[1]	54	1			T41	1		T5	1		T43	1
auto[3892314112:4026531839]	auto[0]	40	1			T51	1		T84	1		T303	1
auto[3892314112:4026531839]	auto[1]	64	1			T3	1		T207	1		T100	1
auto[4026531840:4160749567]	auto[0]	53	1			T14	1		T18	1		T25	1
auto[4026531840:4160749567]	auto[1]	49	1			T248	1		T213	1		T59	1
auto[4160749568:4294967295]	auto[0]	52	1			T18	1		T39	1		T31	1
auto[4160749568:4294967295]	auto[1]	47	1			T41	1		T49	1		T213	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1547

1

T3

4

T14

1

T16

1

auto[1]

1569

1

T2

2

T3

2

T16

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	92	1			T16	1		T18	1		T101	2
auto[134217728:268435455]	71	1			T42	1		T119	1		T150	1
auto[268435456:402653183]	112	1			T35	1		T48	1		T42	1
auto[402653184:536870911]	99	1			T16	1		T76	1		T41	1
auto[536870912:671088639]	96	1			T25	1		T41	3		T42	1
auto[671088640:805306367]	91	1			T76	2		T44	1		T41	1
auto[805306368:939524095]	104	1			T25	1		T39	1		T44	1
auto[939524096:1073741823]	79	1			T18	1		T76	1		T25	1
auto[1073741824:1207959551]	116	1			T18	1		T35	1		T41	2
auto[1207959552:1342177279]	71	1			T3	1		T42	3		T100	1
auto[1342177280:1476395007]	95	1			T18	1		T41	2		T42	1
auto[1476395008:1610612735]	104	1			T3	1		T207	1		T41	1
auto[1610612736:1744830463]	95	1			T18	2		T207	1		T5	1
auto[1744830464:1879048191]	119	1			T3	1		T41	1		T100	1
auto[1879048192:2013265919]	94	1			T207	1		T42	2		T5	2
auto[2013265920:2147483647]	98	1			T30	1		T35	1		T42	1
auto[2147483648:2281701375]	106	1			T2	1		T207	1		T42	3
auto[2281701376:2415919103]	98	1			T35	1		T42	2		T100	1
auto[2415919104:2550136831]	98	1			T78	1		T42	1		T49	1
auto[2550136832:2684354559]	108	1			T25	1		T42	2		T119	1
auto[2684354560:2818572287]	82	1			T3	1		T18	1		T42	2
auto[2818572288:2952790015]	74	1			T207	1		T41	1		T78	1
auto[2952790016:3087007743]	104	1			T18	1		T44	2		T4	1
auto[3087007744:3221225471]	105	1			T42	1		T100	1		T43	1
auto[3221225472:3355443199]	95	1			T3	1		T76	1		T42	2
auto[3355443200:3489660927]	91	1			T18	1		T31	1		T49	2
auto[3489660928:3623878655]	106	1			T3	1		T25	1		T42	2
auto[3623878656:3758096383]	120	1			T14	1		T18	2		T76	1
auto[3758096384:3892314111]	91	1			T41	1		T118	1		T31	1
auto[3892314112:4026531839]	95	1			T18	1		T30	1		T118	1
auto[4026531840:4160749567]	116	1			T39	1		T44	1		T31	1
auto[4160749568:4294967295]	91	1			T2	1		T18	1		T42	1