Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.83 99.07 98.10 98.44 100.00 99.11 98.41 91.66


Total test records in report: 1070
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T1009 /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.888957439 Apr 30 12:29:00 PM PDT 24 Apr 30 12:29:03 PM PDT 24 46470882 ps
T1010 /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2103015117 Apr 30 12:28:48 PM PDT 24 Apr 30 12:29:09 PM PDT 24 858648853 ps
T1011 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1753591433 Apr 30 12:28:49 PM PDT 24 Apr 30 12:28:59 PM PDT 24 387687686 ps
T1012 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.2524944686 Apr 30 12:29:09 PM PDT 24 Apr 30 12:29:14 PM PDT 24 382225403 ps
T1013 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.122208154 Apr 30 12:28:59 PM PDT 24 Apr 30 12:29:01 PM PDT 24 87983068 ps
T1014 /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2573214560 Apr 30 12:28:35 PM PDT 24 Apr 30 12:28:44 PM PDT 24 512244914 ps
T1015 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.4207183404 Apr 30 12:28:48 PM PDT 24 Apr 30 12:28:53 PM PDT 24 345457830 ps
T1016 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.1616102754 Apr 30 12:29:08 PM PDT 24 Apr 30 12:29:16 PM PDT 24 1020158717 ps
T1017 /workspace/coverage/cover_reg_top/28.keymgr_intr_test.2955443078 Apr 30 12:29:16 PM PDT 24 Apr 30 12:29:17 PM PDT 24 17421100 ps
T1018 /workspace/coverage/cover_reg_top/0.keymgr_intr_test.3275845120 Apr 30 12:28:48 PM PDT 24 Apr 30 12:28:50 PM PDT 24 13628639 ps
T1019 /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.1174975998 Apr 30 12:28:34 PM PDT 24 Apr 30 12:28:46 PM PDT 24 1045061141 ps
T163 /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.1532373533 Apr 30 12:29:16 PM PDT 24 Apr 30 12:29:34 PM PDT 24 1076951802 ps
T1020 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2954864558 Apr 30 12:29:00 PM PDT 24 Apr 30 12:29:06 PM PDT 24 217110633 ps
T1021 /workspace/coverage/cover_reg_top/5.keymgr_intr_test.1531541730 Apr 30 12:28:47 PM PDT 24 Apr 30 12:28:48 PM PDT 24 43424411 ps
T1022 /workspace/coverage/cover_reg_top/45.keymgr_intr_test.3106284228 Apr 30 12:29:19 PM PDT 24 Apr 30 12:29:20 PM PDT 24 32630358 ps
T1023 /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.592231144 Apr 30 12:28:34 PM PDT 24 Apr 30 12:28:37 PM PDT 24 98907327 ps
T1024 /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.3074235411 Apr 30 12:28:45 PM PDT 24 Apr 30 12:28:47 PM PDT 24 28464458 ps
T1025 /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.2917098497 Apr 30 12:28:49 PM PDT 24 Apr 30 12:28:59 PM PDT 24 449379818 ps
T1026 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.2804374565 Apr 30 12:28:59 PM PDT 24 Apr 30 12:29:02 PM PDT 24 195232233 ps
T1027 /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1909272566 Apr 30 12:28:56 PM PDT 24 Apr 30 12:28:58 PM PDT 24 17829226 ps
T1028 /workspace/coverage/cover_reg_top/40.keymgr_intr_test.2151030663 Apr 30 12:29:14 PM PDT 24 Apr 30 12:29:16 PM PDT 24 24491221 ps
T1029 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.1914834964 Apr 30 12:28:48 PM PDT 24 Apr 30 12:28:53 PM PDT 24 719202694 ps
T1030 /workspace/coverage/cover_reg_top/32.keymgr_intr_test.3826233858 Apr 30 12:29:15 PM PDT 24 Apr 30 12:29:16 PM PDT 24 10187792 ps
T1031 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.4171671585 Apr 30 12:28:41 PM PDT 24 Apr 30 12:28:44 PM PDT 24 28155853 ps
T1032 /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1374185705 Apr 30 12:28:44 PM PDT 24 Apr 30 12:28:45 PM PDT 24 44746833 ps
T165 /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1750301854 Apr 30 12:29:04 PM PDT 24 Apr 30 12:29:13 PM PDT 24 249293965 ps
T1033 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.560131135 Apr 30 12:29:15 PM PDT 24 Apr 30 12:29:17 PM PDT 24 7853788 ps
T1034 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.3108415337 Apr 30 12:28:43 PM PDT 24 Apr 30 12:28:46 PM PDT 24 76002274 ps
T1035 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2914988007 Apr 30 12:28:51 PM PDT 24 Apr 30 12:28:57 PM PDT 24 1265766925 ps
T172 /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.694337613 Apr 30 12:28:58 PM PDT 24 Apr 30 12:29:05 PM PDT 24 456659744 ps
T1036 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1732519991 Apr 30 12:28:51 PM PDT 24 Apr 30 12:28:55 PM PDT 24 120363168 ps
T1037 /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.769073802 Apr 30 12:28:40 PM PDT 24 Apr 30 12:28:41 PM PDT 24 81928473 ps
T1038 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2121606044 Apr 30 12:29:14 PM PDT 24 Apr 30 12:29:20 PM PDT 24 179949861 ps
T1039 /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.3392083236 Apr 30 12:28:48 PM PDT 24 Apr 30 12:28:50 PM PDT 24 19891143 ps
T1040 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.2118673850 Apr 30 12:28:33 PM PDT 24 Apr 30 12:28:39 PM PDT 24 1929586409 ps
T1041 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.4076282115 Apr 30 12:28:45 PM PDT 24 Apr 30 12:28:58 PM PDT 24 1503406268 ps
T167 /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.2461553730 Apr 30 12:29:10 PM PDT 24 Apr 30 12:29:22 PM PDT 24 476112533 ps
T1042 /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.4134176681 Apr 30 12:28:39 PM PDT 24 Apr 30 12:28:41 PM PDT 24 69490355 ps
T1043 /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.961342271 Apr 30 12:29:07 PM PDT 24 Apr 30 12:29:10 PM PDT 24 90372671 ps
T1044 /workspace/coverage/cover_reg_top/11.keymgr_intr_test.1292991229 Apr 30 12:28:58 PM PDT 24 Apr 30 12:28:59 PM PDT 24 34088312 ps
T1045 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.2809946100 Apr 30 12:28:54 PM PDT 24 Apr 30 12:28:56 PM PDT 24 13176447 ps
T1046 /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.4241295464 Apr 30 12:29:03 PM PDT 24 Apr 30 12:29:05 PM PDT 24 29382312 ps
T1047 /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2114951084 Apr 30 12:29:01 PM PDT 24 Apr 30 12:29:04 PM PDT 24 37960517 ps
T1048 /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.2442253226 Apr 30 12:29:01 PM PDT 24 Apr 30 12:29:06 PM PDT 24 154673982 ps
T1049 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.977059768 Apr 30 12:29:04 PM PDT 24 Apr 30 12:29:10 PM PDT 24 481620776 ps
T1050 /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.1079874414 Apr 30 12:28:41 PM PDT 24 Apr 30 12:28:43 PM PDT 24 43241055 ps
T1051 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.3633106028 Apr 30 12:28:40 PM PDT 24 Apr 30 12:28:44 PM PDT 24 273945557 ps
T1052 /workspace/coverage/cover_reg_top/2.keymgr_intr_test.212330245 Apr 30 12:28:34 PM PDT 24 Apr 30 12:28:35 PM PDT 24 9393433 ps
T171 /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.183030636 Apr 30 12:28:34 PM PDT 24 Apr 30 12:28:38 PM PDT 24 98900013 ps
T1053 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1375621997 Apr 30 12:28:38 PM PDT 24 Apr 30 12:28:46 PM PDT 24 691066332 ps
T1054 /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.892059600 Apr 30 12:28:58 PM PDT 24 Apr 30 12:29:05 PM PDT 24 234617244 ps
T1055 /workspace/coverage/cover_reg_top/26.keymgr_intr_test.2165262840 Apr 30 12:29:16 PM PDT 24 Apr 30 12:29:18 PM PDT 24 29892694 ps
T1056 /workspace/coverage/cover_reg_top/4.keymgr_intr_test.2371505709 Apr 30 12:28:44 PM PDT 24 Apr 30 12:28:46 PM PDT 24 17938243 ps
T1057 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.1000086528 Apr 30 12:28:33 PM PDT 24 Apr 30 12:28:36 PM PDT 24 69005805 ps
T1058 /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.954112 Apr 30 12:28:47 PM PDT 24 Apr 30 12:28:50 PM PDT 24 47541186 ps
T168 /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.2487298508 Apr 30 12:29:07 PM PDT 24 Apr 30 12:29:18 PM PDT 24 5287279609 ps
T174 /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.254093111 Apr 30 12:28:52 PM PDT 24 Apr 30 12:28:57 PM PDT 24 339417516 ps
T1059 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3642804938 Apr 30 12:28:51 PM PDT 24 Apr 30 12:29:07 PM PDT 24 1905161373 ps
T1060 /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1069563710 Apr 30 12:28:44 PM PDT 24 Apr 30 12:28:48 PM PDT 24 87908483 ps
T1061 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.448677044 Apr 30 12:29:00 PM PDT 24 Apr 30 12:29:15 PM PDT 24 1432289772 ps
T1062 /workspace/coverage/cover_reg_top/27.keymgr_intr_test.3138917069 Apr 30 12:29:19 PM PDT 24 Apr 30 12:29:20 PM PDT 24 28139830 ps
T1063 /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.1371194660 Apr 30 12:28:33 PM PDT 24 Apr 30 12:28:35 PM PDT 24 159886692 ps
T154 /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.2591027016 Apr 30 12:29:01 PM PDT 24 Apr 30 12:29:08 PM PDT 24 129917217 ps
T1064 /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.669072551 Apr 30 12:28:48 PM PDT 24 Apr 30 12:28:51 PM PDT 24 85571362 ps
T1065 /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.1138887655 Apr 30 12:28:47 PM PDT 24 Apr 30 12:28:51 PM PDT 24 110940276 ps
T1066 /workspace/coverage/cover_reg_top/17.keymgr_intr_test.409040786 Apr 30 12:29:11 PM PDT 24 Apr 30 12:29:12 PM PDT 24 12062030 ps
T1067 /workspace/coverage/cover_reg_top/8.keymgr_intr_test.3671689346 Apr 30 12:28:50 PM PDT 24 Apr 30 12:28:52 PM PDT 24 13162439 ps
T1068 /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.2647065124 Apr 30 12:29:01 PM PDT 24 Apr 30 12:29:05 PM PDT 24 213991295 ps
T1069 /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.4008475657 Apr 30 12:28:54 PM PDT 24 Apr 30 12:28:57 PM PDT 24 34344738 ps
T1070 /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1475646032 Apr 30 12:28:50 PM PDT 24 Apr 30 12:28:53 PM PDT 24 136020085 ps

Test location /workspace/coverage/default/14.keymgr_stress_all.969346943
Short name T18
Test name
Test status
Simulation time 96653384256 ps
CPU time 372.31 seconds
Started Apr 30 12:31:00 PM PDT 24
Finished Apr 30 12:37:13 PM PDT 24
Peak memory 220048 kb
Host smart-3c52dbfb-3a75-40ce-90f1-7372d72d4949
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969346943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.969346943
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.714330603
Short name T42
Test name
Test status
Simulation time 21556666457 ps
CPU time 255.1 seconds
Started Apr 30 12:30:52 PM PDT 24
Finished Apr 30 12:35:09 PM PDT 24
Peak memory 218632 kb
Host smart-fbe67f06-fc4e-43ad-b8d5-f38d8f7dfafa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714330603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.714330603
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.711828922
Short name T36
Test name
Test status
Simulation time 427628680 ps
CPU time 21.37 seconds
Started Apr 30 12:31:43 PM PDT 24
Finished Apr 30 12:32:06 PM PDT 24
Peak memory 216060 kb
Host smart-29ff2700-86a5-4fa6-97a2-96e2b8f4e26a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711828922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.711828922
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.3583480828
Short name T10
Test name
Test status
Simulation time 7064135797 ps
CPU time 200.68 seconds
Started Apr 30 12:30:36 PM PDT 24
Finished Apr 30 12:33:58 PM PDT 24
Peak memory 283964 kb
Host smart-612cfb3a-2b70-4290-b4ff-587b109e0f43
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583480828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.3583480828
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.2727116374
Short name T125
Test name
Test status
Simulation time 701080460 ps
CPU time 19.47 seconds
Started Apr 30 12:31:59 PM PDT 24
Finished Apr 30 12:32:19 PM PDT 24
Peak memory 220924 kb
Host smart-1ee3e82d-e6fc-41bc-bf94-291946441815
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727116374 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.2727116374
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.132165904
Short name T32
Test name
Test status
Simulation time 125736439 ps
CPU time 4.72 seconds
Started Apr 30 12:31:01 PM PDT 24
Finished Apr 30 12:31:07 PM PDT 24
Peak memory 209176 kb
Host smart-443ee5aa-b745-4aed-b3d4-1aef4d73b927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132165904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.132165904
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.245539427
Short name T213
Test name
Test status
Simulation time 450201312 ps
CPU time 17.51 seconds
Started Apr 30 12:31:34 PM PDT 24
Finished Apr 30 12:31:53 PM PDT 24
Peak memory 220680 kb
Host smart-ea0e0c1b-c24c-48de-9b51-f8ae25380503
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245539427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.245539427
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.4255371195
Short name T37
Test name
Test status
Simulation time 1152693524 ps
CPU time 38.71 seconds
Started Apr 30 12:31:58 PM PDT 24
Finished Apr 30 12:32:38 PM PDT 24
Peak memory 216540 kb
Host smart-9b4bc70a-5dd1-48b2-8272-16e0912dba90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255371195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.4255371195
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.1279450189
Short name T139
Test name
Test status
Simulation time 6585495735 ps
CPU time 18.32 seconds
Started Apr 30 12:31:36 PM PDT 24
Finished Apr 30 12:31:55 PM PDT 24
Peak memory 214048 kb
Host smart-d609c915-c0e4-4614-b9f5-b7f077683d14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1279450189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.1279450189
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.2736324234
Short name T7
Test name
Test status
Simulation time 384117808 ps
CPU time 7.89 seconds
Started Apr 30 12:30:50 PM PDT 24
Finished Apr 30 12:31:00 PM PDT 24
Peak memory 209556 kb
Host smart-c43397bf-baab-4489-aee5-9fda3b552abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736324234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.2736324234
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.3137576608
Short name T5
Test name
Test status
Simulation time 18912364892 ps
CPU time 248.12 seconds
Started Apr 30 12:31:19 PM PDT 24
Finished Apr 30 12:35:28 PM PDT 24
Peak memory 222220 kb
Host smart-bfbaa55f-9547-46ea-bf27-a88e87eb2fa3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137576608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.3137576608
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.2639448285
Short name T117
Test name
Test status
Simulation time 1559126423 ps
CPU time 13.18 seconds
Started Apr 30 12:28:41 PM PDT 24
Finished Apr 30 12:28:55 PM PDT 24
Peak memory 214564 kb
Host smart-192bb43f-f253-4aef-81ad-9090e4999ad7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639448285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.2639448285
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.1381080778
Short name T40
Test name
Test status
Simulation time 106829558 ps
CPU time 3.12 seconds
Started Apr 30 12:31:02 PM PDT 24
Finished Apr 30 12:31:06 PM PDT 24
Peak memory 206416 kb
Host smart-c7cddd16-8eb4-4a84-8092-a16c8bdce631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381080778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.1381080778
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.305751327
Short name T119
Test name
Test status
Simulation time 6765374852 ps
CPU time 84.75 seconds
Started Apr 30 12:31:22 PM PDT 24
Finished Apr 30 12:32:48 PM PDT 24
Peak memory 214148 kb
Host smart-93e21159-2191-433e-b79d-462d01083251
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=305751327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.305751327
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.2538938181
Short name T86
Test name
Test status
Simulation time 989916623 ps
CPU time 5.43 seconds
Started Apr 30 12:30:58 PM PDT 24
Finished Apr 30 12:31:05 PM PDT 24
Peak memory 222080 kb
Host smart-fb3b4096-ca6d-4f07-9590-3ed952e5eb6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538938181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.2538938181
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.1034395011
Short name T359
Test name
Test status
Simulation time 661379145 ps
CPU time 36.41 seconds
Started Apr 30 12:31:32 PM PDT 24
Finished Apr 30 12:32:10 PM PDT 24
Peak memory 214232 kb
Host smart-81afe92b-9dfc-4aa5-9ac9-d406ce596740
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1034395011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.1034395011
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.3691434147
Short name T113
Test name
Test status
Simulation time 232747340 ps
CPU time 9.65 seconds
Started Apr 30 12:32:40 PM PDT 24
Finished Apr 30 12:32:51 PM PDT 24
Peak memory 222312 kb
Host smart-c0ea0457-83d4-4381-8ce6-f2f3b54f7015
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691434147 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.3691434147
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.2628953199
Short name T76
Test name
Test status
Simulation time 144860655 ps
CPU time 9.05 seconds
Started Apr 30 12:30:46 PM PDT 24
Finished Apr 30 12:30:56 PM PDT 24
Peak memory 213968 kb
Host smart-c12deea8-c111-45e7-97dd-a26a068259cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2628953199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.2628953199
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.3604902111
Short name T84
Test name
Test status
Simulation time 799730716 ps
CPU time 5.32 seconds
Started Apr 30 12:31:13 PM PDT 24
Finished Apr 30 12:31:19 PM PDT 24
Peak memory 214672 kb
Host smart-acd94799-938b-4ae0-bb19-372d6aefcf3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604902111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.3604902111
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.529907717
Short name T151
Test name
Test status
Simulation time 27094534 ps
CPU time 1.74 seconds
Started Apr 30 12:29:09 PM PDT 24
Finished Apr 30 12:29:12 PM PDT 24
Peak memory 214332 kb
Host smart-b13974bd-5a5b-408e-9c45-6f85433820e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529907717 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.529907717
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.688646051
Short name T54
Test name
Test status
Simulation time 149858294 ps
CPU time 4.81 seconds
Started Apr 30 12:32:15 PM PDT 24
Finished Apr 30 12:32:21 PM PDT 24
Peak memory 210096 kb
Host smart-9fdbb602-89d4-4044-b742-4cffb23c8e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688646051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.688646051
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.3926890039
Short name T127
Test name
Test status
Simulation time 2044345622 ps
CPU time 17.97 seconds
Started Apr 30 12:31:46 PM PDT 24
Finished Apr 30 12:32:05 PM PDT 24
Peak memory 222352 kb
Host smart-9dfd0bbd-5172-4bc0-b323-6bfd49468726
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926890039 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.3926890039
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.2225495883
Short name T122
Test name
Test status
Simulation time 582884836 ps
CPU time 4.46 seconds
Started Apr 30 12:29:12 PM PDT 24
Finished Apr 30 12:29:17 PM PDT 24
Peak memory 214564 kb
Host smart-fa0b8a03-e53b-40b4-9e47-e63b19fdc0f0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225495883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.2225495883
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.2216635481
Short name T403
Test name
Test status
Simulation time 458748466 ps
CPU time 5.72 seconds
Started Apr 30 12:30:51 PM PDT 24
Finished Apr 30 12:30:58 PM PDT 24
Peak memory 213956 kb
Host smart-8edf1906-1148-4736-bf8a-ab6c9bec9211
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2216635481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.2216635481
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.3309158751
Short name T262
Test name
Test status
Simulation time 1659231757 ps
CPU time 57.59 seconds
Started Apr 30 12:31:52 PM PDT 24
Finished Apr 30 12:32:51 PM PDT 24
Peak memory 222148 kb
Host smart-dfa208c5-c868-4083-accd-62448cc20584
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309158751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.3309158751
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.1232918570
Short name T411
Test name
Test status
Simulation time 918369962 ps
CPU time 13.57 seconds
Started Apr 30 12:31:18 PM PDT 24
Finished Apr 30 12:31:32 PM PDT 24
Peak memory 215188 kb
Host smart-5700aa49-e806-4611-b206-18d8cf03c134
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1232918570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.1232918570
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.1975011489
Short name T27
Test name
Test status
Simulation time 1371635314 ps
CPU time 6.88 seconds
Started Apr 30 12:30:51 PM PDT 24
Finished Apr 30 12:31:00 PM PDT 24
Peak memory 209276 kb
Host smart-23d79268-9eee-4d69-a562-2840e899662d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975011489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.1975011489
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.3474720070
Short name T201
Test name
Test status
Simulation time 17617331609 ps
CPU time 106.76 seconds
Started Apr 30 12:31:55 PM PDT 24
Finished Apr 30 12:33:44 PM PDT 24
Peak memory 222268 kb
Host smart-956bb726-1a31-4623-82a0-1b8d96ecd34a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474720070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.3474720070
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.3762579231
Short name T304
Test name
Test status
Simulation time 51335184 ps
CPU time 3.54 seconds
Started Apr 30 12:31:43 PM PDT 24
Finished Apr 30 12:31:48 PM PDT 24
Peak memory 213936 kb
Host smart-0061b262-2c18-4181-867e-3e6acb3dce08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3762579231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.3762579231
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.830628737
Short name T21
Test name
Test status
Simulation time 346336928 ps
CPU time 2.09 seconds
Started Apr 30 12:31:36 PM PDT 24
Finished Apr 30 12:31:39 PM PDT 24
Peak memory 220940 kb
Host smart-e63d7ea7-de5d-4ef4-86d5-fc1b95aed532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830628737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.830628737
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.1223030023
Short name T90
Test name
Test status
Simulation time 223765246 ps
CPU time 2.59 seconds
Started Apr 30 12:32:48 PM PDT 24
Finished Apr 30 12:32:52 PM PDT 24
Peak memory 220440 kb
Host smart-4bbc6f33-8d8a-4814-9719-8155816a2a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223030023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.1223030023
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.2404365230
Short name T51
Test name
Test status
Simulation time 1883457735 ps
CPU time 19.78 seconds
Started Apr 30 12:31:52 PM PDT 24
Finished Apr 30 12:32:14 PM PDT 24
Peak memory 220520 kb
Host smart-da3b1697-f587-413f-bbcf-1aae2636a411
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404365230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.2404365230
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.1898212912
Short name T181
Test name
Test status
Simulation time 23428746 ps
CPU time 2.11 seconds
Started Apr 30 12:30:46 PM PDT 24
Finished Apr 30 12:30:49 PM PDT 24
Peak memory 222368 kb
Host smart-cf7719c1-928a-437b-9580-24ef4d380e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898212912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.1898212912
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.590886013
Short name T297
Test name
Test status
Simulation time 2160173503 ps
CPU time 117.29 seconds
Started Apr 30 12:31:42 PM PDT 24
Finished Apr 30 12:33:41 PM PDT 24
Peak memory 215580 kb
Host smart-269130a4-031b-4105-ba5e-8d4c75afadd4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=590886013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.590886013
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.2699597087
Short name T159
Test name
Test status
Simulation time 210645730 ps
CPU time 7.81 seconds
Started Apr 30 12:28:49 PM PDT 24
Finished Apr 30 12:28:57 PM PDT 24
Peak memory 209604 kb
Host smart-9df6cc1c-75a0-4e71-89fe-816881dbf311
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699597087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.2699597087
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.2602642657
Short name T416
Test name
Test status
Simulation time 9678970 ps
CPU time 0.81 seconds
Started Apr 30 12:30:45 PM PDT 24
Finished Apr 30 12:30:47 PM PDT 24
Peak memory 205540 kb
Host smart-638bed1d-1bd3-47ae-92f9-5bd7b77d0328
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602642657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.2602642657
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.2302466453
Short name T49
Test name
Test status
Simulation time 842279723 ps
CPU time 22.12 seconds
Started Apr 30 12:30:46 PM PDT 24
Finished Apr 30 12:31:10 PM PDT 24
Peak memory 214100 kb
Host smart-ad7ebec5-0b4d-4938-b437-bdd3a3bb6317
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302466453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.2302466453
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.857077805
Short name T357
Test name
Test status
Simulation time 1617042155 ps
CPU time 30.26 seconds
Started Apr 30 12:32:29 PM PDT 24
Finished Apr 30 12:33:00 PM PDT 24
Peak memory 213964 kb
Host smart-2df74a25-1810-4e3d-b588-9cc0e0101bd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=857077805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.857077805
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.106308947
Short name T161
Test name
Test status
Simulation time 5421987602 ps
CPU time 8.27 seconds
Started Apr 30 12:28:45 PM PDT 24
Finished Apr 30 12:28:54 PM PDT 24
Peak memory 209348 kb
Host smart-0b7546bb-0fb5-4381-aea3-51f62f5bef24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106308947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.
106308947
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.2062078819
Short name T81
Test name
Test status
Simulation time 40468260926 ps
CPU time 62.25 seconds
Started Apr 30 12:30:48 PM PDT 24
Finished Apr 30 12:31:52 PM PDT 24
Peak memory 234052 kb
Host smart-533fae89-e90c-422e-8615-d1d7c2167347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062078819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.2062078819
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.2916042962
Short name T231
Test name
Test status
Simulation time 9451568431 ps
CPU time 97.23 seconds
Started Apr 30 12:31:55 PM PDT 24
Finished Apr 30 12:33:34 PM PDT 24
Peak memory 215888 kb
Host smart-ebbc506b-7506-47a6-8096-f99fd7255311
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916042962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.2916042962
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.2842071352
Short name T202
Test name
Test status
Simulation time 3834402559 ps
CPU time 36.19 seconds
Started Apr 30 12:32:30 PM PDT 24
Finished Apr 30 12:33:07 PM PDT 24
Peak memory 215348 kb
Host smart-8450280a-5f8e-4758-82e2-745991f7bea3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842071352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.2842071352
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.1507000952
Short name T80
Test name
Test status
Simulation time 810451812 ps
CPU time 6.35 seconds
Started Apr 30 12:31:44 PM PDT 24
Finished Apr 30 12:31:52 PM PDT 24
Peak memory 213988 kb
Host smart-ade2077e-87b6-4a94-bf05-4802993ea014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507000952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.1507000952
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.281022904
Short name T326
Test name
Test status
Simulation time 160668888 ps
CPU time 5.97 seconds
Started Apr 30 12:30:55 PM PDT 24
Finished Apr 30 12:31:02 PM PDT 24
Peak memory 214024 kb
Host smart-4d9595fd-4777-4aee-aef4-4d72cda82e32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=281022904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.281022904
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.1638490659
Short name T246
Test name
Test status
Simulation time 621828067 ps
CPU time 3.95 seconds
Started Apr 30 12:31:53 PM PDT 24
Finished Apr 30 12:31:59 PM PDT 24
Peak memory 214108 kb
Host smart-84e11bd1-1789-4aa5-b672-7720be93f102
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1638490659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.1638490659
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.2473612166
Short name T339
Test name
Test status
Simulation time 56896779 ps
CPU time 3.93 seconds
Started Apr 30 12:30:48 PM PDT 24
Finished Apr 30 12:30:53 PM PDT 24
Peak memory 213968 kb
Host smart-c6da1892-6a2a-40d7-ad88-2239c9a3f958
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2473612166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.2473612166
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.3505228889
Short name T3
Test name
Test status
Simulation time 103780641 ps
CPU time 4.65 seconds
Started Apr 30 12:32:34 PM PDT 24
Finished Apr 30 12:32:40 PM PDT 24
Peak memory 209080 kb
Host smart-72dd8a0c-09cc-4bff-bc08-5e3dbdf912a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505228889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.3505228889
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.3986725488
Short name T164
Test name
Test status
Simulation time 1493792376 ps
CPU time 16.24 seconds
Started Apr 30 12:30:42 PM PDT 24
Finished Apr 30 12:30:59 PM PDT 24
Peak memory 210564 kb
Host smart-65c2c95e-2fb6-4c34-ba24-6e67208570f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986725488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.3986725488
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1750301854
Short name T165
Test name
Test status
Simulation time 249293965 ps
CPU time 7.67 seconds
Started Apr 30 12:29:04 PM PDT 24
Finished Apr 30 12:29:13 PM PDT 24
Peak memory 214268 kb
Host smart-e3113086-4530-4d4b-aa3d-f62902f77f9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750301854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.1750301854
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.1348885903
Short name T182
Test name
Test status
Simulation time 179748915 ps
CPU time 3.33 seconds
Started Apr 30 12:32:29 PM PDT 24
Finished Apr 30 12:32:32 PM PDT 24
Peak memory 217568 kb
Host smart-5d954507-5139-4b30-9670-3d80fafac692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348885903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.1348885903
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.85193599
Short name T314
Test name
Test status
Simulation time 570239338 ps
CPU time 6.54 seconds
Started Apr 30 12:30:47 PM PDT 24
Finished Apr 30 12:30:55 PM PDT 24
Peak memory 219080 kb
Host smart-5959ae99-f151-4774-b247-ad6d8ab4720b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85193599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.85193599
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.2527215158
Short name T229
Test name
Test status
Simulation time 1065799004 ps
CPU time 25.59 seconds
Started Apr 30 12:31:45 PM PDT 24
Finished Apr 30 12:32:11 PM PDT 24
Peak memory 222320 kb
Host smart-c74c711d-f174-436e-a50b-f9375a3f4a59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527215158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.2527215158
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.1907057762
Short name T235
Test name
Test status
Simulation time 8134395070 ps
CPU time 52 seconds
Started Apr 30 12:32:15 PM PDT 24
Finished Apr 30 12:33:08 PM PDT 24
Peak memory 215384 kb
Host smart-559a1ee8-0de9-4909-bcec-6da10e7681d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907057762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.1907057762
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.1812165666
Short name T311
Test name
Test status
Simulation time 1697632218 ps
CPU time 6.98 seconds
Started Apr 30 12:32:37 PM PDT 24
Finished Apr 30 12:32:46 PM PDT 24
Peak memory 213956 kb
Host smart-581d7986-e346-4a5a-bcee-c718ff905df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812165666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.1812165666
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.63682244
Short name T179
Test name
Test status
Simulation time 139383315 ps
CPU time 3.11 seconds
Started Apr 30 12:30:46 PM PDT 24
Finished Apr 30 12:30:50 PM PDT 24
Peak memory 222404 kb
Host smart-a9918d59-7823-4b73-b922-0675f4287fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63682244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.63682244
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3438590276
Short name T114
Test name
Test status
Simulation time 508375691 ps
CPU time 3.89 seconds
Started Apr 30 12:28:38 PM PDT 24
Finished Apr 30 12:28:43 PM PDT 24
Peak memory 214556 kb
Host smart-bbf1cccb-478a-4e3c-9e05-d77e4cb9a00f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438590276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.3438590276
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.2591027016
Short name T154
Test name
Test status
Simulation time 129917217 ps
CPU time 5.6 seconds
Started Apr 30 12:29:01 PM PDT 24
Finished Apr 30 12:29:08 PM PDT 24
Peak memory 209708 kb
Host smart-e67f951d-bd07-4c85-b41c-a35026781147
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591027016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.2591027016
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.1570769860
Short name T61
Test name
Test status
Simulation time 38414053 ps
CPU time 2.34 seconds
Started Apr 30 12:31:53 PM PDT 24
Finished Apr 30 12:31:57 PM PDT 24
Peak memory 216288 kb
Host smart-5b504aa0-da43-4877-b184-870c06491c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570769860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.1570769860
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.921805519
Short name T183
Test name
Test status
Simulation time 84505462 ps
CPU time 3.32 seconds
Started Apr 30 12:31:56 PM PDT 24
Finished Apr 30 12:32:01 PM PDT 24
Peak memory 216972 kb
Host smart-d11a365d-8cec-4f6b-94ce-5fffdef419c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921805519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.921805519
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.892722642
Short name T247
Test name
Test status
Simulation time 1363967285 ps
CPU time 34.11 seconds
Started Apr 30 12:30:58 PM PDT 24
Finished Apr 30 12:31:33 PM PDT 24
Peak memory 214060 kb
Host smart-a93f075b-e413-46c5-ab64-c19d8c1ed19c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=892722642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.892722642
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.3676830014
Short name T224
Test name
Test status
Simulation time 840720529 ps
CPU time 20.38 seconds
Started Apr 30 12:31:06 PM PDT 24
Finished Apr 30 12:31:27 PM PDT 24
Peak memory 208320 kb
Host smart-09262a2a-a72d-4e69-b0bc-bcab366b70d8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676830014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.3676830014
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.1781313773
Short name T185
Test name
Test status
Simulation time 87783410 ps
CPU time 3.49 seconds
Started Apr 30 12:31:38 PM PDT 24
Finished Apr 30 12:31:43 PM PDT 24
Peak memory 209756 kb
Host smart-231cff1f-d4c6-468b-9df1-4588baa4a10d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781313773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.1781313773
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.635595621
Short name T374
Test name
Test status
Simulation time 1626669642 ps
CPU time 16.76 seconds
Started Apr 30 12:32:15 PM PDT 24
Finished Apr 30 12:32:33 PM PDT 24
Peak memory 215860 kb
Host smart-7b236c0f-7e9b-44c0-a281-ef1641ff7b16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635595621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.635595621
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.3483044613
Short name T329
Test name
Test status
Simulation time 392610574 ps
CPU time 19.15 seconds
Started Apr 30 12:32:16 PM PDT 24
Finished Apr 30 12:32:36 PM PDT 24
Peak memory 222028 kb
Host smart-5a8f7ffd-5d53-431a-b3bb-6375512c91a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483044613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.3483044613
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_sideload.1714551394
Short name T211
Test name
Test status
Simulation time 234675597 ps
CPU time 6.42 seconds
Started Apr 30 12:30:49 PM PDT 24
Finished Apr 30 12:30:57 PM PDT 24
Peak memory 208396 kb
Host smart-ec9d9002-6c1e-4b44-8afb-dbfbb22f1430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714551394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.1714551394
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.3678517006
Short name T240
Test name
Test status
Simulation time 603437268 ps
CPU time 30.32 seconds
Started Apr 30 12:30:44 PM PDT 24
Finished Apr 30 12:31:15 PM PDT 24
Peak memory 215740 kb
Host smart-9df58dec-12b0-4c28-891e-346d85dfbb00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678517006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.3678517006
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.2461553730
Short name T167
Test name
Test status
Simulation time 476112533 ps
CPU time 11.26 seconds
Started Apr 30 12:29:10 PM PDT 24
Finished Apr 30 12:29:22 PM PDT 24
Peak memory 209356 kb
Host smart-b3106dd1-0770-43bf-83b4-3383ec7255fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461553730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.2461553730
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.2285309644
Short name T385
Test name
Test status
Simulation time 546746017 ps
CPU time 7.62 seconds
Started Apr 30 12:32:39 PM PDT 24
Finished Apr 30 12:32:48 PM PDT 24
Peak memory 209008 kb
Host smart-dd9db68b-2072-46dd-bef2-fbd01b799784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285309644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.2285309644
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.300526884
Short name T552
Test name
Test status
Simulation time 81379490 ps
CPU time 3.32 seconds
Started Apr 30 12:32:36 PM PDT 24
Finished Apr 30 12:32:40 PM PDT 24
Peak memory 214180 kb
Host smart-bbfad871-16cd-4bee-bff6-7f4ef28485ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300526884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.300526884
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.3557203075
Short name T180
Test name
Test status
Simulation time 997529622 ps
CPU time 4.05 seconds
Started Apr 30 12:31:44 PM PDT 24
Finished Apr 30 12:31:49 PM PDT 24
Peak memory 218000 kb
Host smart-f4939aae-e353-4550-9363-3d054e18ffd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557203075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.3557203075
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.2811145883
Short name T31
Test name
Test status
Simulation time 1181982294 ps
CPU time 32.4 seconds
Started Apr 30 12:31:06 PM PDT 24
Finished Apr 30 12:31:39 PM PDT 24
Peak memory 230312 kb
Host smart-b012cda6-47e1-4462-b884-c98cc98ac2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811145883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.2811145883
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.1050171961
Short name T52
Test name
Test status
Simulation time 9943759498 ps
CPU time 109.75 seconds
Started Apr 30 12:30:55 PM PDT 24
Finished Apr 30 12:32:46 PM PDT 24
Peak memory 222148 kb
Host smart-1903bcc0-774a-4bf7-8498-a323a5ffb244
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050171961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.1050171961
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.2649748091
Short name T88
Test name
Test status
Simulation time 277683663 ps
CPU time 6.93 seconds
Started Apr 30 12:31:23 PM PDT 24
Finished Apr 30 12:31:31 PM PDT 24
Peak memory 210752 kb
Host smart-3a2cae8e-b3d9-49e0-a3fc-67acb7c6f913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649748091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.2649748091
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.2761880014
Short name T271
Test name
Test status
Simulation time 1849148705 ps
CPU time 8.4 seconds
Started Apr 30 12:31:45 PM PDT 24
Finished Apr 30 12:31:55 PM PDT 24
Peak memory 213848 kb
Host smart-7ebaa922-b49d-4e67-a990-3b2223d12751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761880014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.2761880014
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.182651600
Short name T24
Test name
Test status
Simulation time 1471574091 ps
CPU time 12.9 seconds
Started Apr 30 12:31:37 PM PDT 24
Finished Apr 30 12:31:50 PM PDT 24
Peak memory 211556 kb
Host smart-02722813-0693-47f8-b0c1-d797eca5198a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182651600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.182651600
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.2783915186
Short name T877
Test name
Test status
Simulation time 605323631 ps
CPU time 13.34 seconds
Started Apr 30 12:31:41 PM PDT 24
Finished Apr 30 12:31:55 PM PDT 24
Peak memory 213956 kb
Host smart-30caa9de-a903-4eca-b949-66219bd0f429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783915186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.2783915186
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.876437177
Short name T365
Test name
Test status
Simulation time 25241456540 ps
CPU time 246.51 seconds
Started Apr 30 12:31:45 PM PDT 24
Finished Apr 30 12:35:53 PM PDT 24
Peak memory 222224 kb
Host smart-5c8eded4-21dd-4110-9ae1-136e627172aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876437177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.876437177
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.1209056494
Short name T386
Test name
Test status
Simulation time 187788381 ps
CPU time 4.37 seconds
Started Apr 30 12:31:48 PM PDT 24
Finished Apr 30 12:31:54 PM PDT 24
Peak memory 208268 kb
Host smart-d86a5415-261b-4d2a-b426-5468ba1f398f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209056494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.1209056494
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.3209465258
Short name T140
Test name
Test status
Simulation time 219215801 ps
CPU time 4.35 seconds
Started Apr 30 12:32:17 PM PDT 24
Finished Apr 30 12:32:22 PM PDT 24
Peak memory 214780 kb
Host smart-7dd71b69-81f1-4816-a8a5-aba08046d962
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3209465258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.3209465258
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.3661417324
Short name T177
Test name
Test status
Simulation time 305114699 ps
CPU time 6.04 seconds
Started Apr 30 12:28:53 PM PDT 24
Finished Apr 30 12:29:00 PM PDT 24
Peak memory 214280 kb
Host smart-b406a8fe-7106-46c4-9afd-c1da5bb89736
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661417324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.3661417324
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.3589191803
Short name T156
Test name
Test status
Simulation time 684159372 ps
CPU time 4.95 seconds
Started Apr 30 12:28:41 PM PDT 24
Finished Apr 30 12:28:46 PM PDT 24
Peak memory 209564 kb
Host smart-251e8ace-bbaa-4317-a211-eea6eadb8f20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589191803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.3589191803
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.1666970253
Short name T176
Test name
Test status
Simulation time 821908115 ps
CPU time 14.45 seconds
Started Apr 30 12:28:43 PM PDT 24
Finished Apr 30 12:28:58 PM PDT 24
Peak memory 221036 kb
Host smart-b2ae5a51-3ef8-4fe8-a5bb-e084b01380aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666970253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.1666970253
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.3622488662
Short name T175
Test name
Test status
Simulation time 138115409 ps
CPU time 2.02 seconds
Started Apr 30 12:31:43 PM PDT 24
Finished Apr 30 12:31:46 PM PDT 24
Peak memory 209412 kb
Host smart-76bff8b2-5dfd-49f8-8729-c65f3fe9658e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622488662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.3622488662
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.946850353
Short name T244
Test name
Test status
Simulation time 56431570 ps
CPU time 3.36 seconds
Started Apr 30 12:30:42 PM PDT 24
Finished Apr 30 12:30:46 PM PDT 24
Peak memory 209252 kb
Host smart-0ad96b67-2601-4022-b017-d98a5842ff0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946850353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.946850353
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.2029172115
Short name T332
Test name
Test status
Simulation time 235858652 ps
CPU time 4.94 seconds
Started Apr 30 12:30:44 PM PDT 24
Finished Apr 30 12:30:50 PM PDT 24
Peak memory 215244 kb
Host smart-107e10f0-f444-4f0d-ba7f-5b30cf83b2da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2029172115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.2029172115
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_sideload.2210127827
Short name T338
Test name
Test status
Simulation time 77260155 ps
CPU time 3.39 seconds
Started Apr 30 12:30:45 PM PDT 24
Finished Apr 30 12:30:49 PM PDT 24
Peak memory 207428 kb
Host smart-8a398132-62c5-4add-934b-eb3864017ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210127827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.2210127827
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.2009543124
Short name T362
Test name
Test status
Simulation time 39504918 ps
CPU time 2.33 seconds
Started Apr 30 12:30:49 PM PDT 24
Finished Apr 30 12:30:52 PM PDT 24
Peak memory 208888 kb
Host smart-36d3a682-9bfb-4e0e-b13a-3db791cf2b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009543124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.2009543124
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.2087663887
Short name T693
Test name
Test status
Simulation time 399859095 ps
CPU time 4.72 seconds
Started Apr 30 12:30:56 PM PDT 24
Finished Apr 30 12:31:01 PM PDT 24
Peak memory 214040 kb
Host smart-803504d1-c250-421b-afab-7206565b97f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087663887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.2087663887
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.3918390157
Short name T349
Test name
Test status
Simulation time 204565306 ps
CPU time 7.01 seconds
Started Apr 30 12:30:55 PM PDT 24
Finished Apr 30 12:31:03 PM PDT 24
Peak memory 210148 kb
Host smart-b5638041-00fb-4829-b3ad-0d4516dba767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918390157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.3918390157
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_random.4032691434
Short name T108
Test name
Test status
Simulation time 101116832 ps
CPU time 4.32 seconds
Started Apr 30 12:30:55 PM PDT 24
Finished Apr 30 12:31:00 PM PDT 24
Peak memory 209456 kb
Host smart-d49982a3-7437-4e56-bd9b-dd8d3007c3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032691434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.4032691434
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.3401379578
Short name T366
Test name
Test status
Simulation time 1607460615 ps
CPU time 39.21 seconds
Started Apr 30 12:31:19 PM PDT 24
Finished Apr 30 12:31:59 PM PDT 24
Peak memory 216040 kb
Host smart-466f0dc7-bf9a-445a-8637-60de60b30159
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401379578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.3401379578
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.97214659
Short name T41
Test name
Test status
Simulation time 587321786 ps
CPU time 7.75 seconds
Started Apr 30 12:31:14 PM PDT 24
Finished Apr 30 12:31:22 PM PDT 24
Peak memory 215452 kb
Host smart-4fd945d9-9f7c-4b92-ab16-0c422dd3290c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97214659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.97214659
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.1790478800
Short name T111
Test name
Test status
Simulation time 324057275 ps
CPU time 5.95 seconds
Started Apr 30 12:31:29 PM PDT 24
Finished Apr 30 12:31:35 PM PDT 24
Peak memory 209696 kb
Host smart-e4fa9b34-2520-4dbd-8944-29d5e3c8e13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790478800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.1790478800
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.2692570471
Short name T295
Test name
Test status
Simulation time 67376036 ps
CPU time 3.89 seconds
Started Apr 30 12:31:21 PM PDT 24
Finished Apr 30 12:31:25 PM PDT 24
Peak memory 210972 kb
Host smart-29ceabd1-c3a7-416e-86d7-76817708237e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692570471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.2692570471
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.2834777472
Short name T68
Test name
Test status
Simulation time 14004467869 ps
CPU time 41.01 seconds
Started Apr 30 12:31:31 PM PDT 24
Finished Apr 30 12:32:13 PM PDT 24
Peak memory 221336 kb
Host smart-54169b17-9778-4835-9e54-1f5e4b4dfc69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834777472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.2834777472
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.1635344858
Short name T236
Test name
Test status
Simulation time 827134406 ps
CPU time 28.71 seconds
Started Apr 30 12:30:53 PM PDT 24
Finished Apr 30 12:31:23 PM PDT 24
Peak memory 222100 kb
Host smart-37ee2b96-35ec-467c-89a7-ac55f607bfe7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635344858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.1635344858
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.1669121747
Short name T853
Test name
Test status
Simulation time 913762465 ps
CPU time 5.2 seconds
Started Apr 30 12:31:30 PM PDT 24
Finished Apr 30 12:31:36 PM PDT 24
Peak memory 209120 kb
Host smart-25668cae-b66e-4d07-8658-9c659bf87b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669121747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.1669121747
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.3843435538
Short name T298
Test name
Test status
Simulation time 713031541 ps
CPU time 5.79 seconds
Started Apr 30 12:31:34 PM PDT 24
Finished Apr 30 12:31:40 PM PDT 24
Peak memory 217804 kb
Host smart-0aab7146-d96a-48cf-bfc6-c9c6a32f37d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843435538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.3843435538
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.4062488692
Short name T351
Test name
Test status
Simulation time 197354548 ps
CPU time 3.92 seconds
Started Apr 30 12:31:42 PM PDT 24
Finished Apr 30 12:31:47 PM PDT 24
Peak memory 215148 kb
Host smart-36c33054-b7d7-44d0-a918-c69178c559d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4062488692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.4062488692
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.2920634348
Short name T370
Test name
Test status
Simulation time 382094101 ps
CPU time 4.48 seconds
Started Apr 30 12:31:43 PM PDT 24
Finished Apr 30 12:31:49 PM PDT 24
Peak memory 209244 kb
Host smart-d0533332-0aab-4788-8f25-f15b4fc4e2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920634348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.2920634348
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.1156056926
Short name T387
Test name
Test status
Simulation time 118523411 ps
CPU time 4.78 seconds
Started Apr 30 12:31:56 PM PDT 24
Finished Apr 30 12:32:02 PM PDT 24
Peak memory 208284 kb
Host smart-4d96b023-7e8b-4549-9a58-cd9c54a36e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156056926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.1156056926
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.2302260784
Short name T225
Test name
Test status
Simulation time 54669222 ps
CPU time 2.26 seconds
Started Apr 30 12:32:17 PM PDT 24
Finished Apr 30 12:32:20 PM PDT 24
Peak memory 208472 kb
Host smart-548a47c4-2275-4333-8267-c2b3a2c58430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302260784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.2302260784
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.3508960504
Short name T227
Test name
Test status
Simulation time 364434050 ps
CPU time 3.21 seconds
Started Apr 30 12:32:19 PM PDT 24
Finished Apr 30 12:32:23 PM PDT 24
Peak memory 222264 kb
Host smart-482fbe62-5d6a-4f5e-8d8b-6a89dbfde21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508960504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.3508960504
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.1665170679
Short name T35
Test name
Test status
Simulation time 239031599 ps
CPU time 3.8 seconds
Started Apr 30 12:32:36 PM PDT 24
Finished Apr 30 12:32:41 PM PDT 24
Peak memory 214020 kb
Host smart-6bafd362-1aa5-4e6e-b43f-1d65416b0083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665170679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.1665170679
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.3105577906
Short name T238
Test name
Test status
Simulation time 69403969 ps
CPU time 2.47 seconds
Started Apr 30 12:32:45 PM PDT 24
Finished Apr 30 12:32:49 PM PDT 24
Peak memory 217120 kb
Host smart-f4c504ee-54f1-43e2-9fa6-c25d838abcd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105577906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.3105577906
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.2368352490
Short name T230
Test name
Test status
Simulation time 410557483 ps
CPU time 3.09 seconds
Started Apr 30 12:30:54 PM PDT 24
Finished Apr 30 12:30:58 PM PDT 24
Peak memory 208496 kb
Host smart-2d32030b-d134-4500-bcf0-bebf8fbd32c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368352490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.2368352490
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.3897502069
Short name T184
Test name
Test status
Simulation time 85980351 ps
CPU time 3.32 seconds
Started Apr 30 12:32:44 PM PDT 24
Finished Apr 30 12:32:49 PM PDT 24
Peak memory 217792 kb
Host smart-5ba69015-662d-4263-b70f-9701e07f75e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897502069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.3897502069
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.4178112869
Short name T995
Test name
Test status
Simulation time 667593693 ps
CPU time 9.05 seconds
Started Apr 30 12:28:47 PM PDT 24
Finished Apr 30 12:28:57 PM PDT 24
Peak memory 206000 kb
Host smart-6ee6e348-d212-4beb-be34-3629b241c4b9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178112869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.4
178112869
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.1174975998
Short name T1019
Test name
Test status
Simulation time 1045061141 ps
CPU time 11.59 seconds
Started Apr 30 12:28:34 PM PDT 24
Finished Apr 30 12:28:46 PM PDT 24
Peak memory 205872 kb
Host smart-711e4105-9a2c-4204-af72-03348a2644fa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174975998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.1
174975998
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.3103878325
Short name T934
Test name
Test status
Simulation time 59048466 ps
CPU time 1.14 seconds
Started Apr 30 12:28:43 PM PDT 24
Finished Apr 30 12:28:45 PM PDT 24
Peak memory 206040 kb
Host smart-eb743ec0-3488-4e87-8a69-6160643f02c8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103878325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.3
103878325
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.1079874414
Short name T1050
Test name
Test status
Simulation time 43241055 ps
CPU time 1.45 seconds
Started Apr 30 12:28:41 PM PDT 24
Finished Apr 30 12:28:43 PM PDT 24
Peak memory 214292 kb
Host smart-46af23ad-4939-47d2-804f-3d085571393d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079874414 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.1079874414
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.1206987960
Short name T974
Test name
Test status
Simulation time 13747913 ps
CPU time 1.04 seconds
Started Apr 30 12:28:32 PM PDT 24
Finished Apr 30 12:28:34 PM PDT 24
Peak memory 205784 kb
Host smart-607a4b61-cc94-45cc-ac71-1f519b930a79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206987960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.1206987960
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.3275845120
Short name T1018
Test name
Test status
Simulation time 13628639 ps
CPU time 0.9 seconds
Started Apr 30 12:28:48 PM PDT 24
Finished Apr 30 12:28:50 PM PDT 24
Peak memory 205716 kb
Host smart-4543abd6-431e-449a-8dff-7180c235755a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275845120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.3275845120
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.1371194660
Short name T1063
Test name
Test status
Simulation time 159886692 ps
CPU time 1.88 seconds
Started Apr 30 12:28:33 PM PDT 24
Finished Apr 30 12:28:35 PM PDT 24
Peak memory 206024 kb
Host smart-7f5b5e2e-375a-4e8c-9621-90c96f24abf5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371194660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.1371194660
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1375621997
Short name T1053
Test name
Test status
Simulation time 691066332 ps
CPU time 6.61 seconds
Started Apr 30 12:28:38 PM PDT 24
Finished Apr 30 12:28:46 PM PDT 24
Peak memory 214532 kb
Host smart-7e10e2c6-9bc2-466b-b42e-a0b4e70f6daa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375621997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.1375621997
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.592231144
Short name T1023
Test name
Test status
Simulation time 98907327 ps
CPU time 3.01 seconds
Started Apr 30 12:28:34 PM PDT 24
Finished Apr 30 12:28:37 PM PDT 24
Peak memory 217320 kb
Host smart-54c8d3bd-aa73-4103-9395-415ba189f2f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592231144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.592231144
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.3492447452
Short name T160
Test name
Test status
Simulation time 392975214 ps
CPU time 10.93 seconds
Started Apr 30 12:28:39 PM PDT 24
Finished Apr 30 12:28:51 PM PDT 24
Peak memory 214184 kb
Host smart-eff819a0-5b5e-412e-98e0-4ee50dbc8919
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492447452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.3492447452
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2573214560
Short name T1014
Test name
Test status
Simulation time 512244914 ps
CPU time 8.5 seconds
Started Apr 30 12:28:35 PM PDT 24
Finished Apr 30 12:28:44 PM PDT 24
Peak memory 206000 kb
Host smart-56a7d759-57b8-4272-9611-e02d27191336
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573214560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.2
573214560
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.947040173
Short name T1007
Test name
Test status
Simulation time 441374812 ps
CPU time 13.8 seconds
Started Apr 30 12:28:33 PM PDT 24
Finished Apr 30 12:28:47 PM PDT 24
Peak memory 205276 kb
Host smart-08d5fede-fe26-4cf4-b5ae-c91aa6cd4fdc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947040173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.947040173
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.4118710257
Short name T929
Test name
Test status
Simulation time 17440776 ps
CPU time 1.14 seconds
Started Apr 30 12:28:39 PM PDT 24
Finished Apr 30 12:28:41 PM PDT 24
Peak memory 205920 kb
Host smart-9a9f309e-a68e-4a8e-b693-c1e72a685c30
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118710257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.4
118710257
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.895309419
Short name T152
Test name
Test status
Simulation time 36659688 ps
CPU time 2.2 seconds
Started Apr 30 12:28:32 PM PDT 24
Finished Apr 30 12:28:34 PM PDT 24
Peak memory 214364 kb
Host smart-84ab19ce-8120-4da8-8765-ed2a47637b20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895309419 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.895309419
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.3430111137
Short name T928
Test name
Test status
Simulation time 37735374 ps
CPU time 1.6 seconds
Started Apr 30 12:28:40 PM PDT 24
Finished Apr 30 12:28:43 PM PDT 24
Peak memory 206300 kb
Host smart-71a5b1a9-c425-4cb4-9fe5-14bfd3100199
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430111137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.3430111137
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.56763074
Short name T955
Test name
Test status
Simulation time 8396889 ps
CPU time 0.7 seconds
Started Apr 30 12:28:34 PM PDT 24
Finished Apr 30 12:28:35 PM PDT 24
Peak memory 205772 kb
Host smart-bf7b42d3-d2a3-4d10-b034-5f92fdc4fd7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56763074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.56763074
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.2366738964
Short name T984
Test name
Test status
Simulation time 113853092 ps
CPU time 2.39 seconds
Started Apr 30 12:28:34 PM PDT 24
Finished Apr 30 12:28:37 PM PDT 24
Peak memory 206004 kb
Host smart-a955949d-af9e-4332-829e-0e80b2fe6879
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366738964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.2366738964
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.1000086528
Short name T1057
Test name
Test status
Simulation time 69005805 ps
CPU time 2.24 seconds
Started Apr 30 12:28:33 PM PDT 24
Finished Apr 30 12:28:36 PM PDT 24
Peak memory 219448 kb
Host smart-73d5fe6d-c089-4048-9e86-8efecd48dcd4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000086528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.1000086528
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.1056424552
Short name T116
Test name
Test status
Simulation time 209572967 ps
CPU time 5.01 seconds
Started Apr 30 12:28:32 PM PDT 24
Finished Apr 30 12:28:38 PM PDT 24
Peak memory 220480 kb
Host smart-ee576d55-40ea-42d2-8ad6-82b1fec7ef39
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056424552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.1056424552
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1590754554
Short name T997
Test name
Test status
Simulation time 142777623 ps
CPU time 3.6 seconds
Started Apr 30 12:28:35 PM PDT 24
Finished Apr 30 12:28:39 PM PDT 24
Peak memory 214272 kb
Host smart-a7c57c2a-f07e-4d6d-910c-42075320ce31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590754554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.1590754554
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.183030636
Short name T171
Test name
Test status
Simulation time 98900013 ps
CPU time 3.91 seconds
Started Apr 30 12:28:34 PM PDT 24
Finished Apr 30 12:28:38 PM PDT 24
Peak memory 209256 kb
Host smart-796a7516-438c-444b-8c8c-01ed86d80af4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183030636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.
183030636
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1909272566
Short name T1027
Test name
Test status
Simulation time 17829226 ps
CPU time 1.51 seconds
Started Apr 30 12:28:56 PM PDT 24
Finished Apr 30 12:28:58 PM PDT 24
Peak memory 214212 kb
Host smart-80313eef-f7ff-4472-9359-69a9bc7f13b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909272566 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.1909272566
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.1476359292
Short name T979
Test name
Test status
Simulation time 29762430 ps
CPU time 1.23 seconds
Started Apr 30 12:28:55 PM PDT 24
Finished Apr 30 12:28:57 PM PDT 24
Peak memory 205992 kb
Host smart-bdfd3a40-7b87-48f4-b0cc-5284ddc6679a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476359292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.1476359292
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.2809946100
Short name T1045
Test name
Test status
Simulation time 13176447 ps
CPU time 0.77 seconds
Started Apr 30 12:28:54 PM PDT 24
Finished Apr 30 12:28:56 PM PDT 24
Peak memory 205676 kb
Host smart-e67d3c6f-3932-4be0-9389-94e39d6ea684
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809946100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.2809946100
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2114951084
Short name T1047
Test name
Test status
Simulation time 37960517 ps
CPU time 2.16 seconds
Started Apr 30 12:29:01 PM PDT 24
Finished Apr 30 12:29:04 PM PDT 24
Peak memory 206068 kb
Host smart-60858d40-20bc-4cc1-ae18-3fdd2fcc8010
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114951084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.2114951084
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.207916571
Short name T961
Test name
Test status
Simulation time 1022005869 ps
CPU time 6.05 seconds
Started Apr 30 12:28:59 PM PDT 24
Finished Apr 30 12:29:06 PM PDT 24
Peak memory 223068 kb
Host smart-8815d818-1ab9-4346-be5d-812817ca9e3c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207916571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shado
w_reg_errors.207916571
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.608029513
Short name T120
Test name
Test status
Simulation time 161251529 ps
CPU time 6.82 seconds
Started Apr 30 12:29:00 PM PDT 24
Finished Apr 30 12:29:08 PM PDT 24
Peak memory 214592 kb
Host smart-4dff6585-ea90-4e5c-9c99-1a7cfd7858b8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608029513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
keymgr_shadow_reg_errors_with_csr_rw.608029513
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2343390031
Short name T1004
Test name
Test status
Simulation time 253817864 ps
CPU time 4.71 seconds
Started Apr 30 12:28:54 PM PDT 24
Finished Apr 30 12:28:59 PM PDT 24
Peak memory 217212 kb
Host smart-58230bfb-3832-4b52-93b9-405b87f90f5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343390031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.2343390031
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.1229821805
Short name T1001
Test name
Test status
Simulation time 60030489 ps
CPU time 2.18 seconds
Started Apr 30 12:28:57 PM PDT 24
Finished Apr 30 12:29:00 PM PDT 24
Peak memory 214184 kb
Host smart-80f93243-cc48-4065-a371-72e9fd376451
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229821805 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.1229821805
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.2738324985
Short name T916
Test name
Test status
Simulation time 56164976 ps
CPU time 0.93 seconds
Started Apr 30 12:28:56 PM PDT 24
Finished Apr 30 12:28:57 PM PDT 24
Peak memory 205804 kb
Host smart-ac0c2018-02d3-4f6c-a225-d60abd1beb1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738324985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.2738324985
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.1292991229
Short name T1044
Test name
Test status
Simulation time 34088312 ps
CPU time 0.79 seconds
Started Apr 30 12:28:58 PM PDT 24
Finished Apr 30 12:28:59 PM PDT 24
Peak memory 205844 kb
Host smart-dfee6785-9962-4d96-ac79-9076714af471
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292991229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.1292991229
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.535839945
Short name T950
Test name
Test status
Simulation time 231018083 ps
CPU time 2.53 seconds
Started Apr 30 12:28:57 PM PDT 24
Finished Apr 30 12:29:00 PM PDT 24
Peak memory 206080 kb
Host smart-78cd49d9-5298-4f20-b2c0-e067aaaa6666
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535839945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_sa
me_csr_outstanding.535839945
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.448677044
Short name T1061
Test name
Test status
Simulation time 1432289772 ps
CPU time 13.9 seconds
Started Apr 30 12:29:00 PM PDT 24
Finished Apr 30 12:29:15 PM PDT 24
Peak memory 214548 kb
Host smart-22534449-2423-45ca-979b-624a872f5cd5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448677044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shado
w_reg_errors.448677044
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3992720321
Short name T941
Test name
Test status
Simulation time 739671842 ps
CPU time 4.95 seconds
Started Apr 30 12:28:56 PM PDT 24
Finished Apr 30 12:29:02 PM PDT 24
Peak memory 220120 kb
Host smart-c6e6d910-2ace-4d91-b7c9-5a1d0e2ba82f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992720321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.3992720321
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.2265804
Short name T953
Test name
Test status
Simulation time 222847422 ps
CPU time 2.25 seconds
Started Apr 30 12:28:55 PM PDT 24
Finished Apr 30 12:28:58 PM PDT 24
Peak memory 214220 kb
Host smart-265d0558-1212-4163-b9cb-e0cb249f3c00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.2265804
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.892059600
Short name T1054
Test name
Test status
Simulation time 234617244 ps
CPU time 6.31 seconds
Started Apr 30 12:28:58 PM PDT 24
Finished Apr 30 12:29:05 PM PDT 24
Peak memory 214280 kb
Host smart-79c083dc-9883-4101-a165-d2da103493e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892059600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_err
.892059600
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.2428155993
Short name T993
Test name
Test status
Simulation time 107618068 ps
CPU time 1.51 seconds
Started Apr 30 12:28:59 PM PDT 24
Finished Apr 30 12:29:02 PM PDT 24
Peak memory 214240 kb
Host smart-4ec62dbe-5de7-415d-b9f6-126e98f6e8a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428155993 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.2428155993
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.1406222448
Short name T962
Test name
Test status
Simulation time 23201820 ps
CPU time 1.26 seconds
Started Apr 30 12:29:00 PM PDT 24
Finished Apr 30 12:29:03 PM PDT 24
Peak memory 205888 kb
Host smart-917df32d-d1db-40d5-81ca-1dbbe35f1871
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406222448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.1406222448
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.267374737
Short name T973
Test name
Test status
Simulation time 13719701 ps
CPU time 0.7 seconds
Started Apr 30 12:28:55 PM PDT 24
Finished Apr 30 12:28:56 PM PDT 24
Peak memory 205624 kb
Host smart-41f8f64b-d160-453b-8a89-63451e70e830
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267374737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.267374737
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.2804374565
Short name T1026
Test name
Test status
Simulation time 195232233 ps
CPU time 2.46 seconds
Started Apr 30 12:28:59 PM PDT 24
Finished Apr 30 12:29:02 PM PDT 24
Peak memory 206120 kb
Host smart-3eb0d3be-48f8-42f1-8c9e-51009a14702c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804374565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.2804374565
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.3423252191
Short name T967
Test name
Test status
Simulation time 36106932 ps
CPU time 1.77 seconds
Started Apr 30 12:28:56 PM PDT 24
Finished Apr 30 12:28:59 PM PDT 24
Peak memory 214452 kb
Host smart-b24d8126-02b1-4c29-8732-f1fb118e052f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423252191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.3423252191
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.2682377839
Short name T957
Test name
Test status
Simulation time 433732296 ps
CPU time 14.69 seconds
Started Apr 30 12:28:55 PM PDT 24
Finished Apr 30 12:29:10 PM PDT 24
Peak memory 214564 kb
Host smart-9a65d600-9dac-4301-9e90-2df09262e4c9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682377839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.2682377839
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.2442253226
Short name T1048
Test name
Test status
Simulation time 154673982 ps
CPU time 3.79 seconds
Started Apr 30 12:29:01 PM PDT 24
Finished Apr 30 12:29:06 PM PDT 24
Peak memory 214136 kb
Host smart-656f44f6-e79d-427c-8061-a463a3718505
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442253226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.2442253226
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.37073304
Short name T162
Test name
Test status
Simulation time 351379776 ps
CPU time 11.56 seconds
Started Apr 30 12:29:00 PM PDT 24
Finished Apr 30 12:29:13 PM PDT 24
Peak memory 222372 kb
Host smart-06633a6c-130d-4d85-a057-921529f85b75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37073304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_err.37073304
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.895558876
Short name T921
Test name
Test status
Simulation time 146395843 ps
CPU time 2.61 seconds
Started Apr 30 12:28:59 PM PDT 24
Finished Apr 30 12:29:03 PM PDT 24
Peak memory 214328 kb
Host smart-6f2581cb-0554-4d55-8147-a5cdce5ac9c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895558876 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.895558876
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.4003644184
Short name T925
Test name
Test status
Simulation time 36747753 ps
CPU time 0.89 seconds
Started Apr 30 12:28:57 PM PDT 24
Finished Apr 30 12:28:58 PM PDT 24
Peak memory 205752 kb
Host smart-5a5acfe1-7f70-4870-b844-460ef1b5f7aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003644184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.4003644184
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3128925756
Short name T956
Test name
Test status
Simulation time 21181104 ps
CPU time 0.7 seconds
Started Apr 30 12:29:04 PM PDT 24
Finished Apr 30 12:29:06 PM PDT 24
Peak memory 205712 kb
Host smart-4cd85678-1723-4e63-ba57-b772f77549d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128925756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.3128925756
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2978831628
Short name T148
Test name
Test status
Simulation time 101516133 ps
CPU time 3.84 seconds
Started Apr 30 12:28:57 PM PDT 24
Finished Apr 30 12:29:02 PM PDT 24
Peak memory 205972 kb
Host smart-ae6c558f-412a-4544-88af-fec4def1902c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978831628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.2978831628
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2954864558
Short name T1020
Test name
Test status
Simulation time 217110633 ps
CPU time 5.59 seconds
Started Apr 30 12:29:00 PM PDT 24
Finished Apr 30 12:29:06 PM PDT 24
Peak memory 214568 kb
Host smart-81d85be4-1f9a-4468-8caa-26d108768620
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954864558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.2954864558
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3786625787
Short name T963
Test name
Test status
Simulation time 339616213 ps
CPU time 4.91 seconds
Started Apr 30 12:29:00 PM PDT 24
Finished Apr 30 12:29:07 PM PDT 24
Peak memory 214512 kb
Host smart-c6d81518-2a33-422c-b0ff-dea2339ee94b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786625787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.3786625787
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.3511548699
Short name T982
Test name
Test status
Simulation time 298319581 ps
CPU time 5.56 seconds
Started Apr 30 12:29:00 PM PDT 24
Finished Apr 30 12:29:07 PM PDT 24
Peak memory 214224 kb
Host smart-9a49c325-4b3c-477e-84ac-d372896995d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511548699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.3511548699
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.694337613
Short name T172
Test name
Test status
Simulation time 456659744 ps
CPU time 6.66 seconds
Started Apr 30 12:28:58 PM PDT 24
Finished Apr 30 12:29:05 PM PDT 24
Peak memory 214340 kb
Host smart-6b775fce-2a04-4a72-ba30-f173578b623a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694337613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err
.694337613
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2868787412
Short name T940
Test name
Test status
Simulation time 37328099 ps
CPU time 1.35 seconds
Started Apr 30 12:29:03 PM PDT 24
Finished Apr 30 12:29:05 PM PDT 24
Peak memory 214260 kb
Host smart-004e5034-be79-4bfa-8050-b3b79c26448b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868787412 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.2868787412
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.73754294
Short name T939
Test name
Test status
Simulation time 47410863 ps
CPU time 1.39 seconds
Started Apr 30 12:29:04 PM PDT 24
Finished Apr 30 12:29:07 PM PDT 24
Peak memory 205932 kb
Host smart-ff26fa95-f898-4785-adb5-4ffa185919b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73754294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.73754294
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.3541303353
Short name T994
Test name
Test status
Simulation time 17822120 ps
CPU time 0.89 seconds
Started Apr 30 12:29:00 PM PDT 24
Finished Apr 30 12:29:02 PM PDT 24
Peak memory 205764 kb
Host smart-ed078f0c-a370-444c-934d-d43702640e5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541303353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.3541303353
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.2650245958
Short name T945
Test name
Test status
Simulation time 71410055 ps
CPU time 1.37 seconds
Started Apr 30 12:29:01 PM PDT 24
Finished Apr 30 12:29:04 PM PDT 24
Peak memory 206136 kb
Host smart-b3999865-4148-4b9e-88af-6ed09e03321f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650245958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.2650245958
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.297641907
Short name T937
Test name
Test status
Simulation time 993340171 ps
CPU time 17 seconds
Started Apr 30 12:29:01 PM PDT 24
Finished Apr 30 12:29:19 PM PDT 24
Peak memory 214896 kb
Host smart-79a9e7ee-2f5c-46f0-b418-f3268c30aa15
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297641907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shado
w_reg_errors.297641907
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1513870506
Short name T946
Test name
Test status
Simulation time 168969730 ps
CPU time 6.59 seconds
Started Apr 30 12:29:01 PM PDT 24
Finished Apr 30 12:29:09 PM PDT 24
Peak memory 220552 kb
Host smart-d4608861-d443-40b8-a2c7-427809a0da8f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513870506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.1513870506
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.888957439
Short name T1009
Test name
Test status
Simulation time 46470882 ps
CPU time 2.19 seconds
Started Apr 30 12:29:00 PM PDT 24
Finished Apr 30 12:29:03 PM PDT 24
Peak memory 217464 kb
Host smart-309c0234-120b-4dcd-8a38-0e058e106655
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888957439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.888957439
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1225401090
Short name T989
Test name
Test status
Simulation time 77460858 ps
CPU time 1.52 seconds
Started Apr 30 12:29:04 PM PDT 24
Finished Apr 30 12:29:07 PM PDT 24
Peak memory 206132 kb
Host smart-1ba581d7-ace2-4ef8-89a0-c89cdb3b8a1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225401090 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.1225401090
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.4241295464
Short name T1046
Test name
Test status
Simulation time 29382312 ps
CPU time 1.56 seconds
Started Apr 30 12:29:03 PM PDT 24
Finished Apr 30 12:29:05 PM PDT 24
Peak memory 206036 kb
Host smart-cc37f63c-9b57-47d8-873f-490c8619cece
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241295464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.4241295464
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.398169450
Short name T942
Test name
Test status
Simulation time 34986900 ps
CPU time 0.71 seconds
Started Apr 30 12:28:59 PM PDT 24
Finished Apr 30 12:29:00 PM PDT 24
Peak memory 205716 kb
Host smart-e18f03c9-63c3-4fef-a7ff-1e34e58c1cdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398169450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.398169450
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3369391630
Short name T930
Test name
Test status
Simulation time 862395397 ps
CPU time 4.5 seconds
Started Apr 30 12:29:03 PM PDT 24
Finished Apr 30 12:29:08 PM PDT 24
Peak memory 206064 kb
Host smart-81006c04-7cae-4011-afe0-31a2e18cb95f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369391630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.3369391630
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.280355552
Short name T115
Test name
Test status
Simulation time 106701089 ps
CPU time 3.63 seconds
Started Apr 30 12:29:04 PM PDT 24
Finished Apr 30 12:29:09 PM PDT 24
Peak memory 214708 kb
Host smart-8a9535ce-4759-4df9-ae5f-60e025cea5b3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280355552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shado
w_reg_errors.280355552
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.3351735277
Short name T971
Test name
Test status
Simulation time 1283000560 ps
CPU time 8 seconds
Started Apr 30 12:29:02 PM PDT 24
Finished Apr 30 12:29:11 PM PDT 24
Peak memory 220604 kb
Host smart-0f3d314c-590f-4f6f-865c-ad3561c21742
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351735277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.3351735277
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.2647065124
Short name T1068
Test name
Test status
Simulation time 213991295 ps
CPU time 2.58 seconds
Started Apr 30 12:29:01 PM PDT 24
Finished Apr 30 12:29:05 PM PDT 24
Peak memory 214256 kb
Host smart-7835fc5b-fe51-4b00-81f5-dad74cc28777
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647065124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.2647065124
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.1578554083
Short name T927
Test name
Test status
Simulation time 16085758 ps
CPU time 1.26 seconds
Started Apr 30 12:29:07 PM PDT 24
Finished Apr 30 12:29:09 PM PDT 24
Peak memory 205940 kb
Host smart-ab6bda0e-5f50-4cc5-a86c-2bb431aa0918
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578554083 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.1578554083
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.2285471251
Short name T924
Test name
Test status
Simulation time 93551252 ps
CPU time 1.48 seconds
Started Apr 30 12:29:11 PM PDT 24
Finished Apr 30 12:29:13 PM PDT 24
Peak memory 205924 kb
Host smart-59bb386c-1a18-4008-9511-574a0cb56dd5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285471251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.2285471251
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3143821413
Short name T910
Test name
Test status
Simulation time 42675367 ps
CPU time 0.82 seconds
Started Apr 30 12:29:05 PM PDT 24
Finished Apr 30 12:29:06 PM PDT 24
Peak memory 205864 kb
Host smart-af045749-6948-48eb-b4ba-bb8eb11d1a4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143821413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.3143821413
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.3540203354
Short name T959
Test name
Test status
Simulation time 876466165 ps
CPU time 2.59 seconds
Started Apr 30 12:29:18 PM PDT 24
Finished Apr 30 12:29:21 PM PDT 24
Peak memory 206112 kb
Host smart-2f921989-550e-4224-aa67-c1c5f85adc1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540203354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.3540203354
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.977059768
Short name T1049
Test name
Test status
Simulation time 481620776 ps
CPU time 5.05 seconds
Started Apr 30 12:29:04 PM PDT 24
Finished Apr 30 12:29:10 PM PDT 24
Peak memory 214484 kb
Host smart-1415d4d6-a914-4909-b960-44df3941a90b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977059768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shado
w_reg_errors.977059768
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.769240007
Short name T960
Test name
Test status
Simulation time 285087047 ps
CPU time 4.6 seconds
Started Apr 30 12:29:04 PM PDT 24
Finished Apr 30 12:29:09 PM PDT 24
Peak memory 214628 kb
Host smart-ea0fc5a5-d237-4973-9673-d7bbbdd45aab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769240007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
keymgr_shadow_reg_errors_with_csr_rw.769240007
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.2459705418
Short name T920
Test name
Test status
Simulation time 61702869 ps
CPU time 1.93 seconds
Started Apr 30 12:29:00 PM PDT 24
Finished Apr 30 12:29:03 PM PDT 24
Peak memory 216716 kb
Host smart-74cdc6e5-5120-4745-8052-86415b9a1ccb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459705418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.2459705418
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.1640077412
Short name T166
Test name
Test status
Simulation time 799225040 ps
CPU time 9.81 seconds
Started Apr 30 12:29:03 PM PDT 24
Finished Apr 30 12:29:14 PM PDT 24
Peak memory 209176 kb
Host smart-1791b237-1a2e-4551-83fb-a254dcbb14d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640077412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.1640077412
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.2761176802
Short name T918
Test name
Test status
Simulation time 49541209 ps
CPU time 0.83 seconds
Started Apr 30 12:29:11 PM PDT 24
Finished Apr 30 12:29:13 PM PDT 24
Peak memory 205832 kb
Host smart-f7ffdd76-49c4-486a-81d5-12c70952edd8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761176802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.2761176802
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.409040786
Short name T1066
Test name
Test status
Simulation time 12062030 ps
CPU time 0.72 seconds
Started Apr 30 12:29:11 PM PDT 24
Finished Apr 30 12:29:12 PM PDT 24
Peak memory 205780 kb
Host smart-b6ff8e63-f98e-4ada-9057-3d97ded3e4ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409040786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.409040786
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3752517055
Short name T146
Test name
Test status
Simulation time 66753538 ps
CPU time 2.17 seconds
Started Apr 30 12:29:07 PM PDT 24
Finished Apr 30 12:29:10 PM PDT 24
Peak memory 206076 kb
Host smart-1d68a6d6-f787-4e00-9bbf-4fc40b474843
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752517055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.3752517055
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.1021818883
Short name T965
Test name
Test status
Simulation time 49206236 ps
CPU time 2.1 seconds
Started Apr 30 12:29:08 PM PDT 24
Finished Apr 30 12:29:11 PM PDT 24
Peak memory 214588 kb
Host smart-ccbfd721-a97d-4807-81ff-b3c2f2a690dc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021818883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.1021818883
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.3218131065
Short name T972
Test name
Test status
Simulation time 1401107548 ps
CPU time 13.39 seconds
Started Apr 30 12:29:07 PM PDT 24
Finished Apr 30 12:29:21 PM PDT 24
Peak memory 214452 kb
Host smart-de9b4e03-e5be-4708-aef3-90b1ff19a71f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218131065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.3218131065
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.527800240
Short name T923
Test name
Test status
Simulation time 171113194 ps
CPU time 2.89 seconds
Started Apr 30 12:29:09 PM PDT 24
Finished Apr 30 12:29:13 PM PDT 24
Peak memory 214132 kb
Host smart-5999cd26-1287-4381-86c5-1930fa36bb08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527800240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.527800240
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.2487298508
Short name T168
Test name
Test status
Simulation time 5287279609 ps
CPU time 10.67 seconds
Started Apr 30 12:29:07 PM PDT 24
Finished Apr 30 12:29:18 PM PDT 24
Peak memory 209660 kb
Host smart-13465259-bce2-46d1-891b-7ca61e5a6ed8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487298508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.2487298508
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.3660495184
Short name T944
Test name
Test status
Simulation time 389308004 ps
CPU time 2.42 seconds
Started Apr 30 12:29:09 PM PDT 24
Finished Apr 30 12:29:12 PM PDT 24
Peak memory 214340 kb
Host smart-9216f02e-c0bc-445d-a0bc-70fc0fadd5f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660495184 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.3660495184
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.846565541
Short name T145
Test name
Test status
Simulation time 26006319 ps
CPU time 1.13 seconds
Started Apr 30 12:29:07 PM PDT 24
Finished Apr 30 12:29:09 PM PDT 24
Peak memory 206004 kb
Host smart-7de587c7-0176-46a0-a4a6-d32e9388e614
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846565541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.846565541
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.4080904737
Short name T922
Test name
Test status
Simulation time 52420902 ps
CPU time 0.88 seconds
Started Apr 30 12:29:08 PM PDT 24
Finished Apr 30 12:29:10 PM PDT 24
Peak memory 205916 kb
Host smart-0b4c1dc0-4479-4322-8d53-4ea9701379ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080904737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.4080904737
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.961342271
Short name T1043
Test name
Test status
Simulation time 90372671 ps
CPU time 2.42 seconds
Started Apr 30 12:29:07 PM PDT 24
Finished Apr 30 12:29:10 PM PDT 24
Peak memory 206044 kb
Host smart-5ec7f5e2-47f0-4b7c-85c4-9d404fcdf530
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961342271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_sa
me_csr_outstanding.961342271
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.2524944686
Short name T1012
Test name
Test status
Simulation time 382225403 ps
CPU time 4.73 seconds
Started Apr 30 12:29:09 PM PDT 24
Finished Apr 30 12:29:14 PM PDT 24
Peak memory 214600 kb
Host smart-7eb70b47-4276-4a25-bdd8-6f70fb042c88
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524944686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.2524944686
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.1616102754
Short name T1016
Test name
Test status
Simulation time 1020158717 ps
CPU time 7.18 seconds
Started Apr 30 12:29:08 PM PDT 24
Finished Apr 30 12:29:16 PM PDT 24
Peak memory 214684 kb
Host smart-79d2964f-7a53-4651-931a-259bef6b1903
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616102754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.1616102754
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.3123422430
Short name T936
Test name
Test status
Simulation time 540676306 ps
CPU time 4.66 seconds
Started Apr 30 12:29:09 PM PDT 24
Finished Apr 30 12:29:15 PM PDT 24
Peak memory 214260 kb
Host smart-cc804989-2f3f-4ca1-96f1-460eda4a974a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123422430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.3123422430
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1437757786
Short name T949
Test name
Test status
Simulation time 191409244 ps
CPU time 2.14 seconds
Started Apr 30 12:29:14 PM PDT 24
Finished Apr 30 12:29:17 PM PDT 24
Peak memory 214372 kb
Host smart-cf460fd2-6449-4802-abb8-88e868330c45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437757786 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.1437757786
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.628480487
Short name T157
Test name
Test status
Simulation time 291086016 ps
CPU time 1.37 seconds
Started Apr 30 12:29:19 PM PDT 24
Finished Apr 30 12:29:21 PM PDT 24
Peak memory 206040 kb
Host smart-65faba43-298b-4830-9eed-9f9df1754af8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628480487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.628480487
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.1995504468
Short name T983
Test name
Test status
Simulation time 16039844 ps
CPU time 0.7 seconds
Started Apr 30 12:29:16 PM PDT 24
Finished Apr 30 12:29:18 PM PDT 24
Peak memory 205764 kb
Host smart-8ae973f2-6029-4386-a4ce-840d47910ea1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995504468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.1995504468
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.2704189173
Short name T1000
Test name
Test status
Simulation time 19366940 ps
CPU time 1.44 seconds
Started Apr 30 12:29:15 PM PDT 24
Finished Apr 30 12:29:18 PM PDT 24
Peak memory 206216 kb
Host smart-13697e28-2a76-47e4-90e2-a8628d757ed9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704189173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.2704189173
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2121606044
Short name T1038
Test name
Test status
Simulation time 179949861 ps
CPU time 4.52 seconds
Started Apr 30 12:29:14 PM PDT 24
Finished Apr 30 12:29:20 PM PDT 24
Peak memory 214480 kb
Host smart-4e6e80fc-937e-4cea-ae70-a657270b4f7f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121606044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.2121606044
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.3836648840
Short name T912
Test name
Test status
Simulation time 40803999 ps
CPU time 1.47 seconds
Started Apr 30 12:29:14 PM PDT 24
Finished Apr 30 12:29:16 PM PDT 24
Peak memory 214084 kb
Host smart-60657f39-87d2-4a47-af78-d0fd5edb9980
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836648840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.3836648840
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.1532373533
Short name T163
Test name
Test status
Simulation time 1076951802 ps
CPU time 16.8 seconds
Started Apr 30 12:29:16 PM PDT 24
Finished Apr 30 12:29:34 PM PDT 24
Peak memory 214208 kb
Host smart-c18d4198-6203-4667-9f51-1aad7fa3d6ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532373533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.1532373533
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3642804938
Short name T1059
Test name
Test status
Simulation time 1905161373 ps
CPU time 14.45 seconds
Started Apr 30 12:28:51 PM PDT 24
Finished Apr 30 12:29:07 PM PDT 24
Peak memory 205976 kb
Host smart-86df44df-669f-4315-8f21-5dd71454fb77
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642804938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.3
642804938
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.2917098497
Short name T1025
Test name
Test status
Simulation time 449379818 ps
CPU time 9.07 seconds
Started Apr 30 12:28:49 PM PDT 24
Finished Apr 30 12:28:59 PM PDT 24
Peak memory 205972 kb
Host smart-b7b5c304-aae5-4ec7-a509-2a1014d6cc0e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917098497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.2
917098497
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1374185705
Short name T1032
Test name
Test status
Simulation time 44746833 ps
CPU time 0.97 seconds
Started Apr 30 12:28:44 PM PDT 24
Finished Apr 30 12:28:45 PM PDT 24
Peak memory 205760 kb
Host smart-defc5952-b4c6-42f3-b1c4-40e2da3d585b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374185705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.1
374185705
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.3780044065
Short name T380
Test name
Test status
Simulation time 59323068 ps
CPU time 2.07 seconds
Started Apr 30 12:28:47 PM PDT 24
Finished Apr 30 12:28:50 PM PDT 24
Peak memory 214408 kb
Host smart-fd9faf84-7aa8-4de2-9c6e-101eeb4bc14f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780044065 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.3780044065
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.55105415
Short name T144
Test name
Test status
Simulation time 56552625 ps
CPU time 1.13 seconds
Started Apr 30 12:28:51 PM PDT 24
Finished Apr 30 12:28:53 PM PDT 24
Peak memory 205840 kb
Host smart-e20a645e-62e5-452f-b497-c56db4794dd8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55105415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.55105415
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.212330245
Short name T1052
Test name
Test status
Simulation time 9393433 ps
CPU time 0.8 seconds
Started Apr 30 12:28:34 PM PDT 24
Finished Apr 30 12:28:35 PM PDT 24
Peak memory 205716 kb
Host smart-9396b999-479c-49b1-9acc-a8ef3ef845a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212330245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.212330245
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.4134176681
Short name T1042
Test name
Test status
Simulation time 69490355 ps
CPU time 1.41 seconds
Started Apr 30 12:28:39 PM PDT 24
Finished Apr 30 12:28:41 PM PDT 24
Peak memory 205896 kb
Host smart-7de12b2f-b885-4349-98b5-f69a5df01c3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134176681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.4134176681
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.2118673850
Short name T1040
Test name
Test status
Simulation time 1929586409 ps
CPU time 5.75 seconds
Started Apr 30 12:28:33 PM PDT 24
Finished Apr 30 12:28:39 PM PDT 24
Peak memory 214384 kb
Host smart-127dab16-dd6b-4eea-b591-9906dfd371fd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118673850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.2118673850
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.3633106028
Short name T1051
Test name
Test status
Simulation time 273945557 ps
CPU time 3.8 seconds
Started Apr 30 12:28:40 PM PDT 24
Finished Apr 30 12:28:44 PM PDT 24
Peak memory 214516 kb
Host smart-47ad0f1f-ec5b-4e96-8a60-d33a449f8e8e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633106028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.3633106028
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.1663921886
Short name T978
Test name
Test status
Simulation time 189981912 ps
CPU time 2.21 seconds
Started Apr 30 12:28:34 PM PDT 24
Finished Apr 30 12:28:37 PM PDT 24
Peak memory 214312 kb
Host smart-7d2f67fa-bbf7-4768-92cb-9afa9b341736
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663921886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.1663921886
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.220466275
Short name T169
Test name
Test status
Simulation time 331854012 ps
CPU time 3.16 seconds
Started Apr 30 12:28:33 PM PDT 24
Finished Apr 30 12:28:37 PM PDT 24
Peak memory 214128 kb
Host smart-fd2e68be-7527-4bad-8a95-8e47386e66c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220466275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err.
220466275
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.2650609629
Short name T998
Test name
Test status
Simulation time 42507017 ps
CPU time 0.73 seconds
Started Apr 30 12:29:20 PM PDT 24
Finished Apr 30 12:29:21 PM PDT 24
Peak memory 205732 kb
Host smart-aabc1d42-7605-4c12-9fd5-58fb5df4444a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650609629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.2650609629
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.2002088083
Short name T981
Test name
Test status
Simulation time 56499550 ps
CPU time 0.89 seconds
Started Apr 30 12:29:16 PM PDT 24
Finished Apr 30 12:29:18 PM PDT 24
Peak memory 205700 kb
Host smart-0746bf83-4d51-4ee1-a243-439af8d26edd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002088083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.2002088083
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2326416967
Short name T911
Test name
Test status
Simulation time 15705629 ps
CPU time 0.82 seconds
Started Apr 30 12:29:16 PM PDT 24
Finished Apr 30 12:29:18 PM PDT 24
Peak memory 205660 kb
Host smart-34449db8-4b55-4c92-a746-389da33887af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326416967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.2326416967
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.302127201
Short name T913
Test name
Test status
Simulation time 173212231 ps
CPU time 0.85 seconds
Started Apr 30 12:29:15 PM PDT 24
Finished Apr 30 12:29:16 PM PDT 24
Peak memory 205760 kb
Host smart-6c6bd0de-969c-4bee-af16-4eaa06ceb439
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302127201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.302127201
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.956049460
Short name T980
Test name
Test status
Simulation time 11334625 ps
CPU time 0.72 seconds
Started Apr 30 12:29:15 PM PDT 24
Finished Apr 30 12:29:16 PM PDT 24
Peak memory 205736 kb
Host smart-af0acf79-a5c9-496d-beac-01e5bd8cca56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956049460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.956049460
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.852578508
Short name T909
Test name
Test status
Simulation time 52123849 ps
CPU time 0.8 seconds
Started Apr 30 12:29:16 PM PDT 24
Finished Apr 30 12:29:18 PM PDT 24
Peak memory 205732 kb
Host smart-4b9fc258-9fcb-4c19-8c18-6fa362ead7db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852578508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.852578508
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.2165262840
Short name T1055
Test name
Test status
Simulation time 29892694 ps
CPU time 0.74 seconds
Started Apr 30 12:29:16 PM PDT 24
Finished Apr 30 12:29:18 PM PDT 24
Peak memory 205776 kb
Host smart-259c38d3-715b-4e25-b302-06204974f68d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165262840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.2165262840
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.3138917069
Short name T1062
Test name
Test status
Simulation time 28139830 ps
CPU time 0.75 seconds
Started Apr 30 12:29:19 PM PDT 24
Finished Apr 30 12:29:20 PM PDT 24
Peak memory 205732 kb
Host smart-ef1a634e-3e14-435d-9b69-920ea6b57c70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138917069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.3138917069
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.2955443078
Short name T1017
Test name
Test status
Simulation time 17421100 ps
CPU time 0.88 seconds
Started Apr 30 12:29:16 PM PDT 24
Finished Apr 30 12:29:17 PM PDT 24
Peak memory 205796 kb
Host smart-95b59e83-4e96-4147-adbe-0669afd92612
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955443078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.2955443078
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.712120719
Short name T1008
Test name
Test status
Simulation time 44552092 ps
CPU time 0.77 seconds
Started Apr 30 12:29:20 PM PDT 24
Finished Apr 30 12:29:21 PM PDT 24
Peak memory 205812 kb
Host smart-a4fa83ad-e24b-4866-a7de-9eb7c1aa5af9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712120719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.712120719
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.4076282115
Short name T1041
Test name
Test status
Simulation time 1503406268 ps
CPU time 11.9 seconds
Started Apr 30 12:28:45 PM PDT 24
Finished Apr 30 12:28:58 PM PDT 24
Peak memory 205908 kb
Host smart-47930948-d55b-4af5-8669-ba081338b023
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076282115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.4
076282115
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.697375917
Short name T933
Test name
Test status
Simulation time 138664632 ps
CPU time 6.27 seconds
Started Apr 30 12:28:46 PM PDT 24
Finished Apr 30 12:28:53 PM PDT 24
Peak memory 205868 kb
Host smart-8fac1cfc-82d3-4308-a583-503352af5338
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697375917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.697375917
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.769073802
Short name T1037
Test name
Test status
Simulation time 81928473 ps
CPU time 1.02 seconds
Started Apr 30 12:28:40 PM PDT 24
Finished Apr 30 12:28:41 PM PDT 24
Peak memory 205828 kb
Host smart-b1f01755-f4fe-4146-90f7-ef1eab1dd67e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769073802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.769073802
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.3074235411
Short name T1024
Test name
Test status
Simulation time 28464458 ps
CPU time 1.5 seconds
Started Apr 30 12:28:45 PM PDT 24
Finished Apr 30 12:28:47 PM PDT 24
Peak memory 214080 kb
Host smart-bd9a3ac8-68f0-4231-b276-bf5f479453ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074235411 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.3074235411
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.2804522720
Short name T143
Test name
Test status
Simulation time 27162881 ps
CPU time 1.1 seconds
Started Apr 30 12:28:49 PM PDT 24
Finished Apr 30 12:28:51 PM PDT 24
Peak memory 205888 kb
Host smart-831b883d-11bb-4bda-ae68-8ad608f753a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804522720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.2804522720
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.3238958055
Short name T996
Test name
Test status
Simulation time 18203206 ps
CPU time 0.71 seconds
Started Apr 30 12:28:39 PM PDT 24
Finished Apr 30 12:28:40 PM PDT 24
Peak memory 205652 kb
Host smart-d4854ae9-b4a5-484e-aff0-dcadde5a4e89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238958055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.3238958055
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.954112
Short name T1058
Test name
Test status
Simulation time 47541186 ps
CPU time 2.04 seconds
Started Apr 30 12:28:47 PM PDT 24
Finished Apr 30 12:28:50 PM PDT 24
Peak memory 206088 kb
Host smart-96019a81-80fa-45ca-b3b3-3bd96ba4df71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_same_c
sr_outstanding.954112
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1732519991
Short name T1036
Test name
Test status
Simulation time 120363168 ps
CPU time 3 seconds
Started Apr 30 12:28:51 PM PDT 24
Finished Apr 30 12:28:55 PM PDT 24
Peak memory 214508 kb
Host smart-b0cedb30-a453-4ce7-9c36-642cfdc30fe1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732519991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.1732519991
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1685594996
Short name T123
Test name
Test status
Simulation time 361954356 ps
CPU time 4.85 seconds
Started Apr 30 12:28:42 PM PDT 24
Finished Apr 30 12:28:47 PM PDT 24
Peak memory 214512 kb
Host smart-a5aa517b-5971-4184-8d0a-9924c4cab1f3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685594996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.1685594996
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.669072551
Short name T1064
Test name
Test status
Simulation time 85571362 ps
CPU time 2.06 seconds
Started Apr 30 12:28:48 PM PDT 24
Finished Apr 30 12:28:51 PM PDT 24
Peak memory 214208 kb
Host smart-50ff08f3-df40-4491-a0ea-a6d72590cdd6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669072551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.669072551
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.3993739345
Short name T951
Test name
Test status
Simulation time 36621453 ps
CPU time 0.87 seconds
Started Apr 30 12:29:14 PM PDT 24
Finished Apr 30 12:29:15 PM PDT 24
Peak memory 205664 kb
Host smart-09b1c1fa-e5e5-4836-b0ef-7a12db1ea6fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993739345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.3993739345
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.4238305783
Short name T947
Test name
Test status
Simulation time 200351739 ps
CPU time 0.87 seconds
Started Apr 30 12:29:14 PM PDT 24
Finished Apr 30 12:29:15 PM PDT 24
Peak memory 205756 kb
Host smart-35cbb354-1338-485a-85a9-6bbd97c868a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238305783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.4238305783
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.3826233858
Short name T1030
Test name
Test status
Simulation time 10187792 ps
CPU time 0.78 seconds
Started Apr 30 12:29:15 PM PDT 24
Finished Apr 30 12:29:16 PM PDT 24
Peak memory 205748 kb
Host smart-d3979c96-b9f0-43a2-9837-e7ed5d62458c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826233858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.3826233858
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.334405505
Short name T926
Test name
Test status
Simulation time 10723227 ps
CPU time 0.74 seconds
Started Apr 30 12:29:16 PM PDT 24
Finished Apr 30 12:29:18 PM PDT 24
Peak memory 205780 kb
Host smart-2caefb01-5ddb-4573-8c8d-ffd1f589cb34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334405505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.334405505
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.560131135
Short name T1033
Test name
Test status
Simulation time 7853788 ps
CPU time 0.77 seconds
Started Apr 30 12:29:15 PM PDT 24
Finished Apr 30 12:29:17 PM PDT 24
Peak memory 205644 kb
Host smart-65fab497-63b2-4be0-a950-f5f2055d110b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560131135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.560131135
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.2121667216
Short name T958
Test name
Test status
Simulation time 41357505 ps
CPU time 0.91 seconds
Started Apr 30 12:29:15 PM PDT 24
Finished Apr 30 12:29:17 PM PDT 24
Peak memory 205624 kb
Host smart-c08ab051-a747-47de-ba1c-77c1b3b6ebae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121667216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.2121667216
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.1076500608
Short name T919
Test name
Test status
Simulation time 30833774 ps
CPU time 0.76 seconds
Started Apr 30 12:29:17 PM PDT 24
Finished Apr 30 12:29:18 PM PDT 24
Peak memory 205732 kb
Host smart-d379f25e-0c9d-4947-a5f3-bdf7a92a3a17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076500608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.1076500608
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.1128676001
Short name T968
Test name
Test status
Simulation time 13936109 ps
CPU time 0.89 seconds
Started Apr 30 12:29:15 PM PDT 24
Finished Apr 30 12:29:17 PM PDT 24
Peak memory 205856 kb
Host smart-9aa8af1c-a6c1-447d-a950-3cb7383f5377
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128676001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.1128676001
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.494656582
Short name T915
Test name
Test status
Simulation time 10903450 ps
CPU time 0.82 seconds
Started Apr 30 12:29:16 PM PDT 24
Finished Apr 30 12:29:18 PM PDT 24
Peak memory 205756 kb
Host smart-67846f70-507d-4951-b9fd-fb57f31a3626
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494656582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.494656582
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.3302922817
Short name T986
Test name
Test status
Simulation time 10783113 ps
CPU time 0.75 seconds
Started Apr 30 12:29:16 PM PDT 24
Finished Apr 30 12:29:18 PM PDT 24
Peak memory 205736 kb
Host smart-e727dd75-31cf-4f60-9404-405444d37fdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302922817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.3302922817
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.1047652186
Short name T985
Test name
Test status
Simulation time 65457442 ps
CPU time 4.1 seconds
Started Apr 30 12:28:45 PM PDT 24
Finished Apr 30 12:28:50 PM PDT 24
Peak memory 205980 kb
Host smart-d884237a-9d3a-4149-af76-3be4c96166d3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047652186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.1
047652186
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2103015117
Short name T1010
Test name
Test status
Simulation time 858648853 ps
CPU time 19.67 seconds
Started Apr 30 12:28:48 PM PDT 24
Finished Apr 30 12:29:09 PM PDT 24
Peak memory 206000 kb
Host smart-9418ce54-c6aa-43f3-a3ef-bcea3dffef89
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103015117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.2
103015117
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.2557305755
Short name T1003
Test name
Test status
Simulation time 96229650 ps
CPU time 1 seconds
Started Apr 30 12:28:45 PM PDT 24
Finished Apr 30 12:28:46 PM PDT 24
Peak memory 205808 kb
Host smart-be1548f9-fc34-4f2c-a19e-2accec9acd7f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557305755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.2
557305755
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.4171671585
Short name T1031
Test name
Test status
Simulation time 28155853 ps
CPU time 1.88 seconds
Started Apr 30 12:28:41 PM PDT 24
Finished Apr 30 12:28:44 PM PDT 24
Peak memory 206052 kb
Host smart-0ccbdab2-2fc5-4628-9f27-21db0e8a769b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171671585 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.4171671585
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.3409984184
Short name T988
Test name
Test status
Simulation time 28916705 ps
CPU time 0.93 seconds
Started Apr 30 12:28:43 PM PDT 24
Finished Apr 30 12:28:44 PM PDT 24
Peak memory 205780 kb
Host smart-8d1aa4eb-6b6d-4799-9f1d-2348c233139b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409984184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.3409984184
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.2371505709
Short name T1056
Test name
Test status
Simulation time 17938243 ps
CPU time 0.79 seconds
Started Apr 30 12:28:44 PM PDT 24
Finished Apr 30 12:28:46 PM PDT 24
Peak memory 205792 kb
Host smart-dcaa363f-6a46-4e3f-b799-e4eff7b887c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371505709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.2371505709
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2808215906
Short name T948
Test name
Test status
Simulation time 346315317 ps
CPU time 2.89 seconds
Started Apr 30 12:28:49 PM PDT 24
Finished Apr 30 12:28:53 PM PDT 24
Peak memory 206036 kb
Host smart-65cb7b70-c301-4f7c-b436-2e9a6ae532e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808215906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.2808215906
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.3108415337
Short name T1034
Test name
Test status
Simulation time 76002274 ps
CPU time 2.64 seconds
Started Apr 30 12:28:43 PM PDT 24
Finished Apr 30 12:28:46 PM PDT 24
Peak memory 222652 kb
Host smart-621e82ee-1b84-4a39-b0dd-44c648ef2f3d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108415337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.3108415337
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.1694341116
Short name T964
Test name
Test status
Simulation time 40554068 ps
CPU time 2.28 seconds
Started Apr 30 12:28:43 PM PDT 24
Finished Apr 30 12:28:46 PM PDT 24
Peak memory 214120 kb
Host smart-cb048754-0215-47f4-812d-1ae1ff0f5509
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694341116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.1694341116
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.2151030663
Short name T1028
Test name
Test status
Simulation time 24491221 ps
CPU time 0.72 seconds
Started Apr 30 12:29:14 PM PDT 24
Finished Apr 30 12:29:16 PM PDT 24
Peak memory 205680 kb
Host smart-818ef2a9-edbd-4983-8b98-3290b6deef5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151030663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.2151030663
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.3197589359
Short name T990
Test name
Test status
Simulation time 27039965 ps
CPU time 0.78 seconds
Started Apr 30 12:29:14 PM PDT 24
Finished Apr 30 12:29:16 PM PDT 24
Peak memory 205636 kb
Host smart-ba8d1228-bd7c-4f22-a449-528986c2361f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197589359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.3197589359
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.2265137606
Short name T914
Test name
Test status
Simulation time 56193284 ps
CPU time 0.69 seconds
Started Apr 30 12:29:16 PM PDT 24
Finished Apr 30 12:29:17 PM PDT 24
Peak memory 205752 kb
Host smart-3c9fd304-2ad4-46d0-941e-9b8f35084d24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265137606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.2265137606
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.558938631
Short name T966
Test name
Test status
Simulation time 9618352 ps
CPU time 0.72 seconds
Started Apr 30 12:29:15 PM PDT 24
Finished Apr 30 12:29:17 PM PDT 24
Peak memory 205692 kb
Host smart-ddba2d99-2f00-4bd9-9c13-bb7d2aaca90a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558938631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.558938631
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.3271388120
Short name T906
Test name
Test status
Simulation time 18951691 ps
CPU time 0.8 seconds
Started Apr 30 12:29:42 PM PDT 24
Finished Apr 30 12:29:45 PM PDT 24
Peak memory 204972 kb
Host smart-7f1388ed-2adb-40e6-9dd3-f957ca95ebfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271388120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.3271388120
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.3106284228
Short name T1022
Test name
Test status
Simulation time 32630358 ps
CPU time 0.71 seconds
Started Apr 30 12:29:19 PM PDT 24
Finished Apr 30 12:29:20 PM PDT 24
Peak memory 205896 kb
Host smart-2fcbb558-a412-444b-af50-3deeb1a50974
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106284228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.3106284228
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.1907335493
Short name T976
Test name
Test status
Simulation time 15019159 ps
CPU time 0.73 seconds
Started Apr 30 12:29:17 PM PDT 24
Finished Apr 30 12:29:19 PM PDT 24
Peak memory 205700 kb
Host smart-419d9019-6714-4ff9-92db-20f3305a445b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907335493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.1907335493
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1034978521
Short name T999
Test name
Test status
Simulation time 17231318 ps
CPU time 0.71 seconds
Started Apr 30 12:29:16 PM PDT 24
Finished Apr 30 12:29:18 PM PDT 24
Peak memory 205720 kb
Host smart-ff3bc382-9951-4a64-b6a1-8ed7d57778fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034978521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.1034978521
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.311352159
Short name T908
Test name
Test status
Simulation time 39583131 ps
CPU time 0.75 seconds
Started Apr 30 12:29:15 PM PDT 24
Finished Apr 30 12:29:17 PM PDT 24
Peak memory 205704 kb
Host smart-4c8c1cba-0803-4f84-b615-be5872063a61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311352159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.311352159
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.16996796
Short name T938
Test name
Test status
Simulation time 39958319 ps
CPU time 0.74 seconds
Started Apr 30 12:29:16 PM PDT 24
Finished Apr 30 12:29:18 PM PDT 24
Peak memory 205828 kb
Host smart-bfc592e8-c1d1-48e2-802f-0cefce924c7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16996796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.16996796
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.1429212154
Short name T917
Test name
Test status
Simulation time 116946096 ps
CPU time 1.35 seconds
Started Apr 30 12:28:49 PM PDT 24
Finished Apr 30 12:28:52 PM PDT 24
Peak memory 214308 kb
Host smart-7253b9ec-f768-43d6-9fb2-22229a8a3c05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429212154 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.1429212154
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.2087116749
Short name T943
Test name
Test status
Simulation time 27567184 ps
CPU time 1.35 seconds
Started Apr 30 12:28:48 PM PDT 24
Finished Apr 30 12:28:50 PM PDT 24
Peak memory 206012 kb
Host smart-56753995-b2d5-48b4-b0f9-3a41a0e01cd9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087116749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.2087116749
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.1531541730
Short name T1021
Test name
Test status
Simulation time 43424411 ps
CPU time 0.77 seconds
Started Apr 30 12:28:47 PM PDT 24
Finished Apr 30 12:28:48 PM PDT 24
Peak memory 205748 kb
Host smart-ab7790da-9370-42a2-9cb5-38f211c513d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531541730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.1531541730
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.3523344937
Short name T931
Test name
Test status
Simulation time 396287556 ps
CPU time 2.94 seconds
Started Apr 30 12:28:43 PM PDT 24
Finished Apr 30 12:28:47 PM PDT 24
Peak memory 205948 kb
Host smart-cbebdf95-ed5a-4d5b-b47b-73cb2f77559d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523344937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.3523344937
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1753591433
Short name T1011
Test name
Test status
Simulation time 387687686 ps
CPU time 8.48 seconds
Started Apr 30 12:28:49 PM PDT 24
Finished Apr 30 12:28:59 PM PDT 24
Peak memory 214524 kb
Host smart-e615eaaf-4c73-47f6-b32b-befd2f0e5bc2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753591433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.1753591433
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.3313339448
Short name T977
Test name
Test status
Simulation time 507615581 ps
CPU time 6.01 seconds
Started Apr 30 12:28:50 PM PDT 24
Finished Apr 30 12:28:57 PM PDT 24
Peak memory 220848 kb
Host smart-e594a36a-5d7a-4f6e-aab1-00d06aa717d0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313339448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.3313339448
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.285786585
Short name T200
Test name
Test status
Simulation time 428893005 ps
CPU time 2.75 seconds
Started Apr 30 12:28:42 PM PDT 24
Finished Apr 30 12:28:45 PM PDT 24
Peak memory 217348 kb
Host smart-d54550bb-ef22-4b5f-9bfb-43bc127c9ec8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285786585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.285786585
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.390045330
Short name T952
Test name
Test status
Simulation time 29460700 ps
CPU time 2.1 seconds
Started Apr 30 12:28:49 PM PDT 24
Finished Apr 30 12:28:52 PM PDT 24
Peak memory 214392 kb
Host smart-6c022983-05ab-41a1-b71f-76ba305505b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390045330 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.390045330
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.2280859497
Short name T149
Test name
Test status
Simulation time 28265903 ps
CPU time 1.23 seconds
Started Apr 30 12:28:40 PM PDT 24
Finished Apr 30 12:28:42 PM PDT 24
Peak memory 205924 kb
Host smart-5745e8d5-3c4d-4ab3-bfce-ececd7cae229
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280859497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.2280859497
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.1966096313
Short name T907
Test name
Test status
Simulation time 8682992 ps
CPU time 0.78 seconds
Started Apr 30 12:28:51 PM PDT 24
Finished Apr 30 12:28:53 PM PDT 24
Peak memory 205760 kb
Host smart-f411697e-5380-4b9b-b32e-ab893a38556d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966096313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.1966096313
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1069563710
Short name T1060
Test name
Test status
Simulation time 87908483 ps
CPU time 3.39 seconds
Started Apr 30 12:28:44 PM PDT 24
Finished Apr 30 12:28:48 PM PDT 24
Peak memory 206000 kb
Host smart-19c00835-477b-4523-abe5-b8f93ec7fe39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069563710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.1069563710
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.1914834964
Short name T1029
Test name
Test status
Simulation time 719202694 ps
CPU time 4.39 seconds
Started Apr 30 12:28:48 PM PDT 24
Finished Apr 30 12:28:53 PM PDT 24
Peak memory 214416 kb
Host smart-9f852e98-9cd9-4009-b13e-390d4df37405
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914834964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.1914834964
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.188341036
Short name T121
Test name
Test status
Simulation time 719408751 ps
CPU time 9.89 seconds
Started Apr 30 12:28:50 PM PDT 24
Finished Apr 30 12:29:01 PM PDT 24
Peak memory 214580 kb
Host smart-4fa5264b-a56a-4035-a1c9-4735fb2fd47b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188341036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_shadow_reg_errors_with_csr_rw.188341036
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.247618126
Short name T975
Test name
Test status
Simulation time 51721876 ps
CPU time 1.47 seconds
Started Apr 30 12:28:49 PM PDT 24
Finished Apr 30 12:28:51 PM PDT 24
Peak memory 222408 kb
Host smart-c9bed7ca-dcf3-4fc7-9966-006e5da561d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247618126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.247618126
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.254093111
Short name T174
Test name
Test status
Simulation time 339417516 ps
CPU time 3.87 seconds
Started Apr 30 12:28:52 PM PDT 24
Finished Apr 30 12:28:57 PM PDT 24
Peak memory 209008 kb
Host smart-7015c22d-d240-4de6-84be-5900095599de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254093111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err.
254093111
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.276106457
Short name T954
Test name
Test status
Simulation time 97781730 ps
CPU time 1.76 seconds
Started Apr 30 12:28:51 PM PDT 24
Finished Apr 30 12:28:54 PM PDT 24
Peak memory 214452 kb
Host smart-b33437f9-c7fe-42ed-b56b-b61aa4696057
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276106457 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.276106457
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.2842942525
Short name T1002
Test name
Test status
Simulation time 27685324 ps
CPU time 1.27 seconds
Started Apr 30 12:28:51 PM PDT 24
Finished Apr 30 12:28:53 PM PDT 24
Peak memory 206024 kb
Host smart-104a6320-ea62-44b1-a7dc-7b9d433ab347
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842942525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.2842942525
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.1011368715
Short name T935
Test name
Test status
Simulation time 134304364 ps
CPU time 0.86 seconds
Started Apr 30 12:28:46 PM PDT 24
Finished Apr 30 12:28:48 PM PDT 24
Peak memory 205744 kb
Host smart-743795e5-c123-4d88-bfb2-41df94bd7c31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011368715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.1011368715
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.4008475657
Short name T1069
Test name
Test status
Simulation time 34344738 ps
CPU time 1.92 seconds
Started Apr 30 12:28:54 PM PDT 24
Finished Apr 30 12:28:57 PM PDT 24
Peak memory 206072 kb
Host smart-d013503e-ff9f-4f6e-9bae-d279b670dc47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008475657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.4008475657
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.2592848180
Short name T1005
Test name
Test status
Simulation time 102321830 ps
CPU time 4.07 seconds
Started Apr 30 12:28:49 PM PDT 24
Finished Apr 30 12:28:55 PM PDT 24
Peak memory 214492 kb
Host smart-c0277d08-848f-4089-809d-16e64bef687a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592848180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.2592848180
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.4207183404
Short name T1015
Test name
Test status
Simulation time 345457830 ps
CPU time 4.72 seconds
Started Apr 30 12:28:48 PM PDT 24
Finished Apr 30 12:28:53 PM PDT 24
Peak memory 214584 kb
Host smart-c3b3b457-aa08-4927-a775-e974c684e75e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207183404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.4207183404
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.1138887655
Short name T1065
Test name
Test status
Simulation time 110940276 ps
CPU time 2.99 seconds
Started Apr 30 12:28:47 PM PDT 24
Finished Apr 30 12:28:51 PM PDT 24
Peak memory 214448 kb
Host smart-0c4316c7-dbdb-4e65-82b8-04d5df91c7dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138887655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.1138887655
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.2338573023
Short name T155
Test name
Test status
Simulation time 121032100 ps
CPU time 3.58 seconds
Started Apr 30 12:28:47 PM PDT 24
Finished Apr 30 12:28:52 PM PDT 24
Peak memory 209620 kb
Host smart-c340305f-2ac9-43c3-b2e3-dba89743e7b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338573023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.2338573023
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1475646032
Short name T1070
Test name
Test status
Simulation time 136020085 ps
CPU time 1.29 seconds
Started Apr 30 12:28:50 PM PDT 24
Finished Apr 30 12:28:53 PM PDT 24
Peak memory 214276 kb
Host smart-3646255f-f7c6-4cfa-9f6d-74bcd248448a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475646032 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.1475646032
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.3392083236
Short name T1039
Test name
Test status
Simulation time 19891143 ps
CPU time 0.85 seconds
Started Apr 30 12:28:48 PM PDT 24
Finished Apr 30 12:28:50 PM PDT 24
Peak memory 205824 kb
Host smart-b65b3e1a-0778-4c11-9071-09d41853b5cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392083236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.3392083236
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.3671689346
Short name T1067
Test name
Test status
Simulation time 13162439 ps
CPU time 0.73 seconds
Started Apr 30 12:28:50 PM PDT 24
Finished Apr 30 12:28:52 PM PDT 24
Peak memory 205624 kb
Host smart-6915c8fb-941e-4ecd-bebf-98496e7ff1a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671689346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.3671689346
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.4196229432
Short name T991
Test name
Test status
Simulation time 703397280 ps
CPU time 2.06 seconds
Started Apr 30 12:28:48 PM PDT 24
Finished Apr 30 12:28:51 PM PDT 24
Peak memory 206040 kb
Host smart-dc15a15c-27e7-421d-b2f2-31940e9f0187
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196229432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.4196229432
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2914988007
Short name T1035
Test name
Test status
Simulation time 1265766925 ps
CPU time 5.67 seconds
Started Apr 30 12:28:51 PM PDT 24
Finished Apr 30 12:28:57 PM PDT 24
Peak memory 214524 kb
Host smart-a226c10f-0ec5-45a6-9d06-10083b55ce76
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914988007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.2914988007
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.3857656629
Short name T987
Test name
Test status
Simulation time 205144370 ps
CPU time 6.83 seconds
Started Apr 30 12:28:50 PM PDT 24
Finished Apr 30 12:28:58 PM PDT 24
Peak memory 214560 kb
Host smart-d9bd057d-2131-4569-a463-e22bc8ddb56c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857656629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.3857656629
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1953162081
Short name T191
Test name
Test status
Simulation time 75063512 ps
CPU time 2.05 seconds
Started Apr 30 12:28:51 PM PDT 24
Finished Apr 30 12:28:54 PM PDT 24
Peak memory 214204 kb
Host smart-6d863f3d-b6b7-430c-8f6b-744449cf8a23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953162081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.1953162081
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.1252887029
Short name T992
Test name
Test status
Simulation time 1598793019 ps
CPU time 34.31 seconds
Started Apr 30 12:28:47 PM PDT 24
Finished Apr 30 12:29:22 PM PDT 24
Peak memory 211476 kb
Host smart-a9a2252b-df26-491e-95fc-fd76fe624878
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252887029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.1252887029
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1673246279
Short name T932
Test name
Test status
Simulation time 84724994 ps
CPU time 1.41 seconds
Started Apr 30 12:28:54 PM PDT 24
Finished Apr 30 12:28:56 PM PDT 24
Peak memory 214244 kb
Host smart-38be09c7-7fcb-4c63-8c13-42b7812f3d17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673246279 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.1673246279
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.122208154
Short name T1013
Test name
Test status
Simulation time 87983068 ps
CPU time 1.11 seconds
Started Apr 30 12:28:59 PM PDT 24
Finished Apr 30 12:29:01 PM PDT 24
Peak memory 205984 kb
Host smart-6e12864c-52b9-4c08-a6d8-b8c8dcca6deb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122208154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.122208154
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.2061402105
Short name T969
Test name
Test status
Simulation time 20755373 ps
CPU time 0.84 seconds
Started Apr 30 12:28:53 PM PDT 24
Finished Apr 30 12:28:54 PM PDT 24
Peak memory 205700 kb
Host smart-38121541-6d9f-469e-83fd-b4a7df21971d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061402105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.2061402105
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.1964331978
Short name T147
Test name
Test status
Simulation time 30260295 ps
CPU time 1.94 seconds
Started Apr 30 12:28:54 PM PDT 24
Finished Apr 30 12:28:57 PM PDT 24
Peak memory 205952 kb
Host smart-b0029e39-8577-4887-bb79-07db934ca243
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964331978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.1964331978
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.4118505307
Short name T124
Test name
Test status
Simulation time 271846116 ps
CPU time 4.92 seconds
Started Apr 30 12:28:48 PM PDT 24
Finished Apr 30 12:28:54 PM PDT 24
Peak memory 214576 kb
Host smart-0bcc3e1d-d41b-4e4b-97aa-4b4a5a60ecae
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118505307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.4118505307
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.3754790035
Short name T970
Test name
Test status
Simulation time 307945286 ps
CPU time 4.45 seconds
Started Apr 30 12:28:49 PM PDT 24
Finished Apr 30 12:28:55 PM PDT 24
Peak memory 220512 kb
Host smart-9e562b59-9bbe-4e7e-a368-6b0c42596978
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754790035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.3754790035
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3795090863
Short name T1006
Test name
Test status
Simulation time 313823731 ps
CPU time 3.2 seconds
Started Apr 30 12:28:47 PM PDT 24
Finished Apr 30 12:28:51 PM PDT 24
Peak memory 216428 kb
Host smart-15b3df83-b1ee-4729-81f0-5d753af60c1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795090863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.3795090863
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.3882794058
Short name T216
Test name
Test status
Simulation time 259206527 ps
CPU time 4.28 seconds
Started Apr 30 12:30:44 PM PDT 24
Finished Apr 30 12:30:49 PM PDT 24
Peak memory 213908 kb
Host smart-146d1745-f13a-4381-9dad-9831ec40890d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3882794058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.3882794058
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.4141653873
Short name T805
Test name
Test status
Simulation time 42730459 ps
CPU time 2.21 seconds
Started Apr 30 12:30:41 PM PDT 24
Finished Apr 30 12:30:45 PM PDT 24
Peak memory 208088 kb
Host smart-0ef89a42-e2ae-4252-b8ad-a55cc45a829d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141653873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.4141653873
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.765003028
Short name T897
Test name
Test status
Simulation time 81614587 ps
CPU time 3.99 seconds
Started Apr 30 12:30:31 PM PDT 24
Finished Apr 30 12:30:36 PM PDT 24
Peak memory 214000 kb
Host smart-f2ca74ec-04a1-4f31-8625-9a732d6d7c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765003028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.765003028
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_random.3406592203
Short name T711
Test name
Test status
Simulation time 753861689 ps
CPU time 6.41 seconds
Started Apr 30 12:30:32 PM PDT 24
Finished Apr 30 12:30:39 PM PDT 24
Peak memory 208012 kb
Host smart-275ec0c9-58c8-4c55-a840-6df05ed2886c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406592203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.3406592203
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.114131894
Short name T34
Test name
Test status
Simulation time 982968059 ps
CPU time 9.86 seconds
Started Apr 30 12:30:47 PM PDT 24
Finished Apr 30 12:30:59 PM PDT 24
Peak memory 231188 kb
Host smart-94d52689-e2aa-47c4-b4e6-e96fe3691f41
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114131894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.114131894
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.1377157263
Short name T898
Test name
Test status
Simulation time 186212418 ps
CPU time 2.76 seconds
Started Apr 30 12:30:39 PM PDT 24
Finished Apr 30 12:30:43 PM PDT 24
Peak memory 206464 kb
Host smart-a9249607-0f32-49ab-8b25-ad67cbf58d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377157263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.1377157263
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.426483805
Short name T879
Test name
Test status
Simulation time 57912490 ps
CPU time 2.73 seconds
Started Apr 30 12:30:36 PM PDT 24
Finished Apr 30 12:30:39 PM PDT 24
Peak memory 207496 kb
Host smart-24629887-da31-4f59-85a8-bd606f794121
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426483805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.426483805
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.1859495924
Short name T570
Test name
Test status
Simulation time 41858513 ps
CPU time 2.5 seconds
Started Apr 30 12:30:44 PM PDT 24
Finished Apr 30 12:30:48 PM PDT 24
Peak memory 206340 kb
Host smart-5b0902a1-48f6-41f9-940a-7ef295726043
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859495924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.1859495924
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.1391305922
Short name T729
Test name
Test status
Simulation time 379045239 ps
CPU time 3.56 seconds
Started Apr 30 12:30:41 PM PDT 24
Finished Apr 30 12:30:46 PM PDT 24
Peak memory 206212 kb
Host smart-3942cc47-7756-4b0f-ad4f-fcf274245f8f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391305922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.1391305922
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.2005495199
Short name T30
Test name
Test status
Simulation time 117129774 ps
CPU time 2.39 seconds
Started Apr 30 12:30:46 PM PDT 24
Finished Apr 30 12:30:50 PM PDT 24
Peak memory 207552 kb
Host smart-c8b94bb4-e333-4471-99b3-f044292716ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005495199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.2005495199
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.17149613
Short name T576
Test name
Test status
Simulation time 246473095 ps
CPU time 5.92 seconds
Started Apr 30 12:30:51 PM PDT 24
Finished Apr 30 12:30:59 PM PDT 24
Peak memory 207964 kb
Host smart-0c8fffb6-7cd2-4a4e-9640-e9d7ef2a6de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17149613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.17149613
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.3282507505
Short name T613
Test name
Test status
Simulation time 777271404 ps
CPU time 6.03 seconds
Started Apr 30 12:30:40 PM PDT 24
Finished Apr 30 12:30:47 PM PDT 24
Peak memory 208972 kb
Host smart-d88d1c4b-984b-4785-8afc-d70cb585da61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282507505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.3282507505
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.872185531
Short name T587
Test name
Test status
Simulation time 91621348 ps
CPU time 0.79 seconds
Started Apr 30 12:30:46 PM PDT 24
Finished Apr 30 12:30:48 PM PDT 24
Peak memory 205572 kb
Host smart-591d6c2d-7d86-453d-a8dd-74fd67e8025c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872185531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.872185531
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.2985394996
Short name T9
Test name
Test status
Simulation time 9022096316 ps
CPU time 28.54 seconds
Started Apr 30 12:30:41 PM PDT 24
Finished Apr 30 12:31:11 PM PDT 24
Peak memory 222468 kb
Host smart-60eff737-b7db-4cf1-ad7e-7bb71c920ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985394996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.2985394996
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.2548206851
Short name T793
Test name
Test status
Simulation time 139660003 ps
CPU time 1.98 seconds
Started Apr 30 12:30:45 PM PDT 24
Finished Apr 30 12:30:48 PM PDT 24
Peak memory 213960 kb
Host smart-e1ba417c-df7c-4e87-a3dc-1114125349be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548206851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.2548206851
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.2592288880
Short name T89
Test name
Test status
Simulation time 645167019 ps
CPU time 4.45 seconds
Started Apr 30 12:30:41 PM PDT 24
Finished Apr 30 12:30:46 PM PDT 24
Peak memory 208756 kb
Host smart-d04f2149-4d22-417b-8961-20e9f44d7854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592288880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.2592288880
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.1398277886
Short name T810
Test name
Test status
Simulation time 138309025 ps
CPU time 3.16 seconds
Started Apr 30 12:30:42 PM PDT 24
Finished Apr 30 12:30:46 PM PDT 24
Peak memory 207968 kb
Host smart-58d8f6a0-03ba-4fd7-9aeb-e4b7422b5459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398277886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.1398277886
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.3561523885
Short name T623
Test name
Test status
Simulation time 232610091 ps
CPU time 5.31 seconds
Started Apr 30 12:30:52 PM PDT 24
Finished Apr 30 12:30:59 PM PDT 24
Peak memory 209508 kb
Host smart-7cea090a-8587-4dc7-b5e3-ac4fe1d22f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561523885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.3561523885
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.76407352
Short name T12
Test name
Test status
Simulation time 502463891 ps
CPU time 9.09 seconds
Started Apr 30 12:30:50 PM PDT 24
Finished Apr 30 12:31:01 PM PDT 24
Peak memory 229588 kb
Host smart-c8fc624f-5385-4b12-97b3-f5058a7ff683
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76407352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.76407352
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.307143750
Short name T683
Test name
Test status
Simulation time 24027976 ps
CPU time 1.98 seconds
Started Apr 30 12:30:40 PM PDT 24
Finished Apr 30 12:30:43 PM PDT 24
Peak memory 207012 kb
Host smart-329efcf3-9f1f-4760-8c69-e776eb4a3518
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307143750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.307143750
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.1366698351
Short name T455
Test name
Test status
Simulation time 371648229 ps
CPU time 7.45 seconds
Started Apr 30 12:30:40 PM PDT 24
Finished Apr 30 12:30:48 PM PDT 24
Peak memory 207568 kb
Host smart-0ccbb66a-f51b-4a76-8b47-c237922b7005
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366698351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.1366698351
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.3237276837
Short name T569
Test name
Test status
Simulation time 734525205 ps
CPU time 5.27 seconds
Started Apr 30 12:30:50 PM PDT 24
Finished Apr 30 12:30:56 PM PDT 24
Peak memory 208140 kb
Host smart-7dadf630-11f6-4506-86d6-926d4e26292f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237276837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.3237276837
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_smoke.2574817555
Short name T423
Test name
Test status
Simulation time 220299795 ps
CPU time 7.2 seconds
Started Apr 30 12:30:46 PM PDT 24
Finished Apr 30 12:30:54 PM PDT 24
Peak memory 208016 kb
Host smart-9eea7909-a856-4524-a3eb-48e4f69c3604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574817555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.2574817555
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.3971267307
Short name T241
Test name
Test status
Simulation time 2736797353 ps
CPU time 18.47 seconds
Started Apr 30 12:30:45 PM PDT 24
Finished Apr 30 12:31:05 PM PDT 24
Peak memory 220484 kb
Host smart-c9372f67-f3eb-4996-82cb-081ee7bc0e1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971267307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.3971267307
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.490787678
Short name T864
Test name
Test status
Simulation time 149481596 ps
CPU time 3.02 seconds
Started Apr 30 12:30:42 PM PDT 24
Finished Apr 30 12:30:46 PM PDT 24
Peak memory 218232 kb
Host smart-7f2c36ab-f26d-4042-851d-9196f35ea92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490787678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.490787678
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.3808438344
Short name T194
Test name
Test status
Simulation time 17029254 ps
CPU time 0.73 seconds
Started Apr 30 12:30:52 PM PDT 24
Finished Apr 30 12:30:59 PM PDT 24
Peak memory 205608 kb
Host smart-94ab51ad-ba90-4086-9f7b-16894592c39f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808438344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.3808438344
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.3460505749
Short name T395
Test name
Test status
Simulation time 170006859 ps
CPU time 8.92 seconds
Started Apr 30 12:31:07 PM PDT 24
Finished Apr 30 12:31:17 PM PDT 24
Peak memory 214040 kb
Host smart-1060e304-f6db-4e51-9efa-f6f2cf811733
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3460505749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.3460505749
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.2873872247
Short name T28
Test name
Test status
Simulation time 54538125 ps
CPU time 2.38 seconds
Started Apr 30 12:30:57 PM PDT 24
Finished Apr 30 12:31:00 PM PDT 24
Peak memory 209320 kb
Host smart-366350f0-3baf-4730-8196-39b153d0ce4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873872247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.2873872247
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.3511060951
Short name T283
Test name
Test status
Simulation time 15579432142 ps
CPU time 30.43 seconds
Started Apr 30 12:31:06 PM PDT 24
Finished Apr 30 12:31:37 PM PDT 24
Peak memory 208984 kb
Host smart-0acbb4a0-34f3-437f-a8db-0f6a461d9001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511060951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.3511060951
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.79134531
Short name T707
Test name
Test status
Simulation time 544607353 ps
CPU time 5.45 seconds
Started Apr 30 12:30:55 PM PDT 24
Finished Apr 30 12:31:01 PM PDT 24
Peak memory 219920 kb
Host smart-a86b5bcf-74f2-43a8-a9ce-8579fcf63675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79134531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.79134531
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.104071411
Short name T575
Test name
Test status
Simulation time 252782602 ps
CPU time 2.51 seconds
Started Apr 30 12:30:55 PM PDT 24
Finished Apr 30 12:30:58 PM PDT 24
Peak memory 214412 kb
Host smart-ab9cea1b-63db-406f-8524-88c55458ef83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104071411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.104071411
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.616428484
Short name T866
Test name
Test status
Simulation time 1727705908 ps
CPU time 5.76 seconds
Started Apr 30 12:30:53 PM PDT 24
Finished Apr 30 12:31:00 PM PDT 24
Peak memory 222092 kb
Host smart-72509f03-f29f-44f5-bce7-d78f8d2756a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616428484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.616428484
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.1883081922
Short name T485
Test name
Test status
Simulation time 75471560 ps
CPU time 3.71 seconds
Started Apr 30 12:30:56 PM PDT 24
Finished Apr 30 12:31:01 PM PDT 24
Peak memory 208532 kb
Host smart-d6083da4-722c-4756-83c2-f6707951648d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883081922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.1883081922
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.1374218699
Short name T221
Test name
Test status
Simulation time 124089816 ps
CPU time 2.57 seconds
Started Apr 30 12:30:53 PM PDT 24
Finished Apr 30 12:30:57 PM PDT 24
Peak memory 206388 kb
Host smart-ae478164-e129-48f3-86a5-a738c46c32b9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374218699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.1374218699
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.879163983
Short name T880
Test name
Test status
Simulation time 376214366 ps
CPU time 3.05 seconds
Started Apr 30 12:31:53 PM PDT 24
Finished Apr 30 12:32:00 PM PDT 24
Peak memory 205604 kb
Host smart-6632d62d-ee69-4bcf-91f0-3e453f277fc5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879163983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.879163983
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.3823261543
Short name T591
Test name
Test status
Simulation time 113250968 ps
CPU time 3.72 seconds
Started Apr 30 12:31:07 PM PDT 24
Finished Apr 30 12:31:12 PM PDT 24
Peak memory 208416 kb
Host smart-a59b943c-5557-427a-a373-bcea04c5694f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823261543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.3823261543
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.2577910334
Short name T268
Test name
Test status
Simulation time 88741873 ps
CPU time 2.45 seconds
Started Apr 30 12:30:54 PM PDT 24
Finished Apr 30 12:30:58 PM PDT 24
Peak memory 214016 kb
Host smart-bb7b7520-a7eb-4ee8-beb8-90366935f51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577910334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.2577910334
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.1457054168
Short name T778
Test name
Test status
Simulation time 119741829 ps
CPU time 3.95 seconds
Started Apr 30 12:31:07 PM PDT 24
Finished Apr 30 12:31:12 PM PDT 24
Peak memory 205796 kb
Host smart-512d40fa-4e3d-401f-95cd-c79a37a274a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457054168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.1457054168
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.50310404
Short name T468
Test name
Test status
Simulation time 99909065 ps
CPU time 3.65 seconds
Started Apr 30 12:31:06 PM PDT 24
Finished Apr 30 12:31:11 PM PDT 24
Peak memory 206840 kb
Host smart-b47a7dea-2958-4916-a74b-c7e3ae6da902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50310404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.50310404
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.56493355
Short name T732
Test name
Test status
Simulation time 105209451 ps
CPU time 3.44 seconds
Started Apr 30 12:30:50 PM PDT 24
Finished Apr 30 12:30:55 PM PDT 24
Peak memory 209276 kb
Host smart-fa7997a8-15b2-4129-b5c2-e99d2638c696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56493355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.56493355
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.1750036350
Short name T672
Test name
Test status
Simulation time 9139428 ps
CPU time 0.82 seconds
Started Apr 30 12:30:51 PM PDT 24
Finished Apr 30 12:30:53 PM PDT 24
Peak memory 205564 kb
Host smart-363d3ce9-f144-4121-b5b3-f6d7e2f263bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750036350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.1750036350
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.4215129812
Short name T249
Test name
Test status
Simulation time 765494705 ps
CPU time 4.51 seconds
Started Apr 30 12:31:15 PM PDT 24
Finished Apr 30 12:31:20 PM PDT 24
Peak memory 214028 kb
Host smart-dc30389f-7542-4979-94da-c5e1fa22ff46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4215129812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.4215129812
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.1840264567
Short name T383
Test name
Test status
Simulation time 515823436 ps
CPU time 6.43 seconds
Started Apr 30 12:30:47 PM PDT 24
Finished Apr 30 12:30:55 PM PDT 24
Peak memory 208292 kb
Host smart-83c525ef-48eb-4b61-9440-42d959465f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840264567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.1840264567
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.574969353
Short name T142
Test name
Test status
Simulation time 497687588 ps
CPU time 1.98 seconds
Started Apr 30 12:30:51 PM PDT 24
Finished Apr 30 12:30:55 PM PDT 24
Peak memory 214000 kb
Host smart-4d404bf0-fc84-4840-8651-c1cd7202315e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574969353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.574969353
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.3104132367
Short name T780
Test name
Test status
Simulation time 4871530286 ps
CPU time 12.03 seconds
Started Apr 30 12:31:07 PM PDT 24
Finished Apr 30 12:31:20 PM PDT 24
Peak memory 208568 kb
Host smart-11a11bf9-d877-45b9-94d8-5954d2113c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104132367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.3104132367
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.3669113124
Short name T622
Test name
Test status
Simulation time 245865562 ps
CPU time 3.06 seconds
Started Apr 30 12:30:56 PM PDT 24
Finished Apr 30 12:31:00 PM PDT 24
Peak memory 206320 kb
Host smart-45b91b16-94ec-4112-83c8-9563a3eac4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669113124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.3669113124
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.1493255913
Short name T896
Test name
Test status
Simulation time 818856410 ps
CPU time 6.78 seconds
Started Apr 30 12:31:07 PM PDT 24
Finished Apr 30 12:31:15 PM PDT 24
Peak memory 208252 kb
Host smart-ccc8a239-b969-4485-9039-d9060e3eea4b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493255913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.1493255913
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.704402302
Short name T854
Test name
Test status
Simulation time 1528385364 ps
CPU time 4.45 seconds
Started Apr 30 12:30:51 PM PDT 24
Finished Apr 30 12:30:58 PM PDT 24
Peak memory 206256 kb
Host smart-37d890cb-6a8c-4759-ad6c-d11ebf84eee0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704402302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.704402302
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.2789228858
Short name T815
Test name
Test status
Simulation time 133736729 ps
CPU time 4.27 seconds
Started Apr 30 12:30:51 PM PDT 24
Finished Apr 30 12:30:57 PM PDT 24
Peak memory 208548 kb
Host smart-fa9f5ae4-12b7-4a3c-946f-77f01554f4d2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789228858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.2789228858
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.2011814606
Short name T407
Test name
Test status
Simulation time 290202269 ps
CPU time 3.42 seconds
Started Apr 30 12:31:01 PM PDT 24
Finished Apr 30 12:31:05 PM PDT 24
Peak memory 209076 kb
Host smart-e3b404a2-ca45-4faa-8338-581df36eb7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011814606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.2011814606
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.656002592
Short name T607
Test name
Test status
Simulation time 108838095 ps
CPU time 2.82 seconds
Started Apr 30 12:30:53 PM PDT 24
Finished Apr 30 12:30:57 PM PDT 24
Peak memory 207708 kb
Host smart-7c0d18c2-4fc9-4626-8fbe-408de3581d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656002592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.656002592
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.2439439897
Short name T566
Test name
Test status
Simulation time 100073609 ps
CPU time 4.41 seconds
Started Apr 30 12:30:58 PM PDT 24
Finished Apr 30 12:31:03 PM PDT 24
Peak memory 208808 kb
Host smart-64a8f940-32b5-4e05-ab5a-d821e3079946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439439897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.2439439897
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.1636460908
Short name T559
Test name
Test status
Simulation time 183085311 ps
CPU time 2.49 seconds
Started Apr 30 12:30:59 PM PDT 24
Finished Apr 30 12:31:02 PM PDT 24
Peak memory 209996 kb
Host smart-05caee69-596e-4973-8484-a073d9167397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636460908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.1636460908
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.3116015466
Short name T514
Test name
Test status
Simulation time 21825226 ps
CPU time 0.88 seconds
Started Apr 30 12:30:56 PM PDT 24
Finished Apr 30 12:30:58 PM PDT 24
Peak memory 205592 kb
Host smart-11221139-ccfe-4aa9-bdbd-d6caab2e1563
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116015466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.3116015466
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.2665143601
Short name T448
Test name
Test status
Simulation time 315464573 ps
CPU time 7.38 seconds
Started Apr 30 12:30:50 PM PDT 24
Finished Apr 30 12:31:00 PM PDT 24
Peak memory 208976 kb
Host smart-06e73dc7-3c0e-4a7f-bb37-fedc856b8879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665143601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.2665143601
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.159012584
Short name T292
Test name
Test status
Simulation time 345413945 ps
CPU time 3.19 seconds
Started Apr 30 12:32:08 PM PDT 24
Finished Apr 30 12:32:12 PM PDT 24
Peak memory 213960 kb
Host smart-105b3846-4e46-4d35-a347-55eb4e22648a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159012584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.159012584
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.3657508459
Short name T93
Test name
Test status
Simulation time 410709159 ps
CPU time 8.42 seconds
Started Apr 30 12:31:05 PM PDT 24
Finished Apr 30 12:31:14 PM PDT 24
Peak memory 209496 kb
Host smart-13c9f8e9-d577-4082-8e8e-2408c67571e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657508459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.3657508459
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.1915867087
Short name T296
Test name
Test status
Simulation time 133749400 ps
CPU time 5.97 seconds
Started Apr 30 12:30:55 PM PDT 24
Finished Apr 30 12:31:02 PM PDT 24
Peak memory 213996 kb
Host smart-0d646fcb-8b97-41aa-9722-100a15230f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915867087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.1915867087
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.46902512
Short name T392
Test name
Test status
Simulation time 65193550 ps
CPU time 2.43 seconds
Started Apr 30 12:30:52 PM PDT 24
Finished Apr 30 12:30:57 PM PDT 24
Peak memory 214004 kb
Host smart-4927cdbc-ebff-4a2d-82e9-cfae69ed38a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46902512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.46902512
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.3767797582
Short name T832
Test name
Test status
Simulation time 3789857363 ps
CPU time 53.41 seconds
Started Apr 30 12:30:56 PM PDT 24
Finished Apr 30 12:31:50 PM PDT 24
Peak memory 209500 kb
Host smart-67b3a6d9-cdaf-4898-9353-a78141c1b6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767797582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.3767797582
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.2507978330
Short name T829
Test name
Test status
Simulation time 155457394 ps
CPU time 4.39 seconds
Started Apr 30 12:30:55 PM PDT 24
Finished Apr 30 12:31:00 PM PDT 24
Peak memory 207876 kb
Host smart-5fb848d5-1621-4601-9f10-c6b0c566d2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507978330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.2507978330
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.469707473
Short name T857
Test name
Test status
Simulation time 124144434 ps
CPU time 3.09 seconds
Started Apr 30 12:30:53 PM PDT 24
Finished Apr 30 12:30:58 PM PDT 24
Peak memory 208232 kb
Host smart-5e950576-d9b1-4e76-81d8-ba7184ea78e4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469707473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.469707473
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.147653062
Short name T266
Test name
Test status
Simulation time 35999655 ps
CPU time 2.4 seconds
Started Apr 30 12:32:08 PM PDT 24
Finished Apr 30 12:32:11 PM PDT 24
Peak memory 206372 kb
Host smart-ad175d45-dea3-4d7c-a289-36f82ff89cee
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147653062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.147653062
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.3606404668
Short name T486
Test name
Test status
Simulation time 907682471 ps
CPU time 21.92 seconds
Started Apr 30 12:30:50 PM PDT 24
Finished Apr 30 12:31:14 PM PDT 24
Peak memory 208264 kb
Host smart-dce327ea-d4ed-474d-a30a-e22bded8903c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606404668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.3606404668
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.3362608199
Short name T691
Test name
Test status
Simulation time 70966287 ps
CPU time 3.24 seconds
Started Apr 30 12:31:06 PM PDT 24
Finished Apr 30 12:31:10 PM PDT 24
Peak memory 213984 kb
Host smart-a1010b8d-af2d-42da-be94-ca9277fa97ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362608199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.3362608199
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.280969912
Short name T538
Test name
Test status
Simulation time 884205084 ps
CPU time 3.14 seconds
Started Apr 30 12:30:54 PM PDT 24
Finished Apr 30 12:30:59 PM PDT 24
Peak memory 207840 kb
Host smart-1782064a-7ffc-4d4e-adf9-0d32da0a5a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280969912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.280969912
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.2783705074
Short name T730
Test name
Test status
Simulation time 572834013 ps
CPU time 8.28 seconds
Started Apr 30 12:30:55 PM PDT 24
Finished Apr 30 12:31:04 PM PDT 24
Peak memory 219500 kb
Host smart-8d80002a-4b87-45c8-9e20-e734c026a78d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783705074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.2783705074
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.1785519075
Short name T110
Test name
Test status
Simulation time 117734242 ps
CPU time 3.85 seconds
Started Apr 30 12:30:59 PM PDT 24
Finished Apr 30 12:31:03 PM PDT 24
Peak memory 218172 kb
Host smart-ea5f0d6f-a628-4134-a594-309e26474400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785519075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.1785519075
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.2131818783
Short name T502
Test name
Test status
Simulation time 168308897 ps
CPU time 3.37 seconds
Started Apr 30 12:30:55 PM PDT 24
Finished Apr 30 12:31:00 PM PDT 24
Peak memory 209424 kb
Host smart-87532856-d2d0-4f20-a5ad-4fff9d5971d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131818783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.2131818783
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.686208120
Short name T702
Test name
Test status
Simulation time 11172189 ps
CPU time 0.71 seconds
Started Apr 30 12:31:03 PM PDT 24
Finished Apr 30 12:31:04 PM PDT 24
Peak memory 205604 kb
Host smart-4b6f13d8-e4c9-4899-b940-1a92c822e2b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686208120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.686208120
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.1101312626
Short name T861
Test name
Test status
Simulation time 63958931 ps
CPU time 2.39 seconds
Started Apr 30 12:30:56 PM PDT 24
Finished Apr 30 12:30:59 PM PDT 24
Peak memory 216416 kb
Host smart-e4cc648b-6e34-48eb-950e-8108250259f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101312626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.1101312626
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.1692993365
Short name T48
Test name
Test status
Simulation time 120209553 ps
CPU time 3.45 seconds
Started Apr 30 12:31:07 PM PDT 24
Finished Apr 30 12:31:11 PM PDT 24
Peak memory 208612 kb
Host smart-bb1082ae-9475-42f4-a587-3f8d9102b6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692993365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.1692993365
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.2589692674
Short name T501
Test name
Test status
Simulation time 238880506 ps
CPU time 3.36 seconds
Started Apr 30 12:30:55 PM PDT 24
Finished Apr 30 12:30:59 PM PDT 24
Peak memory 207952 kb
Host smart-b01fb0ab-83fa-4052-ae68-e40dc9e578a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589692674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.2589692674
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.3555113085
Short name T903
Test name
Test status
Simulation time 101469860 ps
CPU time 3.51 seconds
Started Apr 30 12:30:55 PM PDT 24
Finished Apr 30 12:31:00 PM PDT 24
Peak memory 219548 kb
Host smart-7f047096-1b6f-49d8-8cab-95dae6037d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555113085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.3555113085
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.1584291824
Short name T361
Test name
Test status
Simulation time 265277407 ps
CPU time 3.68 seconds
Started Apr 30 12:31:10 PM PDT 24
Finished Apr 30 12:31:14 PM PDT 24
Peak memory 207128 kb
Host smart-860560e7-8657-4fe0-9b87-5b7ee203387b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584291824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.1584291824
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.287779069
Short name T731
Test name
Test status
Simulation time 237759729 ps
CPU time 3.16 seconds
Started Apr 30 12:30:56 PM PDT 24
Finished Apr 30 12:31:01 PM PDT 24
Peak memory 206252 kb
Host smart-6e5d93c5-6ad8-4252-b7a6-51be18d63250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287779069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.287779069
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.3190276133
Short name T563
Test name
Test status
Simulation time 798510507 ps
CPU time 3.02 seconds
Started Apr 30 12:30:57 PM PDT 24
Finished Apr 30 12:31:01 PM PDT 24
Peak memory 208348 kb
Host smart-8d3b8a10-dcd9-4f21-90ef-d0a5b77c59fc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190276133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.3190276133
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.1049804241
Short name T17
Test name
Test status
Simulation time 36065770 ps
CPU time 2.43 seconds
Started Apr 30 12:31:03 PM PDT 24
Finished Apr 30 12:31:06 PM PDT 24
Peak memory 207840 kb
Host smart-aef9021a-2e65-4214-b51c-b311bddd91de
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049804241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.1049804241
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.2643391449
Short name T863
Test name
Test status
Simulation time 105581143 ps
CPU time 2.46 seconds
Started Apr 30 12:30:59 PM PDT 24
Finished Apr 30 12:31:03 PM PDT 24
Peak memory 208080 kb
Host smart-9b42c02b-414d-4a81-af6f-379e21431206
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643391449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.2643391449
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.3355250081
Short name T281
Test name
Test status
Simulation time 779023100 ps
CPU time 21.29 seconds
Started Apr 30 12:31:04 PM PDT 24
Finished Apr 30 12:31:26 PM PDT 24
Peak memory 209124 kb
Host smart-1ac187f2-c8a5-4f64-bfa1-620af1659b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355250081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.3355250081
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.2255776638
Short name T205
Test name
Test status
Simulation time 337419281 ps
CPU time 2.94 seconds
Started Apr 30 12:31:01 PM PDT 24
Finished Apr 30 12:31:05 PM PDT 24
Peak memory 206540 kb
Host smart-6eab24b4-63ad-4b52-ae16-e7bcb432ec7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255776638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.2255776638
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.2268206809
Short name T232
Test name
Test status
Simulation time 3458645797 ps
CPU time 114.72 seconds
Started Apr 30 12:30:57 PM PDT 24
Finished Apr 30 12:32:52 PM PDT 24
Peak memory 215676 kb
Host smart-66ac0af6-da3a-4cdf-8ef8-3cf94c23d4da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268206809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.2268206809
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.2172722074
Short name T209
Test name
Test status
Simulation time 114390459 ps
CPU time 4.51 seconds
Started Apr 30 12:30:59 PM PDT 24
Finished Apr 30 12:31:04 PM PDT 24
Peak memory 209444 kb
Host smart-3eab54d5-0d07-4020-b283-77feb7fdd6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172722074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.2172722074
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.2414809415
Short name T112
Test name
Test status
Simulation time 64114153 ps
CPU time 2.31 seconds
Started Apr 30 12:30:57 PM PDT 24
Finished Apr 30 12:31:01 PM PDT 24
Peak memory 210032 kb
Host smart-1f8f65bb-f869-4722-a3bd-1d8ab2b1907a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414809415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.2414809415
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.3672205186
Short name T490
Test name
Test status
Simulation time 52551861 ps
CPU time 0.71 seconds
Started Apr 30 12:31:16 PM PDT 24
Finished Apr 30 12:31:17 PM PDT 24
Peak memory 205576 kb
Host smart-9289f76d-d228-4b9d-be2c-cf19a07088e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672205186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.3672205186
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.4274811481
Short name T70
Test name
Test status
Simulation time 289049405 ps
CPU time 4.48 seconds
Started Apr 30 12:31:01 PM PDT 24
Finished Apr 30 12:31:06 PM PDT 24
Peak memory 213948 kb
Host smart-84255963-7a10-4994-9576-c3e0d0c16ba5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4274811481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.4274811481
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.1863251882
Short name T259
Test name
Test status
Simulation time 537937052 ps
CPU time 16.19 seconds
Started Apr 30 12:30:56 PM PDT 24
Finished Apr 30 12:31:13 PM PDT 24
Peak memory 220924 kb
Host smart-ee60a4d3-78b2-4e77-b67f-9285a66d27d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863251882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.1863251882
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.558301462
Short name T565
Test name
Test status
Simulation time 344712793 ps
CPU time 8.12 seconds
Started Apr 30 12:30:54 PM PDT 24
Finished Apr 30 12:31:03 PM PDT 24
Peak memory 207960 kb
Host smart-18c38520-2281-4417-83da-ca38999700b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558301462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.558301462
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.1064330631
Short name T708
Test name
Test status
Simulation time 11471989518 ps
CPU time 55.92 seconds
Started Apr 30 12:30:58 PM PDT 24
Finished Apr 30 12:31:54 PM PDT 24
Peak memory 217040 kb
Host smart-7e19009f-7f8a-4605-aebe-313127c61869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064330631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.1064330631
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.3128267940
Short name T105
Test name
Test status
Simulation time 362783051 ps
CPU time 3.19 seconds
Started Apr 30 12:31:17 PM PDT 24
Finished Apr 30 12:31:21 PM PDT 24
Peak memory 214240 kb
Host smart-b932182a-2498-4bfa-ba27-f530a2efc0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128267940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.3128267940
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_sideload.193463555
Short name T434
Test name
Test status
Simulation time 161112680 ps
CPU time 3.71 seconds
Started Apr 30 12:31:10 PM PDT 24
Finished Apr 30 12:31:15 PM PDT 24
Peak memory 206244 kb
Host smart-7245689a-297e-4b8a-9237-9b585e67f578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193463555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.193463555
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.3143252201
Short name T621
Test name
Test status
Simulation time 99793056 ps
CPU time 2.86 seconds
Started Apr 30 12:31:00 PM PDT 24
Finished Apr 30 12:31:04 PM PDT 24
Peak memory 208188 kb
Host smart-b6946fd1-3440-49ed-9a6e-33ec57a84658
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143252201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.3143252201
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.1686911968
Short name T804
Test name
Test status
Simulation time 333128066 ps
CPU time 4.59 seconds
Started Apr 30 12:30:59 PM PDT 24
Finished Apr 30 12:31:04 PM PDT 24
Peak memory 206216 kb
Host smart-f58fb757-f7a8-4a91-a74f-02fe962777c1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686911968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.1686911968
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.1162150084
Short name T651
Test name
Test status
Simulation time 60352159 ps
CPU time 2.22 seconds
Started Apr 30 12:30:54 PM PDT 24
Finished Apr 30 12:30:58 PM PDT 24
Peak memory 208516 kb
Host smart-3e6c8616-9994-4ffe-aa14-1f1dccc25e72
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162150084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.1162150084
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.1693028020
Short name T579
Test name
Test status
Simulation time 214483073 ps
CPU time 2.25 seconds
Started Apr 30 12:30:59 PM PDT 24
Finished Apr 30 12:31:02 PM PDT 24
Peak memory 207740 kb
Host smart-586d5364-9c31-43d1-839e-1ebe9f706074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693028020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.1693028020
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.2720019559
Short name T803
Test name
Test status
Simulation time 1635148155 ps
CPU time 35.8 seconds
Started Apr 30 12:31:10 PM PDT 24
Finished Apr 30 12:31:47 PM PDT 24
Peak memory 208244 kb
Host smart-51504e03-7e0d-4a62-a2a4-34ee6f19977d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720019559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.2720019559
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.3952434012
Short name T620
Test name
Test status
Simulation time 317509147 ps
CPU time 5 seconds
Started Apr 30 12:31:01 PM PDT 24
Finished Apr 30 12:31:07 PM PDT 24
Peak memory 206916 kb
Host smart-54c68d81-9d8f-42ce-8f70-1a04f5743610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952434012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.3952434012
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.890344510
Short name T137
Test name
Test status
Simulation time 111977136 ps
CPU time 3.81 seconds
Started Apr 30 12:31:00 PM PDT 24
Finished Apr 30 12:31:04 PM PDT 24
Peak memory 210152 kb
Host smart-cb4e319c-82a2-40ca-90ef-8bb5298d77cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890344510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.890344510
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.591972016
Short name T798
Test name
Test status
Simulation time 271298940 ps
CPU time 0.8 seconds
Started Apr 30 12:31:28 PM PDT 24
Finished Apr 30 12:31:29 PM PDT 24
Peak memory 205576 kb
Host smart-20e0c966-ecd1-4b43-b3f1-5d8e7194fc6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591972016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.591972016
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.701561314
Short name T808
Test name
Test status
Simulation time 202513542 ps
CPU time 3.38 seconds
Started Apr 30 12:31:07 PM PDT 24
Finished Apr 30 12:31:11 PM PDT 24
Peak memory 222096 kb
Host smart-0499df65-d13d-4941-b644-cee80a01926c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=701561314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.701561314
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.3775145627
Short name T746
Test name
Test status
Simulation time 307280402 ps
CPU time 2.71 seconds
Started Apr 30 12:31:01 PM PDT 24
Finished Apr 30 12:31:05 PM PDT 24
Peak memory 207468 kb
Host smart-7cf32d89-9c54-44d9-8f5f-a9ffb58f7399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775145627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.3775145627
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.3341011310
Short name T473
Test name
Test status
Simulation time 246977879 ps
CPU time 4.16 seconds
Started Apr 30 12:31:00 PM PDT 24
Finished Apr 30 12:31:05 PM PDT 24
Peak memory 209028 kb
Host smart-c605787d-0dbd-4462-8c45-ea6e61804c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341011310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.3341011310
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.746453569
Short name T96
Test name
Test status
Simulation time 5308897125 ps
CPU time 40.06 seconds
Started Apr 30 12:31:17 PM PDT 24
Finished Apr 30 12:31:57 PM PDT 24
Peak memory 222084 kb
Host smart-d9dace0e-4beb-4893-8518-231b6eacdc8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746453569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.746453569
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.3172777753
Short name T234
Test name
Test status
Simulation time 209316509 ps
CPU time 3.52 seconds
Started Apr 30 12:31:02 PM PDT 24
Finished Apr 30 12:31:07 PM PDT 24
Peak memory 209452 kb
Host smart-785ecdb2-4806-4548-ac58-9766225436f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172777753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.3172777753
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.3062193354
Short name T817
Test name
Test status
Simulation time 1041189778 ps
CPU time 12.09 seconds
Started Apr 30 12:30:59 PM PDT 24
Finished Apr 30 12:31:12 PM PDT 24
Peak memory 213940 kb
Host smart-2d7e097e-3d36-41c1-808e-cde0e7b6d1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062193354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.3062193354
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.2127903881
Short name T830
Test name
Test status
Simulation time 296191287 ps
CPU time 3.39 seconds
Started Apr 30 12:31:03 PM PDT 24
Finished Apr 30 12:31:07 PM PDT 24
Peak memory 207172 kb
Host smart-82118e05-7d6e-4a8a-9f1a-6926a3ef0184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127903881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.2127903881
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.2936425766
Short name T868
Test name
Test status
Simulation time 2077205969 ps
CPU time 53.06 seconds
Started Apr 30 12:31:24 PM PDT 24
Finished Apr 30 12:32:18 PM PDT 24
Peak memory 206728 kb
Host smart-018a3278-27e7-4c43-b04f-595e6527a801
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936425766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.2936425766
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.213435524
Short name T104
Test name
Test status
Simulation time 860588374 ps
CPU time 30.74 seconds
Started Apr 30 12:31:00 PM PDT 24
Finished Apr 30 12:31:32 PM PDT 24
Peak memory 207876 kb
Host smart-e1df2e48-2329-4700-935d-73eebc4f6f66
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213435524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.213435524
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.3374991402
Short name T101
Test name
Test status
Simulation time 201380781 ps
CPU time 2.35 seconds
Started Apr 30 12:31:22 PM PDT 24
Finished Apr 30 12:31:25 PM PDT 24
Peak memory 208640 kb
Host smart-df9e651c-6f95-420e-8560-9eb7c2a140b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374991402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.3374991402
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.4119710222
Short name T675
Test name
Test status
Simulation time 81766454 ps
CPU time 3.35 seconds
Started Apr 30 12:32:08 PM PDT 24
Finished Apr 30 12:32:12 PM PDT 24
Peak memory 208268 kb
Host smart-0628e37f-b512-45cb-b837-5d702d3bd63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119710222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.4119710222
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.1605404224
Short name T709
Test name
Test status
Simulation time 376135385 ps
CPU time 3.29 seconds
Started Apr 30 12:31:04 PM PDT 24
Finished Apr 30 12:31:08 PM PDT 24
Peak memory 207716 kb
Host smart-ea1297ee-5db7-4210-9362-2e8f72218fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605404224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.1605404224
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.2921352962
Short name T806
Test name
Test status
Simulation time 27037644 ps
CPU time 1.58 seconds
Started Apr 30 12:31:21 PM PDT 24
Finished Apr 30 12:31:23 PM PDT 24
Peak memory 209372 kb
Host smart-a518e445-510e-405e-8b14-685fd1b56813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921352962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.2921352962
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.1560081073
Short name T812
Test name
Test status
Simulation time 60616902 ps
CPU time 0.79 seconds
Started Apr 30 12:31:25 PM PDT 24
Finished Apr 30 12:31:26 PM PDT 24
Peak memory 205564 kb
Host smart-03e1d593-2414-412e-93b3-0db563ca712a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560081073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.1560081073
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.3005963731
Short name T397
Test name
Test status
Simulation time 1097806625 ps
CPU time 8.56 seconds
Started Apr 30 12:31:17 PM PDT 24
Finished Apr 30 12:31:26 PM PDT 24
Peak memory 215692 kb
Host smart-1e7f9d28-4a82-4e3c-8f9f-95deac774fdc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3005963731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.3005963731
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.1456717296
Short name T900
Test name
Test status
Simulation time 60321953 ps
CPU time 2.29 seconds
Started Apr 30 12:31:14 PM PDT 24
Finished Apr 30 12:31:17 PM PDT 24
Peak memory 221280 kb
Host smart-b9a392ee-c602-4948-8f9f-620c229b0d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456717296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.1456717296
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.3902960732
Short name T635
Test name
Test status
Simulation time 238795364 ps
CPU time 3.12 seconds
Started Apr 30 12:31:25 PM PDT 24
Finished Apr 30 12:31:29 PM PDT 24
Peak memory 214008 kb
Host smart-90b709b6-2bb0-4e93-bb11-3e500ccf00d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902960732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.3902960732
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.2081753468
Short name T82
Test name
Test status
Simulation time 927707072 ps
CPU time 6.84 seconds
Started Apr 30 12:31:02 PM PDT 24
Finished Apr 30 12:31:10 PM PDT 24
Peak memory 214056 kb
Host smart-f8598f98-3e6c-4d55-bd55-7cd3d80fff7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081753468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.2081753468
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_random.2765036778
Short name T687
Test name
Test status
Simulation time 207154647 ps
CPU time 3.07 seconds
Started Apr 30 12:31:11 PM PDT 24
Finished Apr 30 12:31:15 PM PDT 24
Peak memory 218384 kb
Host smart-c11ec91f-0021-46e0-84a8-37453263840a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765036778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.2765036778
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.2413725571
Short name T479
Test name
Test status
Simulation time 170262530 ps
CPU time 4.68 seconds
Started Apr 30 12:31:18 PM PDT 24
Finished Apr 30 12:31:24 PM PDT 24
Peak memory 208376 kb
Host smart-224fbfaf-3143-4588-89b4-94f856dd02fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413725571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.2413725571
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.2696660431
Short name T619
Test name
Test status
Simulation time 1556738782 ps
CPU time 3.04 seconds
Started Apr 30 12:31:21 PM PDT 24
Finished Apr 30 12:31:25 PM PDT 24
Peak memory 206944 kb
Host smart-0354c90e-49db-4351-8822-c0b9dd0f8784
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696660431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.2696660431
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.2275981508
Short name T433
Test name
Test status
Simulation time 223913715 ps
CPU time 2.04 seconds
Started Apr 30 12:31:08 PM PDT 24
Finished Apr 30 12:31:11 PM PDT 24
Peak memory 208248 kb
Host smart-f9d5ce87-a19e-4728-9cb2-043c8199d25b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275981508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.2275981508
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.1696041477
Short name T498
Test name
Test status
Simulation time 70152708 ps
CPU time 2.42 seconds
Started Apr 30 12:31:02 PM PDT 24
Finished Apr 30 12:31:05 PM PDT 24
Peak memory 208084 kb
Host smart-6bc5e230-2f29-4018-8763-403902ae27dd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696041477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.1696041477
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.1011042079
Short name T347
Test name
Test status
Simulation time 175501701 ps
CPU time 5.33 seconds
Started Apr 30 12:31:16 PM PDT 24
Finished Apr 30 12:31:22 PM PDT 24
Peak memory 214000 kb
Host smart-7d281c28-aafe-40fb-a4c6-c5da54757377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011042079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.1011042079
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.84090199
Short name T504
Test name
Test status
Simulation time 108999928 ps
CPU time 2.02 seconds
Started Apr 30 12:31:21 PM PDT 24
Finished Apr 30 12:31:23 PM PDT 24
Peak memory 206280 kb
Host smart-8aa5d218-299b-41cb-a187-60c5efc56ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84090199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.84090199
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.3765797311
Short name T190
Test name
Test status
Simulation time 1122826088 ps
CPU time 12.31 seconds
Started Apr 30 12:31:17 PM PDT 24
Finished Apr 30 12:31:30 PM PDT 24
Peak memory 219392 kb
Host smart-e204d1de-4959-425b-9312-90024b3f947e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765797311 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.3765797311
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.986588413
Short name T308
Test name
Test status
Simulation time 607262943 ps
CPU time 4.71 seconds
Started Apr 30 12:31:22 PM PDT 24
Finished Apr 30 12:31:27 PM PDT 24
Peak memory 213984 kb
Host smart-0a0223cd-a768-4578-b880-a2d6a3b68d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986588413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.986588413
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.3660407242
Short name T757
Test name
Test status
Simulation time 10096721912 ps
CPU time 30.32 seconds
Started Apr 30 12:31:13 PM PDT 24
Finished Apr 30 12:31:44 PM PDT 24
Peak memory 211312 kb
Host smart-cf9f1695-6a07-45fe-bdb9-37d40c1212b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660407242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.3660407242
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.3633592179
Short name T888
Test name
Test status
Simulation time 31958406 ps
CPU time 0.71 seconds
Started Apr 30 12:31:32 PM PDT 24
Finished Apr 30 12:31:34 PM PDT 24
Peak memory 205608 kb
Host smart-8ef82616-27a3-4953-ade2-3d0d8c101099
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633592179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.3633592179
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.3312910907
Short name T382
Test name
Test status
Simulation time 55028908 ps
CPU time 3.87 seconds
Started Apr 30 12:31:11 PM PDT 24
Finished Apr 30 12:31:16 PM PDT 24
Peak memory 214076 kb
Host smart-a2033e32-3f70-45f0-816c-f7b2ba0124b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3312910907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.3312910907
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.1966858353
Short name T29
Test name
Test status
Simulation time 4763155170 ps
CPU time 83.74 seconds
Started Apr 30 12:31:09 PM PDT 24
Finished Apr 30 12:32:34 PM PDT 24
Peak memory 222436 kb
Host smart-9e0f453b-4080-48b2-b38e-f80221fcc0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966858353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.1966858353
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.3801071050
Short name T489
Test name
Test status
Simulation time 452473114 ps
CPU time 2.95 seconds
Started Apr 30 12:31:22 PM PDT 24
Finished Apr 30 12:31:25 PM PDT 24
Peak memory 206896 kb
Host smart-7e359dc5-25fe-4401-aac3-f39c642df539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801071050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.3801071050
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.410922093
Short name T363
Test name
Test status
Simulation time 183243773 ps
CPU time 5.01 seconds
Started Apr 30 12:31:20 PM PDT 24
Finished Apr 30 12:31:25 PM PDT 24
Peak memory 209356 kb
Host smart-dc2d6ef9-56df-4774-9ac1-74c6524ae95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410922093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.410922093
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.2557743877
Short name T95
Test name
Test status
Simulation time 683035141 ps
CPU time 5.42 seconds
Started Apr 30 12:31:19 PM PDT 24
Finished Apr 30 12:31:25 PM PDT 24
Peak memory 210964 kb
Host smart-cf716170-073a-4323-8d86-6dba5f60ff22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557743877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.2557743877
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.2807982031
Short name T56
Test name
Test status
Simulation time 514347303 ps
CPU time 5.58 seconds
Started Apr 30 12:31:28 PM PDT 24
Finished Apr 30 12:31:34 PM PDT 24
Peak memory 219712 kb
Host smart-59bc05b5-8624-4510-bdc5-f2a0bfeb2a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807982031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.2807982031
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.3581111544
Short name T107
Test name
Test status
Simulation time 1292526196 ps
CPU time 13.01 seconds
Started Apr 30 12:31:20 PM PDT 24
Finished Apr 30 12:31:34 PM PDT 24
Peak memory 208756 kb
Host smart-df16f1a8-d680-4c56-bb0b-e74f64a526fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581111544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.3581111544
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.3755474628
Short name T217
Test name
Test status
Simulation time 115613872 ps
CPU time 3.03 seconds
Started Apr 30 12:31:09 PM PDT 24
Finished Apr 30 12:31:13 PM PDT 24
Peak memory 206256 kb
Host smart-49a3cb99-ef56-4a3a-86f2-5cc94db3d9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755474628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.3755474628
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.3370034357
Short name T418
Test name
Test status
Simulation time 83188055 ps
CPU time 1.91 seconds
Started Apr 30 12:31:20 PM PDT 24
Finished Apr 30 12:31:22 PM PDT 24
Peak memory 206392 kb
Host smart-0939192a-968d-4359-8951-979303356b0b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370034357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.3370034357
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.1271299311
Short name T844
Test name
Test status
Simulation time 1017155305 ps
CPU time 7.48 seconds
Started Apr 30 12:31:15 PM PDT 24
Finished Apr 30 12:31:24 PM PDT 24
Peak memory 208336 kb
Host smart-c0f3c687-a5b1-4fff-8c0f-bf7d5528c4c2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271299311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.1271299311
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.4089854900
Short name T573
Test name
Test status
Simulation time 676021015 ps
CPU time 5.44 seconds
Started Apr 30 12:31:10 PM PDT 24
Finished Apr 30 12:31:16 PM PDT 24
Peak memory 208364 kb
Host smart-a024da9e-5dd4-4010-a356-b8c3592640c2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089854900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.4089854900
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.3333340404
Short name T633
Test name
Test status
Simulation time 51147699 ps
CPU time 2.64 seconds
Started Apr 30 12:31:09 PM PDT 24
Finished Apr 30 12:31:12 PM PDT 24
Peak memory 215372 kb
Host smart-075c329b-2c15-4f82-94df-9a6998857f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333340404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.3333340404
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.1703634071
Short name T420
Test name
Test status
Simulation time 482566423 ps
CPU time 3.82 seconds
Started Apr 30 12:31:25 PM PDT 24
Finished Apr 30 12:31:30 PM PDT 24
Peak memory 207940 kb
Host smart-00b4c889-6fb7-410a-b5c7-b3845c53af7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703634071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.1703634071
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.2980414317
Short name T158
Test name
Test status
Simulation time 195767294 ps
CPU time 2.26 seconds
Started Apr 30 12:31:38 PM PDT 24
Finished Apr 30 12:31:41 PM PDT 24
Peak memory 209676 kb
Host smart-f43e2c20-c01b-4af3-a861-d5c83645ca9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980414317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.2980414317
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.3941316939
Short name T855
Test name
Test status
Simulation time 50278987 ps
CPU time 0.88 seconds
Started Apr 30 12:31:24 PM PDT 24
Finished Apr 30 12:31:26 PM PDT 24
Peak memory 205412 kb
Host smart-75e13b89-1a4b-437e-ac2d-22276617219f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941316939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.3941316939
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.63054527
Short name T542
Test name
Test status
Simulation time 640228689 ps
CPU time 4.97 seconds
Started Apr 30 12:31:26 PM PDT 24
Finished Apr 30 12:31:32 PM PDT 24
Peak memory 208520 kb
Host smart-b61b9288-ef63-49cc-b20f-b09762759fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63054527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.63054527
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.3088722582
Short name T50
Test name
Test status
Simulation time 998928460 ps
CPU time 4.65 seconds
Started Apr 30 12:31:23 PM PDT 24
Finished Apr 30 12:31:29 PM PDT 24
Peak memory 218128 kb
Host smart-ddc0c667-ed5b-4caa-ab36-61ccdc6e32ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088722582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.3088722582
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.3407410369
Short name T893
Test name
Test status
Simulation time 1383339537 ps
CPU time 6.91 seconds
Started Apr 30 12:31:34 PM PDT 24
Finished Apr 30 12:31:42 PM PDT 24
Peak memory 220964 kb
Host smart-21acf276-f649-4d47-acb3-e86bec465027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407410369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.3407410369
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.3479687617
Short name T554
Test name
Test status
Simulation time 152240230 ps
CPU time 3.23 seconds
Started Apr 30 12:31:32 PM PDT 24
Finished Apr 30 12:31:36 PM PDT 24
Peak memory 209592 kb
Host smart-85dd6fe9-52b5-42c6-9335-f1a272335fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479687617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.3479687617
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.2498957208
Short name T305
Test name
Test status
Simulation time 862613741 ps
CPU time 4.58 seconds
Started Apr 30 12:31:25 PM PDT 24
Finished Apr 30 12:31:30 PM PDT 24
Peak memory 209044 kb
Host smart-b85a0260-eda2-450b-b6cd-7c0ba143a70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498957208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.2498957208
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.1334329298
Short name T371
Test name
Test status
Simulation time 60549317 ps
CPU time 2.87 seconds
Started Apr 30 12:31:28 PM PDT 24
Finished Apr 30 12:31:31 PM PDT 24
Peak memory 208004 kb
Host smart-81270a3a-0280-4b7c-a2b8-10393c4cf1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334329298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.1334329298
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.2604286652
Short name T77
Test name
Test status
Simulation time 947920174 ps
CPU time 10.66 seconds
Started Apr 30 12:31:24 PM PDT 24
Finished Apr 30 12:31:35 PM PDT 24
Peak memory 208520 kb
Host smart-141e2d18-d60e-4f1f-a506-ddb3c1f3b23b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604286652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.2604286652
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.771357531
Short name T849
Test name
Test status
Simulation time 242693381 ps
CPU time 4.23 seconds
Started Apr 30 12:31:26 PM PDT 24
Finished Apr 30 12:31:31 PM PDT 24
Peak memory 206192 kb
Host smart-568088e6-1d13-4065-926e-3d0ce1053f19
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771357531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.771357531
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.2758695189
Short name T704
Test name
Test status
Simulation time 266620780 ps
CPU time 6.75 seconds
Started Apr 30 12:31:29 PM PDT 24
Finished Apr 30 12:31:37 PM PDT 24
Peak memory 208240 kb
Host smart-f7e7c642-cda7-4118-a717-5cb258601b5c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758695189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.2758695189
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.2454674922
Short name T456
Test name
Test status
Simulation time 34718334 ps
CPU time 2.49 seconds
Started Apr 30 12:31:22 PM PDT 24
Finished Apr 30 12:31:25 PM PDT 24
Peak memory 215436 kb
Host smart-bddedb01-7ff0-459c-bee1-dcd12739c1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454674922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.2454674922
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.2687693110
Short name T422
Test name
Test status
Simulation time 57728368 ps
CPU time 2.88 seconds
Started Apr 30 12:31:27 PM PDT 24
Finished Apr 30 12:31:30 PM PDT 24
Peak memory 207648 kb
Host smart-e6c958ae-58fc-44e6-b50e-572b6b666baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687693110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.2687693110
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.3652155432
Short name T482
Test name
Test status
Simulation time 43925479 ps
CPU time 3.08 seconds
Started Apr 30 12:31:21 PM PDT 24
Finished Apr 30 12:31:25 PM PDT 24
Peak memory 209784 kb
Host smart-e2d6ccc4-71b7-4fd2-8849-52a442034aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652155432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.3652155432
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.366573522
Short name T136
Test name
Test status
Simulation time 192680567 ps
CPU time 2.74 seconds
Started Apr 30 12:31:35 PM PDT 24
Finished Apr 30 12:31:39 PM PDT 24
Peak memory 209756 kb
Host smart-0c4e5e19-5ce2-458e-b20b-203554581877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366573522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.366573522
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.1966758689
Short name T643
Test name
Test status
Simulation time 78648449 ps
CPU time 0.76 seconds
Started Apr 30 12:31:41 PM PDT 24
Finished Apr 30 12:31:43 PM PDT 24
Peak memory 205548 kb
Host smart-b563bc7d-3f39-4f4c-97ab-cb2e40a75931
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966758689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.1966758689
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.752855268
Short name T8
Test name
Test status
Simulation time 2232317368 ps
CPU time 14.54 seconds
Started Apr 30 12:31:15 PM PDT 24
Finished Apr 30 12:31:30 PM PDT 24
Peak memory 219788 kb
Host smart-c6329560-fcdc-4856-8552-29fb6f8761b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752855268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.752855268
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.1153489341
Short name T859
Test name
Test status
Simulation time 78625246 ps
CPU time 2.38 seconds
Started Apr 30 12:31:40 PM PDT 24
Finished Apr 30 12:31:43 PM PDT 24
Peak memory 207048 kb
Host smart-2bc49c46-6e84-4bc5-a96b-b7144898c627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153489341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.1153489341
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.333160353
Short name T614
Test name
Test status
Simulation time 406385110 ps
CPU time 7.78 seconds
Started Apr 30 12:31:41 PM PDT 24
Finished Apr 30 12:31:50 PM PDT 24
Peak memory 208892 kb
Host smart-c1c4fab1-a61e-4a4c-bc60-1f53e17cc2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333160353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.333160353
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.172856523
Short name T276
Test name
Test status
Simulation time 873905733 ps
CPU time 9.88 seconds
Started Apr 30 12:31:20 PM PDT 24
Finished Apr 30 12:31:31 PM PDT 24
Peak memory 214148 kb
Host smart-4fd760a1-8a07-475c-8904-bbb407d2072c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172856523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.172856523
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.4290219675
Short name T57
Test name
Test status
Simulation time 75959118 ps
CPU time 4.75 seconds
Started Apr 30 12:31:20 PM PDT 24
Finished Apr 30 12:31:25 PM PDT 24
Peak memory 214160 kb
Host smart-cc1ce57b-d46b-4cc8-bd42-fba9a6ab51d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290219675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.4290219675
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.1159219267
Short name T488
Test name
Test status
Simulation time 43250470 ps
CPU time 2.38 seconds
Started Apr 30 12:31:34 PM PDT 24
Finished Apr 30 12:31:37 PM PDT 24
Peak memory 206744 kb
Host smart-8e757e4d-c4a1-4736-b7f8-5e6a75cb6424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159219267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.1159219267
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.2579902203
Short name T535
Test name
Test status
Simulation time 1332052553 ps
CPU time 41.01 seconds
Started Apr 30 12:31:24 PM PDT 24
Finished Apr 30 12:32:06 PM PDT 24
Peak memory 207864 kb
Host smart-e7986855-88e6-4875-a726-9f29db0439dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579902203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.2579902203
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.4109576605
Short name T735
Test name
Test status
Simulation time 61865034 ps
CPU time 3.03 seconds
Started Apr 30 12:31:28 PM PDT 24
Finished Apr 30 12:31:32 PM PDT 24
Peak memory 207964 kb
Host smart-446f6bf2-1a83-4488-9689-c0de8175b6d0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109576605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.4109576605
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.1468550880
Short name T597
Test name
Test status
Simulation time 22086958 ps
CPU time 1.99 seconds
Started Apr 30 12:31:28 PM PDT 24
Finished Apr 30 12:31:31 PM PDT 24
Peak memory 208312 kb
Host smart-ef884c3f-fb1a-437e-8f82-357ff097ca62
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468550880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.1468550880
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.3499806269
Short name T431
Test name
Test status
Simulation time 805600170 ps
CPU time 9.51 seconds
Started Apr 30 12:31:29 PM PDT 24
Finished Apr 30 12:31:39 PM PDT 24
Peak memory 207508 kb
Host smart-4dcff4a9-0940-4ef9-908a-d15b83d7afbc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499806269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.3499806269
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.2034436826
Short name T481
Test name
Test status
Simulation time 41039014 ps
CPU time 2.65 seconds
Started Apr 30 12:31:23 PM PDT 24
Finished Apr 30 12:31:27 PM PDT 24
Peak memory 215704 kb
Host smart-f4f20669-4e30-4377-9d13-34f16f2c58ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034436826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.2034436826
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.3684567510
Short name T713
Test name
Test status
Simulation time 82961652 ps
CPU time 2.92 seconds
Started Apr 30 12:31:29 PM PDT 24
Finished Apr 30 12:31:33 PM PDT 24
Peak memory 206240 kb
Host smart-f035b763-4cf2-411d-82c8-e168f8dcafb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684567510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.3684567510
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.3118561305
Short name T53
Test name
Test status
Simulation time 3161372798 ps
CPU time 27.73 seconds
Started Apr 30 12:31:29 PM PDT 24
Finished Apr 30 12:31:57 PM PDT 24
Peak memory 222132 kb
Host smart-5c6bb2df-9710-4e43-8d17-0f8c404a0428
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118561305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.3118561305
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.2082375388
Short name T186
Test name
Test status
Simulation time 1696469090 ps
CPU time 15.95 seconds
Started Apr 30 12:31:33 PM PDT 24
Finished Apr 30 12:31:50 PM PDT 24
Peak memory 222172 kb
Host smart-86888f4d-c96f-41b8-a0e1-c0863ebda966
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082375388 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.2082375388
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.3388335122
Short name T874
Test name
Test status
Simulation time 566286963 ps
CPU time 6.8 seconds
Started Apr 30 12:31:23 PM PDT 24
Finished Apr 30 12:31:31 PM PDT 24
Peak memory 207648 kb
Host smart-6bfe296b-1b85-4b4a-a26a-a60b2d5ba2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388335122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.3388335122
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.1028883335
Short name T45
Test name
Test status
Simulation time 275983735 ps
CPU time 2.42 seconds
Started Apr 30 12:31:21 PM PDT 24
Finished Apr 30 12:31:29 PM PDT 24
Peak memory 209488 kb
Host smart-2cf4c99e-e588-4262-81fd-ef57c3b2c5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028883335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.1028883335
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.2376191528
Short name T417
Test name
Test status
Simulation time 17185802 ps
CPU time 0.92 seconds
Started Apr 30 12:30:45 PM PDT 24
Finished Apr 30 12:30:47 PM PDT 24
Peak memory 205692 kb
Host smart-51a7027b-0a73-4c9b-b39e-826f29840a94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376191528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.2376191528
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.332511720
Short name T141
Test name
Test status
Simulation time 722146147 ps
CPU time 10.64 seconds
Started Apr 30 12:30:42 PM PDT 24
Finished Apr 30 12:30:54 PM PDT 24
Peak memory 213996 kb
Host smart-652cc24d-65dc-4a6e-8222-825a08a5bb6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=332511720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.332511720
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.1016909977
Short name T665
Test name
Test status
Simulation time 58197573 ps
CPU time 2.98 seconds
Started Apr 30 12:30:39 PM PDT 24
Finished Apr 30 12:30:43 PM PDT 24
Peak memory 209460 kb
Host smart-0dc772cf-3d2b-4c3d-9dc5-8d31889281da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016909977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.1016909977
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.2901417310
Short name T393
Test name
Test status
Simulation time 166261357 ps
CPU time 2.27 seconds
Started Apr 30 12:30:42 PM PDT 24
Finished Apr 30 12:30:45 PM PDT 24
Peak memory 213952 kb
Host smart-3023cb3f-6bbd-444a-8193-e33616f69444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901417310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.2901417310
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.3920928388
Short name T307
Test name
Test status
Simulation time 34048598 ps
CPU time 2.63 seconds
Started Apr 30 12:30:47 PM PDT 24
Finished Apr 30 12:30:51 PM PDT 24
Peak memory 208092 kb
Host smart-98e2a317-14bd-4671-b457-6f20975782d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920928388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.3920928388
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.821045169
Short name T685
Test name
Test status
Simulation time 176443608 ps
CPU time 6.09 seconds
Started Apr 30 12:30:46 PM PDT 24
Finished Apr 30 12:30:54 PM PDT 24
Peak memory 213964 kb
Host smart-dd8ab8ea-edb0-46cd-afb8-55c24c7d3702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821045169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.821045169
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.2415677065
Short name T44
Test name
Test status
Simulation time 1018252804 ps
CPU time 3.02 seconds
Started Apr 30 12:30:49 PM PDT 24
Finished Apr 30 12:30:53 PM PDT 24
Peak memory 214156 kb
Host smart-b0402381-ac20-4a43-870e-c4ab28c3b670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415677065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.2415677065
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.3741609669
Short name T543
Test name
Test status
Simulation time 687956073 ps
CPU time 5.79 seconds
Started Apr 30 12:30:47 PM PDT 24
Finished Apr 30 12:30:54 PM PDT 24
Peak memory 207612 kb
Host smart-0d8736d6-b704-43f6-abe0-8298f9b37e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741609669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.3741609669
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sideload.1458175952
Short name T435
Test name
Test status
Simulation time 162077259 ps
CPU time 3.47 seconds
Started Apr 30 12:30:43 PM PDT 24
Finished Apr 30 12:30:47 PM PDT 24
Peak memory 208300 kb
Host smart-0dcc80a3-416a-4cb4-be67-98dd10a6d337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458175952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.1458175952
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.251408675
Short name T660
Test name
Test status
Simulation time 214167245 ps
CPU time 2.69 seconds
Started Apr 30 12:30:42 PM PDT 24
Finished Apr 30 12:30:46 PM PDT 24
Peak memory 207596 kb
Host smart-d833f875-a2e3-4cfb-915f-2aef2b8575cc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251408675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.251408675
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.1818578101
Short name T436
Test name
Test status
Simulation time 26059435 ps
CPU time 1.98 seconds
Started Apr 30 12:30:41 PM PDT 24
Finished Apr 30 12:30:43 PM PDT 24
Peak memory 207984 kb
Host smart-de49b006-708a-4d13-a0ea-dd756aace94f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818578101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.1818578101
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.1161026428
Short name T446
Test name
Test status
Simulation time 265690331 ps
CPU time 3.93 seconds
Started Apr 30 12:30:47 PM PDT 24
Finished Apr 30 12:30:52 PM PDT 24
Peak memory 207332 kb
Host smart-7050ef65-439b-4332-81f7-8f9b55c87abf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161026428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.1161026428
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.3191627065
Short name T406
Test name
Test status
Simulation time 89997278 ps
CPU time 3.97 seconds
Started Apr 30 12:30:44 PM PDT 24
Finished Apr 30 12:30:49 PM PDT 24
Peak memory 208804 kb
Host smart-a0e5ec11-8684-4c4b-9c64-8e88943bdb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191627065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.3191627065
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.3850564896
Short name T483
Test name
Test status
Simulation time 59059844 ps
CPU time 2.92 seconds
Started Apr 30 12:30:39 PM PDT 24
Finished Apr 30 12:30:43 PM PDT 24
Peak memory 208024 kb
Host smart-790b82c8-332e-42c8-837c-ea6df816c2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850564896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.3850564896
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.4290012300
Short name T545
Test name
Test status
Simulation time 196974876 ps
CPU time 13.58 seconds
Started Apr 30 12:30:50 PM PDT 24
Finished Apr 30 12:31:05 PM PDT 24
Peak memory 222280 kb
Host smart-880f30ca-cd72-447e-b215-f0227e3c7a84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290012300 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.4290012300
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.311157654
Short name T669
Test name
Test status
Simulation time 160622643 ps
CPU time 4.44 seconds
Started Apr 30 12:30:33 PM PDT 24
Finished Apr 30 12:30:39 PM PDT 24
Peak memory 206896 kb
Host smart-9806f95c-704f-4b69-bf00-6bdbdbd0c20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311157654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.311157654
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.1740892009
Short name T55
Test name
Test status
Simulation time 96148097 ps
CPU time 3.67 seconds
Started Apr 30 12:30:42 PM PDT 24
Finished Apr 30 12:30:47 PM PDT 24
Peak memory 209956 kb
Host smart-e73044be-dad6-4abb-a2ea-37f3b7e0b599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740892009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.1740892009
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.3804394746
Short name T629
Test name
Test status
Simulation time 65931528 ps
CPU time 0.78 seconds
Started Apr 30 12:31:31 PM PDT 24
Finished Apr 30 12:31:33 PM PDT 24
Peak memory 205524 kb
Host smart-4678cd91-a5a2-441c-b2ff-81f874babbac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804394746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.3804394746
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.3725491732
Short name T33
Test name
Test status
Simulation time 332361985 ps
CPU time 4.57 seconds
Started Apr 30 12:31:31 PM PDT 24
Finished Apr 30 12:31:37 PM PDT 24
Peak memory 217988 kb
Host smart-4c170ea1-e2cf-42fb-a733-198e95a7d010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725491732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.3725491732
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.883266655
Short name T586
Test name
Test status
Simulation time 726056702 ps
CPU time 16.86 seconds
Started Apr 30 12:31:33 PM PDT 24
Finished Apr 30 12:31:50 PM PDT 24
Peak memory 207952 kb
Host smart-8bc96748-5cdd-40e1-96c8-d378097ed480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883266655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.883266655
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.3899391667
Short name T546
Test name
Test status
Simulation time 486356123 ps
CPU time 9.63 seconds
Started Apr 30 12:31:29 PM PDT 24
Finished Apr 30 12:31:40 PM PDT 24
Peak memory 213932 kb
Host smart-03fe3664-ca18-431b-936a-4e16a7e9b83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899391667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.3899391667
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.3365090000
Short name T270
Test name
Test status
Simulation time 1154098916 ps
CPU time 39.77 seconds
Started Apr 30 12:31:29 PM PDT 24
Finished Apr 30 12:32:09 PM PDT 24
Peak memory 222136 kb
Host smart-61e94cbe-b9d1-4927-a466-a2bfeba65e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365090000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.3365090000
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.665697079
Short name T328
Test name
Test status
Simulation time 278675270 ps
CPU time 3.27 seconds
Started Apr 30 12:31:28 PM PDT 24
Finished Apr 30 12:31:32 PM PDT 24
Peak memory 208004 kb
Host smart-df543b54-4976-4aa1-ae5d-b2fc70d8a1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665697079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.665697079
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.2098476271
Short name T289
Test name
Test status
Simulation time 200053447 ps
CPU time 4.37 seconds
Started Apr 30 12:31:41 PM PDT 24
Finished Apr 30 12:31:47 PM PDT 24
Peak memory 208380 kb
Host smart-10d71b8c-7e25-4366-a525-a07e9c88cc3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098476271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.2098476271
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.3314592703
Short name T524
Test name
Test status
Simulation time 53906834 ps
CPU time 2.9 seconds
Started Apr 30 12:31:30 PM PDT 24
Finished Apr 30 12:31:34 PM PDT 24
Peak memory 207080 kb
Host smart-29419477-d7e7-4732-a8d4-42924820294e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314592703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.3314592703
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.1073819252
Short name T526
Test name
Test status
Simulation time 1104665828 ps
CPU time 37.64 seconds
Started Apr 30 12:31:24 PM PDT 24
Finished Apr 30 12:32:03 PM PDT 24
Peak memory 207332 kb
Host smart-3c883642-efb3-4344-9b3d-3e84617d70c7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073819252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.1073819252
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.2922259982
Short name T666
Test name
Test status
Simulation time 490408994 ps
CPU time 2.45 seconds
Started Apr 30 12:31:33 PM PDT 24
Finished Apr 30 12:31:36 PM PDT 24
Peak memory 208332 kb
Host smart-9336ecf0-82bc-4306-b80f-feb27844dd0c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922259982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.2922259982
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.1949465169
Short name T574
Test name
Test status
Simulation time 48672357 ps
CPU time 2.78 seconds
Started Apr 30 12:31:31 PM PDT 24
Finished Apr 30 12:31:35 PM PDT 24
Peak memory 208224 kb
Host smart-df27120d-84f1-4cef-992b-3a8bccbb722d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949465169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.1949465169
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.2003930703
Short name T720
Test name
Test status
Simulation time 502025883 ps
CPU time 2.83 seconds
Started Apr 30 12:31:33 PM PDT 24
Finished Apr 30 12:31:36 PM PDT 24
Peak memory 209360 kb
Host smart-f650bee8-bb02-4a98-9b5c-bede5cce684f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003930703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.2003930703
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.783368315
Short name T198
Test name
Test status
Simulation time 694256862 ps
CPU time 4.97 seconds
Started Apr 30 12:31:39 PM PDT 24
Finished Apr 30 12:31:45 PM PDT 24
Peak memory 206232 kb
Host smart-b955fba1-1506-497a-8a35-4380732ecd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783368315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.783368315
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.2878443198
Short name T648
Test name
Test status
Simulation time 6890628194 ps
CPU time 204.85 seconds
Started Apr 30 12:31:26 PM PDT 24
Finished Apr 30 12:34:51 PM PDT 24
Peak memory 218432 kb
Host smart-25844d85-f037-44a4-8070-77b1a438b5f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878443198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.2878443198
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.1432923540
Short name T725
Test name
Test status
Simulation time 234737358 ps
CPU time 4 seconds
Started Apr 30 12:31:27 PM PDT 24
Finished Apr 30 12:31:32 PM PDT 24
Peak memory 213940 kb
Host smart-921b30bd-16cb-44b7-831e-e8dca7169048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432923540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.1432923540
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.667299655
Short name T577
Test name
Test status
Simulation time 1259987287 ps
CPU time 3.65 seconds
Started Apr 30 12:31:31 PM PDT 24
Finished Apr 30 12:31:36 PM PDT 24
Peak memory 209368 kb
Host smart-2ae4b0e0-f1e5-4dc4-bed2-e36959f2d596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667299655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.667299655
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.2752911332
Short name T791
Test name
Test status
Simulation time 40803046 ps
CPU time 0.86 seconds
Started Apr 30 12:31:40 PM PDT 24
Finished Apr 30 12:31:42 PM PDT 24
Peak memory 205680 kb
Host smart-b905d174-e125-4008-a397-efc977dfca53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752911332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.2752911332
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.3134146376
Short name T567
Test name
Test status
Simulation time 112651066 ps
CPU time 4.54 seconds
Started Apr 30 12:31:34 PM PDT 24
Finished Apr 30 12:31:39 PM PDT 24
Peak memory 217936 kb
Host smart-1ce30832-da76-482d-b239-686f3fa6d346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134146376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.3134146376
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.1955183336
Short name T14
Test name
Test status
Simulation time 347244976 ps
CPU time 2.46 seconds
Started Apr 30 12:31:42 PM PDT 24
Finished Apr 30 12:31:46 PM PDT 24
Peak memory 206920 kb
Host smart-bb2e0936-3506-458e-9026-05d997b495c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955183336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.1955183336
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.2547963170
Short name T319
Test name
Test status
Simulation time 388009113 ps
CPU time 10.15 seconds
Started Apr 30 12:31:36 PM PDT 24
Finished Apr 30 12:31:46 PM PDT 24
Peak memory 220692 kb
Host smart-3f92c84a-657d-4387-8b23-18566d2bcadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547963170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.2547963170
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_random.1193549238
Short name T324
Test name
Test status
Simulation time 910207209 ps
CPU time 10.65 seconds
Started Apr 30 12:31:40 PM PDT 24
Finished Apr 30 12:31:51 PM PDT 24
Peak memory 208920 kb
Host smart-1bae2a58-8d26-403c-b17a-1b59288d7424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193549238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.1193549238
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.1434550591
Short name T790
Test name
Test status
Simulation time 104000251 ps
CPU time 2.29 seconds
Started Apr 30 12:31:44 PM PDT 24
Finished Apr 30 12:31:48 PM PDT 24
Peak memory 206656 kb
Host smart-11d26c30-cd2c-44c3-a848-c884f9a92f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434550591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.1434550591
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.444496000
Short name T439
Test name
Test status
Simulation time 24781118 ps
CPU time 1.81 seconds
Started Apr 30 12:31:42 PM PDT 24
Finished Apr 30 12:31:46 PM PDT 24
Peak memory 206444 kb
Host smart-14f42979-9025-4fbd-bb43-b68c85f60c5b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444496000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.444496000
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.2763992307
Short name T551
Test name
Test status
Simulation time 273617113 ps
CPU time 2.89 seconds
Started Apr 30 12:31:39 PM PDT 24
Finished Apr 30 12:31:42 PM PDT 24
Peak memory 206264 kb
Host smart-a9dc9d35-ea5b-4ff3-b244-986620127482
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763992307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.2763992307
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.2192060114
Short name T632
Test name
Test status
Simulation time 54221051 ps
CPU time 2.96 seconds
Started Apr 30 12:31:36 PM PDT 24
Finished Apr 30 12:31:40 PM PDT 24
Peak memory 206504 kb
Host smart-6d5c264a-85e2-4dc3-9e0f-76767df99537
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192060114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.2192060114
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.1703733203
Short name T792
Test name
Test status
Simulation time 315338435 ps
CPU time 3.3 seconds
Started Apr 30 12:31:39 PM PDT 24
Finished Apr 30 12:31:43 PM PDT 24
Peak memory 208900 kb
Host smart-8893e9f0-09ca-471d-bd0f-a850870acc1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703733203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.1703733203
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.4271738714
Short name T766
Test name
Test status
Simulation time 68486435 ps
CPU time 2.49 seconds
Started Apr 30 12:31:39 PM PDT 24
Finished Apr 30 12:31:42 PM PDT 24
Peak memory 206288 kb
Host smart-19882496-1dc6-4101-a5c2-03e340dd0fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271738714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.4271738714
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.2363671485
Short name T130
Test name
Test status
Simulation time 3727927700 ps
CPU time 22.13 seconds
Started Apr 30 12:31:41 PM PDT 24
Finished Apr 30 12:32:04 PM PDT 24
Peak memory 221116 kb
Host smart-a662b1a8-80e2-470c-a49a-fbc558ca9795
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363671485 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.2363671485
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.2529609118
Short name T889
Test name
Test status
Simulation time 40150227 ps
CPU time 1.39 seconds
Started Apr 30 12:31:32 PM PDT 24
Finished Apr 30 12:31:34 PM PDT 24
Peak memory 210000 kb
Host smart-9437fb06-24f2-4ad4-86d2-557fc9e048c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529609118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.2529609118
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.3334674469
Short name T618
Test name
Test status
Simulation time 33925744 ps
CPU time 0.81 seconds
Started Apr 30 12:31:43 PM PDT 24
Finished Apr 30 12:31:45 PM PDT 24
Peak memory 205680 kb
Host smart-6e7a0338-70db-477d-b709-0040e795f27f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334674469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.3334674469
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.2055265662
Short name T150
Test name
Test status
Simulation time 45453351 ps
CPU time 3.33 seconds
Started Apr 30 12:31:39 PM PDT 24
Finished Apr 30 12:31:44 PM PDT 24
Peak memory 214016 kb
Host smart-ec781f9c-5e22-4b90-8c88-bb77b02d3979
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2055265662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.2055265662
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.665357806
Short name T534
Test name
Test status
Simulation time 328366028 ps
CPU time 3.6 seconds
Started Apr 30 12:31:31 PM PDT 24
Finished Apr 30 12:31:36 PM PDT 24
Peak memory 213980 kb
Host smart-879b5593-045b-4011-8f03-c0b435b65c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665357806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.665357806
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.912537136
Short name T78
Test name
Test status
Simulation time 2786600724 ps
CPU time 18.18 seconds
Started Apr 30 12:31:35 PM PDT 24
Finished Apr 30 12:31:54 PM PDT 24
Peak memory 208980 kb
Host smart-bd2a1a9a-1139-4be5-b891-cfd1c466573f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912537136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.912537136
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.3542529926
Short name T520
Test name
Test status
Simulation time 888035666 ps
CPU time 4.83 seconds
Started Apr 30 12:31:36 PM PDT 24
Finished Apr 30 12:31:41 PM PDT 24
Peak memory 209116 kb
Host smart-17ce0844-67dc-447f-a084-2fbfed6d460c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542529926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.3542529926
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.922526970
Short name T787
Test name
Test status
Simulation time 1247115810 ps
CPU time 7.96 seconds
Started Apr 30 12:31:34 PM PDT 24
Finished Apr 30 12:31:43 PM PDT 24
Peak memory 208292 kb
Host smart-5ed3ee3a-a5aa-456f-a156-dcbd5cfb71bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922526970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.922526970
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.1760533696
Short name T497
Test name
Test status
Simulation time 23196896 ps
CPU time 1.75 seconds
Started Apr 30 12:31:42 PM PDT 24
Finished Apr 30 12:31:46 PM PDT 24
Peak memory 206460 kb
Host smart-4d15c982-0f73-4b08-9ad6-fb9b6f6905f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760533696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.1760533696
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.3631826004
Short name T612
Test name
Test status
Simulation time 255251577 ps
CPU time 5.09 seconds
Started Apr 30 12:31:41 PM PDT 24
Finished Apr 30 12:31:47 PM PDT 24
Peak memory 206468 kb
Host smart-e2e5394d-4b43-4fa2-bdf7-5de6e3eec50c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631826004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.3631826004
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.302817268
Short name T678
Test name
Test status
Simulation time 38735089 ps
CPU time 2.34 seconds
Started Apr 30 12:31:42 PM PDT 24
Finished Apr 30 12:31:45 PM PDT 24
Peak memory 206424 kb
Host smart-508cd620-3ff6-44d4-9fc3-158dee29e33e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302817268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.302817268
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.1374792267
Short name T580
Test name
Test status
Simulation time 60016824 ps
CPU time 2.49 seconds
Started Apr 30 12:31:35 PM PDT 24
Finished Apr 30 12:31:38 PM PDT 24
Peak memory 206376 kb
Host smart-7c4e6f30-e419-4404-abc6-8000bf54e70a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374792267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.1374792267
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.3698484213
Short name T839
Test name
Test status
Simulation time 216462394 ps
CPU time 2.63 seconds
Started Apr 30 12:31:32 PM PDT 24
Finished Apr 30 12:31:35 PM PDT 24
Peak memory 209488 kb
Host smart-0cd021b2-0c88-4635-bfff-34237c3b23e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698484213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.3698484213
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.969875149
Short name T777
Test name
Test status
Simulation time 33046309 ps
CPU time 2.26 seconds
Started Apr 30 12:31:43 PM PDT 24
Finished Apr 30 12:31:47 PM PDT 24
Peak memory 206224 kb
Host smart-d0c0d397-862a-4611-b95a-dc6a5554d83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969875149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.969875149
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.3769950626
Short name T300
Test name
Test status
Simulation time 903767662 ps
CPU time 23.66 seconds
Started Apr 30 12:31:32 PM PDT 24
Finished Apr 30 12:31:57 PM PDT 24
Peak memory 216476 kb
Host smart-bb823db4-ffc3-4554-9ba0-758c1576ff3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769950626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.3769950626
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.1576346608
Short name T600
Test name
Test status
Simulation time 107248884 ps
CPU time 4.06 seconds
Started Apr 30 12:31:34 PM PDT 24
Finished Apr 30 12:31:39 PM PDT 24
Peak memory 208800 kb
Host smart-9958e936-23ab-4de5-ad9c-2c571c95e518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576346608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.1576346608
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.3842660503
Short name T722
Test name
Test status
Simulation time 88445900 ps
CPU time 0.86 seconds
Started Apr 30 12:31:37 PM PDT 24
Finished Apr 30 12:31:38 PM PDT 24
Peak memory 205616 kb
Host smart-c8912656-2776-46d8-8bdd-cf145b3ff059
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842660503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.3842660503
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.553349679
Short name T396
Test name
Test status
Simulation time 1802020268 ps
CPU time 27.58 seconds
Started Apr 30 12:31:38 PM PDT 24
Finished Apr 30 12:32:07 PM PDT 24
Peak memory 214484 kb
Host smart-0aebcb51-7134-442c-855c-217d88f86d92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=553349679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.553349679
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.1974635857
Short name T610
Test name
Test status
Simulation time 183972785 ps
CPU time 7.69 seconds
Started Apr 30 12:31:40 PM PDT 24
Finished Apr 30 12:31:49 PM PDT 24
Peak memory 221164 kb
Host smart-a7106a31-19a3-49cc-bcb0-b3607a9b6726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974635857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.1974635857
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.4180665427
Short name T723
Test name
Test status
Simulation time 3618918439 ps
CPU time 22.52 seconds
Started Apr 30 12:31:45 PM PDT 24
Finished Apr 30 12:32:09 PM PDT 24
Peak memory 214156 kb
Host smart-fe2a0d77-8bea-4e14-a6f2-d4f62c797a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180665427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.4180665427
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.2744254950
Short name T85
Test name
Test status
Simulation time 97531884 ps
CPU time 3.28 seconds
Started Apr 30 12:31:32 PM PDT 24
Finished Apr 30 12:31:36 PM PDT 24
Peak memory 208396 kb
Host smart-6c1b6ff4-2b4f-4372-b7bc-cbcbb9a96592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744254950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.2744254950
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.2191359359
Short name T550
Test name
Test status
Simulation time 135575339 ps
CPU time 3.75 seconds
Started Apr 30 12:31:33 PM PDT 24
Finished Apr 30 12:31:38 PM PDT 24
Peak memory 207140 kb
Host smart-3093488c-4cea-442d-8c1e-1c00e553e0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191359359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.2191359359
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.1373954134
Short name T699
Test name
Test status
Simulation time 480065772 ps
CPU time 4.51 seconds
Started Apr 30 12:31:33 PM PDT 24
Finished Apr 30 12:31:39 PM PDT 24
Peak memory 207640 kb
Host smart-3fb68f46-5486-4f2e-9e35-8add9317643c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373954134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.1373954134
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.305670071
Short name T843
Test name
Test status
Simulation time 50452901 ps
CPU time 2.91 seconds
Started Apr 30 12:31:35 PM PDT 24
Finished Apr 30 12:31:39 PM PDT 24
Peak memory 208056 kb
Host smart-e015d1ef-b4fe-441c-ade6-b14a8e2b3356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305670071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.305670071
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.1718156607
Short name T315
Test name
Test status
Simulation time 927823008 ps
CPU time 27.75 seconds
Started Apr 30 12:31:40 PM PDT 24
Finished Apr 30 12:32:09 PM PDT 24
Peak memory 208764 kb
Host smart-589e89fa-c055-4d69-b72a-361d69ec7827
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718156607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1718156607
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.549663533
Short name T560
Test name
Test status
Simulation time 2057520810 ps
CPU time 64.06 seconds
Started Apr 30 12:31:45 PM PDT 24
Finished Apr 30 12:32:51 PM PDT 24
Peak memory 208136 kb
Host smart-5d8d4b32-48db-4c8e-a427-b7eecef6979b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549663533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.549663533
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.1986863204
Short name T606
Test name
Test status
Simulation time 40313969 ps
CPU time 2.24 seconds
Started Apr 30 12:31:33 PM PDT 24
Finished Apr 30 12:31:36 PM PDT 24
Peak memory 206616 kb
Host smart-9e0fddba-b293-4b0c-b4c1-54ed263f9de6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986863204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.1986863204
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.218616103
Short name T773
Test name
Test status
Simulation time 309752833 ps
CPU time 3.62 seconds
Started Apr 30 12:31:38 PM PDT 24
Finished Apr 30 12:31:43 PM PDT 24
Peak memory 209284 kb
Host smart-53a09359-9e7a-44dc-8e45-8efce28be606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218616103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.218616103
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.4067602263
Short name T637
Test name
Test status
Simulation time 90506796 ps
CPU time 3.6 seconds
Started Apr 30 12:31:38 PM PDT 24
Finished Apr 30 12:31:43 PM PDT 24
Peak memory 208280 kb
Host smart-d46d5e82-fb4f-4d0a-9b58-b5c647bd8a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067602263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.4067602263
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.783600203
Short name T210
Test name
Test status
Simulation time 9516445594 ps
CPU time 42.61 seconds
Started Apr 30 12:31:32 PM PDT 24
Finished Apr 30 12:32:16 PM PDT 24
Peak memory 208044 kb
Host smart-9a75e39d-a488-48b3-ac3d-7d6946cb0cd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783600203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.783600203
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.1698271905
Short name T724
Test name
Test status
Simulation time 72078843 ps
CPU time 3.5 seconds
Started Apr 30 12:31:48 PM PDT 24
Finished Apr 30 12:31:52 PM PDT 24
Peak memory 207416 kb
Host smart-710c2521-db96-4a28-8a70-28ee3041bb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698271905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.1698271905
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.281043504
Short name T377
Test name
Test status
Simulation time 59000101 ps
CPU time 2.17 seconds
Started Apr 30 12:31:31 PM PDT 24
Finished Apr 30 12:31:34 PM PDT 24
Peak memory 209544 kb
Host smart-685d3ae3-35c8-401d-a7d6-c44c5c94cdd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281043504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.281043504
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.3315923606
Short name T196
Test name
Test status
Simulation time 20672931 ps
CPU time 0.71 seconds
Started Apr 30 12:31:41 PM PDT 24
Finished Apr 30 12:31:43 PM PDT 24
Peak memory 205600 kb
Host smart-379bc745-1d07-49d0-9a85-29464ecffd1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315923606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.3315923606
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.2094872927
Short name T373
Test name
Test status
Simulation time 860325135 ps
CPU time 2.73 seconds
Started Apr 30 12:31:48 PM PDT 24
Finished Apr 30 12:31:51 PM PDT 24
Peak memory 208816 kb
Host smart-f933ed04-c4bb-4d1a-b643-cc18d931731f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094872927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.2094872927
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.958313413
Short name T323
Test name
Test status
Simulation time 214622635 ps
CPU time 5.03 seconds
Started Apr 30 12:31:44 PM PDT 24
Finished Apr 30 12:31:50 PM PDT 24
Peak memory 214100 kb
Host smart-3813b96e-f9cb-4fc6-b485-4b61ae8d9a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958313413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.958313413
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.1195299813
Short name T233
Test name
Test status
Simulation time 143868664 ps
CPU time 2.71 seconds
Started Apr 30 12:31:43 PM PDT 24
Finished Apr 30 12:31:47 PM PDT 24
Peak memory 220112 kb
Host smart-cb1e3e23-84ea-4142-9cdc-6a7c7e199e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195299813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.1195299813
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.774284686
Short name T342
Test name
Test status
Simulation time 70341615 ps
CPU time 2.86 seconds
Started Apr 30 12:31:35 PM PDT 24
Finished Apr 30 12:31:39 PM PDT 24
Peak memory 207136 kb
Host smart-f9975244-7803-4b93-a826-43625b1dff2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774284686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.774284686
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.304034782
Short name T500
Test name
Test status
Simulation time 126057146 ps
CPU time 2.46 seconds
Started Apr 30 12:31:39 PM PDT 24
Finished Apr 30 12:31:43 PM PDT 24
Peak memory 207172 kb
Host smart-70976a2a-0716-480c-be62-ed90a4d7b5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304034782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.304034782
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.3725379047
Short name T278
Test name
Test status
Simulation time 325231587 ps
CPU time 3.66 seconds
Started Apr 30 12:31:38 PM PDT 24
Finished Apr 30 12:31:42 PM PDT 24
Peak memory 208336 kb
Host smart-611fdfc4-47bf-4d3a-b208-912510b7dae4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725379047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.3725379047
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.2129151017
Short name T512
Test name
Test status
Simulation time 685837475 ps
CPU time 16.84 seconds
Started Apr 30 12:31:32 PM PDT 24
Finished Apr 30 12:31:50 PM PDT 24
Peak memory 208384 kb
Host smart-e73ce88b-460b-4bc3-83a2-4444af505acb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129151017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.2129151017
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.2369927610
Short name T74
Test name
Test status
Simulation time 483299475 ps
CPU time 4.16 seconds
Started Apr 30 12:31:40 PM PDT 24
Finished Apr 30 12:31:45 PM PDT 24
Peak memory 208320 kb
Host smart-52252067-ff30-4c0b-9455-c53be3ecb4e2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369927610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.2369927610
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.1698291919
Short name T755
Test name
Test status
Simulation time 254978874 ps
CPU time 6.95 seconds
Started Apr 30 12:31:38 PM PDT 24
Finished Apr 30 12:31:46 PM PDT 24
Peak memory 209016 kb
Host smart-3b1241d1-8321-4294-a9e8-baaa988e0dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698291919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.1698291919
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.2304849411
Short name T640
Test name
Test status
Simulation time 7756454829 ps
CPU time 19.38 seconds
Started Apr 30 12:31:41 PM PDT 24
Finished Apr 30 12:32:01 PM PDT 24
Peak memory 208092 kb
Host smart-fc5a2421-532f-4319-a764-752604da7255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304849411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.2304849411
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.1722326417
Short name T469
Test name
Test status
Simulation time 422872889 ps
CPU time 7.08 seconds
Started Apr 30 12:31:44 PM PDT 24
Finished Apr 30 12:31:52 PM PDT 24
Peak memory 207648 kb
Host smart-1bf069b3-761a-4944-aabd-67023c11b26d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722326417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.1722326417
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.2229592238
Short name T846
Test name
Test status
Simulation time 709018313 ps
CPU time 12.38 seconds
Started Apr 30 12:31:42 PM PDT 24
Finished Apr 30 12:31:55 PM PDT 24
Peak memory 222412 kb
Host smart-aa586cd5-9a30-4a39-8919-580ad2b8a5b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229592238 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.2229592238
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.1081087577
Short name T714
Test name
Test status
Simulation time 90558247 ps
CPU time 3.87 seconds
Started Apr 30 12:31:38 PM PDT 24
Finished Apr 30 12:31:43 PM PDT 24
Peak memory 214248 kb
Host smart-b841bef0-b1e3-4c3d-bf3d-19dc6372768a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081087577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.1081087577
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.283439683
Short name T715
Test name
Test status
Simulation time 54820029 ps
CPU time 0.77 seconds
Started Apr 30 12:31:43 PM PDT 24
Finished Apr 30 12:31:45 PM PDT 24
Peak memory 205488 kb
Host smart-aeb7a6c8-1369-43b3-ae3b-5b90c6cecdf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283439683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.283439683
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.2073731902
Short name T16
Test name
Test status
Simulation time 93292724 ps
CPU time 3.45 seconds
Started Apr 30 12:31:42 PM PDT 24
Finished Apr 30 12:31:47 PM PDT 24
Peak memory 209392 kb
Host smart-7a0811f7-f30e-4f15-a8f4-b0e29b50a74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073731902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.2073731902
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.554982470
Short name T269
Test name
Test status
Simulation time 1242990864 ps
CPU time 13.31 seconds
Started Apr 30 12:31:42 PM PDT 24
Finished Apr 30 12:31:57 PM PDT 24
Peak memory 208880 kb
Host smart-fec26429-6419-408b-82c9-5c43a3a94c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554982470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.554982470
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.4202251334
Short name T317
Test name
Test status
Simulation time 1063307498 ps
CPU time 4.8 seconds
Started Apr 30 12:31:44 PM PDT 24
Finished Apr 30 12:31:50 PM PDT 24
Peak memory 220232 kb
Host smart-e307e7dc-f86c-4ab2-88a1-21701d137e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202251334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.4202251334
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.3615155942
Short name T457
Test name
Test status
Simulation time 350369456 ps
CPU time 3.65 seconds
Started Apr 30 12:31:48 PM PDT 24
Finished Apr 30 12:31:53 PM PDT 24
Peak memory 211312 kb
Host smart-1ec17a13-f223-4da6-ba67-07db5c4e47d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615155942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.3615155942
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.1895817163
Short name T250
Test name
Test status
Simulation time 37852944 ps
CPU time 2.49 seconds
Started Apr 30 12:31:42 PM PDT 24
Finished Apr 30 12:31:46 PM PDT 24
Peak memory 214092 kb
Host smart-f09ad5d2-9032-4235-8c93-90be9a6872fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895817163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.1895817163
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.3933643092
Short name T492
Test name
Test status
Simulation time 519562780 ps
CPU time 6.41 seconds
Started Apr 30 12:31:42 PM PDT 24
Finished Apr 30 12:31:50 PM PDT 24
Peak memory 209828 kb
Host smart-ef90c50a-01cc-4541-b653-2934c271d3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933643092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.3933643092
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.3318418955
Short name T306
Test name
Test status
Simulation time 87553222 ps
CPU time 2.66 seconds
Started Apr 30 12:31:47 PM PDT 24
Finished Apr 30 12:31:50 PM PDT 24
Peak memory 208168 kb
Host smart-3d3c43ed-a4e2-47cb-b267-43e7874ef0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318418955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.3318418955
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.1005941224
Short name T736
Test name
Test status
Simulation time 531389804 ps
CPU time 2.65 seconds
Started Apr 30 12:31:45 PM PDT 24
Finished Apr 30 12:31:49 PM PDT 24
Peak memory 206400 kb
Host smart-e892934d-b1e8-44bb-9ccf-de9c41d01269
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005941224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.1005941224
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.1662395737
Short name T608
Test name
Test status
Simulation time 94446669 ps
CPU time 2.72 seconds
Started Apr 30 12:31:45 PM PDT 24
Finished Apr 30 12:31:48 PM PDT 24
Peak memory 206832 kb
Host smart-ce0e0a34-24de-43d5-9e07-020f96ae1696
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662395737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.1662395737
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.3884771689
Short name T325
Test name
Test status
Simulation time 115840231 ps
CPU time 2.41 seconds
Started Apr 30 12:31:43 PM PDT 24
Finished Apr 30 12:31:47 PM PDT 24
Peak memory 206292 kb
Host smart-ecf848e6-79ad-4e66-90bd-003ffffdab4b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884771689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.3884771689
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.111967372
Short name T452
Test name
Test status
Simulation time 97119545 ps
CPU time 3.08 seconds
Started Apr 30 12:31:45 PM PDT 24
Finished Apr 30 12:31:49 PM PDT 24
Peak memory 208576 kb
Host smart-5bd9af3a-355b-4d56-aea1-dab171242e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111967372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.111967372
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.792810493
Short name T506
Test name
Test status
Simulation time 75410155 ps
CPU time 2.56 seconds
Started Apr 30 12:31:48 PM PDT 24
Finished Apr 30 12:31:52 PM PDT 24
Peak memory 206284 kb
Host smart-93688a08-a047-419a-a1d9-8e303f78a0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792810493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.792810493
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.679261881
Short name T309
Test name
Test status
Simulation time 660280558 ps
CPU time 7.56 seconds
Started Apr 30 12:31:43 PM PDT 24
Finished Apr 30 12:31:52 PM PDT 24
Peak memory 208396 kb
Host smart-26ab37b7-f688-4f4d-832b-4a9ae6d09f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679261881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.679261881
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.4128625942
Short name T752
Test name
Test status
Simulation time 657450199 ps
CPU time 9.47 seconds
Started Apr 30 12:31:42 PM PDT 24
Finished Apr 30 12:31:53 PM PDT 24
Peak memory 210276 kb
Host smart-b9f460d9-1360-4778-85e2-72057b31031b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128625942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.4128625942
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.292187395
Short name T98
Test name
Test status
Simulation time 34059509 ps
CPU time 0.83 seconds
Started Apr 30 12:31:46 PM PDT 24
Finished Apr 30 12:31:48 PM PDT 24
Peak memory 205540 kb
Host smart-cada14f4-7650-44b5-936b-893f479f8d84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292187395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.292187395
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.103246514
Short name T789
Test name
Test status
Simulation time 79695028 ps
CPU time 2.41 seconds
Started Apr 30 12:31:50 PM PDT 24
Finished Apr 30 12:31:54 PM PDT 24
Peak memory 207316 kb
Host smart-1af00ddc-5174-4cc4-874c-45d9a617de03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103246514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.103246514
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.466750807
Short name T841
Test name
Test status
Simulation time 201156057 ps
CPU time 5.4 seconds
Started Apr 30 12:31:43 PM PDT 24
Finished Apr 30 12:31:50 PM PDT 24
Peak memory 209476 kb
Host smart-c1474aff-436f-4431-bf29-11d1eb6cb956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466750807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.466750807
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.3427428593
Short name T367
Test name
Test status
Simulation time 33884184 ps
CPU time 2.35 seconds
Started Apr 30 12:31:39 PM PDT 24
Finished Apr 30 12:31:42 PM PDT 24
Peak memory 208728 kb
Host smart-f00de7bd-3f07-4dc2-8468-38f49d6b5a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427428593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.3427428593
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.3775722686
Short name T461
Test name
Test status
Simulation time 70267175 ps
CPU time 3.21 seconds
Started Apr 30 12:31:43 PM PDT 24
Finished Apr 30 12:31:48 PM PDT 24
Peak memory 209024 kb
Host smart-1c2ead48-25d6-4b57-ad41-d74cb5672e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775722686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.3775722686
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.2107171356
Short name T611
Test name
Test status
Simulation time 1903601365 ps
CPU time 33.04 seconds
Started Apr 30 12:31:41 PM PDT 24
Finished Apr 30 12:32:14 PM PDT 24
Peak memory 218744 kb
Host smart-d096b447-4eec-4f8d-a409-a7f7c76f8620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107171356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.2107171356
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.3667427262
Short name T223
Test name
Test status
Simulation time 126033883 ps
CPU time 1.92 seconds
Started Apr 30 12:31:45 PM PDT 24
Finished Apr 30 12:31:48 PM PDT 24
Peak memory 206284 kb
Host smart-6010d476-a29e-4cb4-8e46-10a0bafeaf41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667427262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.3667427262
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.2283112368
Short name T426
Test name
Test status
Simulation time 282540106 ps
CPU time 3.16 seconds
Started Apr 30 12:31:53 PM PDT 24
Finished Apr 30 12:31:57 PM PDT 24
Peak memory 208128 kb
Host smart-acdbcfaa-525f-4a85-9be0-e2caf3c774a9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283112368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.2283112368
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.2252558248
Short name T719
Test name
Test status
Simulation time 407270085 ps
CPU time 7.61 seconds
Started Apr 30 12:31:43 PM PDT 24
Finished Apr 30 12:31:52 PM PDT 24
Peak memory 207432 kb
Host smart-ef37c07e-01a9-402d-83f3-f61ee00c4467
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252558248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.2252558248
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.937985167
Short name T809
Test name
Test status
Simulation time 289541667 ps
CPU time 3.4 seconds
Started Apr 30 12:31:41 PM PDT 24
Finished Apr 30 12:31:45 PM PDT 24
Peak memory 206344 kb
Host smart-a3b70e69-ed3e-4a4c-9ee3-7ace35ede01b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937985167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.937985167
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.4275937917
Short name T352
Test name
Test status
Simulation time 45298265 ps
CPU time 3.06 seconds
Started Apr 30 12:31:43 PM PDT 24
Finished Apr 30 12:31:47 PM PDT 24
Peak memory 209328 kb
Host smart-57ac3c8d-8bac-4b94-9a0d-4b1352faf02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275937917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.4275937917
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.3427476575
Short name T531
Test name
Test status
Simulation time 50424583 ps
CPU time 2.39 seconds
Started Apr 30 12:31:43 PM PDT 24
Finished Apr 30 12:31:47 PM PDT 24
Peak memory 206328 kb
Host smart-265ca867-6fec-47d4-a53f-f86a7f357d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427476575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.3427476575
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.154772133
Short name T345
Test name
Test status
Simulation time 222829936 ps
CPU time 5.56 seconds
Started Apr 30 12:31:41 PM PDT 24
Finished Apr 30 12:31:48 PM PDT 24
Peak memory 209464 kb
Host smart-c322459f-841c-4230-950c-06a2e6ab805f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154772133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.154772133
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.4121322609
Short name T1
Test name
Test status
Simulation time 80916045 ps
CPU time 1.88 seconds
Started Apr 30 12:31:45 PM PDT 24
Finished Apr 30 12:31:48 PM PDT 24
Peak memory 209776 kb
Host smart-1f92924e-667a-4db0-b9c7-8223b3ea2ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121322609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.4121322609
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.3263637309
Short name T465
Test name
Test status
Simulation time 14326865 ps
CPU time 0.92 seconds
Started Apr 30 12:31:37 PM PDT 24
Finished Apr 30 12:31:39 PM PDT 24
Peak memory 205636 kb
Host smart-ace4433c-87f8-45aa-bec4-4f28a5c9cdb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263637309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.3263637309
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.1831432715
Short name T360
Test name
Test status
Simulation time 1026307499 ps
CPU time 55.52 seconds
Started Apr 30 12:31:42 PM PDT 24
Finished Apr 30 12:32:39 PM PDT 24
Peak memory 214864 kb
Host smart-e2b9ba38-eaf5-450a-a204-fc95a209a9e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1831432715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.1831432715
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.2246514318
Short name T22
Test name
Test status
Simulation time 971894371 ps
CPU time 2.85 seconds
Started Apr 30 12:31:46 PM PDT 24
Finished Apr 30 12:31:50 PM PDT 24
Peak memory 216460 kb
Host smart-a063c3fc-9654-4b28-b9b5-1c27501f98de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246514318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.2246514318
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.3712501896
Short name T256
Test name
Test status
Simulation time 142171441 ps
CPU time 2.08 seconds
Started Apr 30 12:31:45 PM PDT 24
Finished Apr 30 12:31:48 PM PDT 24
Peak memory 208644 kb
Host smart-2756b15f-c5bc-4e50-a1b6-5742f1daa961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712501896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.3712501896
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.635219120
Short name T294
Test name
Test status
Simulation time 1271411928 ps
CPU time 3.69 seconds
Started Apr 30 12:31:42 PM PDT 24
Finished Apr 30 12:31:47 PM PDT 24
Peak memory 209936 kb
Host smart-139b8810-9f35-4520-953e-7737b387cdf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635219120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.635219120
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_random.1318498488
Short name T668
Test name
Test status
Simulation time 2530573614 ps
CPU time 49.47 seconds
Started Apr 30 12:32:29 PM PDT 24
Finished Apr 30 12:33:19 PM PDT 24
Peak memory 219468 kb
Host smart-95d29a6d-ac92-48f3-92b0-c919bc187aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318498488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.1318498488
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.414908508
Short name T356
Test name
Test status
Simulation time 152118424 ps
CPU time 5.36 seconds
Started Apr 30 12:31:41 PM PDT 24
Finished Apr 30 12:31:48 PM PDT 24
Peak memory 207468 kb
Host smart-466aa2fd-dfa2-414d-8a07-2d09681301c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414908508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.414908508
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.2587114213
Short name T261
Test name
Test status
Simulation time 67966677 ps
CPU time 3.37 seconds
Started Apr 30 12:31:41 PM PDT 24
Finished Apr 30 12:31:46 PM PDT 24
Peak memory 208500 kb
Host smart-56e271c1-fe79-4399-8cde-d5afab491894
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587114213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.2587114213
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.2788317432
Short name T343
Test name
Test status
Simulation time 1614728970 ps
CPU time 18.43 seconds
Started Apr 30 12:31:50 PM PDT 24
Finished Apr 30 12:32:10 PM PDT 24
Peak memory 208456 kb
Host smart-fc331352-702f-4217-8752-b3f559645bc2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788317432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.2788317432
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.707757728
Short name T837
Test name
Test status
Simulation time 1050791632 ps
CPU time 3.99 seconds
Started Apr 30 12:31:43 PM PDT 24
Finished Apr 30 12:31:48 PM PDT 24
Peak memory 208288 kb
Host smart-65d6cd9b-b5b3-4dba-ad42-2c999bc7dfc4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707757728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.707757728
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.4163860161
Short name T248
Test name
Test status
Simulation time 63352003 ps
CPU time 1.57 seconds
Started Apr 30 12:31:43 PM PDT 24
Finished Apr 30 12:31:46 PM PDT 24
Peak memory 215248 kb
Host smart-3944562d-4aac-4b69-8025-0ebd708cb641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163860161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.4163860161
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.1394052108
Short name T721
Test name
Test status
Simulation time 696718409 ps
CPU time 5.13 seconds
Started Apr 30 12:31:46 PM PDT 24
Finished Apr 30 12:31:52 PM PDT 24
Peak memory 207748 kb
Host smart-52bf12f3-9987-4538-98a7-d6a5d2e77eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394052108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.1394052108
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.3396607748
Short name T189
Test name
Test status
Simulation time 584496721 ps
CPU time 10.81 seconds
Started Apr 30 12:31:42 PM PDT 24
Finished Apr 30 12:31:54 PM PDT 24
Peak memory 219112 kb
Host smart-0e11059e-964c-4e9c-a593-e41d63fc833b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396607748 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.3396607748
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.3593419547
Short name T364
Test name
Test status
Simulation time 77800280 ps
CPU time 2.8 seconds
Started Apr 30 12:31:45 PM PDT 24
Finished Apr 30 12:31:49 PM PDT 24
Peak memory 214008 kb
Host smart-80d063ac-8965-4689-a3e0-b96bbfc186bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593419547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.3593419547
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.2233206678
Short name T173
Test name
Test status
Simulation time 126271333 ps
CPU time 4.61 seconds
Started Apr 30 12:31:44 PM PDT 24
Finished Apr 30 12:31:50 PM PDT 24
Peak memory 209652 kb
Host smart-13292702-be55-4e6c-bf99-1c01cb757ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233206678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.2233206678
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.409681637
Short name T414
Test name
Test status
Simulation time 23403192 ps
CPU time 0.75 seconds
Started Apr 30 12:31:42 PM PDT 24
Finished Apr 30 12:31:45 PM PDT 24
Peak memory 205548 kb
Host smart-6572e716-a6fc-44fb-bbae-7e64945d34f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409681637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.409681637
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.1006068438
Short name T400
Test name
Test status
Simulation time 188232294 ps
CPU time 9.61 seconds
Started Apr 30 12:31:45 PM PDT 24
Finished Apr 30 12:31:56 PM PDT 24
Peak memory 214188 kb
Host smart-37cb35cc-61da-4a25-8263-8eff4b59080b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1006068438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.1006068438
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.4180897126
Short name T58
Test name
Test status
Simulation time 62755361 ps
CPU time 2.87 seconds
Started Apr 30 12:31:45 PM PDT 24
Finished Apr 30 12:31:49 PM PDT 24
Peak memory 209896 kb
Host smart-0e951154-3d43-4c07-b66a-ccd7270cdef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180897126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.4180897126
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.4038476642
Short name T754
Test name
Test status
Simulation time 65199591 ps
CPU time 3.15 seconds
Started Apr 30 12:31:42 PM PDT 24
Finished Apr 30 12:31:46 PM PDT 24
Peak memory 207776 kb
Host smart-1a426cba-8b20-41fc-99ff-a58c4ae27a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038476642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.4038476642
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.454517054
Short name T816
Test name
Test status
Simulation time 244641270 ps
CPU time 4.45 seconds
Started Apr 30 12:31:42 PM PDT 24
Finished Apr 30 12:31:48 PM PDT 24
Peak memory 218956 kb
Host smart-a3855587-8407-4f81-b41f-1624385b9630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454517054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.454517054
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.272904962
Short name T376
Test name
Test status
Simulation time 415109656 ps
CPU time 4.06 seconds
Started Apr 30 12:31:46 PM PDT 24
Finished Apr 30 12:31:51 PM PDT 24
Peak memory 213836 kb
Host smart-f8286e00-55a6-4ba3-b362-b72d03e53f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272904962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.272904962
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.2895885249
Short name T462
Test name
Test status
Simulation time 46033848 ps
CPU time 1.77 seconds
Started Apr 30 12:31:47 PM PDT 24
Finished Apr 30 12:31:50 PM PDT 24
Peak memory 215936 kb
Host smart-782f3c70-c8b8-4a3e-95a8-8be999871cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895885249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.2895885249
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.2784051760
Short name T267
Test name
Test status
Simulation time 3979365480 ps
CPU time 46.22 seconds
Started Apr 30 12:31:43 PM PDT 24
Finished Apr 30 12:32:30 PM PDT 24
Peak memory 213940 kb
Host smart-a4a697c4-3a17-41df-a3ab-e98e128304f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784051760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.2784051760
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.888609834
Short name T655
Test name
Test status
Simulation time 48660457 ps
CPU time 2.71 seconds
Started Apr 30 12:31:41 PM PDT 24
Finished Apr 30 12:31:45 PM PDT 24
Peak memory 208224 kb
Host smart-c7f1dfd5-3983-4204-b598-6a8ac6dff631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888609834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.888609834
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.3437465958
Short name T848
Test name
Test status
Simulation time 125031398 ps
CPU time 4.93 seconds
Started Apr 30 12:32:28 PM PDT 24
Finished Apr 30 12:32:33 PM PDT 24
Peak memory 206748 kb
Host smart-2f9bb7bf-00c4-4899-98ce-ee8adb8125bf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437465958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.3437465958
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.967378062
Short name T630
Test name
Test status
Simulation time 555310441 ps
CPU time 2.88 seconds
Started Apr 30 12:32:29 PM PDT 24
Finished Apr 30 12:32:32 PM PDT 24
Peak memory 207972 kb
Host smart-f96ed39b-9fc4-47c8-afcf-bb9da340d05d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967378062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.967378062
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.401696496
Short name T255
Test name
Test status
Simulation time 949282161 ps
CPU time 6.61 seconds
Started Apr 30 12:31:42 PM PDT 24
Finished Apr 30 12:31:49 PM PDT 24
Peak memory 207500 kb
Host smart-0e638a12-724c-473d-aaac-6e80723d9de6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401696496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.401696496
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.4035617897
Short name T712
Test name
Test status
Simulation time 310451901 ps
CPU time 2.76 seconds
Started Apr 30 12:31:43 PM PDT 24
Finished Apr 30 12:31:47 PM PDT 24
Peak memory 209528 kb
Host smart-5a691f8b-e169-42d4-bfad-156236282063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035617897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.4035617897
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.3031631233
Short name T432
Test name
Test status
Simulation time 44077708 ps
CPU time 2.26 seconds
Started Apr 30 12:31:42 PM PDT 24
Finished Apr 30 12:31:45 PM PDT 24
Peak memory 206400 kb
Host smart-5d031e84-2fb7-4b9a-86ec-570473b02fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031631233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.3031631233
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.1833548767
Short name T188
Test name
Test status
Simulation time 450022360 ps
CPU time 16.26 seconds
Started Apr 30 12:31:46 PM PDT 24
Finished Apr 30 12:32:03 PM PDT 24
Peak memory 222256 kb
Host smart-d182ca60-1cd4-4223-8644-a4c338146cee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833548767 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.1833548767
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.1089697566
Short name T353
Test name
Test status
Simulation time 103525673 ps
CPU time 4.85 seconds
Started Apr 30 12:31:50 PM PDT 24
Finished Apr 30 12:31:56 PM PDT 24
Peak memory 214036 kb
Host smart-ca29c37b-327d-46f8-8c7f-f40ba0a5213f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089697566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.1089697566
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.927948050
Short name T508
Test name
Test status
Simulation time 46390908 ps
CPU time 2.25 seconds
Started Apr 30 12:31:47 PM PDT 24
Finished Apr 30 12:31:50 PM PDT 24
Peak memory 209396 kb
Host smart-f8551ada-65cd-456a-9f4f-3e5970246c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927948050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.927948050
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.1286782053
Short name T827
Test name
Test status
Simulation time 15866149 ps
CPU time 0.76 seconds
Started Apr 30 12:31:52 PM PDT 24
Finished Apr 30 12:31:54 PM PDT 24
Peak memory 205616 kb
Host smart-4e95d355-25e2-46c2-8d31-6ad2f6b88dfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286782053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.1286782053
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.2076401677
Short name T398
Test name
Test status
Simulation time 83675304 ps
CPU time 4.95 seconds
Started Apr 30 12:32:01 PM PDT 24
Finished Apr 30 12:32:07 PM PDT 24
Peak memory 214696 kb
Host smart-5726f0ed-5182-47ba-843a-15c7fde9c0d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2076401677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.2076401677
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.2746746716
Short name T26
Test name
Test status
Simulation time 473776916 ps
CPU time 11.41 seconds
Started Apr 30 12:31:50 PM PDT 24
Finished Apr 30 12:32:03 PM PDT 24
Peak memory 214236 kb
Host smart-3d6dcd09-b5bf-43a6-af0d-664a8d0d5ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746746716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.2746746716
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.3845708262
Short name T440
Test name
Test status
Simulation time 129264038 ps
CPU time 2.13 seconds
Started Apr 30 12:31:52 PM PDT 24
Finished Apr 30 12:31:55 PM PDT 24
Peak memory 218048 kb
Host smart-ea907cad-d997-4479-9c63-ed8d024d42ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845708262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.3845708262
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.3876755596
Short name T330
Test name
Test status
Simulation time 56867203 ps
CPU time 3.19 seconds
Started Apr 30 12:31:53 PM PDT 24
Finished Apr 30 12:31:59 PM PDT 24
Peak memory 208164 kb
Host smart-36939040-8bce-49e3-a55f-cc09fdcbe1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876755596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.3876755596
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.3290268431
Short name T79
Test name
Test status
Simulation time 2570362441 ps
CPU time 19.72 seconds
Started Apr 30 12:31:51 PM PDT 24
Finished Apr 30 12:32:12 PM PDT 24
Peak memory 211704 kb
Host smart-9f081870-983a-4db9-b3c2-f34e02b8b429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290268431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.3290268431
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.3877080181
Short name T822
Test name
Test status
Simulation time 358419196 ps
CPU time 4.67 seconds
Started Apr 30 12:31:54 PM PDT 24
Finished Apr 30 12:32:00 PM PDT 24
Peak memory 209040 kb
Host smart-6136c974-7682-40a2-8db9-1036dd710ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877080181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.3877080181
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.1224759726
Short name T872
Test name
Test status
Simulation time 271763372 ps
CPU time 4.94 seconds
Started Apr 30 12:31:53 PM PDT 24
Finished Apr 30 12:32:00 PM PDT 24
Peak memory 209448 kb
Host smart-ee81a491-50f1-41b8-8575-595811cf5183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224759726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.1224759726
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.755026022
Short name T334
Test name
Test status
Simulation time 150813813 ps
CPU time 4.31 seconds
Started Apr 30 12:31:47 PM PDT 24
Finished Apr 30 12:31:52 PM PDT 24
Peak memory 208036 kb
Host smart-1fcc811d-c4e9-4485-9192-21c9112b32e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755026022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.755026022
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.1294055470
Short name T824
Test name
Test status
Simulation time 193817188 ps
CPU time 2.76 seconds
Started Apr 30 12:31:41 PM PDT 24
Finished Apr 30 12:31:45 PM PDT 24
Peak memory 206300 kb
Host smart-7135b84e-12ac-4728-bef5-301ca8af787d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294055470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.1294055470
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.131364011
Short name T624
Test name
Test status
Simulation time 344119870 ps
CPU time 6.43 seconds
Started Apr 30 12:31:46 PM PDT 24
Finished Apr 30 12:31:54 PM PDT 24
Peak memory 207892 kb
Host smart-28d43f58-de24-4912-8ac0-86e2d498927e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131364011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.131364011
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.2541783065
Short name T463
Test name
Test status
Simulation time 449156627 ps
CPU time 11.63 seconds
Started Apr 30 12:31:46 PM PDT 24
Finished Apr 30 12:31:58 PM PDT 24
Peak memory 207516 kb
Host smart-3e98b210-9e79-4b52-ba67-773307d50e65
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541783065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.2541783065
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.3490464867
Short name T510
Test name
Test status
Simulation time 1235422356 ps
CPU time 6.66 seconds
Started Apr 30 12:31:46 PM PDT 24
Finished Apr 30 12:31:53 PM PDT 24
Peak memory 207908 kb
Host smart-300455bc-f88a-4671-a794-36121701ae85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490464867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.3490464867
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.766690992
Short name T686
Test name
Test status
Simulation time 1708313684 ps
CPU time 41.18 seconds
Started Apr 30 12:31:44 PM PDT 24
Finished Apr 30 12:32:26 PM PDT 24
Peak memory 207972 kb
Host smart-d4ee3f6e-7e34-495a-a419-2da6f17b9f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766690992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.766690992
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.1309543837
Short name T835
Test name
Test status
Simulation time 1045380015 ps
CPU time 20.38 seconds
Started Apr 30 12:31:52 PM PDT 24
Finished Apr 30 12:32:14 PM PDT 24
Peak memory 218700 kb
Host smart-b94e3e37-1d91-455e-9ced-f3957257c680
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309543837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.1309543837
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.644456302
Short name T335
Test name
Test status
Simulation time 910652301 ps
CPU time 10.57 seconds
Started Apr 30 12:31:52 PM PDT 24
Finished Apr 30 12:32:04 PM PDT 24
Peak memory 214028 kb
Host smart-d6efbedc-24f0-4f97-a08d-daff0fd10072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644456302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.644456302
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.3970799934
Short name T733
Test name
Test status
Simulation time 121509503 ps
CPU time 2.23 seconds
Started Apr 30 12:31:51 PM PDT 24
Finished Apr 30 12:31:55 PM PDT 24
Peak memory 209412 kb
Host smart-c48d2d6d-f967-46de-a182-c8e0b916d9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970799934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.3970799934
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.1513873050
Short name T592
Test name
Test status
Simulation time 51553559 ps
CPU time 0.85 seconds
Started Apr 30 12:30:51 PM PDT 24
Finished Apr 30 12:30:54 PM PDT 24
Peak memory 205556 kb
Host smart-68732591-b5f8-4870-bdd0-81b39116cb73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513873050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.1513873050
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.1668878680
Short name T537
Test name
Test status
Simulation time 54265842 ps
CPU time 1.78 seconds
Started Apr 30 12:30:40 PM PDT 24
Finished Apr 30 12:30:43 PM PDT 24
Peak memory 209380 kb
Host smart-f869ebd7-8f94-4e56-8a1d-8f8268c8e082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668878680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.1668878680
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.4230013372
Short name T60
Test name
Test status
Simulation time 66387489 ps
CPU time 2.49 seconds
Started Apr 30 12:30:46 PM PDT 24
Finished Apr 30 12:30:50 PM PDT 24
Peak memory 214112 kb
Host smart-c9b1727d-ec35-4585-add5-4bd2fecd870d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230013372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.4230013372
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.2884608486
Short name T91
Test name
Test status
Simulation time 306287240 ps
CPU time 5.36 seconds
Started Apr 30 12:30:43 PM PDT 24
Finished Apr 30 12:30:50 PM PDT 24
Peak memory 213944 kb
Host smart-b4b1d7b8-e464-48d8-b170-f9d9cbf4aa40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884608486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.2884608486
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.2551642296
Short name T764
Test name
Test status
Simulation time 59401900 ps
CPU time 3.12 seconds
Started Apr 30 12:30:44 PM PDT 24
Finished Apr 30 12:30:48 PM PDT 24
Peak memory 214096 kb
Host smart-9b2890c9-c188-4c42-be4a-bb35ea98adf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551642296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.2551642296
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.376888517
Short name T800
Test name
Test status
Simulation time 196585584 ps
CPU time 2.72 seconds
Started Apr 30 12:30:50 PM PDT 24
Finished Apr 30 12:30:54 PM PDT 24
Peak memory 219984 kb
Host smart-6b54ca75-c6ab-41b0-85aa-d05f16bc3c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376888517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.376888517
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.3244356744
Short name T131
Test name
Test status
Simulation time 229071415 ps
CPU time 9.03 seconds
Started Apr 30 12:30:40 PM PDT 24
Finished Apr 30 12:30:50 PM PDT 24
Peak memory 208328 kb
Host smart-df0dd0aa-3723-481a-9af1-35ee32671a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244356744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.3244356744
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.598601247
Short name T11
Test name
Test status
Simulation time 1486272658 ps
CPU time 10.33 seconds
Started Apr 30 12:30:46 PM PDT 24
Finished Apr 30 12:30:58 PM PDT 24
Peak memory 237388 kb
Host smart-d700c5d0-a268-4d39-8653-45222e7a4a02
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598601247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.598601247
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.3808708839
Short name T204
Test name
Test status
Simulation time 145040296 ps
CPU time 3.36 seconds
Started Apr 30 12:30:43 PM PDT 24
Finished Apr 30 12:30:48 PM PDT 24
Peak memory 208224 kb
Host smart-681b9971-f456-4467-b677-12f38f05bf35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808708839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.3808708839
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.3023942734
Short name T802
Test name
Test status
Simulation time 5694436361 ps
CPU time 41.8 seconds
Started Apr 30 12:30:43 PM PDT 24
Finished Apr 30 12:31:26 PM PDT 24
Peak memory 208628 kb
Host smart-ed02fabe-5eb0-4a44-936a-0d59e206d4a5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023942734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.3023942734
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.1996342292
Short name T484
Test name
Test status
Simulation time 52470539 ps
CPU time 2.67 seconds
Started Apr 30 12:30:46 PM PDT 24
Finished Apr 30 12:30:51 PM PDT 24
Peak memory 206492 kb
Host smart-279ee788-e7bb-4e10-8f0e-6e717602355c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996342292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.1996342292
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.2248689502
Short name T285
Test name
Test status
Simulation time 550420207 ps
CPU time 18.02 seconds
Started Apr 30 12:30:46 PM PDT 24
Finished Apr 30 12:31:06 PM PDT 24
Peak memory 207592 kb
Host smart-a532f345-8f80-48ff-819a-8729a1ce9510
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248689502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.2248689502
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.637622042
Short name T645
Test name
Test status
Simulation time 65811576 ps
CPU time 1.48 seconds
Started Apr 30 12:30:46 PM PDT 24
Finished Apr 30 12:30:49 PM PDT 24
Peak memory 206916 kb
Host smart-1245e065-881d-4253-9a08-388b1f388745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637622042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.637622042
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.2979520995
Short name T595
Test name
Test status
Simulation time 2092758611 ps
CPU time 15.59 seconds
Started Apr 30 12:30:50 PM PDT 24
Finished Apr 30 12:31:07 PM PDT 24
Peak memory 207708 kb
Host smart-ada4322d-91a2-4c1d-a910-ad9076e09fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979520995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.2979520995
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.2410767252
Short name T671
Test name
Test status
Simulation time 24658481952 ps
CPU time 157.36 seconds
Started Apr 30 12:30:44 PM PDT 24
Finished Apr 30 12:33:22 PM PDT 24
Peak memory 216236 kb
Host smart-bc6f25d3-1956-488d-9bab-f2641c406c93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410767252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.2410767252
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.2502156433
Short name T631
Test name
Test status
Simulation time 78312007 ps
CPU time 4.3 seconds
Started Apr 30 12:30:45 PM PDT 24
Finished Apr 30 12:30:50 PM PDT 24
Peak memory 206964 kb
Host smart-4bba4a78-7304-46d5-8f10-da5b9058fbfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502156433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.2502156433
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.656931835
Short name T901
Test name
Test status
Simulation time 95183219 ps
CPU time 2.88 seconds
Started Apr 30 12:30:50 PM PDT 24
Finished Apr 30 12:30:54 PM PDT 24
Peak memory 209832 kb
Host smart-c065e588-fdcb-498d-b2dc-dad3c7f1875b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656931835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.656931835
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.3549001743
Short name T870
Test name
Test status
Simulation time 10118305 ps
CPU time 0.69 seconds
Started Apr 30 12:31:56 PM PDT 24
Finished Apr 30 12:31:58 PM PDT 24
Peak memory 205496 kb
Host smart-08f960cf-5029-48ad-a575-268e4541d89b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549001743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.3549001743
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.306854317
Short name T118
Test name
Test status
Simulation time 239088746 ps
CPU time 13.29 seconds
Started Apr 30 12:31:53 PM PDT 24
Finished Apr 30 12:32:09 PM PDT 24
Peak memory 214076 kb
Host smart-02a28595-5934-4793-926e-eed8dfa9c331
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=306854317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.306854317
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.1209670789
Short name T749
Test name
Test status
Simulation time 31871835 ps
CPU time 1.46 seconds
Started Apr 30 12:31:49 PM PDT 24
Finished Apr 30 12:31:52 PM PDT 24
Peak memory 207236 kb
Host smart-5d5066ef-53b1-49cf-a9f9-76801f314047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209670789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.1209670789
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.1372599097
Short name T299
Test name
Test status
Simulation time 250958567 ps
CPU time 3.04 seconds
Started Apr 30 12:31:54 PM PDT 24
Finished Apr 30 12:31:59 PM PDT 24
Peak memory 214216 kb
Host smart-ddb81dec-ad02-4028-b600-60950ad13490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372599097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.1372599097
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.136191815
Short name T884
Test name
Test status
Simulation time 224062060 ps
CPU time 4.31 seconds
Started Apr 30 12:31:55 PM PDT 24
Finished Apr 30 12:32:02 PM PDT 24
Peak memory 209704 kb
Host smart-7b74a3e7-6b16-4327-9ad2-117f28b7a8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136191815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.136191815
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.874970814
Short name T821
Test name
Test status
Simulation time 263489527 ps
CPU time 3.54 seconds
Started Apr 30 12:31:50 PM PDT 24
Finished Apr 30 12:31:54 PM PDT 24
Peak memory 208276 kb
Host smart-ba961a40-cb5a-44fd-ad6d-8cf0692410cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874970814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.874970814
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.2779024299
Short name T745
Test name
Test status
Simulation time 413524824 ps
CPU time 4.47 seconds
Started Apr 30 12:31:55 PM PDT 24
Finished Apr 30 12:32:01 PM PDT 24
Peak memory 209928 kb
Host smart-7fc7083e-d474-417b-aeb2-a56056250413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779024299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.2779024299
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.1504992089
Short name T472
Test name
Test status
Simulation time 153657178 ps
CPU time 5.17 seconds
Started Apr 30 12:31:55 PM PDT 24
Finished Apr 30 12:32:03 PM PDT 24
Peak memory 208236 kb
Host smart-84118306-83d8-4610-980b-b22031bede50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504992089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.1504992089
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.2421371901
Short name T748
Test name
Test status
Simulation time 224555049 ps
CPU time 7.92 seconds
Started Apr 30 12:31:52 PM PDT 24
Finished Apr 30 12:32:02 PM PDT 24
Peak memory 208420 kb
Host smart-f7d4dd08-8f14-44f7-8151-6e85f17b5455
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421371901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.2421371901
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.1170310026
Short name T799
Test name
Test status
Simulation time 75164514 ps
CPU time 3.78 seconds
Started Apr 30 12:31:52 PM PDT 24
Finished Apr 30 12:31:57 PM PDT 24
Peak memory 208440 kb
Host smart-ae55afe4-a899-4d3a-bf44-f81e21ddcb00
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170310026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.1170310026
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.2744589267
Short name T572
Test name
Test status
Simulation time 32540897 ps
CPU time 2.37 seconds
Started Apr 30 12:31:46 PM PDT 24
Finished Apr 30 12:31:49 PM PDT 24
Peak memory 206592 kb
Host smart-0766ce4f-41fc-4b2b-843d-c6428ab34685
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744589267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.2744589267
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.143346004
Short name T279
Test name
Test status
Simulation time 273110224 ps
CPU time 3.1 seconds
Started Apr 30 12:31:54 PM PDT 24
Finished Apr 30 12:31:59 PM PDT 24
Peak memory 213952 kb
Host smart-871f62e6-7856-49b7-aca9-2df97e469059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143346004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.143346004
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.1984857068
Short name T192
Test name
Test status
Simulation time 18804931 ps
CPU time 1.68 seconds
Started Apr 30 12:31:52 PM PDT 24
Finished Apr 30 12:31:55 PM PDT 24
Peak memory 206328 kb
Host smart-27f5b773-cb19-4619-a120-d8e3e22c4b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984857068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.1984857068
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.1745103031
Short name T753
Test name
Test status
Simulation time 1339054332 ps
CPU time 8.3 seconds
Started Apr 30 12:31:52 PM PDT 24
Finished Apr 30 12:32:03 PM PDT 24
Peak memory 207668 kb
Host smart-c76f91b4-7808-4d7e-aec4-9c008f74ce56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745103031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.1745103031
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.1775794253
Short name T46
Test name
Test status
Simulation time 55829964 ps
CPU time 1.84 seconds
Started Apr 30 12:31:51 PM PDT 24
Finished Apr 30 12:31:54 PM PDT 24
Peak memory 209460 kb
Host smart-9677d6dd-a1a9-4e97-81ec-d590041d19cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775794253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.1775794253
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.739039916
Short name T544
Test name
Test status
Simulation time 66961705 ps
CPU time 0.84 seconds
Started Apr 30 12:32:06 PM PDT 24
Finished Apr 30 12:32:07 PM PDT 24
Peak memory 205564 kb
Host smart-d6bbf00e-7e71-4492-8553-b7118bf5b72e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739039916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.739039916
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.1536854042
Short name T871
Test name
Test status
Simulation time 32034059 ps
CPU time 2.67 seconds
Started Apr 30 12:31:54 PM PDT 24
Finished Apr 30 12:31:59 PM PDT 24
Peak memory 214020 kb
Host smart-da53204a-bbde-458e-a0df-39c89d863448
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1536854042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.1536854042
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.2082122135
Short name T890
Test name
Test status
Simulation time 436276546 ps
CPU time 12.11 seconds
Started Apr 30 12:31:54 PM PDT 24
Finished Apr 30 12:32:08 PM PDT 24
Peak memory 209756 kb
Host smart-e5b97e97-9408-4ff0-a077-5a783df33318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082122135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.2082122135
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.1423024125
Short name T831
Test name
Test status
Simulation time 4726459538 ps
CPU time 30.43 seconds
Started Apr 30 12:31:55 PM PDT 24
Finished Apr 30 12:32:28 PM PDT 24
Peak memory 222432 kb
Host smart-518e86d6-91ce-4350-b98e-45befb605ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423024125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.1423024125
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.3790767036
Short name T313
Test name
Test status
Simulation time 1358360276 ps
CPU time 38.4 seconds
Started Apr 30 12:31:52 PM PDT 24
Finished Apr 30 12:32:33 PM PDT 24
Peak memory 216060 kb
Host smart-a82f694d-b1e1-48a5-bddc-a6a77db45dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790767036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.3790767036
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.1647116448
Short name T726
Test name
Test status
Simulation time 208987993 ps
CPU time 4.06 seconds
Started Apr 30 12:31:51 PM PDT 24
Finished Apr 30 12:31:57 PM PDT 24
Peak memory 209316 kb
Host smart-3f259798-a852-403c-aa5c-4fd0b4c5d18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647116448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.1647116448
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.2401057482
Short name T654
Test name
Test status
Simulation time 204583515 ps
CPU time 4.78 seconds
Started Apr 30 12:31:54 PM PDT 24
Finished Apr 30 12:32:00 PM PDT 24
Peak memory 208420 kb
Host smart-40add7fb-0818-485f-a735-faf8efa34864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401057482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.2401057482
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.738084918
Short name T801
Test name
Test status
Simulation time 105712231 ps
CPU time 2.89 seconds
Started Apr 30 12:31:52 PM PDT 24
Finished Apr 30 12:31:56 PM PDT 24
Peak memory 206460 kb
Host smart-b408e5b7-dfae-4681-b5a3-4169c3b1970a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738084918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.738084918
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.3013602853
Short name T760
Test name
Test status
Simulation time 24008500 ps
CPU time 1.95 seconds
Started Apr 30 12:31:52 PM PDT 24
Finished Apr 30 12:31:55 PM PDT 24
Peak memory 206628 kb
Host smart-71fedbe3-9c69-463a-9557-24abd46d0df0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013602853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.3013602853
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.4033243643
Short name T346
Test name
Test status
Simulation time 2939122811 ps
CPU time 8.19 seconds
Started Apr 30 12:31:55 PM PDT 24
Finished Apr 30 12:32:06 PM PDT 24
Peak memory 208064 kb
Host smart-7d5d5662-b73f-424d-976d-a12cf953ab2b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033243643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.4033243643
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.803226896
Short name T449
Test name
Test status
Simulation time 4138509348 ps
CPU time 36.59 seconds
Started Apr 30 12:31:54 PM PDT 24
Finished Apr 30 12:32:33 PM PDT 24
Peak memory 208676 kb
Host smart-f8b2392c-1adb-4991-b3cb-2d910ef1cb4f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803226896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.803226896
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.2471253533
Short name T676
Test name
Test status
Simulation time 175553716 ps
CPU time 2.49 seconds
Started Apr 30 12:31:54 PM PDT 24
Finished Apr 30 12:31:59 PM PDT 24
Peak memory 209388 kb
Host smart-d9ba1918-d908-434d-bd6f-5dfd3e8ca27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471253533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.2471253533
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.1333460475
Short name T562
Test name
Test status
Simulation time 3754696761 ps
CPU time 21.19 seconds
Started Apr 30 12:31:55 PM PDT 24
Finished Apr 30 12:32:18 PM PDT 24
Peak memory 207528 kb
Host smart-2520638b-5888-41dd-b748-f9363dc7de25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333460475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.1333460475
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.1566052222
Short name T302
Test name
Test status
Simulation time 616450909 ps
CPU time 12.91 seconds
Started Apr 30 12:32:13 PM PDT 24
Finished Apr 30 12:32:27 PM PDT 24
Peak memory 222324 kb
Host smart-94258277-09e2-4183-94b7-b35cf3bf7672
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566052222 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.1566052222
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.1917509833
Short name T207
Test name
Test status
Simulation time 1192345083 ps
CPU time 7.06 seconds
Started Apr 30 12:31:52 PM PDT 24
Finished Apr 30 12:32:00 PM PDT 24
Peak memory 209680 kb
Host smart-469e9fa2-1dfd-4317-a238-1ce6b8b3ae2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917509833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.1917509833
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.3963766465
Short name T153
Test name
Test status
Simulation time 43844961 ps
CPU time 1.43 seconds
Started Apr 30 12:31:53 PM PDT 24
Finished Apr 30 12:31:56 PM PDT 24
Peak memory 209292 kb
Host smart-2c7d95a6-489f-460f-bdfc-eeb9b287a226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963766465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.3963766465
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.461344952
Short name T527
Test name
Test status
Simulation time 19766638 ps
CPU time 0.93 seconds
Started Apr 30 12:31:57 PM PDT 24
Finished Apr 30 12:31:59 PM PDT 24
Peak memory 205696 kb
Host smart-cec7acef-ed14-4ad5-82d0-f9ab7baa18b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461344952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.461344952
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.1099603135
Short name T2
Test name
Test status
Simulation time 225527481 ps
CPU time 6.51 seconds
Started Apr 30 12:32:15 PM PDT 24
Finished Apr 30 12:32:22 PM PDT 24
Peak memory 220012 kb
Host smart-42915cb0-8e33-4e41-aca7-32e20816997b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099603135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.1099603135
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.3487227813
Short name T333
Test name
Test status
Simulation time 248990768 ps
CPU time 3.05 seconds
Started Apr 30 12:31:54 PM PDT 24
Finished Apr 30 12:31:59 PM PDT 24
Peak memory 208980 kb
Host smart-aae27357-bf61-42f4-9797-5a250fa3081a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487227813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.3487227813
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.3040284622
Short name T505
Test name
Test status
Simulation time 595848558 ps
CPU time 3.48 seconds
Started Apr 30 12:31:56 PM PDT 24
Finished Apr 30 12:32:02 PM PDT 24
Peak memory 213860 kb
Host smart-198c0650-700f-4355-93ec-e35413d53cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040284622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.3040284622
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.2349411889
Short name T350
Test name
Test status
Simulation time 606644037 ps
CPU time 22.09 seconds
Started Apr 30 12:31:56 PM PDT 24
Finished Apr 30 12:32:20 PM PDT 24
Peak memory 217524 kb
Host smart-7fcbaaa2-dc4a-47a6-9a64-4ea967b953e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349411889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.2349411889
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.970056673
Short name T845
Test name
Test status
Simulation time 91293751 ps
CPU time 3.08 seconds
Started Apr 30 12:31:57 PM PDT 24
Finished Apr 30 12:32:02 PM PDT 24
Peak memory 206692 kb
Host smart-5e99b29e-57b8-4ebc-a37a-c5ece11dc294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970056673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.970056673
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.2117498557
Short name T842
Test name
Test status
Simulation time 137564586 ps
CPU time 3.61 seconds
Started Apr 30 12:31:58 PM PDT 24
Finished Apr 30 12:32:03 PM PDT 24
Peak memory 206760 kb
Host smart-166b76fc-44a4-4a86-8082-013248dbb621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117498557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.2117498557
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.1299458250
Short name T602
Test name
Test status
Simulation time 7022196594 ps
CPU time 44.41 seconds
Started Apr 30 12:31:55 PM PDT 24
Finished Apr 30 12:32:42 PM PDT 24
Peak memory 208140 kb
Host smart-7655ebea-4ebd-4f4d-b575-5324dd224ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299458250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.1299458250
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.3879288120
Short name T513
Test name
Test status
Simulation time 49517987 ps
CPU time 2.85 seconds
Started Apr 30 12:31:52 PM PDT 24
Finished Apr 30 12:31:57 PM PDT 24
Peak memory 208432 kb
Host smart-30fc7bb1-8f6c-4256-8658-52b806df4f4d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879288120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.3879288120
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.2284744319
Short name T476
Test name
Test status
Simulation time 308954504 ps
CPU time 6.53 seconds
Started Apr 30 12:31:59 PM PDT 24
Finished Apr 30 12:32:07 PM PDT 24
Peak memory 208648 kb
Host smart-81db4b82-db4f-4db2-82a7-7f5e1bf16537
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284744319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.2284744319
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.3798922492
Short name T727
Test name
Test status
Simulation time 4527217799 ps
CPU time 23.04 seconds
Started Apr 30 12:31:53 PM PDT 24
Finished Apr 30 12:32:19 PM PDT 24
Peak memory 208284 kb
Host smart-c8cd2374-21d9-42f1-a51d-64c7113118b1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798922492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.3798922492
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.1293013464
Short name T670
Test name
Test status
Simulation time 151130919 ps
CPU time 2.51 seconds
Started Apr 30 12:31:56 PM PDT 24
Finished Apr 30 12:32:01 PM PDT 24
Peak memory 207200 kb
Host smart-4667733a-cd3a-48a1-8ecb-c09bced5f467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293013464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.1293013464
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.1454559242
Short name T603
Test name
Test status
Simulation time 98087804 ps
CPU time 2.93 seconds
Started Apr 30 12:31:54 PM PDT 24
Finished Apr 30 12:31:59 PM PDT 24
Peak memory 207684 kb
Host smart-f8f90745-b8f7-493c-a95f-4c5dc13f7d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454559242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.1454559242
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.811087649
Short name T237
Test name
Test status
Simulation time 307912613 ps
CPU time 6.75 seconds
Started Apr 30 12:31:56 PM PDT 24
Finished Apr 30 12:32:04 PM PDT 24
Peak memory 219948 kb
Host smart-d8d789bd-2f00-4583-b0a1-55cb588ffa29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811087649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.811087649
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.3771803583
Short name T187
Test name
Test status
Simulation time 1372686419 ps
CPU time 15.51 seconds
Started Apr 30 12:31:54 PM PDT 24
Finished Apr 30 12:32:12 PM PDT 24
Peak memory 220400 kb
Host smart-fd28955a-571c-460b-aa55-f32f5125d3d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771803583 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.3771803583
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.3964546603
Short name T288
Test name
Test status
Simulation time 1187002955 ps
CPU time 8.95 seconds
Started Apr 30 12:31:54 PM PDT 24
Finished Apr 30 12:32:06 PM PDT 24
Peak memory 213916 kb
Host smart-79f52779-8690-4840-8d97-6537b491367f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964546603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.3964546603
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.3891538305
Short name T807
Test name
Test status
Simulation time 145479829 ps
CPU time 3.34 seconds
Started Apr 30 12:32:18 PM PDT 24
Finished Apr 30 12:32:22 PM PDT 24
Peak memory 209800 kb
Host smart-463edf73-2699-42f9-b1a3-2018d6de381b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891538305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.3891538305
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.3123605643
Short name T442
Test name
Test status
Simulation time 65776472 ps
CPU time 1.04 seconds
Started Apr 30 12:31:55 PM PDT 24
Finished Apr 30 12:31:59 PM PDT 24
Peak memory 205836 kb
Host smart-a5708b12-d145-4ab3-b11c-907ab96f4280
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123605643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.3123605643
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.3142683357
Short name T282
Test name
Test status
Simulation time 145111441 ps
CPU time 7.84 seconds
Started Apr 30 12:32:29 PM PDT 24
Finished Apr 30 12:32:38 PM PDT 24
Peak memory 215140 kb
Host smart-ddf175bb-0fd6-427f-a52f-09b803ab8849
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3142683357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.3142683357
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.3586474108
Short name T728
Test name
Test status
Simulation time 542872732 ps
CPU time 3.66 seconds
Started Apr 30 12:32:02 PM PDT 24
Finished Apr 30 12:32:06 PM PDT 24
Peak memory 214248 kb
Host smart-db06ce31-bb74-4e52-b1bf-bdd4c27cd208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586474108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.3586474108
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.3724404152
Short name T759
Test name
Test status
Simulation time 13558435 ps
CPU time 1.25 seconds
Started Apr 30 12:31:55 PM PDT 24
Finished Apr 30 12:31:59 PM PDT 24
Peak memory 207088 kb
Host smart-1324bf54-5e83-4f72-941b-60a29126ffe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724404152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.3724404152
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.2776026445
Short name T23
Test name
Test status
Simulation time 1926461261 ps
CPU time 9.02 seconds
Started Apr 30 12:31:54 PM PDT 24
Finished Apr 30 12:32:05 PM PDT 24
Peak memory 209012 kb
Host smart-5c01dbce-5cc2-4c7e-b0d7-0cceeef63f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776026445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.2776026445
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.3546954775
Short name T653
Test name
Test status
Simulation time 1594156655 ps
CPU time 11.03 seconds
Started Apr 30 12:31:55 PM PDT 24
Finished Apr 30 12:32:08 PM PDT 24
Peak memory 211308 kb
Host smart-e5e00493-7541-4df5-a5f1-3ee0de9031dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546954775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.3546954775
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.2727251071
Short name T389
Test name
Test status
Simulation time 100285811 ps
CPU time 2.63 seconds
Started Apr 30 12:31:54 PM PDT 24
Finished Apr 30 12:31:59 PM PDT 24
Peak memory 214084 kb
Host smart-5ea14d12-b1fe-42df-8215-fb0fe22b0bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727251071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.2727251071
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.1229835450
Short name T214
Test name
Test status
Simulation time 412958772 ps
CPU time 5.23 seconds
Started Apr 30 12:31:53 PM PDT 24
Finished Apr 30 12:32:01 PM PDT 24
Peak memory 207568 kb
Host smart-c13b9c8b-8f4d-4e01-b124-aaac927a39ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229835450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.1229835450
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.487324649
Short name T638
Test name
Test status
Simulation time 500811246 ps
CPU time 11.8 seconds
Started Apr 30 12:32:15 PM PDT 24
Finished Apr 30 12:32:28 PM PDT 24
Peak memory 207396 kb
Host smart-26bcaebf-2ebb-48be-a514-547d99ff36ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487324649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.487324649
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.4176476567
Short name T838
Test name
Test status
Simulation time 100394830 ps
CPU time 3.65 seconds
Started Apr 30 12:31:56 PM PDT 24
Finished Apr 30 12:32:02 PM PDT 24
Peak memory 206252 kb
Host smart-d5a6f6df-a32e-4139-b567-9d3905299d76
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176476567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.4176476567
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.767424847
Short name T519
Test name
Test status
Simulation time 563486631 ps
CPU time 6.58 seconds
Started Apr 30 12:32:09 PM PDT 24
Finished Apr 30 12:32:16 PM PDT 24
Peak memory 208180 kb
Host smart-4e42a856-f8e9-4f9d-947b-0b4bb009a45f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767424847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.767424847
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.2181794272
Short name T658
Test name
Test status
Simulation time 3082432327 ps
CPU time 5.85 seconds
Started Apr 30 12:32:29 PM PDT 24
Finished Apr 30 12:32:35 PM PDT 24
Peak memory 207660 kb
Host smart-aa185801-b3f4-4ec0-b503-82394cf9a211
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181794272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.2181794272
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.2520648150
Short name T604
Test name
Test status
Simulation time 52280612 ps
CPU time 2.07 seconds
Started Apr 30 12:31:53 PM PDT 24
Finished Apr 30 12:31:56 PM PDT 24
Peak memory 217924 kb
Host smart-bf01cfb7-02af-4949-90ca-603ae379c369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520648150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.2520648150
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.814573155
Short name T751
Test name
Test status
Simulation time 76629413 ps
CPU time 1.78 seconds
Started Apr 30 12:32:15 PM PDT 24
Finished Apr 30 12:32:18 PM PDT 24
Peak memory 206112 kb
Host smart-c1a608c3-3aa6-4f48-b5fe-f29e7bf4ad1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814573155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.814573155
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.3659848324
Short name T404
Test name
Test status
Simulation time 102847130 ps
CPU time 3.83 seconds
Started Apr 30 12:31:55 PM PDT 24
Finished Apr 30 12:32:01 PM PDT 24
Peak memory 213984 kb
Host smart-6323e3cf-25b2-4ce0-a454-82fb5ce04fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659848324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.3659848324
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.3687223340
Short name T819
Test name
Test status
Simulation time 179389294 ps
CPU time 2.55 seconds
Started Apr 30 12:32:34 PM PDT 24
Finished Apr 30 12:32:38 PM PDT 24
Peak memory 209996 kb
Host smart-f34855d4-bd0f-4216-80ff-686524323568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687223340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.3687223340
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.184489089
Short name T427
Test name
Test status
Simulation time 27398282 ps
CPU time 0.68 seconds
Started Apr 30 12:31:56 PM PDT 24
Finished Apr 30 12:31:58 PM PDT 24
Peak memory 205556 kb
Host smart-05fb3a52-ca34-4173-8ca4-936aff64e9bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184489089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.184489089
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.927330258
Short name T718
Test name
Test status
Simulation time 39920166 ps
CPU time 2.96 seconds
Started Apr 30 12:31:52 PM PDT 24
Finished Apr 30 12:31:57 PM PDT 24
Peak memory 214064 kb
Host smart-693ece4b-53f2-4f9a-bd62-21733dacea37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=927330258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.927330258
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.304330664
Short name T20
Test name
Test status
Simulation time 75232099 ps
CPU time 3.71 seconds
Started Apr 30 12:31:57 PM PDT 24
Finished Apr 30 12:32:02 PM PDT 24
Peak memory 222524 kb
Host smart-881fa015-a087-48b6-80cc-74e83da93500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304330664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.304330664
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.501088988
Short name T589
Test name
Test status
Simulation time 49504903 ps
CPU time 2.84 seconds
Started Apr 30 12:31:58 PM PDT 24
Finished Apr 30 12:32:02 PM PDT 24
Peak memory 207072 kb
Host smart-1e7d4019-047e-41ee-ad19-2f29164ef317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501088988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.501088988
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.363903939
Short name T94
Test name
Test status
Simulation time 145888629 ps
CPU time 5.26 seconds
Started Apr 30 12:31:58 PM PDT 24
Finished Apr 30 12:32:04 PM PDT 24
Peak memory 208812 kb
Host smart-91d281e3-5fc7-4cc2-ac28-57ddc95f999c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363903939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.363903939
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.3429768992
Short name T312
Test name
Test status
Simulation time 381860407 ps
CPU time 13.18 seconds
Started Apr 30 12:31:59 PM PDT 24
Finished Apr 30 12:32:13 PM PDT 24
Peak memory 210692 kb
Host smart-654d4c6d-84b4-414d-b25e-fc2799053883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429768992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.3429768992
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.1036546836
Short name T673
Test name
Test status
Simulation time 1768644799 ps
CPU time 3.98 seconds
Started Apr 30 12:31:59 PM PDT 24
Finished Apr 30 12:32:04 PM PDT 24
Peak memory 222184 kb
Host smart-8aafd2b3-53fa-4e56-8000-c748d72df4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036546836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.1036546836
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.1143303745
Short name T503
Test name
Test status
Simulation time 2817806345 ps
CPU time 17.81 seconds
Started Apr 30 12:31:54 PM PDT 24
Finished Apr 30 12:32:14 PM PDT 24
Peak memory 208720 kb
Host smart-f917ddbc-89b4-4e47-91b2-6d375299ee4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143303745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.1143303745
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.2649083574
Short name T539
Test name
Test status
Simulation time 420809711 ps
CPU time 4.88 seconds
Started Apr 30 12:31:53 PM PDT 24
Finished Apr 30 12:32:00 PM PDT 24
Peak memory 206380 kb
Host smart-88c61e62-bf04-4b72-9432-35a732d150da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649083574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.2649083574
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.2067266959
Short name T761
Test name
Test status
Simulation time 116641041 ps
CPU time 3.08 seconds
Started Apr 30 12:31:50 PM PDT 24
Finished Apr 30 12:31:54 PM PDT 24
Peak memory 208188 kb
Host smart-34fcc412-35d2-4ace-bdb5-3564b9a67780
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067266959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.2067266959
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.723562067
Short name T265
Test name
Test status
Simulation time 1029349977 ps
CPU time 25.46 seconds
Started Apr 30 12:31:55 PM PDT 24
Finished Apr 30 12:32:22 PM PDT 24
Peak memory 208032 kb
Host smart-cb41473e-1c4f-40cc-ad9f-128efa89f72e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723562067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.723562067
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.2092319004
Short name T657
Test name
Test status
Simulation time 1116442295 ps
CPU time 6.67 seconds
Started Apr 30 12:31:55 PM PDT 24
Finished Apr 30 12:32:03 PM PDT 24
Peak memory 207812 kb
Host smart-c211dfb5-68ce-4584-bb9e-e95816910545
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092319004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.2092319004
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.3534881356
Short name T662
Test name
Test status
Simulation time 154830255 ps
CPU time 2.61 seconds
Started Apr 30 12:31:59 PM PDT 24
Finished Apr 30 12:32:02 PM PDT 24
Peak memory 206600 kb
Host smart-69e0d3c3-5e50-4808-80f2-23e2a140614c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534881356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.3534881356
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.312699392
Short name T471
Test name
Test status
Simulation time 104114184 ps
CPU time 4.07 seconds
Started Apr 30 12:31:53 PM PDT 24
Finished Apr 30 12:31:59 PM PDT 24
Peak memory 207936 kb
Host smart-4e9d9fee-4dd9-4fdf-945a-98d0279b51cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312699392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.312699392
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.2289428740
Short name T286
Test name
Test status
Simulation time 2488585281 ps
CPU time 26.66 seconds
Started Apr 30 12:31:59 PM PDT 24
Finished Apr 30 12:32:27 PM PDT 24
Peak memory 219976 kb
Host smart-c7914283-0b5d-4276-8460-263ad428d7c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289428740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.2289428740
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.1779944091
Short name T219
Test name
Test status
Simulation time 144085417 ps
CPU time 6.4 seconds
Started Apr 30 12:31:58 PM PDT 24
Finished Apr 30 12:32:06 PM PDT 24
Peak memory 210156 kb
Host smart-1be8f7b3-bb91-4f8d-88e5-7964ad18c5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779944091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.1779944091
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.3609793172
Short name T441
Test name
Test status
Simulation time 54611756 ps
CPU time 1.54 seconds
Started Apr 30 12:31:55 PM PDT 24
Finished Apr 30 12:31:59 PM PDT 24
Peak memory 207956 kb
Host smart-e71ff853-9801-42d1-9da5-60715cc4d957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609793172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.3609793172
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.311495863
Short name T710
Test name
Test status
Simulation time 40960157 ps
CPU time 0.76 seconds
Started Apr 30 12:31:54 PM PDT 24
Finished Apr 30 12:31:57 PM PDT 24
Peak memory 205648 kb
Host smart-9ff5041b-035a-4e8a-8b8f-fd4e4bc43a27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311495863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.311495863
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.96852138
Short name T399
Test name
Test status
Simulation time 351396650 ps
CPU time 17.48 seconds
Started Apr 30 12:32:15 PM PDT 24
Finished Apr 30 12:32:34 PM PDT 24
Peak memory 213980 kb
Host smart-2503fa48-a450-42ee-92a3-540d99668468
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=96852138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.96852138
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.1045176889
Short name T892
Test name
Test status
Simulation time 459692839 ps
CPU time 4.01 seconds
Started Apr 30 12:31:59 PM PDT 24
Finished Apr 30 12:32:04 PM PDT 24
Peak memory 208652 kb
Host smart-b7e93c49-8502-44a4-9685-e1f5d03a7bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045176889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.1045176889
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.2130376817
Short name T548
Test name
Test status
Simulation time 120297951 ps
CPU time 3.36 seconds
Started Apr 30 12:32:14 PM PDT 24
Finished Apr 30 12:32:18 PM PDT 24
Peak memory 208340 kb
Host smart-067854ad-34ca-475f-b23d-5a71ad31cedb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130376817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.2130376817
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.240972904
Short name T750
Test name
Test status
Simulation time 99599951 ps
CPU time 4.53 seconds
Started Apr 30 12:31:57 PM PDT 24
Finished Apr 30 12:32:03 PM PDT 24
Peak memory 210120 kb
Host smart-511f6a01-2c84-4cd2-aca3-1ed63778b505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240972904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.240972904
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.2366699518
Short name T38
Test name
Test status
Simulation time 65217883 ps
CPU time 3.64 seconds
Started Apr 30 12:31:59 PM PDT 24
Finished Apr 30 12:32:04 PM PDT 24
Peak memory 222192 kb
Host smart-c5a64dba-9b6e-4085-966a-1db131c29f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366699518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.2366699518
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.1584594868
Short name T263
Test name
Test status
Simulation time 981092005 ps
CPU time 7.42 seconds
Started Apr 30 12:31:56 PM PDT 24
Finished Apr 30 12:32:06 PM PDT 24
Peak memory 209528 kb
Host smart-7f40edc5-dc62-4754-87b9-5dd667f05196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584594868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.1584594868
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.1834003361
Short name T677
Test name
Test status
Simulation time 2498864526 ps
CPU time 26.36 seconds
Started Apr 30 12:31:53 PM PDT 24
Finished Apr 30 12:32:22 PM PDT 24
Peak memory 208272 kb
Host smart-ad3f157a-c58b-4292-abb2-17c8cf768d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834003361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.1834003361
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.1249205374
Short name T340
Test name
Test status
Simulation time 1909977943 ps
CPU time 36.79 seconds
Started Apr 30 12:31:57 PM PDT 24
Finished Apr 30 12:32:36 PM PDT 24
Peak memory 207744 kb
Host smart-f4c617d7-2659-41bf-b61c-687307f2e479
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249205374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.1249205374
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.1735491521
Short name T450
Test name
Test status
Simulation time 107626838 ps
CPU time 3.34 seconds
Started Apr 30 12:31:56 PM PDT 24
Finished Apr 30 12:32:01 PM PDT 24
Peak memory 206448 kb
Host smart-3b768f46-3d4b-4a6d-a06f-ebecfa731650
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735491521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.1735491521
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.952719422
Short name T904
Test name
Test status
Simulation time 393112260 ps
CPU time 7.85 seconds
Started Apr 30 12:32:02 PM PDT 24
Finished Apr 30 12:32:11 PM PDT 24
Peak memory 207728 kb
Host smart-ccee0f65-6cc9-44c7-be11-179d6d41210f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952719422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.952719422
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.3877109688
Short name T401
Test name
Test status
Simulation time 192576595 ps
CPU time 2.2 seconds
Started Apr 30 12:31:56 PM PDT 24
Finished Apr 30 12:32:00 PM PDT 24
Peak memory 208420 kb
Host smart-f646490e-ec45-417f-a8fb-8124b4c05375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877109688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.3877109688
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.859309718
Short name T737
Test name
Test status
Simulation time 84966109 ps
CPU time 1.87 seconds
Started Apr 30 12:31:59 PM PDT 24
Finished Apr 30 12:32:02 PM PDT 24
Peak memory 206248 kb
Host smart-c6d246c9-602b-49c9-ae84-2f5a34dc4671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859309718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.859309718
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.814579406
Short name T413
Test name
Test status
Simulation time 509513450 ps
CPU time 4.64 seconds
Started Apr 30 12:31:59 PM PDT 24
Finished Apr 30 12:32:04 PM PDT 24
Peak memory 209824 kb
Host smart-3d7a32c4-cc71-4630-b899-eb66f0e3adac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814579406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.814579406
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.3149452750
Short name T170
Test name
Test status
Simulation time 112426589 ps
CPU time 1.8 seconds
Started Apr 30 12:31:53 PM PDT 24
Finished Apr 30 12:31:57 PM PDT 24
Peak memory 209512 kb
Host smart-cc5a2c00-1563-4774-8cc7-f8bc262aa15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149452750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.3149452750
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.4077787863
Short name T499
Test name
Test status
Simulation time 41540951 ps
CPU time 0.77 seconds
Started Apr 30 12:32:08 PM PDT 24
Finished Apr 30 12:32:09 PM PDT 24
Peak memory 205520 kb
Host smart-0021bcca-f886-4bc5-a5a0-6b3499d15693
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077787863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.4077787863
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.3805634463
Short name T667
Test name
Test status
Simulation time 186103841 ps
CPU time 3.91 seconds
Started Apr 30 12:32:08 PM PDT 24
Finished Apr 30 12:32:12 PM PDT 24
Peak memory 213928 kb
Host smart-319528b0-305b-4427-bd9d-dd2c06000424
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3805634463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.3805634463
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.2394701062
Short name T601
Test name
Test status
Simulation time 331873600 ps
CPU time 2 seconds
Started Apr 30 12:32:13 PM PDT 24
Finished Apr 30 12:32:16 PM PDT 24
Peak memory 217072 kb
Host smart-5bfcb1fd-4db1-47af-996f-95d4621126fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394701062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.2394701062
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.2140884936
Short name T507
Test name
Test status
Simulation time 104519602 ps
CPU time 2.64 seconds
Started Apr 30 12:32:22 PM PDT 24
Finished Apr 30 12:32:25 PM PDT 24
Peak memory 206520 kb
Host smart-b088073f-ff9a-424f-9019-70ae19d78edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140884936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.2140884936
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.3718981193
Short name T785
Test name
Test status
Simulation time 2021247497 ps
CPU time 21 seconds
Started Apr 30 12:32:05 PM PDT 24
Finished Apr 30 12:32:27 PM PDT 24
Peak memory 221336 kb
Host smart-90397402-cc39-4577-86f6-544ce9736f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718981193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.3718981193
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.3153849581
Short name T208
Test name
Test status
Simulation time 55455280 ps
CPU time 3.67 seconds
Started Apr 30 12:32:11 PM PDT 24
Finished Apr 30 12:32:16 PM PDT 24
Peak memory 210160 kb
Host smart-e81a8435-ba02-49e3-83e6-47d885f78c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153849581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.3153849581
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.1071501430
Short name T460
Test name
Test status
Simulation time 272545122 ps
CPU time 4.07 seconds
Started Apr 30 12:32:18 PM PDT 24
Finished Apr 30 12:32:23 PM PDT 24
Peak memory 209444 kb
Host smart-dff23b77-fdc1-47d9-94ab-f22b6e3529a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071501430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.1071501430
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.3675418641
Short name T858
Test name
Test status
Simulation time 1359075424 ps
CPU time 11.52 seconds
Started Apr 30 12:32:08 PM PDT 24
Finished Apr 30 12:32:21 PM PDT 24
Peak memory 208572 kb
Host smart-38f4f510-ddb0-4cca-8888-e9dca26c07b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675418641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.3675418641
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.1992488950
Short name T75
Test name
Test status
Simulation time 733126412 ps
CPU time 8.17 seconds
Started Apr 30 12:31:55 PM PDT 24
Finished Apr 30 12:32:06 PM PDT 24
Peak memory 208356 kb
Host smart-09792e0e-9182-4f8b-a64b-011fbe38397f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992488950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.1992488950
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.2005781207
Short name T109
Test name
Test status
Simulation time 254314113 ps
CPU time 2.79 seconds
Started Apr 30 12:32:11 PM PDT 24
Finished Apr 30 12:32:15 PM PDT 24
Peak memory 208252 kb
Host smart-787614d2-6f1a-4bfd-a2e0-db54a830669e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005781207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.2005781207
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.1631067923
Short name T706
Test name
Test status
Simulation time 406132879 ps
CPU time 4.64 seconds
Started Apr 30 12:31:57 PM PDT 24
Finished Apr 30 12:32:03 PM PDT 24
Peak memory 208136 kb
Host smart-cbeaf352-db08-428a-bf4d-5e3819558003
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631067923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.1631067923
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.1307763154
Short name T354
Test name
Test status
Simulation time 420402557 ps
CPU time 3.46 seconds
Started Apr 30 12:31:58 PM PDT 24
Finished Apr 30 12:32:02 PM PDT 24
Peak memory 208112 kb
Host smart-5fea464c-6154-49a7-9a3e-dd3d7ee3d2e1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307763154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.1307763154
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.2662046125
Short name T133
Test name
Test status
Simulation time 51779391 ps
CPU time 1.87 seconds
Started Apr 30 12:32:09 PM PDT 24
Finished Apr 30 12:32:11 PM PDT 24
Peak memory 209320 kb
Host smart-745137a2-e927-43fb-913b-cb208eda9cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662046125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.2662046125
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.2700892440
Short name T459
Test name
Test status
Simulation time 72015310 ps
CPU time 3.02 seconds
Started Apr 30 12:32:06 PM PDT 24
Finished Apr 30 12:32:10 PM PDT 24
Peak memory 207360 kb
Host smart-76dc108c-4251-498c-970e-42163fd84ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700892440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.2700892440
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.4204836016
Short name T59
Test name
Test status
Simulation time 443892236 ps
CPU time 17.86 seconds
Started Apr 30 12:32:18 PM PDT 24
Finished Apr 30 12:32:36 PM PDT 24
Peak memory 222332 kb
Host smart-91c3f7ff-124e-4d77-987f-c6d17adbaadb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204836016 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.4204836016
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.1263193514
Short name T811
Test name
Test status
Simulation time 1186751563 ps
CPU time 6.85 seconds
Started Apr 30 12:32:16 PM PDT 24
Finished Apr 30 12:32:24 PM PDT 24
Peak memory 209536 kb
Host smart-181c7731-0ecb-4631-a7ae-162d6c4c7c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263193514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.1263193514
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.307275578
Short name T578
Test name
Test status
Simulation time 6098369897 ps
CPU time 7.84 seconds
Started Apr 30 12:32:11 PM PDT 24
Finished Apr 30 12:32:20 PM PDT 24
Peak memory 211276 kb
Host smart-89bdd7aa-4b6b-41dc-8eb4-4ac8df023e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307275578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.307275578
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.2890380710
Short name T71
Test name
Test status
Simulation time 21011530 ps
CPU time 0.74 seconds
Started Apr 30 12:32:23 PM PDT 24
Finished Apr 30 12:32:24 PM PDT 24
Peak memory 205688 kb
Host smart-d6f3c494-7c4a-41e9-81d6-f9f05c02cedd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890380710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.2890380710
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.4212215356
Short name T428
Test name
Test status
Simulation time 404834362 ps
CPU time 6.8 seconds
Started Apr 30 12:32:17 PM PDT 24
Finished Apr 30 12:32:24 PM PDT 24
Peak memory 214016 kb
Host smart-09fb46ba-d15d-42d3-a175-914ddfceda8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212215356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.4212215356
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.3165337359
Short name T273
Test name
Test status
Simulation time 189865795 ps
CPU time 3.28 seconds
Started Apr 30 12:32:13 PM PDT 24
Finished Apr 30 12:32:18 PM PDT 24
Peak memory 210024 kb
Host smart-3516e842-b5ee-4a80-a707-d53bdc92ae6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165337359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.3165337359
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.3916662855
Short name T701
Test name
Test status
Simulation time 702460398 ps
CPU time 3.9 seconds
Started Apr 30 12:32:26 PM PDT 24
Finished Apr 30 12:32:30 PM PDT 24
Peak memory 209316 kb
Host smart-ad9c86f8-cef9-41e9-820c-1ea2b0f0ffe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916662855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.3916662855
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.1111779095
Short name T280
Test name
Test status
Simulation time 50998933 ps
CPU time 3.17 seconds
Started Apr 30 12:32:17 PM PDT 24
Finished Apr 30 12:32:21 PM PDT 24
Peak memory 217880 kb
Host smart-cb847adb-e496-4da5-a8a9-048e8cb25a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111779095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.1111779095
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.2218147911
Short name T684
Test name
Test status
Simulation time 725513197 ps
CPU time 10.09 seconds
Started Apr 30 12:32:17 PM PDT 24
Finished Apr 30 12:32:27 PM PDT 24
Peak memory 207484 kb
Host smart-65b2e197-c9ff-4d22-a42c-4704ef9cc11d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218147911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.2218147911
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.878758925
Short name T220
Test name
Test status
Simulation time 64009227 ps
CPU time 3.27 seconds
Started Apr 30 12:32:24 PM PDT 24
Finished Apr 30 12:32:27 PM PDT 24
Peak memory 206516 kb
Host smart-da4b238f-3fc4-4d2f-acaf-2c7968c80f3d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878758925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.878758925
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.3221368462
Short name T659
Test name
Test status
Simulation time 78273352 ps
CPU time 1.83 seconds
Started Apr 30 12:32:13 PM PDT 24
Finished Apr 30 12:32:16 PM PDT 24
Peak memory 207072 kb
Host smart-cd210cbf-8a04-4550-9859-d94f06e6c7b5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221368462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.3221368462
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.2766457416
Short name T833
Test name
Test status
Simulation time 409436914 ps
CPU time 4.2 seconds
Started Apr 30 12:32:13 PM PDT 24
Finished Apr 30 12:32:18 PM PDT 24
Peak memory 206408 kb
Host smart-d1e26fb3-4177-4ed7-9d59-5a064de7601c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766457416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.2766457416
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.265592948
Short name T555
Test name
Test status
Simulation time 456249571 ps
CPU time 8.32 seconds
Started Apr 30 12:32:28 PM PDT 24
Finished Apr 30 12:32:37 PM PDT 24
Peak memory 218080 kb
Host smart-1b5c4e93-a3eb-4bf3-9a65-e9d254b420ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265592948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.265592948
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.533091616
Short name T429
Test name
Test status
Simulation time 76782440 ps
CPU time 2.79 seconds
Started Apr 30 12:32:14 PM PDT 24
Finished Apr 30 12:32:18 PM PDT 24
Peak memory 206348 kb
Host smart-363ba4d4-cf74-4608-afcb-2b64804a8d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533091616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.533091616
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.2332513482
Short name T178
Test name
Test status
Simulation time 304524506 ps
CPU time 16.71 seconds
Started Apr 30 12:32:17 PM PDT 24
Finished Apr 30 12:32:34 PM PDT 24
Peak memory 222400 kb
Host smart-0f3709cf-23e3-4033-8e77-a4f70cfa45ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332513482 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.2332513482
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.990945427
Short name T786
Test name
Test status
Simulation time 466448496 ps
CPU time 5.99 seconds
Started Apr 30 12:33:24 PM PDT 24
Finished Apr 30 12:33:32 PM PDT 24
Peak memory 207420 kb
Host smart-eea34c51-bf0f-4a43-b57d-1db78c8fbd01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990945427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.990945427
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.2703171949
Short name T437
Test name
Test status
Simulation time 33699735 ps
CPU time 0.78 seconds
Started Apr 30 12:32:26 PM PDT 24
Finished Apr 30 12:32:28 PM PDT 24
Peak memory 205576 kb
Host smart-e30d5206-5a99-4eb1-b2f1-6404e0a9566e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703171949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.2703171949
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.2099042389
Short name T869
Test name
Test status
Simulation time 940739370 ps
CPU time 2.56 seconds
Started Apr 30 12:32:15 PM PDT 24
Finished Apr 30 12:32:18 PM PDT 24
Peak memory 221484 kb
Host smart-7ca41327-e104-482a-b3ab-f935b0c18427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099042389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.2099042389
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.1907466300
Short name T532
Test name
Test status
Simulation time 92757831 ps
CPU time 1.48 seconds
Started Apr 30 12:33:24 PM PDT 24
Finished Apr 30 12:33:27 PM PDT 24
Peak memory 206788 kb
Host smart-8a7e5a07-5070-47c5-bf49-f0e9a68f5699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907466300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.1907466300
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.4257077696
Short name T474
Test name
Test status
Simulation time 141875987 ps
CPU time 4.17 seconds
Started Apr 30 12:32:15 PM PDT 24
Finished Apr 30 12:32:21 PM PDT 24
Peak memory 208716 kb
Host smart-641be6e3-97f2-408b-a932-79be8460a4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257077696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.4257077696
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.1005213765
Short name T272
Test name
Test status
Simulation time 141343406 ps
CPU time 6.75 seconds
Started Apr 30 12:32:31 PM PDT 24
Finished Apr 30 12:32:38 PM PDT 24
Peak memory 222144 kb
Host smart-b7c2ab96-8f4b-4c59-93f3-a9316c5e26c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005213765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.1005213765
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.2037722458
Short name T193
Test name
Test status
Simulation time 452493850 ps
CPU time 3.83 seconds
Started Apr 30 12:32:15 PM PDT 24
Finished Apr 30 12:32:20 PM PDT 24
Peak memory 218156 kb
Host smart-4897a10e-57a9-46a1-b3d5-75ff60fbc6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037722458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.2037722458
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.2610307673
Short name T795
Test name
Test status
Simulation time 1251330906 ps
CPU time 9.33 seconds
Started Apr 30 12:32:13 PM PDT 24
Finished Apr 30 12:32:23 PM PDT 24
Peak memory 208316 kb
Host smart-e79e5a82-9056-4095-88f1-b457f7c3aa85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610307673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.2610307673
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.1281213120
Short name T494
Test name
Test status
Simulation time 373235331 ps
CPU time 7.76 seconds
Started Apr 30 12:32:26 PM PDT 24
Finished Apr 30 12:32:34 PM PDT 24
Peak memory 207608 kb
Host smart-ac71619c-2f1d-4965-be44-8c5d0e64e041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281213120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.1281213120
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.2793256854
Short name T522
Test name
Test status
Simulation time 238424197 ps
CPU time 6.5 seconds
Started Apr 30 12:32:13 PM PDT 24
Finished Apr 30 12:32:21 PM PDT 24
Peak memory 207432 kb
Host smart-a85a5865-42c9-4d5c-81b5-90d0976f0265
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793256854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.2793256854
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.2548885171
Short name T480
Test name
Test status
Simulation time 1787312513 ps
CPU time 7.92 seconds
Started Apr 30 12:32:26 PM PDT 24
Finished Apr 30 12:32:34 PM PDT 24
Peak memory 206364 kb
Host smart-ef10e52d-e0e3-4b2b-87bf-98791b1e486c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548885171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.2548885171
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.2281048916
Short name T470
Test name
Test status
Simulation time 42740804 ps
CPU time 1.89 seconds
Started Apr 30 12:32:20 PM PDT 24
Finished Apr 30 12:32:22 PM PDT 24
Peak memory 206940 kb
Host smart-6111b01d-5c85-41db-982f-29e0e33bd8b2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281048916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.2281048916
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.2003677996
Short name T828
Test name
Test status
Simulation time 158730187 ps
CPU time 3.38 seconds
Started Apr 30 12:32:12 PM PDT 24
Finished Apr 30 12:32:16 PM PDT 24
Peak memory 209388 kb
Host smart-1c846f0c-6997-4b19-84e7-89abbbb0aec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003677996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.2003677996
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.1749364239
Short name T762
Test name
Test status
Simulation time 596087915 ps
CPU time 13.77 seconds
Started Apr 30 12:32:14 PM PDT 24
Finished Apr 30 12:32:29 PM PDT 24
Peak memory 208004 kb
Host smart-cfa804da-8d7e-41e3-9295-c531a9386edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749364239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.1749364239
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.3992220518
Short name T585
Test name
Test status
Simulation time 50244575 ps
CPU time 3 seconds
Started Apr 30 12:32:23 PM PDT 24
Finished Apr 30 12:32:26 PM PDT 24
Peak memory 206500 kb
Host smart-194b8f0a-ea29-412a-ac9a-54db7334a130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992220518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.3992220518
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.3483969922
Short name T379
Test name
Test status
Simulation time 53616926 ps
CPU time 1.49 seconds
Started Apr 30 12:32:10 PM PDT 24
Finished Apr 30 12:32:12 PM PDT 24
Peak memory 218484 kb
Host smart-3c65e5d7-f35e-451f-aabb-81662ea2138c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483969922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.3483969922
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.3145929052
Short name T882
Test name
Test status
Simulation time 18971617 ps
CPU time 0.75 seconds
Started Apr 30 12:32:37 PM PDT 24
Finished Apr 30 12:32:39 PM PDT 24
Peak memory 205572 kb
Host smart-c58a4a36-f158-40ed-a198-aec8eecb3308
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145929052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.3145929052
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.1219703555
Short name T337
Test name
Test status
Simulation time 56860047 ps
CPU time 2.41 seconds
Started Apr 30 12:32:26 PM PDT 24
Finished Apr 30 12:32:28 PM PDT 24
Peak memory 214020 kb
Host smart-5e71c17d-71c5-4818-b6a8-fa7d64337a34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1219703555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.1219703555
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.727489103
Short name T783
Test name
Test status
Simulation time 527521239 ps
CPU time 2.66 seconds
Started Apr 30 12:32:15 PM PDT 24
Finished Apr 30 12:32:19 PM PDT 24
Peak memory 206812 kb
Host smart-9816a67e-40f1-4aa5-ad8a-08c904e1a7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727489103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.727489103
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.493070231
Short name T331
Test name
Test status
Simulation time 31384878 ps
CPU time 2.32 seconds
Started Apr 30 12:32:18 PM PDT 24
Finished Apr 30 12:32:21 PM PDT 24
Peak memory 210000 kb
Host smart-56207fde-eced-4272-af92-9c450d973a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493070231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.493070231
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.2342100898
Short name T43
Test name
Test status
Simulation time 85299138 ps
CPU time 3.32 seconds
Started Apr 30 12:32:13 PM PDT 24
Finished Apr 30 12:32:17 PM PDT 24
Peak memory 215644 kb
Host smart-5cdc08c8-24ab-49a2-ac48-96881699aa4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342100898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.2342100898
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.15756838
Short name T744
Test name
Test status
Simulation time 757132608 ps
CPU time 4.31 seconds
Started Apr 30 12:32:16 PM PDT 24
Finished Apr 30 12:32:21 PM PDT 24
Peak memory 208680 kb
Host smart-c24b3533-940a-4ff2-8f2b-2e0da6273bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15756838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.15756838
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.2487377725
Short name T878
Test name
Test status
Simulation time 1969329520 ps
CPU time 14.66 seconds
Started Apr 30 12:32:14 PM PDT 24
Finished Apr 30 12:32:30 PM PDT 24
Peak memory 206348 kb
Host smart-5dd813de-d9d8-4c02-8b37-57115ce4c3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487377725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.2487377725
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.2094180225
Short name T775
Test name
Test status
Simulation time 223776967 ps
CPU time 3.27 seconds
Started Apr 30 12:32:12 PM PDT 24
Finished Apr 30 12:32:16 PM PDT 24
Peak memory 206340 kb
Host smart-93ebf122-03c6-412c-a462-204190a3442e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094180225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.2094180225
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.2859626839
Short name T776
Test name
Test status
Simulation time 32689819 ps
CPU time 2.24 seconds
Started Apr 30 12:32:36 PM PDT 24
Finished Apr 30 12:32:39 PM PDT 24
Peak memory 206352 kb
Host smart-6162edf6-4212-43eb-b092-1057c2311860
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859626839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.2859626839
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.2177231534
Short name T197
Test name
Test status
Simulation time 449995592 ps
CPU time 7.13 seconds
Started Apr 30 12:33:24 PM PDT 24
Finished Apr 30 12:33:33 PM PDT 24
Peak memory 206960 kb
Host smart-def89f26-fd9c-4b1c-a692-3c6284e50cf2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177231534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.2177231534
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.4286646917
Short name T318
Test name
Test status
Simulation time 219751172 ps
CPU time 5.71 seconds
Started Apr 30 12:32:35 PM PDT 24
Finished Apr 30 12:32:42 PM PDT 24
Peak memory 217832 kb
Host smart-d16739d9-2409-4295-960a-e5cdf379e563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286646917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.4286646917
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.2259597102
Short name T899
Test name
Test status
Simulation time 789914384 ps
CPU time 5.4 seconds
Started Apr 30 12:32:20 PM PDT 24
Finished Apr 30 12:32:25 PM PDT 24
Peak memory 207340 kb
Host smart-5a947782-ceb3-4af0-9570-ef94b5e232e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259597102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.2259597102
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.311846704
Short name T518
Test name
Test status
Simulation time 881881094 ps
CPU time 5.36 seconds
Started Apr 30 12:33:35 PM PDT 24
Finished Apr 30 12:33:43 PM PDT 24
Peak memory 208956 kb
Host smart-a4259d9f-cfff-4c56-aa3f-3a8bd58c619d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311846704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.311846704
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.3125028199
Short name T425
Test name
Test status
Simulation time 37763468 ps
CPU time 2.03 seconds
Started Apr 30 12:32:28 PM PDT 24
Finished Apr 30 12:32:31 PM PDT 24
Peak memory 209432 kb
Host smart-ad03b63b-c0c5-4506-ad0d-aee1a8eb5695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125028199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.3125028199
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.1805799666
Short name T419
Test name
Test status
Simulation time 31711294 ps
CPU time 0.8 seconds
Started Apr 30 12:30:47 PM PDT 24
Finished Apr 30 12:30:50 PM PDT 24
Peak memory 205556 kb
Host smart-6ba8774f-c68d-4d35-be7f-dc9da929b104
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805799666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.1805799666
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.200775186
Short name T739
Test name
Test status
Simulation time 126613235 ps
CPU time 3.75 seconds
Started Apr 30 12:30:47 PM PDT 24
Finished Apr 30 12:30:52 PM PDT 24
Peak memory 213888 kb
Host smart-499acfd6-2233-4f80-b138-d662299bf16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200775186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.200775186
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.1245323883
Short name T310
Test name
Test status
Simulation time 6387838338 ps
CPU time 24.41 seconds
Started Apr 30 12:30:46 PM PDT 24
Finished Apr 30 12:31:11 PM PDT 24
Peak memory 214072 kb
Host smart-903550aa-a7f4-4d66-876e-0f8ef2c6594e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245323883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.1245323883
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.2102385714
Short name T758
Test name
Test status
Simulation time 197298357 ps
CPU time 3.38 seconds
Started Apr 30 12:30:52 PM PDT 24
Finished Apr 30 12:30:57 PM PDT 24
Peak memory 208764 kb
Host smart-1de9f5e0-64eb-4c8f-bce6-f1a4181e363e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102385714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.2102385714
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.4121958014
Short name T847
Test name
Test status
Simulation time 178391036 ps
CPU time 6.7 seconds
Started Apr 30 12:30:48 PM PDT 24
Finished Apr 30 12:30:56 PM PDT 24
Peak memory 222144 kb
Host smart-f4e67279-dff7-4479-8cb8-9b47082aa662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121958014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.4121958014
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.2512286536
Short name T717
Test name
Test status
Simulation time 69556381 ps
CPU time 3.69 seconds
Started Apr 30 12:30:48 PM PDT 24
Finished Apr 30 12:30:53 PM PDT 24
Peak memory 208296 kb
Host smart-f42da663-9fe0-44b3-b5e8-ce534bcf82b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512286536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.2512286536
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.2306180850
Short name T215
Test name
Test status
Simulation time 1333851687 ps
CPU time 9.09 seconds
Started Apr 30 12:30:48 PM PDT 24
Finished Apr 30 12:30:58 PM PDT 24
Peak memory 213968 kb
Host smart-ca05cfbb-da24-4e5c-9cc7-19ec7b7a4736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306180850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.2306180850
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.965732905
Short name T102
Test name
Test status
Simulation time 994151483 ps
CPU time 28.55 seconds
Started Apr 30 12:30:44 PM PDT 24
Finished Apr 30 12:31:13 PM PDT 24
Peak memory 235240 kb
Host smart-e00f531c-8b86-41eb-a859-64181762b005
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965732905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.965732905
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.1584802245
Short name T533
Test name
Test status
Simulation time 177081708 ps
CPU time 2.8 seconds
Started Apr 30 12:30:34 PM PDT 24
Finished Apr 30 12:30:38 PM PDT 24
Peak memory 206708 kb
Host smart-29bf3005-6748-49a0-bfa1-8419bf14749d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584802245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.1584802245
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.3571595013
Short name T902
Test name
Test status
Simulation time 123570093 ps
CPU time 3.9 seconds
Started Apr 30 12:30:48 PM PDT 24
Finished Apr 30 12:30:53 PM PDT 24
Peak memory 208560 kb
Host smart-a8cadbe8-eda3-4cd5-9ae9-eb4e8a22ba5c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571595013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.3571595013
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.3898525506
Short name T515
Test name
Test status
Simulation time 217863307 ps
CPU time 5.47 seconds
Started Apr 30 12:30:42 PM PDT 24
Finished Apr 30 12:30:49 PM PDT 24
Peak memory 208048 kb
Host smart-f4bff01e-3b27-4ba0-8cd1-fa718a834800
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898525506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.3898525506
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.4210137797
Short name T564
Test name
Test status
Simulation time 31958645 ps
CPU time 1.88 seconds
Started Apr 30 12:30:47 PM PDT 24
Finished Apr 30 12:30:50 PM PDT 24
Peak memory 206412 kb
Host smart-fa6b5616-a9c2-4eca-a3da-4a76c23afa0b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210137797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.4210137797
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.2611313669
Short name T797
Test name
Test status
Simulation time 59616860 ps
CPU time 2.67 seconds
Started Apr 30 12:30:49 PM PDT 24
Finished Apr 30 12:30:53 PM PDT 24
Peak memory 208720 kb
Host smart-adb9c663-ef04-4f4e-a9f3-ff9b0cf2b14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611313669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.2611313669
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.165833055
Short name T788
Test name
Test status
Simulation time 23723153 ps
CPU time 1.78 seconds
Started Apr 30 12:30:41 PM PDT 24
Finished Apr 30 12:30:44 PM PDT 24
Peak memory 206164 kb
Host smart-8e67e70e-54f8-4e2c-85c9-dbda188a9b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165833055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.165833055
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.913828805
Short name T663
Test name
Test status
Simulation time 212137950 ps
CPU time 6.86 seconds
Started Apr 30 12:30:48 PM PDT 24
Finished Apr 30 12:30:56 PM PDT 24
Peak memory 206568 kb
Host smart-10d8b987-1e71-46b0-a7b2-47b05670e842
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913828805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.913828805
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.3287283876
Short name T239
Test name
Test status
Simulation time 276184932 ps
CPU time 16.31 seconds
Started Apr 30 12:30:48 PM PDT 24
Finished Apr 30 12:31:06 PM PDT 24
Peak memory 222468 kb
Host smart-775e9adb-7aac-42ce-ae5a-9b8f7417b577
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287283876 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.3287283876
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.4242074018
Short name T316
Test name
Test status
Simulation time 37340766 ps
CPU time 2.96 seconds
Started Apr 30 12:30:48 PM PDT 24
Finished Apr 30 12:30:52 PM PDT 24
Peak memory 213884 kb
Host smart-6bbb4c17-60fb-4be9-8d42-52dbc8e4839d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242074018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.4242074018
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.2521476920
Short name T138
Test name
Test status
Simulation time 62121837 ps
CPU time 2.26 seconds
Started Apr 30 12:30:51 PM PDT 24
Finished Apr 30 12:30:56 PM PDT 24
Peak memory 210308 kb
Host smart-b1c0f23e-8789-4f02-9357-300aa57a953c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521476920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.2521476920
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.2136184774
Short name T99
Test name
Test status
Simulation time 10835359 ps
CPU time 0.89 seconds
Started Apr 30 12:32:27 PM PDT 24
Finished Apr 30 12:32:28 PM PDT 24
Peak memory 205464 kb
Host smart-713e56f5-04f3-49ab-a768-3debd8418c10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136184774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.2136184774
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.2211457593
Short name T402
Test name
Test status
Simulation time 314214150 ps
CPU time 5.05 seconds
Started Apr 30 12:32:24 PM PDT 24
Finished Apr 30 12:32:30 PM PDT 24
Peak memory 213988 kb
Host smart-49af4636-6441-4d50-bb22-cfe54474f4f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2211457593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.2211457593
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.2111907806
Short name T688
Test name
Test status
Simulation time 418861519 ps
CPU time 2.61 seconds
Started Apr 30 12:32:30 PM PDT 24
Finished Apr 30 12:32:33 PM PDT 24
Peak memory 214416 kb
Host smart-cd3acba2-690f-4eb9-a53c-7ee88a8f05d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111907806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.2111907806
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.3839002733
Short name T430
Test name
Test status
Simulation time 19695519 ps
CPU time 1.74 seconds
Started Apr 30 12:32:27 PM PDT 24
Finished Apr 30 12:32:30 PM PDT 24
Peak memory 207048 kb
Host smart-a9e010ca-bb72-41a3-890d-3527bed39eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839002733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.3839002733
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.1524710317
Short name T862
Test name
Test status
Simulation time 367941526 ps
CPU time 4.86 seconds
Started Apr 30 12:32:29 PM PDT 24
Finished Apr 30 12:32:35 PM PDT 24
Peak memory 209244 kb
Host smart-67166064-63f4-41b8-910b-fe74c2ec0455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524710317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.1524710317
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.1497755481
Short name T765
Test name
Test status
Simulation time 120534552 ps
CPU time 4.92 seconds
Started Apr 30 12:32:30 PM PDT 24
Finished Apr 30 12:32:35 PM PDT 24
Peak memory 209568 kb
Host smart-9c36ab6b-9248-4b73-8977-17d35c2ae5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497755481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.1497755481
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.3561303062
Short name T856
Test name
Test status
Simulation time 100503852 ps
CPU time 4.71 seconds
Started Apr 30 12:32:30 PM PDT 24
Finished Apr 30 12:32:35 PM PDT 24
Peak memory 208208 kb
Host smart-419d2117-c8d0-4b6d-ba27-40e8c1d8e430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561303062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.3561303062
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.3225784023
Short name T287
Test name
Test status
Simulation time 90839948 ps
CPU time 4.38 seconds
Started Apr 30 12:32:20 PM PDT 24
Finished Apr 30 12:32:25 PM PDT 24
Peak memory 206616 kb
Host smart-c86bc50d-7c2d-4c54-bbdf-911389cbf6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225784023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.3225784023
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.4193332072
Short name T69
Test name
Test status
Simulation time 175841709 ps
CPU time 7.29 seconds
Started Apr 30 12:32:27 PM PDT 24
Finished Apr 30 12:32:34 PM PDT 24
Peak memory 208488 kb
Host smart-6356d8b9-5ac1-4ece-880a-c331992fd9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193332072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.4193332072
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.1876091443
Short name T743
Test name
Test status
Simulation time 1075499789 ps
CPU time 14.6 seconds
Started Apr 30 12:32:34 PM PDT 24
Finished Apr 30 12:32:50 PM PDT 24
Peak memory 208708 kb
Host smart-ea1f4db4-fd80-4a58-8cee-ba44ffcaea3d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876091443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.1876091443
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.1824701643
Short name T779
Test name
Test status
Simulation time 524526056 ps
CPU time 7.38 seconds
Started Apr 30 12:32:35 PM PDT 24
Finished Apr 30 12:32:43 PM PDT 24
Peak memory 207728 kb
Host smart-2db9db20-5f21-4807-b8d0-ca26aec39d24
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824701643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.1824701643
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.1413687325
Short name T320
Test name
Test status
Simulation time 46732900 ps
CPU time 1.31 seconds
Started Apr 30 12:32:36 PM PDT 24
Finished Apr 30 12:32:39 PM PDT 24
Peak memory 206908 kb
Host smart-f29dd3a3-69b3-4a91-814c-a653568f4eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413687325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.1413687325
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.670712184
Short name T391
Test name
Test status
Simulation time 158466028 ps
CPU time 3.81 seconds
Started Apr 30 12:32:32 PM PDT 24
Finished Apr 30 12:32:36 PM PDT 24
Peak memory 206416 kb
Host smart-a22006f8-5a62-4c97-86b8-6f830d014217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670712184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.670712184
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.1747186819
Short name T257
Test name
Test status
Simulation time 1100262865 ps
CPU time 32.82 seconds
Started Apr 30 12:32:28 PM PDT 24
Finished Apr 30 12:33:02 PM PDT 24
Peak memory 215244 kb
Host smart-097ef8e9-7d97-44bb-a06e-3c4836d58adf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747186819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.1747186819
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.2982764083
Short name T372
Test name
Test status
Simulation time 273450480 ps
CPU time 3.19 seconds
Started Apr 30 12:32:28 PM PDT 24
Finished Apr 30 12:32:31 PM PDT 24
Peak memory 209312 kb
Host smart-ef3ae50e-47e5-4a47-b4c2-ef121a222158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982764083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.2982764083
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.4101433818
Short name T690
Test name
Test status
Simulation time 164410303 ps
CPU time 1.79 seconds
Started Apr 30 12:32:35 PM PDT 24
Finished Apr 30 12:32:38 PM PDT 24
Peak memory 210140 kb
Host smart-ac043241-9ceb-4eb8-83aa-5d2b874a4c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101433818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.4101433818
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.747753900
Short name T557
Test name
Test status
Simulation time 17754405 ps
CPU time 0.81 seconds
Started Apr 30 12:32:32 PM PDT 24
Finished Apr 30 12:32:33 PM PDT 24
Peak memory 205596 kb
Host smart-4f70bf9d-105c-4102-9e9b-d9ed29bac5c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747753900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.747753900
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.1503927888
Short name T408
Test name
Test status
Simulation time 39882588 ps
CPU time 3.14 seconds
Started Apr 30 12:32:28 PM PDT 24
Finished Apr 30 12:32:31 PM PDT 24
Peak memory 213984 kb
Host smart-93da1d98-c318-4042-b9c2-de248afbfbf0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1503927888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.1503927888
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.965367417
Short name T39
Test name
Test status
Simulation time 25566199 ps
CPU time 2.04 seconds
Started Apr 30 12:32:33 PM PDT 24
Finished Apr 30 12:32:35 PM PDT 24
Peak memory 207876 kb
Host smart-6b16215d-009a-42a8-8faa-4aaf9bfbc11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965367417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.965367417
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.267507434
Short name T83
Test name
Test status
Simulation time 479874577 ps
CPU time 4.11 seconds
Started Apr 30 12:32:27 PM PDT 24
Finished Apr 30 12:32:32 PM PDT 24
Peak memory 214008 kb
Host smart-279367a8-f85f-40c3-b087-f9ab54329f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267507434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.267507434
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.1294431947
Short name T228
Test name
Test status
Simulation time 388179634 ps
CPU time 4.84 seconds
Started Apr 30 12:32:29 PM PDT 24
Finished Apr 30 12:32:34 PM PDT 24
Peak memory 220112 kb
Host smart-d85213d3-bd8e-4990-9129-fb70a891b1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294431947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.1294431947
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.3726335477
Short name T303
Test name
Test status
Simulation time 259120528 ps
CPU time 6.9 seconds
Started Apr 30 12:32:29 PM PDT 24
Finished Apr 30 12:32:37 PM PDT 24
Peak memory 214016 kb
Host smart-b38dfa2c-b6fd-4204-a533-7a004d18b70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726335477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.3726335477
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.1317218891
Short name T698
Test name
Test status
Simulation time 1053365007 ps
CPU time 5.31 seconds
Started Apr 30 12:32:38 PM PDT 24
Finished Apr 30 12:32:44 PM PDT 24
Peak memory 206760 kb
Host smart-fea42a69-8ff9-4860-b314-be02b21e9fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317218891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.1317218891
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.403873736
Short name T742
Test name
Test status
Simulation time 1617972884 ps
CPU time 16.33 seconds
Started Apr 30 12:32:34 PM PDT 24
Finished Apr 30 12:32:51 PM PDT 24
Peak memory 207548 kb
Host smart-06a0e7eb-f32e-43c7-b9f7-7b1ed0f4192b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403873736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.403873736
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.1552201442
Short name T627
Test name
Test status
Simulation time 367996147 ps
CPU time 3.95 seconds
Started Apr 30 12:32:34 PM PDT 24
Finished Apr 30 12:32:39 PM PDT 24
Peak memory 208388 kb
Host smart-919e83c8-a4f5-4097-8703-2d55230f6793
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552201442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.1552201442
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.3565927161
Short name T756
Test name
Test status
Simulation time 787233866 ps
CPU time 8.31 seconds
Started Apr 30 12:32:34 PM PDT 24
Finished Apr 30 12:32:43 PM PDT 24
Peak memory 208140 kb
Host smart-d01f79e7-7208-4429-bac8-f02baa6c0912
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565927161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.3565927161
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.536298106
Short name T496
Test name
Test status
Simulation time 27425311 ps
CPU time 1.97 seconds
Started Apr 30 12:32:36 PM PDT 24
Finished Apr 30 12:32:39 PM PDT 24
Peak memory 207780 kb
Host smart-79a56637-ef11-442c-bae2-8fa642933633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536298106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.536298106
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.370822915
Short name T516
Test name
Test status
Simulation time 64935922 ps
CPU time 2.62 seconds
Started Apr 30 12:32:35 PM PDT 24
Finished Apr 30 12:32:38 PM PDT 24
Peak memory 206656 kb
Host smart-9b61dfdc-bcca-4709-a19c-ebfb2dad8da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370822915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.370822915
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.353498704
Short name T491
Test name
Test status
Simulation time 3808316791 ps
CPU time 29.62 seconds
Started Apr 30 12:32:34 PM PDT 24
Finished Apr 30 12:33:05 PM PDT 24
Peak memory 218836 kb
Host smart-2b47828c-bd55-4dbc-be04-8f452f498836
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353498704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.353498704
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.4281723919
Short name T100
Test name
Test status
Simulation time 1175537533 ps
CPU time 11.73 seconds
Started Apr 30 12:32:34 PM PDT 24
Finished Apr 30 12:32:46 PM PDT 24
Peak memory 222200 kb
Host smart-ebd80148-6909-4cbe-ae1c-bf64a713f334
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281723919 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.4281723919
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.1791447091
Short name T571
Test name
Test status
Simulation time 3587185361 ps
CPU time 22.93 seconds
Started Apr 30 12:32:37 PM PDT 24
Finished Apr 30 12:33:01 PM PDT 24
Peak memory 207936 kb
Host smart-049db5c8-a40d-45f9-ae31-4035088a99b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791447091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.1791447091
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.2328189276
Short name T823
Test name
Test status
Simulation time 1005052356 ps
CPU time 14.83 seconds
Started Apr 30 12:32:39 PM PDT 24
Finished Apr 30 12:32:55 PM PDT 24
Peak memory 210656 kb
Host smart-70fb6a92-5c1a-490f-aeab-cc860a164453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328189276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.2328189276
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.3736960825
Short name T415
Test name
Test status
Simulation time 11775174 ps
CPU time 0.74 seconds
Started Apr 30 12:32:33 PM PDT 24
Finished Apr 30 12:32:34 PM PDT 24
Peak memory 205608 kb
Host smart-640127e6-902b-4198-b0f6-bb7d35651c07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736960825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.3736960825
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.2864204268
Short name T245
Test name
Test status
Simulation time 637036099 ps
CPU time 9.3 seconds
Started Apr 30 12:32:39 PM PDT 24
Finished Apr 30 12:32:50 PM PDT 24
Peak memory 214160 kb
Host smart-cf119d92-352e-4391-b275-1b2d3bba80d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2864204268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.2864204268
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.2709710171
Short name T4
Test name
Test status
Simulation time 528519225 ps
CPU time 3.93 seconds
Started Apr 30 12:32:41 PM PDT 24
Finished Apr 30 12:32:46 PM PDT 24
Peak memory 208820 kb
Host smart-dc0f8b9a-4344-400e-b120-702cf1c3b4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709710171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.2709710171
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.1870953252
Short name T65
Test name
Test status
Simulation time 651404300 ps
CPU time 6.64 seconds
Started Apr 30 12:32:41 PM PDT 24
Finished Apr 30 12:32:54 PM PDT 24
Peak memory 218172 kb
Host smart-e9fdde71-a1ff-4796-bdaa-848c3e321faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870953252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.1870953252
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.39515336
Short name T549
Test name
Test status
Simulation time 32440127 ps
CPU time 2.24 seconds
Started Apr 30 12:32:34 PM PDT 24
Finished Apr 30 12:32:37 PM PDT 24
Peak memory 208892 kb
Host smart-d9456431-cea0-465d-8354-2bc4a66aba60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39515336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.39515336
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.206165919
Short name T774
Test name
Test status
Simulation time 108576466 ps
CPU time 3.1 seconds
Started Apr 30 12:32:33 PM PDT 24
Finished Apr 30 12:32:37 PM PDT 24
Peak memory 209964 kb
Host smart-1901e99a-853d-47e1-9c0d-87a5a6112052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206165919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.206165919
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.2226352084
Short name T825
Test name
Test status
Simulation time 1040889005 ps
CPU time 7.99 seconds
Started Apr 30 12:32:33 PM PDT 24
Finished Apr 30 12:32:42 PM PDT 24
Peak memory 206776 kb
Host smart-012c2115-11d7-40fa-9200-0091469b19b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226352084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2226352084
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.4283786709
Short name T763
Test name
Test status
Simulation time 79409737 ps
CPU time 2.46 seconds
Started Apr 30 12:32:24 PM PDT 24
Finished Apr 30 12:32:27 PM PDT 24
Peak memory 206460 kb
Host smart-d26e3991-8df5-46e1-a158-4dd6ffffaae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283786709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.4283786709
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.2668224890
Short name T598
Test name
Test status
Simulation time 479585554 ps
CPU time 4.39 seconds
Started Apr 30 12:32:37 PM PDT 24
Finished Apr 30 12:32:43 PM PDT 24
Peak memory 208268 kb
Host smart-4db11bc1-805c-4bbd-a9f0-66a6430a538d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668224890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.2668224890
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.133213637
Short name T584
Test name
Test status
Simulation time 4764891238 ps
CPU time 48.39 seconds
Started Apr 30 12:32:30 PM PDT 24
Finished Apr 30 12:33:19 PM PDT 24
Peak memory 207968 kb
Host smart-6f16a6f5-c37e-4f7d-85d1-ebe0177f4656
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133213637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.133213637
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.3126312313
Short name T636
Test name
Test status
Simulation time 300642745 ps
CPU time 4.38 seconds
Started Apr 30 12:32:36 PM PDT 24
Finished Apr 30 12:32:41 PM PDT 24
Peak memory 206392 kb
Host smart-40b771d3-d070-468b-a36f-33422657c5f0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126312313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.3126312313
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.274442118
Short name T851
Test name
Test status
Simulation time 294521336 ps
CPU time 2.5 seconds
Started Apr 30 12:32:44 PM PDT 24
Finished Apr 30 12:32:47 PM PDT 24
Peak memory 215200 kb
Host smart-203c65f8-1cf4-4984-ad02-9a86af2b7d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274442118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.274442118
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.4290995905
Short name T834
Test name
Test status
Simulation time 305092346 ps
CPU time 3.04 seconds
Started Apr 30 12:32:35 PM PDT 24
Finished Apr 30 12:32:38 PM PDT 24
Peak memory 208280 kb
Host smart-d03923e7-5245-4b88-9f16-5e5a2f02a3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290995905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.4290995905
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.2979527335
Short name T242
Test name
Test status
Simulation time 9184104694 ps
CPU time 31.62 seconds
Started Apr 30 12:32:37 PM PDT 24
Finished Apr 30 12:33:10 PM PDT 24
Peak memory 216188 kb
Host smart-0e36c85c-5a77-449a-bb8b-562aece0ece2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979527335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.2979527335
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.2395262346
Short name T528
Test name
Test status
Simulation time 1229225304 ps
CPU time 8.15 seconds
Started Apr 30 12:32:36 PM PDT 24
Finished Apr 30 12:32:45 PM PDT 24
Peak memory 208764 kb
Host smart-d8d4883c-bafa-45e2-b881-57ed871ba882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395262346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.2395262346
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.464650631
Short name T378
Test name
Test status
Simulation time 254959029 ps
CPU time 2.09 seconds
Started Apr 30 12:32:35 PM PDT 24
Finished Apr 30 12:32:38 PM PDT 24
Peak memory 209484 kb
Host smart-5cede511-2860-4bfe-b71c-3e2b11cb35b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464650631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.464650631
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.3909284647
Short name T681
Test name
Test status
Simulation time 35462138 ps
CPU time 0.77 seconds
Started Apr 30 12:32:40 PM PDT 24
Finished Apr 30 12:32:42 PM PDT 24
Peak memory 205680 kb
Host smart-a1ec87eb-75ce-4a91-8be8-a97af6278985
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909284647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.3909284647
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.3248842272
Short name T409
Test name
Test status
Simulation time 526059477 ps
CPU time 8.24 seconds
Started Apr 30 12:32:34 PM PDT 24
Finished Apr 30 12:32:43 PM PDT 24
Peak memory 215096 kb
Host smart-693c7243-04a2-42c4-9148-8d3f5a0ebffc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3248842272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.3248842272
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.647245364
Short name T692
Test name
Test status
Simulation time 86660234 ps
CPU time 2.66 seconds
Started Apr 30 12:32:37 PM PDT 24
Finished Apr 30 12:32:41 PM PDT 24
Peak memory 208896 kb
Host smart-89302f57-8cc5-4e1b-aa46-9509fc4db214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647245364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.647245364
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.4049271088
Short name T447
Test name
Test status
Simulation time 306761835 ps
CPU time 2.79 seconds
Started Apr 30 12:32:30 PM PDT 24
Finished Apr 30 12:32:34 PM PDT 24
Peak memory 206808 kb
Host smart-659e7384-f5e7-4c81-b6e2-edd6140c9b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049271088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.4049271088
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.4177073036
Short name T384
Test name
Test status
Simulation time 425940007 ps
CPU time 5.58 seconds
Started Apr 30 12:32:38 PM PDT 24
Finished Apr 30 12:32:45 PM PDT 24
Peak memory 214024 kb
Host smart-dcace5f8-eb42-49d7-88b6-ebbd03968903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177073036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.4177073036
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.1423393774
Short name T885
Test name
Test status
Simulation time 572676086 ps
CPU time 4.02 seconds
Started Apr 30 12:32:34 PM PDT 24
Finished Apr 30 12:32:39 PM PDT 24
Peak memory 219468 kb
Host smart-e5cc98b6-1ea3-46ca-b3de-3d57440b9c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423393774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.1423393774
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.3296819383
Short name T895
Test name
Test status
Simulation time 494271758 ps
CPU time 5.11 seconds
Started Apr 30 12:32:37 PM PDT 24
Finished Apr 30 12:32:43 PM PDT 24
Peak memory 209900 kb
Host smart-a8502547-a5e5-4580-84cc-d352217c3b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296819383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.3296819383
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.2477282107
Short name T72
Test name
Test status
Simulation time 210086312 ps
CPU time 2.92 seconds
Started Apr 30 12:32:43 PM PDT 24
Finished Apr 30 12:32:47 PM PDT 24
Peak memory 207932 kb
Host smart-6e00502f-41bd-44bd-9f64-f0e09b489bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477282107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.2477282107
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.3451443889
Short name T644
Test name
Test status
Simulation time 1659921887 ps
CPU time 41.06 seconds
Started Apr 30 12:32:35 PM PDT 24
Finished Apr 30 12:33:16 PM PDT 24
Peak memory 208544 kb
Host smart-eb90bd0b-bd04-4158-b0c7-27c75791c019
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451443889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.3451443889
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.4242277122
Short name T740
Test name
Test status
Simulation time 491194316 ps
CPU time 5.95 seconds
Started Apr 30 12:32:35 PM PDT 24
Finished Apr 30 12:32:42 PM PDT 24
Peak memory 206340 kb
Host smart-d67e458d-6979-4a7d-a52c-561c49bce95d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242277122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.4242277122
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.3898859620
Short name T541
Test name
Test status
Simulation time 824825852 ps
CPU time 2.65 seconds
Started Apr 30 12:32:37 PM PDT 24
Finished Apr 30 12:32:40 PM PDT 24
Peak memory 206540 kb
Host smart-1e602b10-db1a-4266-b6a6-780634af6c0b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898859620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.3898859620
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.1157755859
Short name T405
Test name
Test status
Simulation time 278861322 ps
CPU time 3.15 seconds
Started Apr 30 12:32:33 PM PDT 24
Finished Apr 30 12:32:36 PM PDT 24
Peak memory 209312 kb
Host smart-ada42978-1502-4a01-b7c9-800f9746bc2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157755859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.1157755859
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.1431375839
Short name T13
Test name
Test status
Simulation time 5803411749 ps
CPU time 31.68 seconds
Started Apr 30 12:32:39 PM PDT 24
Finished Apr 30 12:33:12 PM PDT 24
Peak memory 207348 kb
Host smart-2f12fb4d-0c71-4c03-a2cb-16c028b038da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431375839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.1431375839
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.334013252
Short name T596
Test name
Test status
Simulation time 408892075 ps
CPU time 16.7 seconds
Started Apr 30 12:32:40 PM PDT 24
Finished Apr 30 12:32:57 PM PDT 24
Peak memory 220452 kb
Host smart-5561ab13-f83b-4a2d-bf86-0ed41f7ccfc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334013252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.334013252
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.1285116838
Short name T206
Test name
Test status
Simulation time 45233121 ps
CPU time 2.95 seconds
Started Apr 30 12:32:40 PM PDT 24
Finished Apr 30 12:32:44 PM PDT 24
Peak memory 207692 kb
Host smart-09478216-9af0-4167-a354-a0c1da9723f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285116838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.1285116838
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.1178376402
Short name T679
Test name
Test status
Simulation time 54292492 ps
CPU time 2.34 seconds
Started Apr 30 12:32:34 PM PDT 24
Finished Apr 30 12:32:37 PM PDT 24
Peak memory 209928 kb
Host smart-b4cb6744-0fdd-4468-b794-4f76e86bf5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178376402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.1178376402
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.139091625
Short name T865
Test name
Test status
Simulation time 13670444 ps
CPU time 0.84 seconds
Started Apr 30 12:32:36 PM PDT 24
Finished Apr 30 12:32:38 PM PDT 24
Peak memory 205576 kb
Host smart-85c9140d-2b7f-4051-bef7-7d0ef739dfb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139091625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.139091625
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.1807137041
Short name T826
Test name
Test status
Simulation time 37500694 ps
CPU time 3.09 seconds
Started Apr 30 12:32:40 PM PDT 24
Finished Apr 30 12:32:44 PM PDT 24
Peak memory 214196 kb
Host smart-b390ad20-e878-4189-93b7-862d3d9f8c19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1807137041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.1807137041
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.1103217966
Short name T226
Test name
Test status
Simulation time 746261888 ps
CPU time 5.73 seconds
Started Apr 30 12:32:35 PM PDT 24
Finished Apr 30 12:32:41 PM PDT 24
Peak memory 209560 kb
Host smart-12b27a0f-4f31-4144-b5dc-2485edc99ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103217966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.1103217966
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.3942596482
Short name T738
Test name
Test status
Simulation time 35371141 ps
CPU time 2.25 seconds
Started Apr 30 12:32:37 PM PDT 24
Finished Apr 30 12:32:40 PM PDT 24
Peak memory 206576 kb
Host smart-6dc54dd6-f228-41f9-877d-84b8a42e52bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942596482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.3942596482
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.1984873462
Short name T375
Test name
Test status
Simulation time 974066107 ps
CPU time 7.6 seconds
Started Apr 30 12:32:46 PM PDT 24
Finished Apr 30 12:32:55 PM PDT 24
Peak memory 209776 kb
Host smart-60c2c5b7-db63-4e13-9b6b-837e10b502b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984873462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.1984873462
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_random.1051371736
Short name T321
Test name
Test status
Simulation time 666614804 ps
CPU time 21.38 seconds
Started Apr 30 12:32:37 PM PDT 24
Finished Apr 30 12:33:00 PM PDT 24
Peak memory 218032 kb
Host smart-a296d716-d307-4f91-9b1d-e40ef9abc677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051371736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.1051371736
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.2215918261
Short name T464
Test name
Test status
Simulation time 708320571 ps
CPU time 10.21 seconds
Started Apr 30 12:32:37 PM PDT 24
Finished Apr 30 12:32:48 PM PDT 24
Peak memory 207488 kb
Host smart-ced1eba9-2433-49f9-a05a-6081fd3ef2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215918261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.2215918261
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.53980521
Short name T656
Test name
Test status
Simulation time 1826338590 ps
CPU time 51.87 seconds
Started Apr 30 12:32:35 PM PDT 24
Finished Apr 30 12:33:28 PM PDT 24
Peak memory 207720 kb
Host smart-d426951e-f98c-4e73-8eae-03733d935d0e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53980521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.53980521
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.1013456119
Short name T814
Test name
Test status
Simulation time 5893625799 ps
CPU time 60.92 seconds
Started Apr 30 12:32:36 PM PDT 24
Finished Apr 30 12:33:37 PM PDT 24
Peak memory 208688 kb
Host smart-07c716b9-bf93-4ca4-8a94-2ff31e747035
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013456119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.1013456119
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.3144702414
Short name T696
Test name
Test status
Simulation time 64941961 ps
CPU time 3.33 seconds
Started Apr 30 12:32:39 PM PDT 24
Finished Apr 30 12:32:43 PM PDT 24
Peak memory 208556 kb
Host smart-9eeeb8d0-a93d-4c92-9a0b-7bd93d3d8920
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144702414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.3144702414
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.4069859006
Short name T344
Test name
Test status
Simulation time 146799501 ps
CPU time 3.35 seconds
Started Apr 30 12:32:35 PM PDT 24
Finished Apr 30 12:32:40 PM PDT 24
Peak memory 215372 kb
Host smart-043019cc-9220-42ad-84a7-11b5cb302394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069859006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.4069859006
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.2332443868
Short name T487
Test name
Test status
Simulation time 97460045 ps
CPU time 3.95 seconds
Started Apr 30 12:32:36 PM PDT 24
Finished Apr 30 12:32:41 PM PDT 24
Peak memory 208384 kb
Host smart-1612dbd6-667d-4526-9cd1-5182b6cedac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332443868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.2332443868
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.3878861444
Short name T599
Test name
Test status
Simulation time 4997344683 ps
CPU time 38.61 seconds
Started Apr 30 12:32:42 PM PDT 24
Finished Apr 30 12:33:21 PM PDT 24
Peak memory 215852 kb
Host smart-0a09de9c-5d27-4357-b6e2-d79232cdc720
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878861444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.3878861444
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.2256973158
Short name T583
Test name
Test status
Simulation time 743602542 ps
CPU time 5.83 seconds
Started Apr 30 12:32:34 PM PDT 24
Finished Apr 30 12:32:41 PM PDT 24
Peak memory 217936 kb
Host smart-e30ed016-d672-492f-849a-0975811182b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256973158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.2256973158
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.2251932398
Short name T530
Test name
Test status
Simulation time 202126188 ps
CPU time 4.79 seconds
Started Apr 30 12:32:37 PM PDT 24
Finished Apr 30 12:32:43 PM PDT 24
Peak memory 209928 kb
Host smart-50291990-ad60-41db-aacb-55b3b3fa4f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251932398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.2251932398
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.1969267581
Short name T593
Test name
Test status
Simulation time 25083444 ps
CPU time 0.78 seconds
Started Apr 30 12:32:37 PM PDT 24
Finished Apr 30 12:32:39 PM PDT 24
Peak memory 205504 kb
Host smart-dba3bd7d-de84-40fa-ade4-28d0a5201e67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969267581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.1969267581
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.2733593372
Short name T381
Test name
Test status
Simulation time 218117044 ps
CPU time 3.97 seconds
Started Apr 30 12:32:29 PM PDT 24
Finished Apr 30 12:32:33 PM PDT 24
Peak memory 213984 kb
Host smart-fb0651fe-ca96-44c6-a301-6dd6648c249b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2733593372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.2733593372
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.3614465950
Short name T291
Test name
Test status
Simulation time 54062385 ps
CPU time 2.81 seconds
Started Apr 30 12:32:39 PM PDT 24
Finished Apr 30 12:32:43 PM PDT 24
Peak memory 208980 kb
Host smart-47eda4d9-2d27-4b5d-a1c5-90475bbd7c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614465950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.3614465950
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.2501467651
Short name T767
Test name
Test status
Simulation time 186565027 ps
CPU time 5.11 seconds
Started Apr 30 12:32:36 PM PDT 24
Finished Apr 30 12:32:42 PM PDT 24
Peak memory 219548 kb
Host smart-552a498c-0162-40cd-ba16-25d17c048cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501467651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.2501467651
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.205186990
Short name T649
Test name
Test status
Simulation time 277967908 ps
CPU time 8.89 seconds
Started Apr 30 12:32:38 PM PDT 24
Finished Apr 30 12:32:48 PM PDT 24
Peak memory 213916 kb
Host smart-49f4fcbc-f0ed-448f-9646-62c2f59f17fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205186990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.205186990
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.2539975136
Short name T617
Test name
Test status
Simulation time 394561840 ps
CPU time 3.91 seconds
Started Apr 30 12:32:33 PM PDT 24
Finished Apr 30 12:32:38 PM PDT 24
Peak memory 209016 kb
Host smart-2920b9dc-897d-49b2-9ead-50c7500df6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539975136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.2539975136
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.2866217379
Short name T674
Test name
Test status
Simulation time 470662125 ps
CPU time 6.03 seconds
Started Apr 30 12:32:33 PM PDT 24
Finished Apr 30 12:32:40 PM PDT 24
Peak memory 210208 kb
Host smart-ae898ecd-4e58-41c1-9003-09d96bc0fc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866217379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.2866217379
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.3433557380
Short name T477
Test name
Test status
Simulation time 96655091 ps
CPU time 4.08 seconds
Started Apr 30 12:32:38 PM PDT 24
Finished Apr 30 12:32:44 PM PDT 24
Peak memory 206796 kb
Host smart-2c4620d9-f2bb-46dd-9ee5-5f2970eba12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433557380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.3433557380
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.2757660189
Short name T850
Test name
Test status
Simulation time 361091391 ps
CPU time 6.67 seconds
Started Apr 30 12:32:40 PM PDT 24
Finished Apr 30 12:32:48 PM PDT 24
Peak memory 207644 kb
Host smart-ff36561b-af04-478b-9449-594f80a30ad0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757660189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.2757660189
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.3665726302
Short name T588
Test name
Test status
Simulation time 122439217 ps
CPU time 4.89 seconds
Started Apr 30 12:32:39 PM PDT 24
Finished Apr 30 12:32:45 PM PDT 24
Peak memory 208056 kb
Host smart-a64114a0-0e3f-4f80-837c-f59e6d57e565
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665726302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.3665726302
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.3359961010
Short name T523
Test name
Test status
Simulation time 225345492 ps
CPU time 7.29 seconds
Started Apr 30 12:32:38 PM PDT 24
Finished Apr 30 12:32:46 PM PDT 24
Peak memory 208416 kb
Host smart-2a69007f-dca1-4a61-bd36-4e67b936bab9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359961010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.3359961010
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.429690180
Short name T509
Test name
Test status
Simulation time 1423925478 ps
CPU time 3.86 seconds
Started Apr 30 12:32:39 PM PDT 24
Finished Apr 30 12:32:44 PM PDT 24
Peak memory 209440 kb
Host smart-ba8662ff-838a-44c4-aba2-6d5cd61c72fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429690180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.429690180
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.549341701
Short name T132
Test name
Test status
Simulation time 561747924 ps
CPU time 9.96 seconds
Started Apr 30 12:32:36 PM PDT 24
Finished Apr 30 12:32:47 PM PDT 24
Peak memory 207672 kb
Host smart-ab3c4310-87e0-4649-893b-94c6fdc70ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549341701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.549341701
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.2384363529
Short name T540
Test name
Test status
Simulation time 5237965944 ps
CPU time 46.09 seconds
Started Apr 30 12:32:48 PM PDT 24
Finished Apr 30 12:33:35 PM PDT 24
Peak memory 216360 kb
Host smart-54788649-9d3b-44b4-bd1a-f7d2d933ea12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384363529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.2384363529
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.3516546014
Short name T495
Test name
Test status
Simulation time 73351902 ps
CPU time 2.57 seconds
Started Apr 30 12:32:36 PM PDT 24
Finished Apr 30 12:32:40 PM PDT 24
Peak memory 213996 kb
Host smart-aca12306-e598-4fe8-af42-acc1d3492f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516546014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.3516546014
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.2471533633
Short name T466
Test name
Test status
Simulation time 67079789 ps
CPU time 2.09 seconds
Started Apr 30 12:32:36 PM PDT 24
Finished Apr 30 12:32:39 PM PDT 24
Peak memory 209664 kb
Host smart-31dac1f0-c422-4575-98e4-6752dd52745f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471533633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.2471533633
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.2917128260
Short name T626
Test name
Test status
Simulation time 14441621 ps
CPU time 0.88 seconds
Started Apr 30 12:32:40 PM PDT 24
Finished Apr 30 12:32:42 PM PDT 24
Peak memory 205696 kb
Host smart-6abe9f98-265f-40f8-98b1-4afccff12632
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917128260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.2917128260
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.797324587
Short name T284
Test name
Test status
Simulation time 40808823 ps
CPU time 3.18 seconds
Started Apr 30 12:32:34 PM PDT 24
Finished Apr 30 12:32:38 PM PDT 24
Peak memory 214016 kb
Host smart-e156f40d-fc11-4793-a7db-21529e7b03c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=797324587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.797324587
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.1102528396
Short name T840
Test name
Test status
Simulation time 104516401 ps
CPU time 4.56 seconds
Started Apr 30 12:32:45 PM PDT 24
Finished Apr 30 12:32:50 PM PDT 24
Peak memory 208328 kb
Host smart-f0b5f895-4062-4633-a2ef-86049c147530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102528396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.1102528396
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.262859390
Short name T768
Test name
Test status
Simulation time 50134144 ps
CPU time 1.55 seconds
Started Apr 30 12:32:36 PM PDT 24
Finished Apr 30 12:32:39 PM PDT 24
Peak memory 206976 kb
Host smart-f5cd6db0-1e9e-4ec0-bc1f-ed773703b567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262859390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.262859390
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.4166188530
Short name T388
Test name
Test status
Simulation time 124900619 ps
CPU time 3.89 seconds
Started Apr 30 12:32:52 PM PDT 24
Finished Apr 30 12:32:57 PM PDT 24
Peak memory 218060 kb
Host smart-d6be8324-2b54-408e-9b05-e7074822ea09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166188530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.4166188530
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.3621725591
Short name T716
Test name
Test status
Simulation time 4900447213 ps
CPU time 13.18 seconds
Started Apr 30 12:32:36 PM PDT 24
Finished Apr 30 12:32:50 PM PDT 24
Peak memory 214036 kb
Host smart-12ea4ece-ce00-4a06-913a-753e829908a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621725591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.3621725591
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.3220901783
Short name T741
Test name
Test status
Simulation time 32067866 ps
CPU time 2.51 seconds
Started Apr 30 12:32:36 PM PDT 24
Finished Apr 30 12:32:40 PM PDT 24
Peak memory 215812 kb
Host smart-8f405e48-1f17-43d5-850f-f7d229685ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220901783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.3220901783
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.209805994
Short name T438
Test name
Test status
Simulation time 444456540 ps
CPU time 4.87 seconds
Started Apr 30 12:32:41 PM PDT 24
Finished Apr 30 12:32:47 PM PDT 24
Peak memory 209208 kb
Host smart-275c81f9-1ddb-4a6f-bc9d-ee4d9e3020d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209805994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.209805994
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.2248200136
Short name T443
Test name
Test status
Simulation time 1563036612 ps
CPU time 4.38 seconds
Started Apr 30 12:32:34 PM PDT 24
Finished Apr 30 12:32:39 PM PDT 24
Peak memory 206456 kb
Host smart-3263dccb-e298-488b-8773-f9b83e5caafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248200136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.2248200136
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.1025278632
Short name T642
Test name
Test status
Simulation time 459438690 ps
CPU time 2.51 seconds
Started Apr 30 12:32:40 PM PDT 24
Finished Apr 30 12:32:44 PM PDT 24
Peak memory 208240 kb
Host smart-d43f51cc-232a-4cbe-9972-66fe406e2f16
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025278632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.1025278632
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.2282245327
Short name T590
Test name
Test status
Simulation time 38604685 ps
CPU time 2.4 seconds
Started Apr 30 12:32:38 PM PDT 24
Finished Apr 30 12:32:42 PM PDT 24
Peak memory 206340 kb
Host smart-b50cf34f-4ddb-4643-ab3c-9cbfec43bb3e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282245327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.2282245327
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.688873717
Short name T511
Test name
Test status
Simulation time 620099326 ps
CPU time 15.98 seconds
Started Apr 30 12:32:36 PM PDT 24
Finished Apr 30 12:32:53 PM PDT 24
Peak memory 207580 kb
Host smart-32b6edea-0829-4f1c-a7da-1cbf0f4f1e00
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688873717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.688873717
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.3987738295
Short name T695
Test name
Test status
Simulation time 252569918 ps
CPU time 4.73 seconds
Started Apr 30 12:32:44 PM PDT 24
Finished Apr 30 12:32:49 PM PDT 24
Peak memory 208876 kb
Host smart-0feb35d0-59d8-41fc-a35a-533a9d44dbc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987738295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.3987738295
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.1561797477
Short name T536
Test name
Test status
Simulation time 119630930 ps
CPU time 2.94 seconds
Started Apr 30 12:32:39 PM PDT 24
Finished Apr 30 12:32:43 PM PDT 24
Peak memory 206360 kb
Host smart-da8833a3-d20b-4c58-b174-fa8d84ce3f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561797477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.1561797477
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.3375942508
Short name T260
Test name
Test status
Simulation time 707566303 ps
CPU time 23.55 seconds
Started Apr 30 12:32:43 PM PDT 24
Finished Apr 30 12:33:07 PM PDT 24
Peak memory 214916 kb
Host smart-77466173-9e7e-4dd7-a277-d87536740047
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375942508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.3375942508
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.2947600693
Short name T128
Test name
Test status
Simulation time 218114148 ps
CPU time 5.73 seconds
Started Apr 30 12:32:44 PM PDT 24
Finished Apr 30 12:32:51 PM PDT 24
Peak memory 219496 kb
Host smart-950c480f-68ef-4192-b2af-4bb5b67fc773
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947600693 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.2947600693
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.1013345106
Short name T634
Test name
Test status
Simulation time 174350357 ps
CPU time 5.61 seconds
Started Apr 30 12:32:38 PM PDT 24
Finished Apr 30 12:32:45 PM PDT 24
Peak memory 209580 kb
Host smart-3a33e538-42da-41e7-98a4-edad63d68959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013345106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.1013345106
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.1994986340
Short name T664
Test name
Test status
Simulation time 85078681 ps
CPU time 3.2 seconds
Started Apr 30 12:32:44 PM PDT 24
Finished Apr 30 12:32:48 PM PDT 24
Peak memory 209456 kb
Host smart-ac19d49d-8cc8-46f0-afd7-e5487e96b794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994986340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.1994986340
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.2204341501
Short name T451
Test name
Test status
Simulation time 13057304 ps
CPU time 0.8 seconds
Started Apr 30 12:32:42 PM PDT 24
Finished Apr 30 12:32:43 PM PDT 24
Peak memory 205568 kb
Host smart-ac5f121b-1698-4ec0-b974-a6d33239cd5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204341501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.2204341501
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.388027197
Short name T412
Test name
Test status
Simulation time 184564278 ps
CPU time 2.89 seconds
Started Apr 30 12:32:45 PM PDT 24
Finished Apr 30 12:32:49 PM PDT 24
Peak memory 213924 kb
Host smart-4a0ae151-aa9d-467c-8531-22fa1ad25820
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=388027197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.388027197
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.1831979468
Short name T615
Test name
Test status
Simulation time 41286110 ps
CPU time 2.26 seconds
Started Apr 30 12:32:41 PM PDT 24
Finished Apr 30 12:32:44 PM PDT 24
Peak memory 220068 kb
Host smart-5435a243-c979-49ff-80f1-a579b71c504d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831979468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.1831979468
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.1447039918
Short name T64
Test name
Test status
Simulation time 424085593 ps
CPU time 5.2 seconds
Started Apr 30 12:32:41 PM PDT 24
Finished Apr 30 12:32:47 PM PDT 24
Peak memory 208288 kb
Host smart-a38f72f0-ceb2-4098-92ec-68c30ecc9bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447039918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.1447039918
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.736655505
Short name T25
Test name
Test status
Simulation time 1478616255 ps
CPU time 13.18 seconds
Started Apr 30 12:32:35 PM PDT 24
Finished Apr 30 12:32:49 PM PDT 24
Peak memory 211576 kb
Host smart-c440ba45-cf02-480c-9409-5586acee46d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736655505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.736655505
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.2966089362
Short name T641
Test name
Test status
Simulation time 182111460 ps
CPU time 3.59 seconds
Started Apr 30 12:32:40 PM PDT 24
Finished Apr 30 12:32:45 PM PDT 24
Peak memory 209372 kb
Host smart-46eb3868-71cf-43ce-9af2-b08d5700bd71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966089362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.2966089362
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.560362137
Short name T341
Test name
Test status
Simulation time 4278401908 ps
CPU time 12.35 seconds
Started Apr 30 12:32:39 PM PDT 24
Finished Apr 30 12:32:53 PM PDT 24
Peak memory 217964 kb
Host smart-d19ad048-76de-41dc-a25e-71cc30a9955f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560362137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.560362137
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.4139209620
Short name T106
Test name
Test status
Simulation time 138647711 ps
CPU time 4.54 seconds
Started Apr 30 12:32:41 PM PDT 24
Finished Apr 30 12:32:46 PM PDT 24
Peak memory 208116 kb
Host smart-0912542e-ae8e-4421-a535-b5c00ce08964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139209620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.4139209620
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.3482414953
Short name T646
Test name
Test status
Simulation time 287404026 ps
CPU time 3.44 seconds
Started Apr 30 12:32:37 PM PDT 24
Finished Apr 30 12:32:41 PM PDT 24
Peak memory 207972 kb
Host smart-b7dd0c61-5d72-4282-94f0-9fa7ea0c03c1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482414953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.3482414953
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.2416478163
Short name T199
Test name
Test status
Simulation time 325750356 ps
CPU time 10.75 seconds
Started Apr 30 12:32:37 PM PDT 24
Finished Apr 30 12:32:50 PM PDT 24
Peak memory 208476 kb
Host smart-1f7f70d6-0390-488f-ab3f-4a48429a65d6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416478163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.2416478163
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.1037253784
Short name T625
Test name
Test status
Simulation time 106806513 ps
CPU time 4.59 seconds
Started Apr 30 12:32:40 PM PDT 24
Finished Apr 30 12:32:46 PM PDT 24
Peak memory 206396 kb
Host smart-a11a6507-d1ce-484e-9e58-17ac2f8aa750
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037253784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.1037253784
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.1714974645
Short name T251
Test name
Test status
Simulation time 149973214 ps
CPU time 4.39 seconds
Started Apr 30 12:32:39 PM PDT 24
Finished Apr 30 12:32:45 PM PDT 24
Peak memory 208248 kb
Host smart-04d06aae-f195-4162-9dce-9a1bfa8da63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714974645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.1714974645
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.1878943176
Short name T873
Test name
Test status
Simulation time 2737563066 ps
CPU time 24.68 seconds
Started Apr 30 12:32:43 PM PDT 24
Finished Apr 30 12:33:08 PM PDT 24
Peak memory 207576 kb
Host smart-9632b3e3-6abb-42bb-a014-b9a682209430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878943176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.1878943176
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.257626527
Short name T860
Test name
Test status
Simulation time 468483952 ps
CPU time 16.36 seconds
Started Apr 30 12:32:44 PM PDT 24
Finished Apr 30 12:33:01 PM PDT 24
Peak memory 216692 kb
Host smart-35ce07c6-8d94-4244-b981-7a9a007ea5f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257626527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.257626527
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.2247599984
Short name T734
Test name
Test status
Simulation time 78841930 ps
CPU time 3.93 seconds
Started Apr 30 12:32:40 PM PDT 24
Finished Apr 30 12:32:45 PM PDT 24
Peak memory 206664 kb
Host smart-ac706693-a90b-4e4a-ac2d-260e3d660e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247599984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.2247599984
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.1823445732
Short name T852
Test name
Test status
Simulation time 51991870 ps
CPU time 2.72 seconds
Started Apr 30 12:32:40 PM PDT 24
Finished Apr 30 12:32:43 PM PDT 24
Peak memory 209680 kb
Host smart-049eeab3-a685-4936-87f7-2c43e8af24bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823445732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.1823445732
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.2440265388
Short name T475
Test name
Test status
Simulation time 26690233 ps
CPU time 0.88 seconds
Started Apr 30 12:32:39 PM PDT 24
Finished Apr 30 12:32:41 PM PDT 24
Peak memory 205596 kb
Host smart-85d9f885-f2b8-4392-bc99-79b53fc1473a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440265388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.2440265388
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.3367055946
Short name T301
Test name
Test status
Simulation time 186438435 ps
CPU time 3.48 seconds
Started Apr 30 12:32:37 PM PDT 24
Finished Apr 30 12:32:42 PM PDT 24
Peak memory 213956 kb
Host smart-b22c120a-7389-4544-8bf5-c35629a841d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3367055946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.3367055946
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.2307376602
Short name T881
Test name
Test status
Simulation time 297969869 ps
CPU time 3.57 seconds
Started Apr 30 12:32:42 PM PDT 24
Finished Apr 30 12:32:47 PM PDT 24
Peak memory 217868 kb
Host smart-8e0dcc38-6e8f-4015-9687-50a91b2cd529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307376602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.2307376602
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.69582620
Short name T769
Test name
Test status
Simulation time 391706682 ps
CPU time 5.95 seconds
Started Apr 30 12:32:38 PM PDT 24
Finished Apr 30 12:32:46 PM PDT 24
Peak memory 213980 kb
Host smart-0bdca195-a151-44df-9f4a-7f9b510ee8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69582620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.69582620
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.2472848016
Short name T258
Test name
Test status
Simulation time 367996139 ps
CPU time 10.27 seconds
Started Apr 30 12:32:45 PM PDT 24
Finished Apr 30 12:32:57 PM PDT 24
Peak memory 213888 kb
Host smart-0d902458-5566-48c4-a689-cac9a2a81c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472848016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.2472848016
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.1060063285
Short name T905
Test name
Test status
Simulation time 107162698 ps
CPU time 3.76 seconds
Started Apr 30 12:32:39 PM PDT 24
Finished Apr 30 12:32:44 PM PDT 24
Peak memory 213988 kb
Host smart-8450a65f-54b1-4af4-9075-62bdc60b14e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060063285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.1060063285
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.3613374813
Short name T73
Test name
Test status
Simulation time 134125903 ps
CPU time 3.71 seconds
Started Apr 30 12:32:38 PM PDT 24
Finished Apr 30 12:32:43 PM PDT 24
Peak memory 206592 kb
Host smart-cf4702dd-b541-4808-bf9d-b4dd77c321ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613374813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.3613374813
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.395932923
Short name T582
Test name
Test status
Simulation time 246855129 ps
CPU time 3.16 seconds
Started Apr 30 12:32:42 PM PDT 24
Finished Apr 30 12:32:46 PM PDT 24
Peak memory 208504 kb
Host smart-86a57e91-0eda-4d8e-b62f-4bcaec740f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395932923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.395932923
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.2601156006
Short name T355
Test name
Test status
Simulation time 303283976 ps
CPU time 7.81 seconds
Started Apr 30 12:32:37 PM PDT 24
Finished Apr 30 12:32:46 PM PDT 24
Peak memory 208168 kb
Host smart-24150d48-ae00-4b75-8071-f0927f3b5b8a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601156006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.2601156006
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.412160004
Short name T820
Test name
Test status
Simulation time 151583358 ps
CPU time 5.49 seconds
Started Apr 30 12:32:59 PM PDT 24
Finished Apr 30 12:33:05 PM PDT 24
Peak memory 207524 kb
Host smart-0e01f0c1-aa4a-42c2-871b-dad2b64cab1c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412160004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.412160004
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.2468029556
Short name T697
Test name
Test status
Simulation time 314839252 ps
CPU time 5.26 seconds
Started Apr 30 12:32:37 PM PDT 24
Finished Apr 30 12:32:43 PM PDT 24
Peak memory 208244 kb
Host smart-0fafbfd8-1e98-497c-bb41-375300aeeedc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468029556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.2468029556
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.1830833571
Short name T529
Test name
Test status
Simulation time 1756092395 ps
CPU time 15.98 seconds
Started Apr 30 12:32:41 PM PDT 24
Finished Apr 30 12:32:58 PM PDT 24
Peak memory 213904 kb
Host smart-258757c9-0b9f-41d7-a5c5-a5a164426148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830833571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.1830833571
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.2774440892
Short name T813
Test name
Test status
Simulation time 38471356 ps
CPU time 2.17 seconds
Started Apr 30 12:32:40 PM PDT 24
Finished Apr 30 12:32:43 PM PDT 24
Peak memory 206320 kb
Host smart-9fa8294e-a631-4114-8c90-37d864da7557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774440892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.2774440892
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.907056704
Short name T867
Test name
Test status
Simulation time 2723336794 ps
CPU time 90.58 seconds
Started Apr 30 12:32:40 PM PDT 24
Finished Apr 30 12:34:12 PM PDT 24
Peak memory 216232 kb
Host smart-cd21c70c-aeeb-4bc1-9c9e-9bdfdb9bafa1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907056704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.907056704
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.1326709190
Short name T784
Test name
Test status
Simulation time 83213768 ps
CPU time 3.99 seconds
Started Apr 30 12:32:43 PM PDT 24
Finished Apr 30 12:32:48 PM PDT 24
Peak memory 213980 kb
Host smart-8f351d3c-e04b-4323-979d-38d89db003f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326709190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.1326709190
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.1295328990
Short name T581
Test name
Test status
Simulation time 102573282 ps
CPU time 2.27 seconds
Started Apr 30 12:32:42 PM PDT 24
Finished Apr 30 12:32:45 PM PDT 24
Peak memory 209456 kb
Host smart-359282f4-b398-41e2-b081-583322ea4112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295328990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.1295328990
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.644436401
Short name T639
Test name
Test status
Simulation time 52095225 ps
CPU time 0.79 seconds
Started Apr 30 12:32:45 PM PDT 24
Finished Apr 30 12:32:47 PM PDT 24
Peak memory 205584 kb
Host smart-b9ba807e-4e88-4dc3-bc49-6d2029f7fe54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644436401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.644436401
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.3136900704
Short name T212
Test name
Test status
Simulation time 191963990 ps
CPU time 10.66 seconds
Started Apr 30 12:32:42 PM PDT 24
Finished Apr 30 12:32:53 PM PDT 24
Peak memory 214352 kb
Host smart-2660dab7-6706-4662-a9a2-67811abbe63e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3136900704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.3136900704
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.3427999585
Short name T67
Test name
Test status
Simulation time 785618790 ps
CPU time 6.29 seconds
Started Apr 30 12:32:43 PM PDT 24
Finished Apr 30 12:32:50 PM PDT 24
Peak memory 208604 kb
Host smart-28c05a22-18c1-4e8e-8c75-4727467528e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427999585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.3427999585
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.3127693595
Short name T794
Test name
Test status
Simulation time 908993793 ps
CPU time 7.87 seconds
Started Apr 30 12:32:39 PM PDT 24
Finished Apr 30 12:32:48 PM PDT 24
Peak memory 209112 kb
Host smart-7d3de524-ad3b-4d9d-b763-13fe2d07e598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127693595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.3127693595
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.52545926
Short name T293
Test name
Test status
Simulation time 201497750 ps
CPU time 5.13 seconds
Started Apr 30 12:32:44 PM PDT 24
Finished Apr 30 12:33:00 PM PDT 24
Peak memory 210676 kb
Host smart-26a570e2-a369-4dfc-9047-e386ad6ac3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52545926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.52545926
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.2553113578
Short name T770
Test name
Test status
Simulation time 1426311143 ps
CPU time 3.41 seconds
Started Apr 30 12:32:39 PM PDT 24
Finished Apr 30 12:32:43 PM PDT 24
Peak memory 222336 kb
Host smart-7f083625-ff57-46a4-b808-7841a6dff24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553113578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.2553113578
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.1475086027
Short name T478
Test name
Test status
Simulation time 89317300 ps
CPU time 2.69 seconds
Started Apr 30 12:33:05 PM PDT 24
Finished Apr 30 12:33:08 PM PDT 24
Peak memory 208604 kb
Host smart-5e277c40-afd6-437b-b123-de7a8e52b51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475086027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.1475086027
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.247661416
Short name T195
Test name
Test status
Simulation time 188184066 ps
CPU time 4.06 seconds
Started Apr 30 12:32:41 PM PDT 24
Finished Apr 30 12:32:46 PM PDT 24
Peak memory 207952 kb
Host smart-0bb4b953-a24f-41fe-a207-d6455e3d2e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247661416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.247661416
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.4257377082
Short name T368
Test name
Test status
Simulation time 184004416 ps
CPU time 5.86 seconds
Started Apr 30 12:32:44 PM PDT 24
Finished Apr 30 12:32:50 PM PDT 24
Peak memory 208160 kb
Host smart-0238c49a-9368-42c5-aaf9-36e9aeab6211
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257377082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.4257377082
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.3940776337
Short name T394
Test name
Test status
Simulation time 48399041 ps
CPU time 2.67 seconds
Started Apr 30 12:32:40 PM PDT 24
Finished Apr 30 12:32:44 PM PDT 24
Peak memory 208528 kb
Host smart-41e62d58-a904-4122-a044-31d02666dd18
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940776337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.3940776337
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.4020967449
Short name T818
Test name
Test status
Simulation time 231037777 ps
CPU time 3.22 seconds
Started Apr 30 12:32:53 PM PDT 24
Finished Apr 30 12:32:57 PM PDT 24
Peak memory 206240 kb
Host smart-47d9a421-e79f-4e8b-b540-549e9aec4b37
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020967449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.4020967449
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.2391508549
Short name T103
Test name
Test status
Simulation time 57173630 ps
CPU time 3.08 seconds
Started Apr 30 12:32:45 PM PDT 24
Finished Apr 30 12:32:49 PM PDT 24
Peak memory 214012 kb
Host smart-8e620beb-1579-4759-8fa5-bd0817fe4d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391508549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.2391508549
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.2759581381
Short name T19
Test name
Test status
Simulation time 70902646 ps
CPU time 2.36 seconds
Started Apr 30 12:32:41 PM PDT 24
Finished Apr 30 12:32:44 PM PDT 24
Peak memory 206232 kb
Host smart-f85331fd-7fd4-4994-bfec-4e0ee50330c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759581381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.2759581381
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.1716627538
Short name T680
Test name
Test status
Simulation time 939165189 ps
CPU time 16.71 seconds
Started Apr 30 12:32:46 PM PDT 24
Finished Apr 30 12:33:04 PM PDT 24
Peak memory 214772 kb
Host smart-dc663afd-f38d-4227-b3e7-56980129464a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716627538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.1716627538
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.1882455576
Short name T796
Test name
Test status
Simulation time 385860386 ps
CPU time 7.87 seconds
Started Apr 30 12:32:39 PM PDT 24
Finished Apr 30 12:32:48 PM PDT 24
Peak memory 209068 kb
Host smart-936f856e-e1c4-4272-98a1-025e5f994804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882455576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.1882455576
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.3958083058
Short name T689
Test name
Test status
Simulation time 329737172 ps
CPU time 2.11 seconds
Started Apr 30 12:32:58 PM PDT 24
Finished Apr 30 12:33:01 PM PDT 24
Peak memory 210044 kb
Host smart-312437a2-83ac-4d83-8b36-3e708c767f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958083058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.3958083058
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.947617537
Short name T703
Test name
Test status
Simulation time 12567868 ps
CPU time 0.74 seconds
Started Apr 30 12:30:44 PM PDT 24
Finished Apr 30 12:30:45 PM PDT 24
Peak memory 205572 kb
Host smart-a882358e-fc09-496c-87eb-718d08e31ac4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947617537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.947617537
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.1816684064
Short name T661
Test name
Test status
Simulation time 203370054 ps
CPU time 3.21 seconds
Started Apr 30 12:30:51 PM PDT 24
Finished Apr 30 12:30:57 PM PDT 24
Peak memory 213952 kb
Host smart-b31d9abd-cbcf-4a80-982e-1535522d61bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1816684064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.1816684064
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.2641372245
Short name T876
Test name
Test status
Simulation time 534381441 ps
CPU time 3.16 seconds
Started Apr 30 12:30:46 PM PDT 24
Finished Apr 30 12:30:51 PM PDT 24
Peak memory 214000 kb
Host smart-20d409f1-3da0-44dc-8352-815bd9a69e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641372245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.2641372245
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.3228548022
Short name T87
Test name
Test status
Simulation time 212629456 ps
CPU time 4.99 seconds
Started Apr 30 12:30:46 PM PDT 24
Finished Apr 30 12:30:53 PM PDT 24
Peak memory 219640 kb
Host smart-3b9b3ef4-99a5-404f-a57e-0a5032718e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228548022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.3228548022
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.304705642
Short name T47
Test name
Test status
Simulation time 271611847 ps
CPU time 10.39 seconds
Started Apr 30 12:30:53 PM PDT 24
Finished Apr 30 12:31:05 PM PDT 24
Peak memory 213968 kb
Host smart-967b444a-cba5-4469-8e11-e98dbbcfcc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304705642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.304705642
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.935874470
Short name T390
Test name
Test status
Simulation time 116917896 ps
CPU time 5.11 seconds
Started Apr 30 12:30:50 PM PDT 24
Finished Apr 30 12:30:57 PM PDT 24
Peak memory 209512 kb
Host smart-7079f155-de1f-4328-856b-603c02a8eebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935874470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.935874470
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.3635737425
Short name T700
Test name
Test status
Simulation time 46335745 ps
CPU time 3.14 seconds
Started Apr 30 12:30:50 PM PDT 24
Finished Apr 30 12:30:55 PM PDT 24
Peak memory 207632 kb
Host smart-5f7241e8-c5cb-4686-b5f7-b8f12f6179d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635737425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.3635737425
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.3218530951
Short name T561
Test name
Test status
Simulation time 37687486 ps
CPU time 1.94 seconds
Started Apr 30 12:30:50 PM PDT 24
Finished Apr 30 12:30:54 PM PDT 24
Peak memory 208244 kb
Host smart-a9b7f61c-66ae-49bc-be87-0ce1a62c33f5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218530951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.3218530951
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.1449039629
Short name T628
Test name
Test status
Simulation time 31799609 ps
CPU time 2.32 seconds
Started Apr 30 12:30:48 PM PDT 24
Finished Apr 30 12:30:51 PM PDT 24
Peak memory 206488 kb
Host smart-50e0116d-4b20-4c32-b426-d68487fdbccf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449039629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.1449039629
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.3453299331
Short name T290
Test name
Test status
Simulation time 277010005 ps
CPU time 5.59 seconds
Started Apr 30 12:30:54 PM PDT 24
Finished Apr 30 12:31:01 PM PDT 24
Peak memory 208180 kb
Host smart-aa91fdf7-cad8-4e1e-bdc0-253c29114024
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453299331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.3453299331
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.1798938343
Short name T594
Test name
Test status
Simulation time 77164553 ps
CPU time 2.94 seconds
Started Apr 30 12:30:46 PM PDT 24
Finished Apr 30 12:30:51 PM PDT 24
Peak memory 208324 kb
Host smart-9eb1b928-1869-4d7d-9882-f15c1a12f1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798938343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.1798938343
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.1915682832
Short name T467
Test name
Test status
Simulation time 231890373 ps
CPU time 5.43 seconds
Started Apr 30 12:30:48 PM PDT 24
Finished Apr 30 12:30:55 PM PDT 24
Peak memory 207388 kb
Host smart-5b92b26f-5281-4295-b2f1-3713723f09f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915682832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.1915682832
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.2253168064
Short name T6
Test name
Test status
Simulation time 753658366 ps
CPU time 9.18 seconds
Started Apr 30 12:30:51 PM PDT 24
Finished Apr 30 12:31:02 PM PDT 24
Peak memory 215868 kb
Host smart-1d159bac-1dda-489a-9bfd-a454c4aa94f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253168064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.2253168064
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.1324660441
Short name T129
Test name
Test status
Simulation time 329690029 ps
CPU time 12.94 seconds
Started Apr 30 12:30:48 PM PDT 24
Finished Apr 30 12:31:02 PM PDT 24
Peak memory 222304 kb
Host smart-9e5579fe-9d3b-4c29-848d-597c346867be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324660441 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.1324660441
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.1437377787
Short name T358
Test name
Test status
Simulation time 1145951089 ps
CPU time 16.82 seconds
Started Apr 30 12:30:49 PM PDT 24
Finished Apr 30 12:31:07 PM PDT 24
Peak memory 207896 kb
Host smart-b88ab375-f8f1-4689-9ea4-440b40f06db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437377787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.1437377787
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.3135971109
Short name T445
Test name
Test status
Simulation time 84342626 ps
CPU time 3.49 seconds
Started Apr 30 12:30:52 PM PDT 24
Finished Apr 30 12:30:57 PM PDT 24
Peak memory 209840 kb
Host smart-23b86484-9e9b-4899-b6d5-59b38969c0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135971109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.3135971109
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.2593167414
Short name T605
Test name
Test status
Simulation time 12845566 ps
CPU time 0.81 seconds
Started Apr 30 12:30:50 PM PDT 24
Finished Apr 30 12:30:52 PM PDT 24
Peak memory 205584 kb
Host smart-79cdd528-8238-49c6-9853-19f64cbc82d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593167414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.2593167414
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.2168416867
Short name T253
Test name
Test status
Simulation time 1421009057 ps
CPU time 6.86 seconds
Started Apr 30 12:30:51 PM PDT 24
Finished Apr 30 12:31:00 PM PDT 24
Peak memory 222156 kb
Host smart-5f6ccc4f-7b8e-4211-9b02-f4bbd656af67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2168416867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.2168416867
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.3519611190
Short name T650
Test name
Test status
Simulation time 334810973 ps
CPU time 3.06 seconds
Started Apr 30 12:30:50 PM PDT 24
Finished Apr 30 12:30:55 PM PDT 24
Peak memory 218052 kb
Host smart-8a80f1ba-02e4-44f3-9f6a-7c1152a57099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519611190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.3519611190
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.1698258219
Short name T883
Test name
Test status
Simulation time 1280870953 ps
CPU time 8.24 seconds
Started Apr 30 12:30:53 PM PDT 24
Finished Apr 30 12:31:03 PM PDT 24
Peak memory 213880 kb
Host smart-15723cb2-a076-45f4-b00e-86332fe8df3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698258219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.1698258219
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_random.2462103151
Short name T252
Test name
Test status
Simulation time 109012282 ps
CPU time 3.21 seconds
Started Apr 30 12:30:50 PM PDT 24
Finished Apr 30 12:30:54 PM PDT 24
Peak memory 207424 kb
Host smart-e3a851ca-c37a-4877-8ef6-bcea7341c403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462103151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.2462103151
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.1180267953
Short name T453
Test name
Test status
Simulation time 1357744630 ps
CPU time 14.46 seconds
Started Apr 30 12:30:46 PM PDT 24
Finished Apr 30 12:31:02 PM PDT 24
Peak memory 206272 kb
Host smart-7537de46-6642-48eb-bc00-a31d7029ae4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180267953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.1180267953
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.1998226897
Short name T444
Test name
Test status
Simulation time 52216309 ps
CPU time 3.05 seconds
Started Apr 30 12:30:51 PM PDT 24
Finished Apr 30 12:30:56 PM PDT 24
Peak memory 206504 kb
Host smart-0a8e73f1-e27f-4056-bed6-30ce29d1002b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998226897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.1998226897
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.1799259337
Short name T525
Test name
Test status
Simulation time 234054543 ps
CPU time 6.74 seconds
Started Apr 30 12:30:46 PM PDT 24
Finished Apr 30 12:30:54 PM PDT 24
Peak memory 208316 kb
Host smart-419bd95d-2986-454a-92b6-45f2cf16c845
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799259337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.1799259337
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.3759739481
Short name T218
Test name
Test status
Simulation time 200034836 ps
CPU time 2.63 seconds
Started Apr 30 12:30:54 PM PDT 24
Finished Apr 30 12:30:58 PM PDT 24
Peak memory 206480 kb
Host smart-630c1ab1-e1e2-4113-a564-c6f1f30821f8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759739481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.3759739481
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.255410442
Short name T521
Test name
Test status
Simulation time 58288920 ps
CPU time 2.69 seconds
Started Apr 30 12:30:51 PM PDT 24
Finished Apr 30 12:30:56 PM PDT 24
Peak memory 208416 kb
Host smart-1861228f-c435-46ac-8e87-1d8ee268513a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255410442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.255410442
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.679506584
Short name T421
Test name
Test status
Simulation time 65378133 ps
CPU time 1.83 seconds
Started Apr 30 12:30:48 PM PDT 24
Finished Apr 30 12:30:51 PM PDT 24
Peak memory 207412 kb
Host smart-a36a2295-d045-44d8-bae7-4fa53ec1d35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679506584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.679506584
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.477826455
Short name T62
Test name
Test status
Simulation time 405009964 ps
CPU time 11.86 seconds
Started Apr 30 12:30:51 PM PDT 24
Finished Apr 30 12:31:05 PM PDT 24
Peak memory 221984 kb
Host smart-a943fbcb-212b-4526-b459-d5fe322f3219
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477826455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.477826455
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.126750621
Short name T694
Test name
Test status
Simulation time 62638289 ps
CPU time 2.26 seconds
Started Apr 30 12:30:51 PM PDT 24
Finished Apr 30 12:30:55 PM PDT 24
Peak memory 207468 kb
Host smart-14d51ea3-cd6b-451d-847f-1275407a5ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126750621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.126750621
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.2823239518
Short name T135
Test name
Test status
Simulation time 60904856 ps
CPU time 2 seconds
Started Apr 30 12:30:52 PM PDT 24
Finished Apr 30 12:30:56 PM PDT 24
Peak memory 209468 kb
Host smart-7a833230-54ee-4aa2-b39e-6a53de34a2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823239518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.2823239518
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.2342355962
Short name T553
Test name
Test status
Simulation time 10855310 ps
CPU time 0.75 seconds
Started Apr 30 12:30:51 PM PDT 24
Finished Apr 30 12:30:54 PM PDT 24
Peak memory 205500 kb
Host smart-1173f543-4f78-4ac3-8079-bbcb99dce289
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342355962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.2342355962
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.3781221280
Short name T568
Test name
Test status
Simulation time 68463197 ps
CPU time 2.63 seconds
Started Apr 30 12:30:51 PM PDT 24
Finished Apr 30 12:30:56 PM PDT 24
Peak memory 206944 kb
Host smart-23b640c9-b489-4040-a1ef-2f79e6a9f1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781221280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.3781221280
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.807906917
Short name T782
Test name
Test status
Simulation time 423893990 ps
CPU time 6.33 seconds
Started Apr 30 12:30:49 PM PDT 24
Finished Apr 30 12:30:56 PM PDT 24
Peak memory 209420 kb
Host smart-127b72d6-1424-46d6-881c-c153841015f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807906917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.807906917
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.441761279
Short name T458
Test name
Test status
Simulation time 116203739 ps
CPU time 2.99 seconds
Started Apr 30 12:30:52 PM PDT 24
Finished Apr 30 12:30:57 PM PDT 24
Peak memory 214396 kb
Host smart-bc97647c-cd35-481f-9967-7b89faf0afa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441761279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.441761279
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.3752207095
Short name T875
Test name
Test status
Simulation time 218620356 ps
CPU time 3.94 seconds
Started Apr 30 12:30:57 PM PDT 24
Finished Apr 30 12:31:02 PM PDT 24
Peak memory 208728 kb
Host smart-3ce74c3c-0261-4160-a61e-bc6f36483a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752207095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.3752207095
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.3747893376
Short name T134
Test name
Test status
Simulation time 1344636627 ps
CPU time 23.32 seconds
Started Apr 30 12:30:51 PM PDT 24
Finished Apr 30 12:31:17 PM PDT 24
Peak memory 206576 kb
Host smart-7c12b0d6-511c-41c7-8c9d-840a94486517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747893376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.3747893376
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.4021664110
Short name T369
Test name
Test status
Simulation time 33795265 ps
CPU time 2.63 seconds
Started Apr 30 12:30:50 PM PDT 24
Finished Apr 30 12:30:54 PM PDT 24
Peak memory 208316 kb
Host smart-586cabc6-59a1-4735-906b-8ae8d4b2c6ac
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021664110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.4021664110
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.3051053044
Short name T772
Test name
Test status
Simulation time 465182638 ps
CPU time 8.94 seconds
Started Apr 30 12:30:51 PM PDT 24
Finished Apr 30 12:31:02 PM PDT 24
Peak memory 208204 kb
Host smart-33ec1b52-3333-4284-8cbc-5db417c3947d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051053044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.3051053044
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.1875224919
Short name T891
Test name
Test status
Simulation time 1390614059 ps
CPU time 18.34 seconds
Started Apr 30 12:30:50 PM PDT 24
Finished Apr 30 12:31:10 PM PDT 24
Peak memory 207248 kb
Host smart-6e50252c-cb64-469e-9c02-45bdb67fd722
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875224919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.1875224919
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.991838672
Short name T322
Test name
Test status
Simulation time 606061479 ps
CPU time 8.31 seconds
Started Apr 30 12:30:52 PM PDT 24
Finished Apr 30 12:31:03 PM PDT 24
Peak memory 209008 kb
Host smart-f2a77960-3e40-4e6e-b0bf-9e27386aeff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991838672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.991838672
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.3819308190
Short name T609
Test name
Test status
Simulation time 110167005 ps
CPU time 4.62 seconds
Started Apr 30 12:30:45 PM PDT 24
Finished Apr 30 12:30:51 PM PDT 24
Peak memory 208436 kb
Host smart-98358146-3b90-42ff-94b4-41af124b3b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819308190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.3819308190
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.4183737892
Short name T264
Test name
Test status
Simulation time 1717820393 ps
CPU time 35.98 seconds
Started Apr 30 12:30:52 PM PDT 24
Finished Apr 30 12:31:30 PM PDT 24
Peak memory 214568 kb
Host smart-52f1a2f5-00c8-4461-aae6-358e75ce5ac1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183737892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.4183737892
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.1075660718
Short name T254
Test name
Test status
Simulation time 526000968 ps
CPU time 4.76 seconds
Started Apr 30 12:30:54 PM PDT 24
Finished Apr 30 12:31:00 PM PDT 24
Peak memory 209536 kb
Host smart-c0cd2999-2472-43af-9d55-f26976511ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075660718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.1075660718
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.1186286610
Short name T682
Test name
Test status
Simulation time 61163574 ps
CPU time 2.75 seconds
Started Apr 30 12:30:53 PM PDT 24
Finished Apr 30 12:30:57 PM PDT 24
Peak memory 209576 kb
Host smart-7c4cd860-d804-4f58-95df-5cecb0ce8c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186286610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.1186286610
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.570097934
Short name T887
Test name
Test status
Simulation time 10487822 ps
CPU time 0.77 seconds
Started Apr 30 12:30:49 PM PDT 24
Finished Apr 30 12:30:51 PM PDT 24
Peak memory 205576 kb
Host smart-b741b83b-9554-46f0-bd37-9ebc81db30da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570097934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.570097934
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.2192948105
Short name T327
Test name
Test status
Simulation time 463221030 ps
CPU time 7.65 seconds
Started Apr 30 12:30:51 PM PDT 24
Finished Apr 30 12:31:00 PM PDT 24
Peak memory 222180 kb
Host smart-4f182443-4a41-4559-86a7-00a5abdac4c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2192948105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.2192948105
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.2404873562
Short name T836
Test name
Test status
Simulation time 107197297 ps
CPU time 3.23 seconds
Started Apr 30 12:30:49 PM PDT 24
Finished Apr 30 12:30:53 PM PDT 24
Peak memory 216180 kb
Host smart-497d06ee-9911-4d16-a619-fd7315080c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404873562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.2404873562
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.3291844255
Short name T66
Test name
Test status
Simulation time 167600151 ps
CPU time 3.61 seconds
Started Apr 30 12:30:57 PM PDT 24
Finished Apr 30 12:31:02 PM PDT 24
Peak memory 209336 kb
Host smart-532fb056-3027-4a86-80f8-c9cb96a13c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291844255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.3291844255
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.2496960386
Short name T92
Test name
Test status
Simulation time 117848733 ps
CPU time 2.95 seconds
Started Apr 30 12:30:50 PM PDT 24
Finished Apr 30 12:30:54 PM PDT 24
Peak memory 213980 kb
Host smart-9034b762-09ac-46f0-99d4-4f50c2e3c1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496960386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.2496960386
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.3714137604
Short name T274
Test name
Test status
Simulation time 84546762 ps
CPU time 4.21 seconds
Started Apr 30 12:30:51 PM PDT 24
Finished Apr 30 12:30:57 PM PDT 24
Peak memory 210456 kb
Host smart-508f39a9-7c62-42ff-8287-45c1013ededc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714137604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.3714137604
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.1099124003
Short name T243
Test name
Test status
Simulation time 49130280 ps
CPU time 3.1 seconds
Started Apr 30 12:30:48 PM PDT 24
Finished Apr 30 12:30:53 PM PDT 24
Peak memory 209064 kb
Host smart-3cf60e89-9b8a-43bd-8bed-9f99a2abd51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099124003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.1099124003
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.3870032653
Short name T556
Test name
Test status
Simulation time 143197957 ps
CPU time 3.48 seconds
Started Apr 30 12:30:51 PM PDT 24
Finished Apr 30 12:30:56 PM PDT 24
Peak memory 209632 kb
Host smart-38e80531-35ae-407d-9db7-9b1ac621ce00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870032653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.3870032653
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.121191012
Short name T705
Test name
Test status
Simulation time 888271949 ps
CPU time 6.52 seconds
Started Apr 30 12:30:44 PM PDT 24
Finished Apr 30 12:30:51 PM PDT 24
Peak memory 208220 kb
Host smart-21fcefa1-c5e4-4cf2-8b5e-d4e7e45285a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121191012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.121191012
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.3946382362
Short name T348
Test name
Test status
Simulation time 46020253 ps
CPU time 2.57 seconds
Started Apr 30 12:30:47 PM PDT 24
Finished Apr 30 12:30:51 PM PDT 24
Peak memory 206332 kb
Host smart-36ce663e-fbc2-4612-91f8-271857941dc7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946382362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.3946382362
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.2789633198
Short name T454
Test name
Test status
Simulation time 730955811 ps
CPU time 6.59 seconds
Started Apr 30 12:30:48 PM PDT 24
Finished Apr 30 12:30:56 PM PDT 24
Peak memory 207628 kb
Host smart-6a91274b-b51b-43ea-9535-774764c190c7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789633198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.2789633198
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.1933982386
Short name T547
Test name
Test status
Simulation time 427359882 ps
CPU time 6.11 seconds
Started Apr 30 12:30:51 PM PDT 24
Finished Apr 30 12:30:59 PM PDT 24
Peak memory 208248 kb
Host smart-2801d672-ecac-4158-993c-150a68dc5ffb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933982386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.1933982386
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.2919189091
Short name T558
Test name
Test status
Simulation time 26051204 ps
CPU time 1.48 seconds
Started Apr 30 12:30:51 PM PDT 24
Finished Apr 30 12:30:55 PM PDT 24
Peak memory 208744 kb
Host smart-23e1d1de-d65f-4c83-bc9d-8ed1b63b7cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919189091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.2919189091
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.1063481255
Short name T15
Test name
Test status
Simulation time 69742520 ps
CPU time 2.27 seconds
Started Apr 30 12:30:53 PM PDT 24
Finished Apr 30 12:30:57 PM PDT 24
Peak memory 206460 kb
Host smart-11805620-cd88-4900-bd11-d224ac3668c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063481255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.1063481255
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.3046954222
Short name T747
Test name
Test status
Simulation time 151345294 ps
CPU time 6.4 seconds
Started Apr 30 12:30:51 PM PDT 24
Finished Apr 30 12:30:59 PM PDT 24
Peak memory 209156 kb
Host smart-6bde9549-8278-419e-9678-5aefaa5b90bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046954222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.3046954222
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.2426596563
Short name T203
Test name
Test status
Simulation time 113444133 ps
CPU time 1.79 seconds
Started Apr 30 12:30:50 PM PDT 24
Finished Apr 30 12:30:54 PM PDT 24
Peak memory 209416 kb
Host smart-5ddac63a-b696-4708-92d6-b651b46bd05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426596563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.2426596563
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.3988934157
Short name T97
Test name
Test status
Simulation time 43363503 ps
CPU time 0.86 seconds
Started Apr 30 12:30:49 PM PDT 24
Finished Apr 30 12:30:51 PM PDT 24
Peak memory 205568 kb
Host smart-f5d9e2b9-2788-4a15-b098-8b5b86985add
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988934157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.3988934157
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.3079562525
Short name T410
Test name
Test status
Simulation time 52540758 ps
CPU time 3.64 seconds
Started Apr 30 12:30:53 PM PDT 24
Finished Apr 30 12:30:58 PM PDT 24
Peak memory 214872 kb
Host smart-93e59579-5583-4f1c-8463-a48394e6bbf7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3079562525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.3079562525
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.2994926382
Short name T616
Test name
Test status
Simulation time 56791374 ps
CPU time 3.28 seconds
Started Apr 30 12:30:54 PM PDT 24
Finished Apr 30 12:30:59 PM PDT 24
Peak memory 209792 kb
Host smart-d92fed16-3e0e-4789-8576-2911d70b9f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994926382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.2994926382
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.1899895935
Short name T652
Test name
Test status
Simulation time 237754749 ps
CPU time 4.77 seconds
Started Apr 30 12:30:51 PM PDT 24
Finished Apr 30 12:30:58 PM PDT 24
Peak memory 209144 kb
Host smart-43f39cb4-4587-43c9-a82c-cb973766e4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899895935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.1899895935
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.1292999294
Short name T277
Test name
Test status
Simulation time 1503803315 ps
CPU time 4.97 seconds
Started Apr 30 12:30:52 PM PDT 24
Finished Apr 30 12:30:59 PM PDT 24
Peak memory 222248 kb
Host smart-0c38b8de-02dd-4dac-83fe-6f288155f766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292999294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.1292999294
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.1088879036
Short name T275
Test name
Test status
Simulation time 130445053 ps
CPU time 5.49 seconds
Started Apr 30 12:30:45 PM PDT 24
Finished Apr 30 12:30:51 PM PDT 24
Peak memory 211616 kb
Host smart-90e0ec2d-f931-4147-9148-72d315f657a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088879036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.1088879036
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.3613690519
Short name T781
Test name
Test status
Simulation time 307314861 ps
CPU time 3.75 seconds
Started Apr 30 12:30:52 PM PDT 24
Finished Apr 30 12:30:58 PM PDT 24
Peak memory 220008 kb
Host smart-eed7d077-cba4-44e6-9adf-35fde81bc53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613690519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.3613690519
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.2860477607
Short name T894
Test name
Test status
Simulation time 279035926 ps
CPU time 7.79 seconds
Started Apr 30 12:30:51 PM PDT 24
Finished Apr 30 12:31:01 PM PDT 24
Peak memory 218152 kb
Host smart-3715df0a-cadb-4ce2-99d5-f564b620d07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860477607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.2860477607
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.2654901826
Short name T886
Test name
Test status
Simulation time 35020144 ps
CPU time 2.3 seconds
Started Apr 30 12:30:49 PM PDT 24
Finished Apr 30 12:30:53 PM PDT 24
Peak memory 206268 kb
Host smart-b9b44db3-368c-45af-b524-7b09f64bea62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654901826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.2654901826
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.2510160714
Short name T493
Test name
Test status
Simulation time 76576782 ps
CPU time 3.24 seconds
Started Apr 30 12:30:49 PM PDT 24
Finished Apr 30 12:30:53 PM PDT 24
Peak memory 208268 kb
Host smart-39e5f1ba-ae55-4fd8-8bed-8b925c8ea1a2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510160714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.2510160714
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.926030097
Short name T222
Test name
Test status
Simulation time 109863669 ps
CPU time 3.05 seconds
Started Apr 30 12:30:51 PM PDT 24
Finished Apr 30 12:30:56 PM PDT 24
Peak memory 206492 kb
Host smart-df509bd1-93d0-48eb-a2be-733f5badff2a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926030097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.926030097
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.33164653
Short name T647
Test name
Test status
Simulation time 445684528 ps
CPU time 4.1 seconds
Started Apr 30 12:30:47 PM PDT 24
Finished Apr 30 12:30:52 PM PDT 24
Peak memory 206252 kb
Host smart-410c2100-3dbe-451f-9234-fefe0274c2a5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33164653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.33164653
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.3761091058
Short name T336
Test name
Test status
Simulation time 3312379794 ps
CPU time 36.64 seconds
Started Apr 30 12:30:50 PM PDT 24
Finished Apr 30 12:31:29 PM PDT 24
Peak memory 209364 kb
Host smart-547b5bf0-e824-4c40-8aef-18dee9f57643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761091058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.3761091058
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.3112909745
Short name T517
Test name
Test status
Simulation time 117784057 ps
CPU time 3.58 seconds
Started Apr 30 12:30:52 PM PDT 24
Finished Apr 30 12:30:57 PM PDT 24
Peak memory 207840 kb
Host smart-b85fe7d9-8b8c-4403-a7e2-575d47544f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112909745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.3112909745
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.1305501644
Short name T63
Test name
Test status
Simulation time 11558523750 ps
CPU time 42.67 seconds
Started Apr 30 12:30:54 PM PDT 24
Finished Apr 30 12:31:38 PM PDT 24
Peak memory 215656 kb
Host smart-d5af2c1e-fc6c-4ac9-98d0-141f73897da8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305501644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.1305501644
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.4029825453
Short name T126
Test name
Test status
Simulation time 251490316 ps
CPU time 13.9 seconds
Started Apr 30 12:30:52 PM PDT 24
Finished Apr 30 12:31:08 PM PDT 24
Peak memory 220508 kb
Host smart-58d07e0d-0fb0-4e2a-9dc2-447ce738386a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029825453 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.4029825453
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.1182285402
Short name T771
Test name
Test status
Simulation time 1991394534 ps
CPU time 43.07 seconds
Started Apr 30 12:30:50 PM PDT 24
Finished Apr 30 12:31:35 PM PDT 24
Peak memory 209352 kb
Host smart-a95b644d-9423-45cd-b277-114aa56ece41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182285402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.1182285402
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.1149167986
Short name T424
Test name
Test status
Simulation time 145580088 ps
CPU time 1.95 seconds
Started Apr 30 12:30:58 PM PDT 24
Finished Apr 30 12:31:00 PM PDT 24
Peak memory 209372 kb
Host smart-f3b8dcb5-2d61-4090-8c7c-8af2774865c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149167986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.1149167986
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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