Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
56890 |
1 |
|
|
T1 |
28 |
|
T2 |
69 |
|
T3 |
51 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
32741 |
1 |
|
|
T3 |
18 |
|
T4 |
51 |
|
T15 |
61 |
auto[1] |
24149 |
1 |
|
|
T1 |
28 |
|
T2 |
69 |
|
T3 |
33 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
28284 |
1 |
|
|
T2 |
35 |
|
T3 |
26 |
|
T4 |
26 |
auto[1] |
28606 |
1 |
|
|
T1 |
28 |
|
T2 |
34 |
|
T3 |
25 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for intr_cg_cc
Bins
cp_intr | cp_intr_en | cp_intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
16215 |
1 |
|
|
T3 |
9 |
|
T4 |
26 |
|
T15 |
31 |
all_values[0] |
auto[0] |
auto[1] |
16526 |
1 |
|
|
T3 |
9 |
|
T4 |
25 |
|
T15 |
30 |
all_values[0] |
auto[1] |
auto[0] |
12069 |
1 |
|
|
T2 |
35 |
|
T3 |
17 |
|
T14 |
17 |
all_values[0] |
auto[1] |
auto[1] |
12080 |
1 |
|
|
T1 |
28 |
|
T2 |
34 |
|
T3 |
16 |