Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
76.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	14	35	71.43

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	13	22	62.86	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	50	1			T17	1		T45	1		T46	1
auto[OpGenId]	10	1			T40	1		T53	1		T31	1
auto[OpGenSwOut]	21	1			T52	1		T56	1		T45	1
auto[OpGenHwOut]	17	1			T55	1		T5	1		T6	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1559	1			T19	6		T83	1		T53	2
auto[StInit]	87	1			T19	1		T37	1		T52	1
auto[StCreatorRootKey]	61	1			T39	1		T56	1		T40	1
auto[StOwnerIntKey]	35	1			T19	1		T38	1		T71	1
auto[StOwnerKey]	29	1			T19	1		T20	1		T71	1
auto[StDisabled]	455	1			T1	1		T17	1		T19	1
auto[StInvalid]	42	1			T30	1		T25	1		T27	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3249

1

T1

2

T2

1

T3

1

auto[1]

98

1

T17

1

T52

1

T56

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1549	1			T19	6		T83	1		T53	2
auto[StReset]	auto[1]	10	1			T49	1		T50	1		T34	1
auto[StInit]	auto[0]	45	1			T19	1		T37	1		T71	1
auto[StInit]	auto[1]	42	1			T52	1		T53	1		T55	1
auto[StCreatorRootKey]	auto[0]	42	1			T39	1		T63	1		T207	1
auto[StCreatorRootKey]	auto[1]	19	1			T56	1		T40	1		T46	1
auto[StOwnerIntKey]	auto[0]	25	1			T19	1		T38	1		T71	1
auto[StOwnerIntKey]	auto[1]	10	1			T63	1		T64	1		T6	1
auto[StOwnerKey]	auto[0]	21	1			T19	1		T20	1		T71	1
auto[StOwnerKey]	auto[1]	8	1			T45	1		T67	1		T68	1
auto[StDisabled]	auto[0]	446	1			T1	1		T19	1		T53	5
auto[StDisabled]	auto[1]	9	1			T17	1		T45	1		T7	1
auto[StInvalid]	auto[0]	42	1			T30	1		T25	1		T27	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	13	22	62.86	13

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset] , auto[StInit] , auto[StCreatorRootKey]]	[auto[OpDisable]]	--	--	3
[auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpGenId]]	--	--	2
[auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	2
[auto[StDisabled]]	[auto[OpDisable]]	0	1	1

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	7	1			T49	1		T50	1		T34	1
auto[StReset]	auto[OpGenId]	1	1			T24	1		-	-		-	-
auto[StReset]	auto[OpGenSwOut]	1	1			T8	1		-	-		-	-
auto[StReset]	auto[OpGenHwOut]	1	1			T43	1		-	-		-	-
auto[StInit]	auto[OpAdvance]	18	1			T144	1		T67	1		T208	1
auto[StInit]	auto[OpGenId]	5	1			T53	1		T31	1		T209	1
auto[StInit]	auto[OpGenSwOut]	12	1			T52	1		T65	1		T210	1
auto[StInit]	auto[OpGenHwOut]	7	1			T55	1		T5	1		T211	1
auto[StCreatorRootKey]	auto[OpAdvance]	12	1			T46	1		T212	1		T213	1
auto[StCreatorRootKey]	auto[OpGenId]	2	1			T40	1		T130	1		-	-
auto[StCreatorRootKey]	auto[OpGenSwOut]	3	1			T56	1		T58	1		T214	1
auto[StCreatorRootKey]	auto[OpGenHwOut]	2	1			T9	1		T215	1		-	-
auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T63	1		T216	1		T217	1
auto[StOwnerIntKey]	auto[OpGenSwOut]	2	1			T64	1		T218	1		-	-
auto[StOwnerIntKey]	auto[OpGenHwOut]	3	1			T6	1		T219	1		T220	1
auto[StOwnerKey]	auto[OpAdvance]	5	1			T45	1		T67	1		T221	1
auto[StOwnerKey]	auto[OpGenSwOut]	1	1			T68	1		-	-		-	-
auto[StOwnerKey]	auto[OpGenHwOut]	2	1			T222	1		T223	1		-	-
auto[StDisabled]	auto[OpAdvance]	3	1			T17	1		T224	1		T225	1
auto[StDisabled]	auto[OpGenId]	2	1			T226	1		T227	1		-	-
auto[StDisabled]	auto[OpGenSwOut]	2	1			T45	1		T228	1		-	-
auto[StDisabled]	auto[OpGenHwOut]	2	1			T7	1		T227	1		-	-