Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.58	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	74	256	77.58

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	55	225	80.36	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4758

1

T2

4

T3

10

T4

4

auto[1]

571

1

T1

3

T3

3

T4

2

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4758

1

T2

4

T3

10

T4

4

auto[1]

571

1

T1

3

T3

3

T4

2

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4765

1

T2

4

T3

13

T4

4

auto[1]

564

1

T1

3

T4

2

T15

1

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4765

1

T2

4

T3

13

T4

4

auto[1]

564

1

T1

3

T4

2

T15

1

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	404	1			T4	2		T17	1		T19	1
auto[OpGenId]	1130	1			T2	2		T4	2		T15	3
auto[OpGenSwOut]	1128	1			T2	2		T15	2		T16	2
auto[OpGenHwOut]	2589	1			T1	3		T3	13		T4	2
auto[OpDisable]	78	1			T16	1		T47	1		T48	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	404	1			T4	2		T17	1		T19	1
auto[OpGenId]	1130	1			T2	2		T4	2		T15	3
auto[OpGenSwOut]	1128	1			T2	2		T15	2		T16	2
auto[OpGenHwOut]	2589	1			T1	3		T3	13		T4	2
auto[OpDisable]	78	1			T16	1		T47	1		T48	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4783

1

T2

2

T3

13

T4

6

auto[1]

546

1

T1

3

T2

2

T17

2

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4783

1

T2

2

T3

13

T4

6

auto[1]

546

1

T1

3

T2

2

T17

2

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5088

1

T1

3

T2

4

T3

13

auto[1]

241

1

T4

2

T110

9

T139

7

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1826	1			T1	3		T2	1		T3	3
auto[1]	680	1			T3	2		T15	1		T16	2
auto[2]	729	1			T2	3		T15	3		T16	1
auto[3]	684	1			T3	5		T4	3		T15	1
auto[4]	344	1			T3	1		T4	1		T17	1
auto[5]	380	1			T3	1		T15	1		T110	9
auto[6]	334	1			T16	1		T85	4		T110	1
auto[7]	352	1			T3	1		T4	1		T18	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1410	1			T3	3		T4	2		T15	1
clear_one[1]	680	1			T3	2		T15	1		T16	2
clear_one[2]	729	1			T2	3		T15	3		T16	1
clear_one[3]	684	1			T3	5		T4	3		T15	1
clear_none	1826	1			T1	3		T2	1		T3	3

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1027	1			T3	5		T4	2		T15	1
auto[StInit]	760	1			T2	1		T3	1		T4	2
auto[StCreatorRootKey]	582	1			T3	1		T15	1		T16	1
auto[StOwnerIntKey]	520	1			T1	1		T2	1		T3	1
auto[StOwnerKey]	481	1			T3	1		T15	1		T18	1
auto[StDisabled]	1814	1			T1	2		T2	2		T3	4
auto[StInvalid]	145	1			T30	3		T25	2		T27	5

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1027	1			T3	5		T4	2		T15	1
auto[StInit]	760	1			T2	1		T3	1		T4	2
auto[StCreatorRootKey]	582	1			T3	1		T15	1		T16	1
auto[StOwnerIntKey]	520	1			T1	1		T2	1		T3	1
auto[StOwnerKey]	481	1			T3	1		T15	1		T18	1
auto[StDisabled]	1814	1			T1	2		T2	2		T3	4
auto[StInvalid]	145	1			T30	3		T25	2		T27	5

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	55	225	80.36	55

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[2]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	15
[auto[0] - auto[2]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	3
[auto[3] - auto[4]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	2
[auto[3] - auto[4]]	[auto[StReset]]	[auto[OpDisable]]	--	--	2
[auto[3] - auto[4]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	8
[auto[3] - auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2
[auto[5]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[5]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[5]]	[auto[StInvalid]]	[auto[OpAdvance]]	0	1	1
[auto[5]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[6]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[6]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[7]]	[auto[StInvalid]]	[auto[OpGenHwOut] , auto[OpDisable]]	--	--	2

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	2	1			T229	1		T230	1		-	-
auto[0]	auto[StReset]	auto[OpGenId]	165	1			T139	1		T29	1		T79	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	192	1			T15	1		T110	1		T124	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	228	1			T3	2		T4	1		T16	1
auto[0]	auto[StInit]	auto[OpAdvance]	47	1			T19	1		T110	1		T28	1
auto[0]	auto[StInit]	auto[OpGenId]	100	1			T17	1		T231	1		T191	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	98	1			T2	1		T19	1		T53	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	199	1			T18	1		T201	1		T204	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	16	1			T141	1		T129	1		T232	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	52	1			T20	1		T125	1		T71	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	45	1			T188	1		T59	1		T71	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	88	1			T19	2		T201	1		T187	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	9	1			T186	1		T193	1		T233	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	33	1			T60	1		T142	1		T73	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	25	1			T234	1		T142	1		T232	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	76	1			T1	1		T71	1		T202	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	10	1			T186	1		T232	1		T235	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	15	1			T105	1		T236	1		T237	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	21	1			T48	1		T185	1		T45	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	47	1			T53	1		T202	1		T70	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	18	1			T67	1		T238	1		T209	1
auto[0]	auto[StDisabled]	auto[OpGenId]	64	1			T48	1		T79	1		T53	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	53	1			T79	1		T53	1		T239	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	165	1			T1	2		T3	1		T16	1
auto[0]	auto[StDisabled]	auto[OpDisable]	22	1			T53	1		T232	1		T130	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	5	1			T30	1		T91	1		T240	1
auto[0]	auto[StInvalid]	auto[OpGenId]	12	1			T25	1		T91	1		T241	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T189	1		T197	1		T195	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	11	1			T30	1		T25	1		T27	1
auto[1]	auto[StReset]	auto[OpAdvance]	1	1			T129	1		-	-		-	-
auto[1]	auto[StReset]	auto[OpGenId]	20	1			T124	1		T139	1		T242	2
auto[1]	auto[StReset]	auto[OpGenSwOut]	18	1			T139	1		T29	1		T140	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	41	1			T3	1		T124	1		T205	1
auto[1]	auto[StInit]	auto[OpAdvance]	12	1			T129	1		T89	1		T243	1
auto[1]	auto[StInit]	auto[OpGenId]	10	1			T67	1		T63	1		T243	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	20	1			T28	1		T86	1		T88	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	21	1			T124	1		T206	1		T130	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T130	1		T244	1		T245	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	13	1			T246	1		T247	1		T122	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T71	1		T234	1		T73	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	49	1			T202	1		T248	1		T249	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T250	1		T251	1		T252	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	13	1			T253	1		T122	1		T68	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T16	1		T254	1		T255	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	43	1			T29	1		T256	1		T257	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T256	1		T148	1		T177	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	12	1			T110	2		T73	1		T258	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	16	1			T71	1		T114	1		T259	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	41	1			T45	1		T260	1		T67	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	9	1			T188	1		T209	1		T51	1
auto[1]	auto[StDisabled]	auto[OpGenId]	55	1			T141	1		T234	1		T69	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	52	1			T139	2		T193	1		T73	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	160	1			T3	1		T15	1		T85	2
auto[1]	auto[StDisabled]	auto[OpDisable]	17	1			T16	1		T47	1		T53	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	3	1			T27	1		T261	1		T262	1
auto[1]	auto[StInvalid]	auto[OpGenId]	11	1			T27	1		T189	1		T91	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T195	2		T263	1		T98	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T237	1		T264	1		T265	1
auto[2]	auto[StReset]	auto[OpAdvance]	2	1			T266	2		-	-		-	-
auto[2]	auto[StReset]	auto[OpGenId]	34	1			T124	1		T125	1		T60	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	25	1			T53	1		T25	1		T144	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	36	1			T85	1		T71	1		T206	1
auto[2]	auto[StInit]	auto[OpAdvance]	14	1			T267	3		T268	1		T269	1
auto[2]	auto[StInit]	auto[OpGenId]	16	1			T56	1		T71	1		T28	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	19	1			T139	1		T79	1		T45	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	27	1			T139	1		T25	1		T232	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	12	1			T87	1		T270	2		T271	2
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	13	1			T53	1		T259	1		T272	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	15	1			T53	1		T192	1		T74	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	46	1			T16	1		T18	1		T205	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	8	1			T139	1		T187	1		T273	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	11	1			T121	1		T274	1		T275	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	14	1			T2	1		T276	1		T67	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	37	1			T17	1		T19	1		T205	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T129	2		T277	1		T271	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	13	1			T15	1		T278	1		T279	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	13	1			T234	1		T280	1		T250	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	51	1			T201	1		T205	1		T79	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	28	1			T139	1		T67	2		T281	1
auto[2]	auto[StDisabled]	auto[OpGenId]	55	1			T2	2		T15	1		T125	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	47	1			T53	1		T114	1		T129	2
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	162	1			T15	1		T85	1		T139	1
auto[2]	auto[StDisabled]	auto[OpDisable]	9	1			T48	1		T278	1		T282	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	6	1			T273	1		T283	1		T284	1
auto[2]	auto[StInvalid]	auto[OpGenId]	4	1			T285	1		T286	1		T287	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T288	1		T289	1		T264	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T57	1		T263	1		T290	1
auto[3]	auto[StReset]	auto[OpGenId]	21	1			T71	4		T192	1		T61	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	20	1			T16	1		T60	1		T232	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	46	1			T3	2		T139	1		T187	1
auto[3]	auto[StInit]	auto[OpAdvance]	9	1			T4	1		T51	1		T291	1
auto[3]	auto[StInit]	auto[OpGenId]	10	1			T292	1		T97	1		T68	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	13	1			T28	1		T63	1		T293	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	19	1			T3	1		T89	1		T294	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T295	1		T121	1		T250	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	18	1			T239	1		T129	1		T238	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	14	1			T15	1		T232	1		T64	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	31	1			T85	1		T204	1		T203	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T106	1		T250	1		T296	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	16	1			T63	1		T297	1		T209	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	17	1			T53	1		T192	1		T232	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	44	1			T85	1		T20	1		T201	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T298	1		T299	1		T300	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	11	1			T73	1		T130	2		T211	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T232	1		T67	1		T23	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	49	1			T3	1		T18	1		T203	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	34	1			T140	1		T234	1		T301	1
auto[3]	auto[StDisabled]	auto[OpGenId]	52	1			T4	1		T73	1		T63	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	54	1			T193	1		T231	1		T302	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	152	1			T3	1		T4	1		T18	2
auto[3]	auto[StDisabled]	auto[OpDisable]	12	1			T69	1		T130	1		T102	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	5	1			T263	1		T303	1		T304	1
auto[3]	auto[StInvalid]	auto[OpGenId]	7	1			T189	1		T197	1		T92	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T284	1		T305	1		T306	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T189	1		T290	1		T94	1
auto[4]	auto[StReset]	auto[OpGenId]	13	1			T61	1		T307	1		T63	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	10	1			T29	1		T67	1		T57	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	14	1			T202	1		T249	1		T308	1
auto[4]	auto[StInit]	auto[OpAdvance]	5	1			T4	1		T88	1		T89	1
auto[4]	auto[StInit]	auto[OpGenId]	1	1			T309	1		-	-		-	-
auto[4]	auto[StInit]	auto[OpGenSwOut]	7	1			T140	1		T86	1		T74	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	15	1			T85	1		T310	2		T243	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T17	1		T98	1		T311	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	6	1			T29	1		T274	1		T296	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	11	1			T65	1		T122	1		T312	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	20	1			T3	1		T45	1		T73	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	1	1			T313	1		-	-		-	-
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T140	1		T87	1		T130	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T68	1		T314	1		T182	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	13	1			T18	1		T19	1		T67	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T281	1		T315	1		-	-
auto[4]	auto[StOwnerKey]	auto[OpGenId]	10	1			T73	1		T209	1		T316	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T67	1		T238	1		T122	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	22	1			T206	1		T69	1		T317	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	11	1			T45	1		T129	1		T307	1
auto[4]	auto[StDisabled]	auto[OpGenId]	33	1			T87	1		T129	1		T67	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	23	1			T232	1		T63	1		T318	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	79	1			T18	1		T201	1		T82	1
auto[4]	auto[StDisabled]	auto[OpDisable]	6	1			T60	1		T319	1		T220	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	3	1			T27	1		T92	1		T241	1
auto[4]	auto[StInvalid]	auto[OpGenId]	4	1			T27	1		T273	1		T289	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T57	1		T288	1		T289	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T92	1		T195	1		T91	1
auto[5]	auto[StReset]	auto[OpGenId]	9	1			T26	1		T61	1		T320	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	12	1			T49	1		T129	1		T278	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	33	1			T202	1		T321	2		T249	1
auto[5]	auto[StInit]	auto[OpAdvance]	2	1			T285	1		T322	1		-	-
auto[5]	auto[StInit]	auto[OpGenId]	13	1			T15	1		T87	1		T72	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	5	1			T57	1		T323	1		T324	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	15	1			T202	1		T325	1		T326	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T141	1		T327	1		T328	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T110	2		T329	1		T330	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T45	1		T232	1		T323	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	21	1			T308	1		T326	1		T331	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T141	1		T332	1		T333	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T110	2		T279	1		T74	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T334	1		T229	1		T322	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	19	1			T260	1		T335	1		T51	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	11	1			T106	1		T333	6		T336	2
auto[5]	auto[StOwnerKey]	auto[OpGenId]	2	1			T333	1		T337	1		-	-
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T141	1		T192	1		T302	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	20	1			T193	1		T130	1		T338	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	19	1			T188	1		T79	2		T131	1
auto[5]	auto[StDisabled]	auto[OpGenId]	26	1			T110	2		T73	1		T339	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	30	1			T209	1		T340	1		T341	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	77	1			T3	1		T110	3		T201	1
auto[5]	auto[StDisabled]	auto[OpDisable]	2	1			T59	1		T220	1		-	-
auto[5]	auto[StInvalid]	auto[OpGenId]	3	1			T91	1		T342	1		T283	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T30	1		T189	1		T57	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T189	1		T92	1		T303	1
auto[6]	auto[StReset]	auto[OpGenId]	7	1			T16	1		T110	1		T25	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	11	1			T232	1		T242	1		T295	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	24	1			T85	2		T52	1		T25	1
auto[6]	auto[StInit]	auto[OpAdvance]	2	1			T238	1		T343	1		-	-
auto[6]	auto[StInit]	auto[OpGenId]	11	1			T70	1		T67	1		T63	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	5	1			T67	1		T217	1		T344	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	11	1			T205	1		T203	1		T67	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T336	1		T345	1		T346	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T282	1		T7	1		T293	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T319	1		T347	1		T348	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	20	1			T206	1		T349	1		T67	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T350	1		T351	2		-	-
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T124	1		T352	1		T353	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	5	1			T354	1		T65	1		T344	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	20	1			T206	1		T63	1		T355	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T274	1		T211	1		T250	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	9	1			T45	1		T33	1		T356	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T68	1		T322	1		T227	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	15	1			T85	1		T253	1		T294	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	12	1			T142	2		T130	1		T297	1
auto[6]	auto[StDisabled]	auto[OpGenId]	30	1			T139	4		T71	1		T232	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	28	1			T71	2		T142	1		T130	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	69	1			T85	1		T201	1		T205	1
auto[6]	auto[StDisabled]	auto[OpDisable]	5	1			T220	1		T357	1		T358	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	2	1			T57	1		T290	1		-	-
auto[6]	auto[StInvalid]	auto[OpGenId]	2	1			T241	1		T304	1		-	-
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	2	1			T61	1		T265	1		-	-
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	2	1			T241	1		T262	1		-	-
auto[7]	auto[StReset]	auto[OpGenId]	10	1			T4	1		T359	1		T217	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	14	1			T61	1		T63	2		T272	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	19	1			T205	1		T249	2		T360	1
auto[7]	auto[StInit]	auto[OpAdvance]	4	1			T361	1		T243	1		T362	1
auto[7]	auto[StInit]	auto[OpGenId]	7	1			T26	2		T282	1		T363	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	10	1			T67	1		T64	1		T364	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	13	1			T278	1		T365	1		T366	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	1	1			T121	1		-	-		-	-
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	5	1			T53	1		T354	1		T67	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T367	1		T368	1		T345	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	17	1			T82	1		T260	1		T130	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T369	1		T370	1		T371	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T232	1		T238	1		T130	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	11	1			T71	2		T232	1		T321	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	36	1			T3	1		T125	1		T82	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T371	1		T258	1		-	-
auto[7]	auto[StOwnerKey]	auto[OpGenId]	3	1			T121	1		T372	1		T373	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T71	1		T354	1		T246	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	26	1			T204	1		T82	1		T349	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	15	1			T70	1		T209	1		T374	1
auto[7]	auto[StDisabled]	auto[OpGenId]	25	1			T125	1		T53	1		T71	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	22	1			T125	1		T142	1		T232	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	77	1			T18	1		T139	1		T205	1
auto[7]	auto[StDisabled]	auto[OpDisable]	5	1			T72	1		T51	1		T220	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	3	1			T264	1		T375	1		T305	1
auto[7]	auto[StInvalid]	auto[OpGenId]	3	1			T285	1		T283	1		T261	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T195	1		T94	1		T284	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1410

1

T3

3

T4

2

T15

1

clear_one[1]

auto[0]

auto[0]

auto[0]

398

1

T3

2

T16

2

T85

2

clear_one[1]

auto[0]

auto[0]

auto[1]

118

1

T186

1

T188

1

T71

1

clear_one[1]

auto[0]

auto[1]

auto[0]

130

1

T15

1

T29

1

T193

1

clear_one[1]

auto[0]

auto[1]

auto[1]

34

1

T139

2

T45

2

T256

2

clear_one[2]

auto[0]

auto[0]

auto[0]

417

1

T2

1

T15

3

T16

1

clear_one[2]

auto[0]

auto[0]

auto[1]

130

1

T2

2

T17

1

T18

1

clear_one[2]

auto[1]

auto[0]

auto[0]

144

1

T85

1

T204

3

T53

1

clear_one[2]

auto[1]

auto[0]

auto[1]

38

1

T125

1

T79

1

T53

1

clear_one[3]

auto[0]

auto[0]

auto[0]

400

1

T3

3

T4

1

T15

1

clear_one[3]

auto[0]

auto[1]

auto[0]

126

1

T20

1

T201

1

T205

1

clear_one[3]

auto[1]

auto[0]

auto[0]

111

1

T3

2

T85

2

T204

2

clear_one[3]

auto[1]

auto[1]

auto[0]

47

1

T4

2

T193

1

T185

1

clear_none

auto[0]

auto[0]

auto[0]

1281

1

T2

1

T3

2

T4

1

clear_none

auto[0]

auto[0]

auto[1]

135

1

T48

2

T79

1

T53

1

clear_none

auto[0]

auto[1]

auto[0]

148

1

T16

1

T19

1

T201

2

clear_none

auto[0]

auto[1]

auto[1]

31

1

T17

1

T142

3

T376

1

clear_none

auto[1]

auto[0]

auto[0]

147

1

T3

1

T125

1

T204

1

clear_none

auto[1]

auto[0]

auto[1]

36

1

T377

1

T130

2

T131

3

clear_none

auto[1]

auto[1]

auto[0]

24

1

T60

1

T129

1

T67

1

clear_none

auto[1]

auto[1]

auto[1]

24

1

T1

3

T53

1

T67

2

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1344	1			T3	3		T4	2		T15	1
clear_all	auto[1]	66	1			T110	8		T139	3		T140	1
clear_one[1]	auto[0]	649	1			T3	2		T15	1		T16	2
clear_one[1]	auto[1]	31	1			T110	1		T139	1		T129	1
clear_one[2]	auto[0]	670	1			T2	3		T15	3		T16	1
clear_one[2]	auto[1]	59	1			T139	3		T79	1		T129	3
clear_one[3]	auto[0]	648	1			T3	5		T4	1		T15	1
clear_one[3]	auto[1]	36	1			T4	2		T140	1		T277	1
clear_none	auto[0]	1777	1			T1	3		T2	1		T3	3
clear_none	auto[1]	49	1			T142	1		T129	2		T131	11