Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11800

1

T1

11

T2

10

T3

13

auto[Attestation]

8206

1

T1

11

T2

16

T3

4

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2954	1			T1	3		T2	1		T4	2
auto[Aes]	3596	1			T1	4		T2	5		T3	17
auto[Kmac]	3526	1			T1	8		T2	5		T4	4
auto[Otbn]	3666	1			T1	3		T2	7		T4	3

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	8004	1			T1	6		T2	8		T3	8
auto[OpGenId]	6264	1			T1	4		T2	8		T4	6
auto[OpGenSwOut]	6366	1			T1	8		T2	13		T4	2
auto[OpGenHwOut]	7376	1			T1	10		T2	5		T3	17
auto[OpDisable]	145	1			T16	1		T47	1		T48	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10661

1

T1

15

T2

13

T3

8

auto[OpDoneFail]

17494

1

T1

13

T2

21

T3

17

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6614	1			T1	1		T2	1		T3	10
auto[StInit]	4358	1			T1	5		T2	3		T3	2
auto[StCreatorRootKey]	3171	1			T1	3		T2	1		T3	2
auto[StOwnerIntKey]	2838	1			T1	4		T2	4		T3	2
auto[StOwnerKey]	2465	1			T1	6		T2	6		T3	2
auto[StDisabled]	7742	1			T1	9		T2	19		T3	7
auto[StInvalid]	967	1			T30	29		T25	27		T27	15

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	367	1			T15	3		T17	1		T38	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	121	1			T37	1		T139	1		T29	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	73	1			T1	1		T19	1		T71	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	76	1			T17	1		T79	1		T53	3
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	85	1			T19	1		T71	1		T185	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	187	1			T14	1		T29	1		T186	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	28	1			T30	2		T27	1		T92	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	346	1			T4	1		T15	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	142	1			T1	1		T2	1		T139	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	93	1			T187	1		T188	2		T185	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	66	1			T2	1		T188	1		T114	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	56	1			T124	1		T125	1		T53	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	182	1			T19	1		T125	1		T53	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	41	1			T30	2		T25	1		T189	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	355	1			T15	3		T16	1		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	120	1			T1	1		T39	1		T56	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	82	1			T38	1		T39	1		T187	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	85	1			T16	1		T190	1		T70	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	71	1			T191	1		T45	1		T192	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	219	1			T1	3		T2	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	31	1			T30	2		T25	1		T189	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	345	1			T15	1		T16	2		T38	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	127	1			T14	1		T19	1		T56	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	94	1			T15	1		T19	1		T124	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	72	1			T17	1		T53	1		T71	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	49	1			T193	1		T71	1		T194	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	206	1			T2	1		T14	1		T110	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	36	1			T25	2		T189	1		T195	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	71	1			T53	1		T45	1		T73	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	121	1			T20	1		T79	2		T53	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	93	1			T38	1		T124	1		T71	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	78	1			T14	1		T17	1		T125	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	60	1			T80	1		T53	1		T196	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	217	1			T4	1		T139	1		T29	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	32	1			T30	3		T189	1		T197	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	72	1			T25	1		T73	1		T61	4
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	116	1			T19	1		T53	1		T71	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	95	1			T59	1		T193	1		T70	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	73	1			T48	1		T71	1		T198	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	65	1			T1	1		T199	1		T70	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	191	1			T2	3		T110	1		T29	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	32	1			T30	1		T189	1		T92	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	78	1			T27	1		T61	2		T67	4
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	109	1			T53	1		T193	1		T71	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	85	1			T20	1		T56	1		T188	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	57	1			T125	1		T140	1		T45	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	63	1			T48	1		T71	1		T140	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	196	1			T1	1		T2	3		T29	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	34	1			T30	2		T25	2		T197	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	83	1			T53	1		T45	1		T25	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	141	1			T2	1		T16	1		T29	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	88	1			T38	1		T124	1		T48	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	74	1			T2	2		T110	1		T196	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	54	1			T140	1		T45	1		T200	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	205	1			T110	1		T125	1		T139	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	28	1			T27	1		T189	2		T197	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	277	1			T4	1		T17	1		T110	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	107	1			T124	1		T139	1		T30	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	89	1			T16	1		T19	1		T125	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	67	1			T19	1		T125	1		T29	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	57	1			T139	1		T53	1		T193	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	181	1			T1	1		T15	1		T186	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	26	1			T30	1		T25	1		T197	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	460	1			T3	9		T15	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	151	1			T85	1		T125	1		T82	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	126	1			T3	1		T85	1		T29	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	98	1			T1	1		T3	1		T53	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	97	1			T3	1		T85	1		T110	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	265	1			T1	1		T3	1		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	33	1			T30	1		T25	2		T189	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	414	1			T4	2		T15	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	128	1			T38	1		T201	1		T47	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	124	1			T16	1		T38	1		T139	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	102	1			T19	1		T125	1		T202	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	78	1			T125	1		T139	1		T79	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	262	1			T4	1		T15	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	22	1			T30	1		T25	1		T27	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	511	1			T4	1		T16	2		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	146	1			T18	1		T203	1		T26	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	111	1			T18	1		T48	1		T71	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	104	1			T1	1		T18	1		T187	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	99	1			T1	1		T2	1		T124	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	278	1			T2	1		T4	1		T18	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	28	1			T25	1		T189	1		T197	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	56	1			T53	1		T25	1		T27	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	119	1			T139	1		T187	1		T71	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	75	1			T29	1		T40	1		T73	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	56	1			T110	1		T125	1		T29	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	52	1			T1	1		T2	1		T188	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	165	1			T110	1		T29	1		T186	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	18	1			T30	1		T189	1		T197	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	61	1			T53	1		T25	1		T27	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	123	1			T3	1		T38	1		T125	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	85	1			T124	1		T125	1		T53	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	105	1			T85	1		T124	1		T187	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	96	1			T124	1		T29	1		T204	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	293	1			T3	3		T85	3		T29	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	33	1			T30	2		T197	1		T92	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	57	1			T25	2		T27	1		T73	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	139	1			T38	1		T124	2		T205	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	105	1			T1	1		T19	1		T187	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	105	1			T1	1		T4	1		T20	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	91	1			T1	1		T2	1		T201	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	289	1			T16	1		T17	1		T110	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	25	1			T25	4		T27	1		T197	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	64	1			T45	1		T25	1		T73	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	111	1			T20	1		T30	1		T206	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	102	1			T39	1		T53	1		T71	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	94	1			T17	1		T187	1		T79	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	93	1			T18	1		T125	1		T203	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	289	1			T1	1		T2	1		T4	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	34	1			T25	1		T27	4		T189	2

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	223	1			T1	1		T17	1		T19	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	714	1			T14	1		T15	3		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	198	1			T2	1		T124	1		T125	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	728	1			T1	1		T2	1		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	226	1			T16	1		T38	1		T39	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	737	1			T1	4		T2	1		T15	4
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	199	1			T15	1		T17	1		T124	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	730	1			T2	1		T14	2		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	209	1			T14	1		T17	1		T38	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	463	1			T4	1		T20	1		T139	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	220	1			T1	1		T48	1		T199	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	424	1			T2	3		T19	1		T110	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	193	1			T20	1		T125	1		T56	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	429	1			T1	1		T2	3		T29	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	205	1			T2	2		T110	1		T38	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	468	1			T2	1		T16	1		T110	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	197	1			T16	1		T19	2		T125	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	607	1			T1	1		T4	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	303	1			T1	1		T3	3		T85	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	927	1			T1	1		T3	10		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	289	1			T16	1		T38	1		T125	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	841	1			T4	3		T15	2		T16	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	295	1			T1	2		T2	1		T18	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	982	1			T2	1		T4	2		T16	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	167	1			T1	1		T2	1		T110	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	374	1			T110	1		T139	1		T187	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	274	1			T85	1		T124	3		T125	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	522	1			T3	4		T85	3		T38	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	290	1			T1	3		T2	1		T4	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	521	1			T16	1		T17	1		T110	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	272	1			T17	1		T18	1		T39	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	515	1			T1	1		T2	1		T4	1