Unified Coverage Report :: Group Instance : attest_sw_binding_2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32135

1

T1

30

T2

39

T3

30

auto[1]

232

1

T4

5

T110

7

T139

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	32146	1			T1	30		T2	39		T3	30
auto[134217728:268435455]	4	1			T383	1		T296	1		T371	1
auto[268435456:402653183]	3	1			T270	1		T271	1		T404	1
auto[402653184:536870911]	6	1			T4	1		T333	1		T405	2
auto[536870912:671088639]	4	1			T406	1		T230	1		T351	1
auto[671088640:805306367]	9	1			T110	1		T142	1		T129	2
auto[805306368:939524095]	6	1			T4	1		T129	1		T131	1
auto[939524096:1073741823]	10	1			T277	1		T406	1		T350	1
auto[1073741824:1207959551]	8	1			T141	1		T229	1		T406	1
auto[1207959552:1342177279]	10	1			T140	1		T129	1		T230	1
auto[1342177280:1476395007]	3	1			T407	1		T408	1		T409	1
auto[1476395008:1610612735]	5	1			T131	1		T271	2		T410	1
auto[1610612736:1744830463]	6	1			T110	1		T142	1		T131	2
auto[1744830464:1879048191]	10	1			T141	1		T129	1		T270	1
auto[1879048192:2013265919]	6	1			T79	2		T141	1		T131	1
auto[2013265920:2147483647]	9	1			T129	1		T131	1		T371	1
auto[2147483648:2281701375]	3	1			T267	1		T333	1		T336	1
auto[2281701376:2415919103]	13	1			T4	2		T141	1		T131	2
auto[2415919104:2550136831]	8	1			T4	1		T229	1		T406	1
auto[2550136832:2684354559]	5	1			T383	1		T410	1		T409	1
auto[2684354560:2818572287]	7	1			T110	1		T142	1		T271	1
auto[2818572288:2952790015]	5	1			T110	1		T267	1		T266	1
auto[2952790016:3087007743]	12	1			T110	1		T131	1		T229	1
auto[3087007744:3221225471]	12	1			T139	1		T142	1		T300	1
auto[3221225472:3355443199]	11	1			T131	1		T277	1		T229	1
auto[3355443200:3489660927]	4	1			T110	1		T129	1		T230	1
auto[3489660928:3623878655]	8	1			T110	1		T129	2		T267	1
auto[3623878656:3758096383]	5	1			T267	1		T271	2		T387	1
auto[3758096384:3892314111]	4	1			T385	1		T350	1		T411	1
auto[3892314112:4026531839]	10	1			T139	1		T141	1		T131	1
auto[4026531840:4160749567]	6	1			T406	1		T296	1		T408	1
auto[4160749568:4294967295]	9	1			T131	1		T406	1		T270	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	32135	1			T1	30		T2	39		T3	30
auto[0:134217727]	auto[1]	11	1			T131	3		T277	1		T406	1
auto[134217728:268435455]	auto[1]	4	1			T383	1		T296	1		T371	1
auto[268435456:402653183]	auto[1]	3	1			T270	1		T271	1		T404	1
auto[402653184:536870911]	auto[1]	6	1			T4	1		T333	1		T405	2
auto[536870912:671088639]	auto[1]	4	1			T406	1		T230	1		T351	1
auto[671088640:805306367]	auto[1]	9	1			T110	1		T142	1		T129	2
auto[805306368:939524095]	auto[1]	6	1			T4	1		T129	1		T131	1
auto[939524096:1073741823]	auto[1]	10	1			T277	1		T406	1		T350	1
auto[1073741824:1207959551]	auto[1]	8	1			T141	1		T229	1		T406	1
auto[1207959552:1342177279]	auto[1]	10	1			T140	1		T129	1		T230	1
auto[1342177280:1476395007]	auto[1]	3	1			T407	1		T408	1		T409	1
auto[1476395008:1610612735]	auto[1]	5	1			T131	1		T271	2		T410	1
auto[1610612736:1744830463]	auto[1]	6	1			T110	1		T142	1		T131	2
auto[1744830464:1879048191]	auto[1]	10	1			T141	1		T129	1		T270	1
auto[1879048192:2013265919]	auto[1]	6	1			T79	2		T141	1		T131	1
auto[2013265920:2147483647]	auto[1]	9	1			T129	1		T131	1		T371	1
auto[2147483648:2281701375]	auto[1]	3	1			T267	1		T333	1		T336	1
auto[2281701376:2415919103]	auto[1]	13	1			T4	2		T141	1		T131	2
auto[2415919104:2550136831]	auto[1]	8	1			T4	1		T229	1		T406	1
auto[2550136832:2684354559]	auto[1]	5	1			T383	1		T410	1		T409	1
auto[2684354560:2818572287]	auto[1]	7	1			T110	1		T142	1		T271	1
auto[2818572288:2952790015]	auto[1]	5	1			T110	1		T267	1		T266	1
auto[2952790016:3087007743]	auto[1]	12	1			T110	1		T131	1		T229	1
auto[3087007744:3221225471]	auto[1]	12	1			T139	1		T142	1		T300	1
auto[3221225472:3355443199]	auto[1]	11	1			T131	1		T277	1		T229	1
auto[3355443200:3489660927]	auto[1]	4	1			T110	1		T129	1		T230	1
auto[3489660928:3623878655]	auto[1]	8	1			T110	1		T129	2		T267	1
auto[3623878656:3758096383]	auto[1]	5	1			T267	1		T271	2		T387	1
auto[3758096384:3892314111]	auto[1]	4	1			T385	1		T350	1		T411	1
auto[3892314112:4026531839]	auto[1]	10	1			T139	1		T141	1		T131	1
auto[4026531840:4160749567]	auto[1]	6	1			T406	1		T296	1		T408	1
auto[4160749568:4294967295]	auto[1]	9	1			T131	1		T406	1		T270	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2938

1

T1

5

T2

2

T4

7

auto[1]

249

1

T4

3

T110

6

T139

6

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	90	1			T16	1		T187	1		T29	1
auto[134217728:268435455]	103	1			T2	1		T19	1		T139	1
auto[268435456:402653183]	97	1			T4	1		T16	1		T186	1
auto[402653184:536870911]	104	1			T1	1		T110	1		T125	1
auto[536870912:671088639]	112	1			T125	1		T140	1		T141	1
auto[671088640:805306367]	97	1			T1	1		T17	1		T110	1
auto[805306368:939524095]	95	1			T2	1		T19	2		T110	1
auto[939524096:1073741823]	97	1			T4	1		T110	1		T40	1
auto[1073741824:1207959551]	105	1			T19	1		T110	1		T79	1
auto[1207959552:1342177279]	110	1			T20	1		T52	1		T188	1
auto[1342177280:1476395007]	96	1			T4	1		T139	1		T52	2
auto[1476395008:1610612735]	104	1			T1	1		T16	1		T124	1
auto[1610612736:1744830463]	106	1			T79	1		T53	1		T59	1
auto[1744830464:1879048191]	90	1			T139	1		T53	1		T72	1
auto[1879048192:2013265919]	101	1			T19	1		T139	1		T71	1
auto[2013265920:2147483647]	94	1			T17	1		T19	1		T187	1
auto[2147483648:2281701375]	82	1			T4	1		T59	1		T140	1
auto[2281701376:2415919103]	96	1			T1	1		T110	1		T139	1
auto[2415919104:2550136831]	107	1			T4	1		T16	1		T79	1
auto[2550136832:2684354559]	93	1			T125	1		T45	1		T86	1
auto[2684354560:2818572287]	102	1			T186	2		T188	1		T53	1
auto[2818572288:2952790015]	109	1			T4	1		T125	1		T47	1
auto[2952790016:3087007743]	104	1			T4	1		T17	1		T139	1
auto[3087007744:3221225471]	91	1			T19	1		T110	1		T125	1
auto[3221225472:3355443199]	88	1			T4	1		T125	1		T45	1
auto[3355443200:3489660927]	104	1			T124	1		T185	1		T141	1
auto[3489660928:3623878655]	108	1			T19	1		T124	1		T125	1
auto[3623878656:3758096383]	93	1			T4	1		T17	1		T124	1
auto[3758096384:3892314111]	97	1			T110	1		T124	1		T139	1
auto[3892314112:4026531839]	113	1			T19	1		T30	1		T186	1
auto[4026531840:4160749567]	86	1			T1	1		T4	1		T19	1
auto[4160749568:4294967295]	113	1			T110	2		T124	1		T30	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	1	63	98.44	1

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0:134217727]]	[auto[1]]	0	1	1

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	90	1			T16	1		T187	1		T29	1
auto[134217728:268435455]	auto[0]	97	1			T2	1		T19	1		T139	1
auto[134217728:268435455]	auto[1]	6	1			T229	1		T271	1		T266	1
auto[268435456:402653183]	auto[0]	88	1			T4	1		T16	1		T186	1
auto[268435456:402653183]	auto[1]	9	1			T142	1		T129	1		T350	1
auto[402653184:536870911]	auto[0]	97	1			T1	1		T125	1		T139	2
auto[402653184:536870911]	auto[1]	7	1			T110	1		T277	1		T229	1
auto[536870912:671088639]	auto[0]	100	1			T125	1		T140	1		T27	2
auto[536870912:671088639]	auto[1]	12	1			T141	1		T142	1		T229	1
auto[671088640:805306367]	auto[0]	89	1			T1	1		T17	1		T110	1
auto[671088640:805306367]	auto[1]	8	1			T129	1		T406	1		T296	2
auto[805306368:939524095]	auto[0]	89	1			T2	1		T19	2		T110	1
auto[805306368:939524095]	auto[1]	6	1			T267	1		T386	1		T371	1
auto[939524096:1073741823]	auto[0]	90	1			T4	1		T40	1		T53	1
auto[939524096:1073741823]	auto[1]	7	1			T110	1		T141	1		T129	1
auto[1073741824:1207959551]	auto[0]	95	1			T19	1		T110	1		T79	1
auto[1073741824:1207959551]	auto[1]	10	1			T129	1		T267	1		T296	1
auto[1207959552:1342177279]	auto[0]	103	1			T20	1		T52	1		T188	1
auto[1207959552:1342177279]	auto[1]	7	1			T129	1		T385	1		T266	1
auto[1342177280:1476395007]	auto[0]	85	1			T4	1		T52	2		T56	1
auto[1342177280:1476395007]	auto[1]	11	1			T139	1		T229	1		T300	1
auto[1476395008:1610612735]	auto[0]	96	1			T1	1		T16	1		T124	1
auto[1476395008:1610612735]	auto[1]	8	1			T142	1		T229	1		T270	1
auto[1610612736:1744830463]	auto[0]	93	1			T53	1		T59	1		T141	1
auto[1610612736:1744830463]	auto[1]	13	1			T79	1		T142	2		T267	1
auto[1744830464:1879048191]	auto[0]	85	1			T53	1		T72	1		T61	2
auto[1744830464:1879048191]	auto[1]	5	1			T139	1		T296	1		T409	1
auto[1879048192:2013265919]	auto[0]	96	1			T19	1		T139	1		T71	1
auto[1879048192:2013265919]	auto[1]	5	1			T388	1		T258	1		T410	2
auto[2013265920:2147483647]	auto[0]	88	1			T17	1		T19	1		T187	1
auto[2013265920:2147483647]	auto[1]	6	1			T141	1		T131	1		T383	1
auto[2147483648:2281701375]	auto[0]	73	1			T59	1		T140	1		T412	1
auto[2147483648:2281701375]	auto[1]	9	1			T4	1		T131	1		T383	1
auto[2281701376:2415919103]	auto[0]	87	1			T1	1		T110	1		T29	1
auto[2281701376:2415919103]	auto[1]	9	1			T139	1		T79	1		T131	1
auto[2415919104:2550136831]	auto[0]	103	1			T4	1		T16	1		T79	1
auto[2415919104:2550136831]	auto[1]	4	1			T142	1		T267	1		T406	1
auto[2550136832:2684354559]	auto[0]	85	1			T125	1		T45	1		T86	1
auto[2550136832:2684354559]	auto[1]	8	1			T131	1		T271	1		T258	1
auto[2684354560:2818572287]	auto[0]	92	1			T186	2		T188	1		T53	1
auto[2684354560:2818572287]	auto[1]	10	1			T131	2		T267	1		T271	1
auto[2818572288:2952790015]	auto[0]	101	1			T4	1		T125	1		T47	1
auto[2818572288:2952790015]	auto[1]	8	1			T131	1		T270	2		T230	1
auto[2952790016:3087007743]	auto[0]	96	1			T17	1		T53	2		T189	1
auto[2952790016:3087007743]	auto[1]	8	1			T4	1		T139	1		T271	2
auto[3087007744:3221225471]	auto[0]	82	1			T19	1		T125	1		T30	1
auto[3087007744:3221225471]	auto[1]	9	1			T110	1		T131	1		T270	1
auto[3221225472:3355443199]	auto[0]	80	1			T125	1		T45	1		T141	1
auto[3221225472:3355443199]	auto[1]	8	1			T4	1		T267	1		T266	1
auto[3355443200:3489660927]	auto[0]	100	1			T124	1		T185	1		T234	1
auto[3355443200:3489660927]	auto[1]	4	1			T141	1		T271	1		T333	1
auto[3489660928:3623878655]	auto[0]	106	1			T19	1		T124	1		T125	1
auto[3489660928:3623878655]	auto[1]	2	1			T139	1		T131	1		-	-
auto[3623878656:3758096383]	auto[0]	82	1			T4	1		T17	1		T124	1
auto[3623878656:3758096383]	auto[1]	11	1			T141	1		T129	1		T131	2
auto[3758096384:3892314111]	auto[0]	88	1			T124	1		T29	1		T48	2
auto[3758096384:3892314111]	auto[1]	9	1			T110	1		T139	1		T131	1
auto[3892314112:4026531839]	auto[0]	102	1			T19	1		T30	1		T186	1
auto[3892314112:4026531839]	auto[1]	11	1			T79	1		T131	1		T258	1
auto[4026531840:4160749567]	auto[0]	79	1			T1	1		T4	1		T19	1
auto[4026531840:4160749567]	auto[1]	7	1			T110	1		T277	1		T229	1
auto[4160749568:4294967295]	auto[0]	101	1			T110	1		T124	1		T30	1
auto[4160749568:4294967295]	auto[1]	12	1			T110	1		T142	2		T129	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1603

1

T1

1

T4

2

T16

3

auto[1]

1739

1

T1

4

T2

2

T4

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	92	1			T1	1		T16	1		T79	1
auto[134217728:268435455]	101	1			T2	1		T29	1		T186	1
auto[268435456:402653183]	95	1			T19	1		T186	1		T52	1
auto[402653184:536870911]	109	1			T4	1		T110	1		T139	1
auto[536870912:671088639]	116	1			T19	1		T125	1		T56	2
auto[671088640:805306367]	115	1			T1	1		T4	1		T19	1
auto[805306368:939524095]	106	1			T139	1		T52	1		T47	1
auto[939524096:1073741823]	116	1			T16	1		T17	1		T19	1
auto[1073741824:1207959551]	104	1			T16	1		T56	1		T40	1
auto[1207959552:1342177279]	102	1			T17	1		T29	1		T47	1
auto[1342177280:1476395007]	105	1			T124	1		T48	1		T53	1
auto[1476395008:1610612735]	97	1			T139	1		T186	1		T56	1
auto[1610612736:1744830463]	132	1			T1	1		T19	1		T20	1
auto[1744830464:1879048191]	100	1			T1	1		T124	1		T53	1
auto[1879048192:2013265919]	94	1			T19	2		T186	1		T48	1
auto[2013265920:2147483647]	93	1			T16	1		T125	1		T29	1
auto[2147483648:2281701375]	87	1			T110	1		T125	1		T52	3
auto[2281701376:2415919103]	132	1			T17	1		T110	1		T56	1
auto[2415919104:2550136831]	96	1			T4	1		T124	1		T70	1
auto[2550136832:2684354559]	99	1			T4	1		T187	1		T53	1
auto[2684354560:2818572287]	112	1			T4	1		T124	1		T125	2
auto[2818572288:2952790015]	106	1			T125	1		T83	1		T53	2
auto[2952790016:3087007743]	88	1			T17	2		T187	1		T83	2
auto[3087007744:3221225471]	105	1			T17	1		T19	1		T110	1
auto[3221225472:3355443199]	110	1			T19	1		T125	2		T56	1
auto[3355443200:3489660927]	103	1			T52	1		T53	1		T45	1
auto[3489660928:3623878655]	101	1			T2	1		T52	1		T140	1
auto[3623878656:3758096383]	99	1			T52	1		T25	1		T234	1
auto[3758096384:3892314111]	96	1			T1	1		T4	1		T139	1
auto[3892314112:4026531839]	120	1			T19	1		T186	1		T53	3
auto[4026531840:4160749567]	115	1			T124	1		T56	1		T53	1
auto[4160749568:4294967295]	96	1			T4	1		T110	1		T139	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	42	1			T53	1		T46	1		T232	1
auto[0:134217727]	auto[1]	50	1			T1	1		T16	1		T79	1
auto[134217728:268435455]	auto[0]	45	1			T186	1		T86	1		T197	1
auto[134217728:268435455]	auto[1]	56	1			T2	1		T29	1		T188	1
auto[268435456:402653183]	auto[0]	43	1			T186	1		T52	1		T26	1
auto[268435456:402653183]	auto[1]	52	1			T19	1		T185	1		T63	2
auto[402653184:536870911]	auto[0]	48	1			T139	1		T52	1		T53	1
auto[402653184:536870911]	auto[1]	61	1			T4	1		T110	1		T188	1
auto[536870912:671088639]	auto[0]	48	1			T56	1		T83	1		T53	1
auto[536870912:671088639]	auto[1]	68	1			T19	1		T125	1		T56	1
auto[671088640:805306367]	auto[0]	60	1			T124	1		T29	1		T232	1
auto[671088640:805306367]	auto[1]	55	1			T1	1		T4	1		T19	1
auto[805306368:939524095]	auto[0]	36	1			T71	1		T276	1		T67	1
auto[805306368:939524095]	auto[1]	70	1			T139	1		T52	1		T47	1
auto[939524096:1073741823]	auto[0]	49	1			T16	1		T17	1		T19	1
auto[939524096:1073741823]	auto[1]	67	1			T29	1		T25	1		T67	1
auto[1073741824:1207959551]	auto[0]	56	1			T16	1		T40	1		T53	1
auto[1073741824:1207959551]	auto[1]	48	1			T56	1		T45	1		T22	1
auto[1207959552:1342177279]	auto[0]	55	1			T17	1		T29	1		T83	1
auto[1207959552:1342177279]	auto[1]	47	1			T47	1		T31	1		T67	1
auto[1342177280:1476395007]	auto[0]	57	1			T53	1		T49	1		T61	1
auto[1342177280:1476395007]	auto[1]	48	1			T124	1		T48	1		T46	1
auto[1476395008:1610612735]	auto[0]	45	1			T186	1		T53	1		T193	1
auto[1476395008:1610612735]	auto[1]	52	1			T139	1		T56	1		T193	1
auto[1610612736:1744830463]	auto[0]	76	1			T1	1		T53	1		T70	1
auto[1610612736:1744830463]	auto[1]	56	1			T19	1		T20	1		T49	1
auto[1744830464:1879048191]	auto[0]	47	1			T53	1		T140	1		T234	1
auto[1744830464:1879048191]	auto[1]	53	1			T1	1		T124	1		T189	1
auto[1879048192:2013265919]	auto[0]	42	1			T48	1		T28	1		T73	1
auto[1879048192:2013265919]	auto[1]	52	1			T19	2		T186	1		T67	1
auto[2013265920:2147483647]	auto[0]	42	1			T16	1		T27	3		T234	1
auto[2013265920:2147483647]	auto[1]	51	1			T125	1		T29	1		T53	1
auto[2147483648:2281701375]	auto[0]	35	1			T125	1		T52	2		T53	1
auto[2147483648:2281701375]	auto[1]	52	1			T110	1		T52	1		T53	2
auto[2281701376:2415919103]	auto[0]	64	1			T56	1		T79	1		T83	1
auto[2281701376:2415919103]	auto[1]	68	1			T17	1		T110	1		T45	2
auto[2415919104:2550136831]	auto[0]	50	1			T4	1		T124	1		T70	1
auto[2415919104:2550136831]	auto[1]	46	1			T141	1		T354	1		T63	1
auto[2550136832:2684354559]	auto[0]	39	1			T53	1		T64	1		T21	1
auto[2550136832:2684354559]	auto[1]	60	1			T4	1		T187	1		T193	1
auto[2684354560:2818572287]	auto[0]	51	1			T124	1		T129	1		T232	1
auto[2684354560:2818572287]	auto[1]	61	1			T4	1		T125	2		T59	1
auto[2818572288:2952790015]	auto[0]	60	1			T125	1		T83	1		T53	2
auto[2818572288:2952790015]	auto[1]	46	1			T5	1		T280	1		T63	1
auto[2952790016:3087007743]	auto[0]	45	1			T187	1		T83	2		T86	1
auto[2952790016:3087007743]	auto[1]	43	1			T17	2		T53	1		T193	1
auto[3087007744:3221225471]	auto[0]	44	1			T19	1		T30	1		T40	1
auto[3087007744:3221225471]	auto[1]	61	1			T17	1		T110	1		T393	1
auto[3221225472:3355443199]	auto[0]	54	1			T19	1		T393	1		T87	1
auto[3221225472:3355443199]	auto[1]	56	1			T125	2		T56	1		T48	1
auto[3355443200:3489660927]	auto[0]	58	1			T52	1		T53	1		T86	1
auto[3355443200:3489660927]	auto[1]	45	1			T45	1		T189	1		T377	1
auto[3489660928:3623878655]	auto[0]	49	1			T52	1		T25	1		T141	1
auto[3489660928:3623878655]	auto[1]	52	1			T2	1		T140	1		T25	1
auto[3623878656:3758096383]	auto[0]	54	1			T25	1		T234	1		T86	1
auto[3623878656:3758096383]	auto[1]	45	1			T52	1		T61	1		T67	2
auto[3758096384:3892314111]	auto[0]	48	1			T4	1		T139	1		T56	2
auto[3758096384:3892314111]	auto[1]	48	1			T1	1		T40	1		T329	1
auto[3892314112:4026531839]	auto[0]	59	1			T19	1		T53	2		T393	1
auto[3892314112:4026531839]	auto[1]	61	1			T186	1		T53	1		T60	1
auto[4026531840:4160749567]	auto[0]	60	1			T56	1		T53	1		T71	1
auto[4026531840:4160749567]	auto[1]	55	1			T124	1		T193	1		T60	1
auto[4160749568:4294967295]	auto[0]	42	1			T139	1		T30	1		T52	1
auto[4160749568:4294967295]	auto[1]	54	1			T4	1		T110	1		T60	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1608

1

T2

2

T4

1

T16

2

auto[1]

1734

1

T1

5

T4

6

T16

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	106	1			T17	1		T29	1		T56	1
auto[134217728:268435455]	112	1			T19	1		T30	1		T52	1
auto[268435456:402653183]	107	1			T52	1		T47	1		T79	1
auto[402653184:536870911]	116	1			T4	1		T16	1		T17	1
auto[536870912:671088639]	122	1			T124	2		T125	1		T329	1
auto[671088640:805306367]	108	1			T2	1		T17	1		T19	1
auto[805306368:939524095]	107	1			T1	1		T4	2		T56	1
auto[939524096:1073741823]	107	1			T4	1		T19	2		T53	1
auto[1073741824:1207959551]	107	1			T16	1		T29	1		T393	1
auto[1207959552:1342177279]	94	1			T110	1		T188	1		T45	1
auto[1342177280:1476395007]	102	1			T139	1		T186	2		T52	1
auto[1476395008:1610612735]	100	1			T125	1		T30	1		T52	1
auto[1610612736:1744830463]	111	1			T110	1		T125	1		T193	1
auto[1744830464:1879048191]	105	1			T186	1		T56	1		T79	1
auto[1879048192:2013265919]	101	1			T4	1		T30	2		T186	1
auto[2013265920:2147483647]	98	1			T17	1		T19	1		T139	1
auto[2147483648:2281701375]	104	1			T187	1		T56	1		T53	1
auto[2281701376:2415919103]	100	1			T19	1		T110	1		T124	2
auto[2415919104:2550136831]	102	1			T52	1		T185	1		T87	1
auto[2550136832:2684354559]	101	1			T125	1		T56	1		T47	1
auto[2684354560:2818572287]	96	1			T125	1		T52	1		T56	1
auto[2818572288:2952790015]	86	1			T16	1		T19	1		T29	1
auto[2952790016:3087007743]	113	1			T1	1		T4	1		T19	1
auto[3087007744:3221225471]	106	1			T4	1		T19	1		T29	1
auto[3221225472:3355443199]	95	1			T1	2		T17	1		T19	1
auto[3355443200:3489660927]	107	1			T124	1		T48	1		T53	3
auto[3489660928:3623878655]	96	1			T1	1		T30	1		T56	1
auto[3623878656:3758096383]	108	1			T16	1		T52	1		T83	1
auto[3758096384:3892314111]	117	1			T20	1		T125	1		T186	1
auto[3892314112:4026531839]	102	1			T110	1		T52	2		T53	1
auto[4026531840:4160749567]	101	1			T53	2		T140	1		T60	1
auto[4160749568:4294967295]	105	1			T2	1		T17	1		T56	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	43	1			T29	1		T56	1		T79	1
auto[0:134217727]	auto[1]	63	1			T17	1		T188	1		T45	1
auto[134217728:268435455]	auto[0]	61	1			T30	1		T52	1		T56	1
auto[134217728:268435455]	auto[1]	51	1			T19	1		T53	1		T45	1
auto[268435456:402653183]	auto[0]	54	1			T52	1		T79	1		T193	1
auto[268435456:402653183]	auto[1]	53	1			T47	1		T71	2		T45	1
auto[402653184:536870911]	auto[0]	57	1			T17	1		T79	1		T53	2
auto[402653184:536870911]	auto[1]	59	1			T4	1		T16	1		T125	1
auto[536870912:671088639]	auto[0]	58	1			T124	1		T87	1		T141	1
auto[536870912:671088639]	auto[1]	64	1			T124	1		T125	1		T329	1
auto[671088640:805306367]	auto[0]	51	1			T2	1		T124	1		T125	1
auto[671088640:805306367]	auto[1]	57	1			T17	1		T19	1		T110	1
auto[805306368:939524095]	auto[0]	50	1			T53	1		T86	1		T278	1
auto[805306368:939524095]	auto[1]	57	1			T1	1		T4	2		T56	1
auto[939524096:1073741823]	auto[0]	52	1			T19	1		T59	1		T28	1
auto[939524096:1073741823]	auto[1]	55	1			T4	1		T19	1		T53	1
auto[1073741824:1207959551]	auto[0]	58	1			T49	1		T88	1		T377	1
auto[1073741824:1207959551]	auto[1]	49	1			T16	1		T29	1		T393	1
auto[1207959552:1342177279]	auto[0]	41	1			T25	1		T5	1		T67	1
auto[1207959552:1342177279]	auto[1]	53	1			T110	1		T188	1		T45	1
auto[1342177280:1476395007]	auto[0]	50	1			T139	1		T186	1		T53	1
auto[1342177280:1476395007]	auto[1]	52	1			T186	1		T52	1		T48	1
auto[1476395008:1610612735]	auto[0]	48	1			T30	1		T52	1		T87	1
auto[1476395008:1610612735]	auto[1]	52	1			T125	1		T188	1		T45	1
auto[1610612736:1744830463]	auto[0]	55	1			T110	1		T70	1		T87	1
auto[1610612736:1744830463]	auto[1]	56	1			T125	1		T193	1		T71	1
auto[1744830464:1879048191]	auto[0]	43	1			T186	1		T79	1		T53	1
auto[1744830464:1879048191]	auto[1]	62	1			T56	1		T193	1		T60	1
auto[1879048192:2013265919]	auto[0]	50	1			T4	1		T30	2		T140	1
auto[1879048192:2013265919]	auto[1]	51	1			T186	1		T56	1		T140	1
auto[2013265920:2147483647]	auto[0]	42	1			T17	1		T139	1		T83	1
auto[2013265920:2147483647]	auto[1]	56	1			T19	1		T187	1		T48	1
auto[2147483648:2281701375]	auto[0]	52	1			T187	1		T56	1		T53	1
auto[2147483648:2281701375]	auto[1]	52	1			T59	1		T234	2		T73	1
auto[2281701376:2415919103]	auto[0]	36	1			T124	1		T83	1		T53	1
auto[2281701376:2415919103]	auto[1]	64	1			T19	1		T110	1		T124	1
auto[2415919104:2550136831]	auto[0]	51	1			T52	1		T185	1		T87	1
auto[2415919104:2550136831]	auto[1]	51	1			T45	2		T25	1		T189	1
auto[2550136832:2684354559]	auto[0]	47	1			T56	1		T70	1		T25	1
auto[2550136832:2684354559]	auto[1]	54	1			T125	1		T47	1		T61	1
auto[2684354560:2818572287]	auto[0]	47	1			T52	1		T53	2		T27	1
auto[2684354560:2818572287]	auto[1]	49	1			T125	1		T56	1		T193	1
auto[2818572288:2952790015]	auto[0]	49	1			T16	1		T29	1		T40	1
auto[2818572288:2952790015]	auto[1]	37	1			T19	1		T53	1		T27	1
auto[2952790016:3087007743]	auto[0]	57	1			T139	1		T29	1		T27	1
auto[2952790016:3087007743]	auto[1]	56	1			T1	1		T4	1		T19	1
auto[3087007744:3221225471]	auto[0]	43	1			T53	1		T67	1		T130	1
auto[3087007744:3221225471]	auto[1]	63	1			T4	1		T19	1		T29	1
auto[3221225472:3355443199]	auto[0]	38	1			T17	1		T53	1		T86	1
auto[3221225472:3355443199]	auto[1]	57	1			T1	2		T19	1		T139	1
auto[3355443200:3489660927]	auto[0]	54	1			T48	1		T53	2		T46	1
auto[3355443200:3489660927]	auto[1]	53	1			T124	1		T53	1		T189	1
auto[3489660928:3623878655]	auto[0]	47	1			T30	1		T40	1		T193	1
auto[3489660928:3623878655]	auto[1]	49	1			T1	1		T56	1		T140	1
auto[3623878656:3758096383]	auto[0]	59	1			T16	1		T52	1		T393	1
auto[3623878656:3758096383]	auto[1]	49	1			T83	1		T25	1		T46	1
auto[3758096384:3892314111]	auto[0]	64	1			T125	1		T186	1		T140	1
auto[3758096384:3892314111]	auto[1]	53	1			T20	1		T142	1		T192	1
auto[3892314112:4026531839]	auto[0]	52	1			T52	1		T53	1		T393	1
auto[3892314112:4026531839]	auto[1]	50	1			T110	1		T52	1		T71	1
auto[4026531840:4160749567]	auto[0]	51	1			T53	1		T393	1		T55	1
auto[4026531840:4160749567]	auto[1]	50	1			T53	1		T140	1		T60	1
auto[4160749568:4294967295]	auto[0]	48	1			T2	1		T56	1		T53	1
auto[4160749568:4294967295]	auto[1]	57	1			T17	1		T141	1		T67	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1585

1

T4

2

T16

1

T17

2

auto[1]

1758

1

T1

5

T2

2

T4

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	94	1			T56	1		T48	1		T79	1
auto[134217728:268435455]	101	1			T125	1		T186	1		T52	1
auto[268435456:402653183]	105	1			T52	1		T53	1		T55	1
auto[402653184:536870911]	105	1			T4	1		T19	1		T53	2
auto[536870912:671088639]	94	1			T19	1		T125	1		T188	1
auto[671088640:805306367]	115	1			T4	1		T139	1		T187	1
auto[805306368:939524095]	108	1			T17	1		T20	1		T110	1
auto[939524096:1073741823]	88	1			T19	1		T139	1		T47	1
auto[1073741824:1207959551]	90	1			T29	1		T56	1		T53	2
auto[1207959552:1342177279]	113	1			T1	1		T4	1		T30	1
auto[1342177280:1476395007]	108	1			T52	2		T53	1		T71	1
auto[1476395008:1610612735]	101	1			T19	1		T56	1		T53	1
auto[1610612736:1744830463]	113	1			T17	2		T125	1		T29	1
auto[1744830464:1879048191]	101	1			T125	1		T48	1		T53	1
auto[1879048192:2013265919]	121	1			T4	1		T16	1		T83	1
auto[2013265920:2147483647]	109	1			T19	1		T79	1		T53	1
auto[2147483648:2281701375]	102	1			T40	1		T59	1		T193	1
auto[2281701376:2415919103]	106	1			T1	1		T56	2		T53	1
auto[2415919104:2550136831]	112	1			T124	1		T125	2		T186	1
auto[2550136832:2684354559]	137	1			T16	1		T125	2		T29	1
auto[2684354560:2818572287]	108	1			T4	1		T17	2		T19	1
auto[2818572288:2952790015]	92	1			T79	1		T232	1		T67	2
auto[2952790016:3087007743]	103	1			T1	1		T16	1		T19	1
auto[3087007744:3221225471]	111	1			T4	1		T52	1		T83	2
auto[3221225472:3355443199]	92	1			T1	1		T2	2		T4	1
auto[3355443200:3489660927]	96	1			T1	1		T16	1		T139	1
auto[3489660928:3623878655]	80	1			T187	1		T393	1		T185	1
auto[3623878656:3758096383]	108	1			T52	1		T56	1		T53	1
auto[3758096384:3892314111]	112	1			T19	1		T110	2		T30	1
auto[3892314112:4026531839]	105	1			T17	1		T110	1		T124	1
auto[4026531840:4160749567]	99	1			T40	1		T45	1		T28	1
auto[4160749568:4294967295]	114	1			T19	2		T124	2		T30	1