Unified Coverage Report :: Group Instance : salt_0

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2938

1

T1

5

T2

2

T4

7

auto[1]

207

1

T4

4

T110

2

T139

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	99	1			T19	1		T125	2		T139	1
auto[134217728:268435455]	82	1			T4	2		T17	1		T19	2
auto[268435456:402653183]	97	1			T4	1		T193	1		T45	1
auto[402653184:536870911]	97	1			T70	1		T87	1		T26	1
auto[536870912:671088639]	104	1			T2	1		T110	1		T53	2
auto[671088640:805306367]	90	1			T4	1		T20	1		T110	1
auto[805306368:939524095]	101	1			T16	1		T30	1		T329	1
auto[939524096:1073741823]	107	1			T124	1		T125	1		T56	1
auto[1073741824:1207959551]	94	1			T4	1		T110	1		T29	1
auto[1207959552:1342177279]	112	1			T2	1		T124	1		T186	1
auto[1342177280:1476395007]	85	1			T186	1		T53	1		T27	1
auto[1476395008:1610612735]	113	1			T16	1		T110	1		T187	1
auto[1610612736:1744830463]	92	1			T4	1		T139	1		T47	1
auto[1744830464:1879048191]	99	1			T124	1		T125	1		T47	1
auto[1879048192:2013265919]	94	1			T140	1		T60	1		T25	1
auto[2013265920:2147483647]	106	1			T1	1		T139	1		T187	1
auto[2147483648:2281701375]	94	1			T139	1		T53	2		T193	1
auto[2281701376:2415919103]	99	1			T17	2		T19	2		T110	1
auto[2415919104:2550136831]	95	1			T1	1		T110	1		T40	1
auto[2550136832:2684354559]	109	1			T16	1		T52	1		T188	1
auto[2684354560:2818572287]	99	1			T19	1		T125	1		T139	1
auto[2818572288:2952790015]	111	1			T4	1		T139	1		T186	1
auto[2952790016:3087007743]	100	1			T1	1		T139	1		T29	1
auto[3087007744:3221225471]	112	1			T1	1		T4	2		T110	1
auto[3221225472:3355443199]	98	1			T19	1		T125	1		T29	1
auto[3355443200:3489660927]	84	1			T4	1		T16	1		T139	1
auto[3489660928:3623878655]	99	1			T124	1		T188	1		T79	1
auto[3623878656:3758096383]	108	1			T193	1		T185	1		T142	1
auto[3758096384:3892314111]	99	1			T17	1		T19	2		T125	1
auto[3892314112:4026531839]	88	1			T4	1		T29	1		T79	1
auto[4026531840:4160749567]	83	1			T45	1		T25	1		T27	1
auto[4160749568:4294967295]	95	1			T1	1		T19	1		T125	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	94	1			T19	1		T125	2		T186	1
auto[0:134217727]	auto[1]	5	1			T139	1		T271	2		T409	1
auto[134217728:268435455]	auto[0]	77	1			T4	2		T17	1		T19	2
auto[134217728:268435455]	auto[1]	5	1			T129	1		T387	1		T350	1
auto[268435456:402653183]	auto[0]	92	1			T193	1		T45	1		T238	2
auto[268435456:402653183]	auto[1]	5	1			T4	1		T229	1		T371	1
auto[402653184:536870911]	auto[0]	94	1			T70	1		T87	1		T26	1
auto[402653184:536870911]	auto[1]	3	1			T142	1		T300	1		T271	1
auto[536870912:671088639]	auto[0]	100	1			T2	1		T110	1		T53	2
auto[536870912:671088639]	auto[1]	4	1			T129	1		T416	1		T417	1
auto[671088640:805306367]	auto[0]	83	1			T4	1		T20	1		T110	1
auto[671088640:805306367]	auto[1]	7	1			T131	2		T270	1		T333	1
auto[805306368:939524095]	auto[0]	94	1			T16	1		T30	1		T329	1
auto[805306368:939524095]	auto[1]	7	1			T141	1		T258	1		T408	1
auto[939524096:1073741823]	auto[0]	101	1			T124	1		T125	1		T56	1
auto[939524096:1073741823]	auto[1]	6	1			T129	2		T131	1		T267	1
auto[1073741824:1207959551]	auto[0]	81	1			T4	1		T110	1		T29	1
auto[1073741824:1207959551]	auto[1]	13	1			T142	1		T129	1		T131	1
auto[1207959552:1342177279]	auto[0]	105	1			T2	1		T124	1		T186	1
auto[1207959552:1342177279]	auto[1]	7	1			T129	1		T408	1		T410	1
auto[1342177280:1476395007]	auto[0]	79	1			T186	1		T53	1		T27	1
auto[1342177280:1476395007]	auto[1]	6	1			T142	1		T129	3		T383	1
auto[1476395008:1610612735]	auto[0]	103	1			T16	1		T110	1		T187	1
auto[1476395008:1610612735]	auto[1]	10	1			T131	1		T267	1		T229	1
auto[1610612736:1744830463]	auto[0]	91	1			T139	1		T47	1		T71	1
auto[1610612736:1744830463]	auto[1]	1	1			T4	1		-	-		-	-
auto[1744830464:1879048191]	auto[0]	93	1			T124	1		T125	1		T47	1
auto[1744830464:1879048191]	auto[1]	6	1			T131	2		T418	1		T404	2
auto[1879048192:2013265919]	auto[0]	80	1			T140	1		T60	1		T25	1
auto[1879048192:2013265919]	auto[1]	14	1			T141	1		T131	2		T418	1
auto[2013265920:2147483647]	auto[0]	99	1			T1	1		T187	1		T140	1
auto[2013265920:2147483647]	auto[1]	7	1			T139	1		T131	1		T267	1
auto[2147483648:2281701375]	auto[0]	90	1			T139	1		T53	2		T193	1
auto[2147483648:2281701375]	auto[1]	4	1			T270	1		T371	2		T419	1
auto[2281701376:2415919103]	auto[0]	96	1			T17	2		T19	2		T110	1
auto[2281701376:2415919103]	auto[1]	3	1			T139	1		T383	1		T411	1
auto[2415919104:2550136831]	auto[0]	84	1			T1	1		T40	1		T53	2
auto[2415919104:2550136831]	auto[1]	11	1			T110	1		T277	1		T229	1
auto[2550136832:2684354559]	auto[0]	106	1			T16	1		T52	1		T188	1
auto[2550136832:2684354559]	auto[1]	3	1			T142	1		T406	1		T420	1
auto[2684354560:2818572287]	auto[0]	87	1			T19	1		T125	1		T139	1
auto[2684354560:2818572287]	auto[1]	12	1			T142	1		T229	1		T270	1
auto[2818572288:2952790015]	auto[0]	102	1			T4	1		T139	1		T186	1
auto[2818572288:2952790015]	auto[1]	9	1			T271	3		T333	1		T351	1
auto[2952790016:3087007743]	auto[0]	95	1			T1	1		T29	1		T30	1
auto[2952790016:3087007743]	auto[1]	5	1			T139	1		T129	1		T229	1
auto[3087007744:3221225471]	auto[0]	104	1			T1	1		T4	1		T79	1
auto[3087007744:3221225471]	auto[1]	8	1			T4	1		T110	1		T79	1
auto[3221225472:3355443199]	auto[0]	92	1			T19	1		T125	1		T29	1
auto[3221225472:3355443199]	auto[1]	6	1			T141	1		T271	1		T421	1
auto[3355443200:3489660927]	auto[0]	79	1			T4	1		T16	1		T30	1
auto[3355443200:3489660927]	auto[1]	5	1			T139	1		T383	1		T421	1
auto[3489660928:3623878655]	auto[0]	92	1			T124	1		T188	1		T79	1
auto[3489660928:3623878655]	auto[1]	7	1			T131	1		T267	1		T383	1
auto[3623878656:3758096383]	auto[0]	99	1			T193	1		T185	1		T142	1
auto[3623878656:3758096383]	auto[1]	9	1			T129	1		T270	1		T418	1
auto[3758096384:3892314111]	auto[0]	95	1			T17	1		T19	2		T125	1
auto[3758096384:3892314111]	auto[1]	4	1			T406	1		T271	1		T408	1
auto[3892314112:4026531839]	auto[0]	80	1			T29	1		T79	1		T71	1
auto[3892314112:4026531839]	auto[1]	8	1			T4	1		T229	1		T271	3
auto[4026531840:4160749567]	auto[0]	78	1			T45	1		T25	1		T27	1
auto[4026531840:4160749567]	auto[1]	5	1			T142	1		T296	1		T350	2
auto[4160749568:4294967295]	auto[0]	93	1			T1	1		T19	1		T125	1
auto[4160749568:4294967295]	auto[1]	2	1			T385	1		T333	1		-	-