Unified Coverage Report :: Group Instance : sealing_sw_binding_7

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1591

1

T2

1

T4

1

T16

2

auto[1]

1751

1

T1

5

T2

1

T4

6

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	118	1			T4	1		T125	1		T53	1
auto[134217728:268435455]	115	1			T124	1		T30	1		T56	1
auto[268435456:402653183]	92	1			T110	1		T56	1		T53	1
auto[402653184:536870911]	92	1			T19	2		T53	1		T193	1
auto[536870912:671088639]	116	1			T17	2		T187	1		T56	1
auto[671088640:805306367]	92	1			T79	1		T26	1		T377	1
auto[805306368:939524095]	87	1			T29	1		T56	1		T188	1
auto[939524096:1073741823]	117	1			T124	1		T125	1		T79	1
auto[1073741824:1207959551]	108	1			T1	1		T30	1		T53	1
auto[1207959552:1342177279]	96	1			T19	1		T48	1		T79	1
auto[1342177280:1476395007]	93	1			T125	1		T56	1		T83	2
auto[1476395008:1610612735]	107	1			T125	2		T30	1		T186	1
auto[1610612736:1744830463]	101	1			T4	1		T52	1		T25	1
auto[1744830464:1879048191]	75	1			T4	1		T186	1		T70	1
auto[1879048192:2013265919]	105	1			T2	1		T19	2		T20	1
auto[2013265920:2147483647]	113	1			T4	1		T110	1		T139	1
auto[2147483648:2281701375]	99	1			T16	1		T52	1		T71	1
auto[2281701376:2415919103]	111	1			T17	1		T110	1		T139	1
auto[2415919104:2550136831]	106	1			T193	1		T46	1		T278	1
auto[2550136832:2684354559]	121	1			T17	2		T19	1		T110	1
auto[2684354560:2818572287]	109	1			T19	1		T139	1		T30	1
auto[2818572288:2952790015]	90	1			T124	1		T393	1		T55	1
auto[2952790016:3087007743]	126	1			T1	1		T4	1		T16	1
auto[3087007744:3221225471]	104	1			T17	1		T19	1		T110	1
auto[3221225472:3355443199]	101	1			T4	1		T19	1		T29	1
auto[3355443200:3489660927]	112	1			T1	1		T124	1		T186	1
auto[3489660928:3623878655]	107	1			T16	1		T124	1		T186	1
auto[3623878656:3758096383]	115	1			T1	1		T52	1		T83	1
auto[3758096384:3892314111]	106	1			T2	1		T124	1		T52	1
auto[3892314112:4026531839]	114	1			T1	1		T125	2		T139	1
auto[4026531840:4160749567]	92	1			T4	1		T16	1		T40	1
auto[4160749568:4294967295]	102	1			T52	1		T188	2		T193	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	58	1			T140	1		T393	1		T25	1
auto[0:134217727]	auto[1]	60	1			T4	1		T125	1		T53	1
auto[134217728:268435455]	auto[0]	48	1			T30	1		T83	1		T53	1
auto[134217728:268435455]	auto[1]	67	1			T124	1		T56	1		T276	1
auto[268435456:402653183]	auto[0]	45	1			T53	1		T25	1		T141	1
auto[268435456:402653183]	auto[1]	47	1			T110	1		T56	1		T412	1
auto[402653184:536870911]	auto[0]	40	1			T53	1		T142	1		T232	1
auto[402653184:536870911]	auto[1]	52	1			T19	2		T193	1		T140	1
auto[536870912:671088639]	auto[0]	62	1			T17	2		T56	1		T59	1
auto[536870912:671088639]	auto[1]	54	1			T187	1		T47	1		T53	1
auto[671088640:805306367]	auto[0]	47	1			T26	1		T377	1		T130	1
auto[671088640:805306367]	auto[1]	45	1			T79	1		T281	1		T212	1
auto[805306368:939524095]	auto[0]	36	1			T56	1		T53	1		T67	2
auto[805306368:939524095]	auto[1]	51	1			T29	1		T188	1		T47	1
auto[939524096:1073741823]	auto[0]	65	1			T124	1		T79	1		T53	1
auto[939524096:1073741823]	auto[1]	52	1			T125	1		T71	1		T234	1
auto[1073741824:1207959551]	auto[0]	49	1			T30	1		T53	1		T63	1
auto[1073741824:1207959551]	auto[1]	59	1			T1	1		T45	2		T280	1
auto[1207959552:1342177279]	auto[0]	40	1			T48	1		T79	1		T393	1
auto[1207959552:1342177279]	auto[1]	56	1			T19	1		T185	1		T234	1
auto[1342177280:1476395007]	auto[0]	43	1			T125	1		T56	1		T83	2
auto[1342177280:1476395007]	auto[1]	50	1			T140	1		T142	1		T377	1
auto[1476395008:1610612735]	auto[0]	43	1			T125	1		T30	1		T140	1
auto[1476395008:1610612735]	auto[1]	64	1			T125	1		T186	1		T45	1
auto[1610612736:1744830463]	auto[0]	40	1			T52	1		T25	1		T130	1
auto[1610612736:1744830463]	auto[1]	61	1			T4	1		T73	1		T63	1
auto[1744830464:1879048191]	auto[0]	35	1			T186	1		T70	1		T87	1
auto[1744830464:1879048191]	auto[1]	40	1			T4	1		T192	1		T256	1
auto[1879048192:2013265919]	auto[0]	48	1			T2	1		T19	1		T20	1
auto[1879048192:2013265919]	auto[1]	57	1			T19	1		T60	1		T26	1
auto[2013265920:2147483647]	auto[0]	55	1			T4	1		T139	1		T53	3
auto[2013265920:2147483647]	auto[1]	58	1			T110	1		T52	1		T45	2
auto[2147483648:2281701375]	auto[0]	55	1			T16	1		T45	1		T73	1
auto[2147483648:2281701375]	auto[1]	44	1			T52	1		T71	1		T70	1
auto[2281701376:2415919103]	auto[0]	52	1			T139	1		T187	1		T186	1
auto[2281701376:2415919103]	auto[1]	59	1			T17	1		T110	1		T56	1
auto[2415919104:2550136831]	auto[0]	44	1			T193	1		T46	1		T278	1
auto[2415919104:2550136831]	auto[1]	62	1			T292	1		T131	1		T297	1
auto[2550136832:2684354559]	auto[0]	46	1			T19	1		T56	1		T53	1
auto[2550136832:2684354559]	auto[1]	75	1			T17	2		T110	1		T125	1
auto[2684354560:2818572287]	auto[0]	59	1			T30	1		T48	1		T71	1
auto[2684354560:2818572287]	auto[1]	50	1			T19	1		T139	1		T60	1
auto[2818572288:2952790015]	auto[0]	46	1			T55	1		T87	1		T25	1
auto[2818572288:2952790015]	auto[1]	44	1			T124	1		T393	1		T329	1
auto[2952790016:3087007743]	auto[0]	54	1			T46	1		T88	1		T242	1
auto[2952790016:3087007743]	auto[1]	72	1			T1	1		T4	1		T16	1
auto[3087007744:3221225471]	auto[0]	51	1			T19	1		T52	1		T83	1
auto[3087007744:3221225471]	auto[1]	53	1			T17	1		T110	1		T193	1
auto[3221225472:3355443199]	auto[0]	45	1			T27	1		T72	1		T61	1
auto[3221225472:3355443199]	auto[1]	56	1			T4	1		T19	1		T29	1
auto[3355443200:3489660927]	auto[0]	58	1			T124	1		T186	1		T52	1
auto[3355443200:3489660927]	auto[1]	54	1			T1	1		T56	1		T185	1
auto[3489660928:3623878655]	auto[0]	66	1			T124	1		T186	1		T53	1
auto[3489660928:3623878655]	auto[1]	41	1			T16	1		T193	1		T54	1
auto[3623878656:3758096383]	auto[0]	59	1			T52	1		T83	1		T25	1
auto[3623878656:3758096383]	auto[1]	56	1			T1	1		T53	1		T45	1
auto[3758096384:3892314111]	auto[0]	48	1			T40	1		T53	1		T185	1
auto[3758096384:3892314111]	auto[1]	58	1			T2	1		T124	1		T52	1
auto[3892314112:4026531839]	auto[0]	55	1			T29	1		T79	2		T53	1
auto[3892314112:4026531839]	auto[1]	59	1			T1	1		T125	2		T139	1
auto[4026531840:4160749567]	auto[0]	51	1			T16	1		T40	1		T83	1
auto[4026531840:4160749567]	auto[1]	41	1			T4	1		T60	1		T234	1
auto[4160749568:4294967295]	auto[0]	48	1			T86	1		T88	1		T144	1
auto[4160749568:4294967295]	auto[1]	54	1			T52	1		T188	2		T193	1