Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6917

1

T1

8

T2

4

T4

11

auto[1]

253

1

T4

3

T110

6

T139

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	2865	1			T1	2		T2	2		T4	4
auto[134217728:268435455]	167	1			T19	2		T110	1		T139	1
auto[268435456:402653183]	157	1			T1	1		T393	1		T45	1
auto[402653184:536870911]	170	1			T110	2		T186	2		T79	1
auto[536870912:671088639]	168	1			T16	1		T17	1		T110	1
auto[671088640:805306367]	143	1			T1	1		T2	1		T17	1
auto[805306368:939524095]	133	1			T124	1		T139	1		T47	1
auto[939524096:1073741823]	132	1			T4	1		T110	1		T70	1
auto[1073741824:1207959551]	132	1			T124	1		T29	1		T56	1
auto[1207959552:1342177279]	135	1			T4	1		T110	1		T139	1
auto[1342177280:1476395007]	126	1			T1	1		T19	2		T110	1
auto[1476395008:1610612735]	123	1			T4	1		T110	1		T60	2
auto[1610612736:1744830463]	143	1			T2	1		T4	1		T19	1
auto[1744830464:1879048191]	141	1			T4	1		T19	1		T20	1
auto[1879048192:2013265919]	126	1			T110	1		T125	1		T30	1
auto[2013265920:2147483647]	130	1			T19	1		T30	1		T188	1
auto[2147483648:2281701375]	118	1			T1	2		T19	1		T79	1
auto[2281701376:2415919103]	155	1			T4	1		T29	1		T53	2
auto[2415919104:2550136831]	140	1			T110	1		T125	1		T29	1
auto[2550136832:2684354559]	151	1			T17	1		T53	1		T70	1
auto[2684354560:2818572287]	137	1			T1	1		T16	1		T124	1
auto[2818572288:2952790015]	118	1			T186	1		T25	1		T26	1
auto[2952790016:3087007743]	141	1			T4	1		T17	1		T19	1
auto[3087007744:3221225471]	143	1			T16	1		T139	1		T29	1
auto[3221225472:3355443199]	128	1			T124	1		T125	1		T53	1
auto[3355443200:3489660927]	145	1			T124	1		T29	1		T52	1
auto[3489660928:3623878655]	144	1			T139	1		T29	1		T52	1
auto[3623878656:3758096383]	114	1			T4	1		T139	1		T30	1
auto[3758096384:3892314111]	126	1			T19	1		T110	1		T52	1
auto[3892314112:4026531839]	131	1			T4	1		T125	1		T139	1
auto[4026531840:4160749567]	156	1			T4	1		T16	1		T17	1
auto[4160749568:4294967295]	132	1			T110	2		T186	1		T188	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	2857	1			T1	2		T2	2		T4	4
auto[0:134217727]	auto[1]	8	1			T385	1		T371	1		T271	1
auto[134217728:268435455]	auto[0]	158	1			T19	2		T47	1		T40	1
auto[134217728:268435455]	auto[1]	9	1			T110	1		T139	1		T141	1
auto[268435456:402653183]	auto[0]	147	1			T1	1		T393	1		T45	1
auto[268435456:402653183]	auto[1]	10	1			T142	2		T129	1		T277	1
auto[402653184:536870911]	auto[0]	162	1			T110	1		T186	2		T79	1
auto[402653184:536870911]	auto[1]	8	1			T110	1		T129	1		T406	1
auto[536870912:671088639]	auto[0]	162	1			T16	1		T17	1		T110	1
auto[536870912:671088639]	auto[1]	6	1			T129	1		T300	1		T333	1
auto[671088640:805306367]	auto[0]	139	1			T1	1		T2	1		T17	1
auto[671088640:805306367]	auto[1]	4	1			T277	1		T385	1		T411	1
auto[805306368:939524095]	auto[0]	125	1			T124	1		T139	1		T47	1
auto[805306368:939524095]	auto[1]	8	1			T142	1		T129	1		T131	1
auto[939524096:1073741823]	auto[0]	122	1			T4	1		T70	1		T189	1
auto[939524096:1073741823]	auto[1]	10	1			T110	1		T131	2		T267	1
auto[1073741824:1207959551]	auto[0]	123	1			T124	1		T29	1		T56	1
auto[1073741824:1207959551]	auto[1]	9	1			T142	1		T131	1		T296	1
auto[1207959552:1342177279]	auto[0]	130	1			T4	1		T110	1		T139	1
auto[1207959552:1342177279]	auto[1]	5	1			T141	1		T131	1		T296	1
auto[1342177280:1476395007]	auto[0]	118	1			T1	1		T19	2		T110	1
auto[1342177280:1476395007]	auto[1]	8	1			T79	1		T129	1		T371	1
auto[1476395008:1610612735]	auto[0]	113	1			T60	2		T45	2		T276	1
auto[1476395008:1610612735]	auto[1]	10	1			T4	1		T110	1		T131	1
auto[1610612736:1744830463]	auto[0]	140	1			T2	1		T4	1		T19	1
auto[1610612736:1744830463]	auto[1]	3	1			T388	1		T410	1		T333	1
auto[1744830464:1879048191]	auto[0]	132	1			T4	1		T19	1		T20	1
auto[1744830464:1879048191]	auto[1]	9	1			T139	1		T142	2		T270	1
auto[1879048192:2013265919]	auto[0]	115	1			T110	1		T125	1		T30	1
auto[1879048192:2013265919]	auto[1]	11	1			T79	1		T129	1		T229	1
auto[2013265920:2147483647]	auto[0]	124	1			T19	1		T30	1		T188	1
auto[2013265920:2147483647]	auto[1]	6	1			T142	1		T271	2		T413	1
auto[2147483648:2281701375]	auto[0]	113	1			T1	2		T19	1		T79	1
auto[2147483648:2281701375]	auto[1]	5	1			T270	1		T271	2		T414	1
auto[2281701376:2415919103]	auto[0]	147	1			T29	1		T53	2		T71	1
auto[2281701376:2415919103]	auto[1]	8	1			T4	1		T142	1		T270	1
auto[2415919104:2550136831]	auto[0]	127	1			T125	1		T29	1		T186	1
auto[2415919104:2550136831]	auto[1]	13	1			T110	1		T142	1		T129	1
auto[2550136832:2684354559]	auto[0]	143	1			T17	1		T53	1		T70	1
auto[2550136832:2684354559]	auto[1]	8	1			T277	1		T229	1		T371	2
auto[2684354560:2818572287]	auto[0]	133	1			T1	1		T16	1		T124	1
auto[2684354560:2818572287]	auto[1]	4	1			T79	1		T142	1		T131	1
auto[2818572288:2952790015]	auto[0]	108	1			T186	1		T25	1		T26	1
auto[2818572288:2952790015]	auto[1]	10	1			T129	1		T267	1		T270	1
auto[2952790016:3087007743]	auto[0]	139	1			T4	1		T17	1		T19	1
auto[2952790016:3087007743]	auto[1]	2	1			T267	1		T271	1		-	-
auto[3087007744:3221225471]	auto[0]	137	1			T16	1		T29	1		T193	3
auto[3087007744:3221225471]	auto[1]	6	1			T139	1		T142	1		T267	1
auto[3221225472:3355443199]	auto[0]	123	1			T124	1		T125	1		T53	1
auto[3221225472:3355443199]	auto[1]	5	1			T267	1		T229	1		T383	1
auto[3355443200:3489660927]	auto[0]	133	1			T124	1		T29	1		T52	1
auto[3355443200:3489660927]	auto[1]	12	1			T131	1		T277	1		T267	1
auto[3489660928:3623878655]	auto[0]	135	1			T139	1		T29	1		T52	1
auto[3489660928:3623878655]	auto[1]	9	1			T142	1		T267	1		T230	1
auto[3623878656:3758096383]	auto[0]	107	1			T4	1		T139	1		T30	1
auto[3623878656:3758096383]	auto[1]	7	1			T388	1		T258	1		T387	1
auto[3758096384:3892314111]	auto[0]	119	1			T19	1		T110	1		T52	1
auto[3758096384:3892314111]	auto[1]	7	1			T131	1		T296	1		T230	1
auto[3892314112:4026531839]	auto[0]	120	1			T125	1		T139	1		T29	1
auto[3892314112:4026531839]	auto[1]	11	1			T4	1		T131	1		T267	1
auto[4026531840:4160749567]	auto[0]	143	1			T4	1		T16	1		T17	1
auto[4026531840:4160749567]	auto[1]	13	1			T142	2		T129	1		T131	1
auto[4160749568:4294967295]	auto[0]	123	1			T110	1		T186	1		T188	1
auto[4160749568:4294967295]	auto[1]	9	1			T110	1		T142	1		T131	2