Unified Coverage Report :: Group Instance : max_creator_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4620

1

T1

8

T2

2

T4

8

auto[1]

2064

1

T1

2

T2

2

T4

6

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	242	1			T1	2		T19	2		T124	2
auto[134217728:268435455]	170	1			T52	2		T40	2		T87	2
auto[268435456:402653183]	234	1			T4	2		T17	2		T52	2
auto[402653184:536870911]	204	1			T125	2		T52	4		T47	2
auto[536870912:671088639]	234	1			T4	2		T110	2		T124	2
auto[671088640:805306367]	220	1			T17	4		T19	2		T125	2
auto[805306368:939524095]	244	1			T17	2		T139	2		T29	2
auto[939524096:1073741823]	214	1			T19	2		T110	2		T125	2
auto[1073741824:1207959551]	182	1			T25	4		T27	2		T28	2
auto[1207959552:1342177279]	202	1			T30	2		T83	2		T27	4
auto[1342177280:1476395007]	216	1			T16	2		T53	2		T193	2
auto[1476395008:1610612735]	170	1			T187	2		T56	2		T83	2
auto[1610612736:1744830463]	200	1			T110	2		T125	2		T30	2
auto[1744830464:1879048191]	166	1			T19	2		T186	2		T53	2
auto[1879048192:2013265919]	196	1			T19	2		T56	4		T53	2
auto[2013265920:2147483647]	194	1			T4	2		T19	2		T124	2
auto[2147483648:2281701375]	210	1			T125	2		T56	2		T188	2
auto[2281701376:2415919103]	222	1			T16	2		T48	2		T53	2
auto[2415919104:2550136831]	256	1			T19	2		T29	6		T48	2
auto[2550136832:2684354559]	224	1			T4	2		T17	2		T19	2
auto[2684354560:2818572287]	212	1			T16	2		T110	2		T124	2
auto[2818572288:2952790015]	214	1			T19	2		T71	2		T60	2
auto[2952790016:3087007743]	198	1			T19	2		T83	2		T53	2
auto[3087007744:3221225471]	208	1			T1	2		T2	2		T20	2
auto[3221225472:3355443199]	226	1			T2	2		T139	2		T29	2
auto[3355443200:3489660927]	212	1			T83	2		T53	2		T71	2
auto[3489660928:3623878655]	180	1			T1	2		T56	4		T53	4
auto[3623878656:3758096383]	186	1			T30	2		T52	2		T53	2
auto[3758096384:3892314111]	224	1			T4	2		T16	2		T17	2
auto[3892314112:4026531839]	216	1			T1	2		T4	2		T186	2
auto[4026531840:4160749567]	214	1			T53	2		T70	2		T140	2
auto[4160749568:4294967295]	194	1			T1	2		T4	2		T124	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	178	1			T1	2		T19	2		T124	2
auto[0:134217727]	auto[1]	64	1			T55	2		T295	2		T97	2
auto[134217728:268435455]	auto[0]	118	1			T52	2		T40	2		T87	2
auto[134217728:268435455]	auto[1]	52	1			T58	2		T63	2		T64	2
auto[268435456:402653183]	auto[0]	166	1			T4	2		T17	2		T52	2
auto[268435456:402653183]	auto[1]	68	1			T86	2		T31	2		T278	2
auto[402653184:536870911]	auto[0]	142	1			T125	2		T52	4		T47	2
auto[402653184:536870911]	auto[1]	62	1			T140	2		T192	2		T92	2
auto[536870912:671088639]	auto[0]	164	1			T4	2		T110	2		T124	2
auto[536870912:671088639]	auto[1]	70	1			T188	2		T60	2		T141	2
auto[671088640:805306367]	auto[0]	146	1			T17	4		T19	2		T125	2
auto[671088640:805306367]	auto[1]	74	1			T139	2		T30	2		T40	2
auto[805306368:939524095]	auto[0]	168	1			T17	2		T29	2		T79	2
auto[805306368:939524095]	auto[1]	76	1			T139	2		T79	2		T53	2
auto[939524096:1073741823]	auto[0]	140	1			T19	2		T110	2		T125	2
auto[939524096:1073741823]	auto[1]	74	1			T197	2		T242	2		T130	2
auto[1073741824:1207959551]	auto[0]	120	1			T25	2		T49	2		T73	2
auto[1073741824:1207959551]	auto[1]	62	1			T25	2		T27	2		T28	2
auto[1207959552:1342177279]	auto[0]	140	1			T30	2		T83	2		T27	2
auto[1207959552:1342177279]	auto[1]	62	1			T27	2		T280	2		T22	2
auto[1342177280:1476395007]	auto[0]	164	1			T16	2		T53	2		T193	2
auto[1342177280:1476395007]	auto[1]	52	1			T234	2		T58	2		T33	2
auto[1476395008:1610612735]	auto[0]	120	1			T187	2		T83	2		T140	2
auto[1476395008:1610612735]	auto[1]	50	1			T56	2		T70	2		T28	2
auto[1610612736:1744830463]	auto[0]	138	1			T125	2		T30	2		T53	2
auto[1610612736:1744830463]	auto[1]	62	1			T110	2		T185	2		T192	2
auto[1744830464:1879048191]	auto[0]	108	1			T186	2		T53	2		T26	2
auto[1744830464:1879048191]	auto[1]	58	1			T19	2		T25	2		T278	2
auto[1879048192:2013265919]	auto[0]	128	1			T56	4		T189	2		T49	2
auto[1879048192:2013265919]	auto[1]	68	1			T19	2		T53	2		T60	2
auto[2013265920:2147483647]	auto[0]	144	1			T4	2		T19	2		T187	2
auto[2013265920:2147483647]	auto[1]	50	1			T124	2		T64	2		T330	2
auto[2147483648:2281701375]	auto[0]	138	1			T125	2		T60	2		T55	2
auto[2147483648:2281701375]	auto[1]	72	1			T56	2		T188	2		T40	2
auto[2281701376:2415919103]	auto[0]	158	1			T16	2		T48	2		T53	2
auto[2281701376:2415919103]	auto[1]	64	1			T192	2		T144	2		T280	2
auto[2415919104:2550136831]	auto[0]	184	1			T19	2		T29	6		T48	2
auto[2415919104:2550136831]	auto[1]	72	1			T140	2		T189	2		T256	2
auto[2550136832:2684354559]	auto[0]	152	1			T110	2		T52	2		T56	2
auto[2550136832:2684354559]	auto[1]	72	1			T4	2		T17	2		T19	2
auto[2684354560:2818572287]	auto[0]	142	1			T16	2		T110	2		T124	2
auto[2684354560:2818572287]	auto[1]	70	1			T53	2		T58	2		T238	2
auto[2818572288:2952790015]	auto[0]	132	1			T19	2		T71	2		T393	2
auto[2818572288:2952790015]	auto[1]	82	1			T60	2		T412	2		T232	2
auto[2952790016:3087007743]	auto[0]	146	1			T19	2		T83	2		T53	2
auto[2952790016:3087007743]	auto[1]	52	1			T376	2		T89	2		T67	2
auto[3087007744:3221225471]	auto[0]	150	1			T1	2		T2	2		T52	2
auto[3087007744:3221225471]	auto[1]	58	1			T20	2		T124	2		T139	2
auto[3221225472:3355443199]	auto[0]	162	1			T139	2		T29	2		T186	2
auto[3221225472:3355443199]	auto[1]	64	1			T2	2		T71	4		T25	2
auto[3355443200:3489660927]	auto[0]	156	1			T83	2		T329	2		T45	2
auto[3355443200:3489660927]	auto[1]	56	1			T53	2		T71	2		T70	2
auto[3489660928:3623878655]	auto[0]	128	1			T56	2		T53	2		T193	2
auto[3489660928:3623878655]	auto[1]	52	1			T1	2		T56	2		T53	2
auto[3623878656:3758096383]	auto[0]	132	1			T30	2		T52	2		T86	2
auto[3623878656:3758096383]	auto[1]	54	1			T53	2		T232	2		T278	2
auto[3758096384:3892314111]	auto[0]	146	1			T4	2		T16	2		T17	2
auto[3758096384:3892314111]	auto[1]	78	1			T186	2		T52	2		T71	2
auto[3892314112:4026531839]	auto[0]	140	1			T1	2		T186	2		T52	2
auto[3892314112:4026531839]	auto[1]	76	1			T4	2		T188	2		T393	2
auto[4026531840:4160749567]	auto[0]	140	1			T53	2		T70	2		T140	2
auto[4026531840:4160749567]	auto[1]	74	1			T28	2		T234	2		T376	2
auto[4160749568:4294967295]	auto[0]	130	1			T1	2		T124	2		T56	4
auto[4160749568:4294967295]	auto[1]	64	1			T4	2		T139	2		T193	2