Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.80 99.07 98.03 98.32 100.00 99.11 98.41 91.66


Total test records in report: 1079
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T1009 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.638136725 May 02 12:46:43 PM PDT 24 May 02 12:46:47 PM PDT 24 16922947 ps
T168 /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.2500062035 May 02 12:46:46 PM PDT 24 May 02 12:46:52 PM PDT 24 68275238 ps
T1010 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.254747204 May 02 12:46:36 PM PDT 24 May 02 12:46:40 PM PDT 24 114537630 ps
T1011 /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.1826772546 May 02 12:46:52 PM PDT 24 May 02 12:46:56 PM PDT 24 80352821 ps
T1012 /workspace/coverage/cover_reg_top/26.keymgr_intr_test.216720053 May 02 12:47:15 PM PDT 24 May 02 12:47:20 PM PDT 24 13257390 ps
T1013 /workspace/coverage/cover_reg_top/13.keymgr_intr_test.1465750341 May 02 12:46:52 PM PDT 24 May 02 12:46:57 PM PDT 24 18591658 ps
T1014 /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.85915354 May 02 12:46:22 PM PDT 24 May 02 12:46:25 PM PDT 24 21040284 ps
T1015 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.253441250 May 02 12:46:31 PM PDT 24 May 02 12:46:43 PM PDT 24 483478884 ps
T153 /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.3627955504 May 02 12:46:22 PM PDT 24 May 02 12:46:35 PM PDT 24 1861217172 ps
T1016 /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1131673173 May 02 12:46:50 PM PDT 24 May 02 12:46:55 PM PDT 24 19604019 ps
T1017 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.965543291 May 02 12:46:35 PM PDT 24 May 02 12:46:43 PM PDT 24 202084853 ps
T156 /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.696385624 May 02 12:46:25 PM PDT 24 May 02 12:46:45 PM PDT 24 3045020324 ps
T1018 /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.446468808 May 02 12:46:41 PM PDT 24 May 02 12:46:45 PM PDT 24 65411213 ps
T1019 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.1317878665 May 02 12:46:54 PM PDT 24 May 02 12:47:04 PM PDT 24 419307906 ps
T1020 /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.496711398 May 02 12:46:31 PM PDT 24 May 02 12:46:37 PM PDT 24 264149745 ps
T1021 /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.1535744830 May 02 12:47:12 PM PDT 24 May 02 12:47:17 PM PDT 24 54125407 ps
T1022 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3665185783 May 02 12:46:52 PM PDT 24 May 02 12:46:58 PM PDT 24 316173014 ps
T1023 /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.186565228 May 02 12:46:51 PM PDT 24 May 02 12:46:56 PM PDT 24 54802924 ps
T1024 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.83729765 May 02 12:46:48 PM PDT 24 May 02 12:47:01 PM PDT 24 2386878600 ps
T1025 /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.1522311402 May 02 12:46:26 PM PDT 24 May 02 12:46:31 PM PDT 24 107404505 ps
T1026 /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.4162036983 May 02 12:46:40 PM PDT 24 May 02 12:46:44 PM PDT 24 20776196 ps
T1027 /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1688324870 May 02 12:46:46 PM PDT 24 May 02 12:46:49 PM PDT 24 28990622 ps
T1028 /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.1543437314 May 02 12:46:17 PM PDT 24 May 02 12:46:22 PM PDT 24 203690773 ps
T1029 /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1569962884 May 02 12:46:50 PM PDT 24 May 02 12:46:55 PM PDT 24 61332488 ps
T1030 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.565546522 May 02 12:46:53 PM PDT 24 May 02 12:47:03 PM PDT 24 609592081 ps
T1031 /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.2092608235 May 02 12:46:55 PM PDT 24 May 02 12:47:03 PM PDT 24 209925702 ps
T1032 /workspace/coverage/cover_reg_top/40.keymgr_intr_test.141020668 May 02 12:46:52 PM PDT 24 May 02 12:46:56 PM PDT 24 9785849 ps
T1033 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.170858322 May 02 12:46:37 PM PDT 24 May 02 12:46:41 PM PDT 24 33895951 ps
T151 /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1917113082 May 02 12:46:55 PM PDT 24 May 02 12:47:08 PM PDT 24 808322257 ps
T1034 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.4062989509 May 02 12:46:38 PM PDT 24 May 02 12:46:44 PM PDT 24 57305651 ps
T1035 /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.2716283955 May 02 12:47:07 PM PDT 24 May 02 12:47:11 PM PDT 24 74387337 ps
T1036 /workspace/coverage/cover_reg_top/12.keymgr_intr_test.3773651606 May 02 12:46:30 PM PDT 24 May 02 12:46:34 PM PDT 24 104221927 ps
T1037 /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.1082701886 May 02 12:46:25 PM PDT 24 May 02 12:46:29 PM PDT 24 144590826 ps
T1038 /workspace/coverage/cover_reg_top/27.keymgr_intr_test.3565892553 May 02 12:46:53 PM PDT 24 May 02 12:46:58 PM PDT 24 12202310 ps
T158 /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.2189653880 May 02 12:46:52 PM PDT 24 May 02 12:47:43 PM PDT 24 1847740691 ps
T1039 /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.2028944456 May 02 12:46:53 PM PDT 24 May 02 12:47:02 PM PDT 24 240620408 ps
T1040 /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.3428139762 May 02 12:46:36 PM PDT 24 May 02 12:46:40 PM PDT 24 56020067 ps
T1041 /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.3826868950 May 02 12:46:48 PM PDT 24 May 02 12:46:51 PM PDT 24 113860595 ps
T1042 /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.2961034677 May 02 12:46:24 PM PDT 24 May 02 12:46:30 PM PDT 24 126746005 ps
T1043 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.4134793671 May 02 12:46:46 PM PDT 24 May 02 12:46:49 PM PDT 24 53470909 ps
T1044 /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.4010947934 May 02 12:46:51 PM PDT 24 May 02 12:47:02 PM PDT 24 183422342 ps
T1045 /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.1122407625 May 02 12:47:25 PM PDT 24 May 02 12:47:33 PM PDT 24 186535053 ps
T1046 /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.2218117141 May 02 12:46:31 PM PDT 24 May 02 12:46:38 PM PDT 24 416406667 ps
T1047 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2821391393 May 02 12:46:50 PM PDT 24 May 02 12:47:01 PM PDT 24 844222073 ps
T1048 /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.11716361 May 02 12:46:52 PM PDT 24 May 02 12:46:57 PM PDT 24 199891484 ps
T1049 /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.180123650 May 02 12:46:49 PM PDT 24 May 02 12:46:54 PM PDT 24 82793653 ps
T1050 /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.2965572470 May 02 12:46:30 PM PDT 24 May 02 12:46:38 PM PDT 24 662264993 ps
T1051 /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2907617748 May 02 12:46:48 PM PDT 24 May 02 12:46:51 PM PDT 24 97773582 ps
T1052 /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.705360114 May 02 12:46:42 PM PDT 24 May 02 12:46:48 PM PDT 24 236729898 ps
T1053 /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.3929761580 May 02 12:46:22 PM PDT 24 May 02 12:46:37 PM PDT 24 436999588 ps
T161 /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.3302505030 May 02 12:46:46 PM PDT 24 May 02 12:47:01 PM PDT 24 532567197 ps
T157 /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.785120384 May 02 12:46:49 PM PDT 24 May 02 12:46:56 PM PDT 24 246004951 ps
T1054 /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.2207171334 May 02 12:46:38 PM PDT 24 May 02 12:46:42 PM PDT 24 13246411 ps
T1055 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1673160551 May 02 12:46:49 PM PDT 24 May 02 12:46:54 PM PDT 24 128435542 ps
T1056 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3664119527 May 02 12:46:35 PM PDT 24 May 02 12:46:39 PM PDT 24 174025103 ps
T1057 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.2614167580 May 02 12:46:50 PM PDT 24 May 02 12:46:55 PM PDT 24 246851859 ps
T1058 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.2171399165 May 02 12:46:41 PM PDT 24 May 02 12:46:59 PM PDT 24 421527861 ps
T1059 /workspace/coverage/cover_reg_top/45.keymgr_intr_test.1534683649 May 02 12:46:45 PM PDT 24 May 02 12:46:48 PM PDT 24 33375161 ps
T1060 /workspace/coverage/cover_reg_top/43.keymgr_intr_test.2419932652 May 02 12:46:58 PM PDT 24 May 02 12:47:02 PM PDT 24 24759271 ps
T1061 /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.1443505860 May 02 12:46:24 PM PDT 24 May 02 12:46:31 PM PDT 24 583896340 ps
T1062 /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.1116880969 May 02 12:46:38 PM PDT 24 May 02 12:46:43 PM PDT 24 212226392 ps
T1063 /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.479050784 May 02 12:46:38 PM PDT 24 May 02 12:46:43 PM PDT 24 122744004 ps
T1064 /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.277660956 May 02 12:46:36 PM PDT 24 May 02 12:46:41 PM PDT 24 229496830 ps
T1065 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.860102837 May 02 12:46:24 PM PDT 24 May 02 12:46:29 PM PDT 24 326782876 ps
T154 /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.120844882 May 02 12:46:32 PM PDT 24 May 02 12:46:40 PM PDT 24 196992418 ps
T1066 /workspace/coverage/cover_reg_top/6.keymgr_intr_test.1183923433 May 02 12:46:25 PM PDT 24 May 02 12:46:27 PM PDT 24 32078234 ps
T1067 /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.1823102110 May 02 12:46:31 PM PDT 24 May 02 12:46:37 PM PDT 24 468291094 ps
T1068 /workspace/coverage/cover_reg_top/30.keymgr_intr_test.185703125 May 02 12:46:47 PM PDT 24 May 02 12:46:50 PM PDT 24 15475743 ps
T1069 /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.2433190270 May 02 12:46:40 PM PDT 24 May 02 12:46:47 PM PDT 24 49235186 ps
T1070 /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2379438054 May 02 12:46:47 PM PDT 24 May 02 12:47:01 PM PDT 24 482474361 ps
T1071 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.2578437022 May 02 12:46:21 PM PDT 24 May 02 12:46:31 PM PDT 24 418343779 ps
T1072 /workspace/coverage/cover_reg_top/42.keymgr_intr_test.3207156626 May 02 12:46:52 PM PDT 24 May 02 12:46:56 PM PDT 24 27930053 ps
T1073 /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.3115713724 May 02 12:46:22 PM PDT 24 May 02 12:46:25 PM PDT 24 25754776 ps
T1074 /workspace/coverage/cover_reg_top/0.keymgr_intr_test.241915817 May 02 12:46:43 PM PDT 24 May 02 12:46:46 PM PDT 24 84342920 ps
T1075 /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.3932040551 May 02 12:46:24 PM PDT 24 May 02 12:46:30 PM PDT 24 201515752 ps
T1076 /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.2860739619 May 02 12:46:29 PM PDT 24 May 02 12:46:39 PM PDT 24 1109364419 ps
T1077 /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3198400611 May 02 12:46:27 PM PDT 24 May 02 12:46:30 PM PDT 24 94300627 ps
T1078 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.4212036778 May 02 12:46:43 PM PDT 24 May 02 12:46:55 PM PDT 24 509455853 ps
T1079 /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.3395785815 May 02 12:46:29 PM PDT 24 May 02 12:46:33 PM PDT 24 193220006 ps

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.987383207
Short name T19
Test name
Test status
Simulation time 370536993 ps
CPU time 9.13 seconds
Started May 02 12:49:20 PM PDT 24
Finished May 02 12:49:32 PM PDT 24
Peak memory 222328 kb
Host smart-f41ab84f-c5f1-4f91-bc15-0f1ada0a6b63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987383207 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.987383207
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.2067077082
Short name T67
Test name
Test status
Simulation time 8191258116 ps
CPU time 58.31 seconds
Started May 02 12:47:32 PM PDT 24
Finished May 02 12:48:32 PM PDT 24
Peak memory 221992 kb
Host smart-c7f7d5d7-7c14-47d2-8ef5-f9c0fdcd5772
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067077082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.2067077082
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.3309097663
Short name T1
Test name
Test status
Simulation time 598734484 ps
CPU time 4.11 seconds
Started May 02 12:48:03 PM PDT 24
Finished May 02 12:48:12 PM PDT 24
Peak memory 220584 kb
Host smart-387a4e93-c400-42b8-9693-e4afcf7c35c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309097663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.3309097663
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.2357991071
Short name T53
Test name
Test status
Simulation time 8285634832 ps
CPU time 253.18 seconds
Started May 02 12:48:13 PM PDT 24
Finished May 02 12:52:30 PM PDT 24
Peak memory 222220 kb
Host smart-0e32f24e-4a8c-4cd0-8420-46220725ac5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357991071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.2357991071
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.4124287995
Short name T11
Test name
Test status
Simulation time 337323574 ps
CPU time 11.28 seconds
Started May 02 12:47:27 PM PDT 24
Finished May 02 12:47:41 PM PDT 24
Peak memory 234036 kb
Host smart-c7944566-dc6c-4f99-84df-49f3a61b7ffa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124287995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.4124287995
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.1777036992
Short name T130
Test name
Test status
Simulation time 970126680 ps
CPU time 38.41 seconds
Started May 02 12:49:09 PM PDT 24
Finished May 02 12:49:53 PM PDT 24
Peak memory 216696 kb
Host smart-c6950a03-0459-4f1e-8365-d619ecf32f66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777036992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.1777036992
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.3615685362
Short name T63
Test name
Test status
Simulation time 800894925 ps
CPU time 26.3 seconds
Started May 02 12:47:41 PM PDT 24
Finished May 02 12:48:10 PM PDT 24
Peak memory 222616 kb
Host smart-c9ea36cf-5210-48c9-8257-5c8a257806fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615685362 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.3615685362
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.559710737
Short name T142
Test name
Test status
Simulation time 3099816445 ps
CPU time 77.89 seconds
Started May 02 12:48:03 PM PDT 24
Finished May 02 12:49:25 PM PDT 24
Peak memory 215688 kb
Host smart-e83b3bb2-42d7-44a6-aa75-9f1c2e04c930
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=559710737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.559710737
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.1968029678
Short name T111
Test name
Test status
Simulation time 336031611 ps
CPU time 5.12 seconds
Started May 02 12:46:31 PM PDT 24
Finished May 02 12:46:40 PM PDT 24
Peak memory 214604 kb
Host smart-cb111a99-1973-4ef0-b725-1dc0db90f2a8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968029678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.1968029678
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.3715775078
Short name T27
Test name
Test status
Simulation time 97731857 ps
CPU time 5.08 seconds
Started May 02 12:49:04 PM PDT 24
Finished May 02 12:49:14 PM PDT 24
Peak memory 222184 kb
Host smart-d69ec126-d001-4c0b-a77b-3ef5582dcc75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715775078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.3715775078
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.858685922
Short name T51
Test name
Test status
Simulation time 40859533502 ps
CPU time 241.58 seconds
Started May 02 12:49:05 PM PDT 24
Finished May 02 12:53:12 PM PDT 24
Peak memory 218144 kb
Host smart-66763494-b0f6-4b53-969c-1be0da514c77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858685922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.858685922
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.4021777235
Short name T110
Test name
Test status
Simulation time 502194882 ps
CPU time 7.43 seconds
Started May 02 12:48:13 PM PDT 24
Finished May 02 12:48:24 PM PDT 24
Peak memory 214900 kb
Host smart-be393887-a3a1-46ac-968f-ead8da2d55c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4021777235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.4021777235
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.2387033923
Short name T836
Test name
Test status
Simulation time 49298697 ps
CPU time 1.95 seconds
Started May 02 12:49:22 PM PDT 24
Finished May 02 12:49:26 PM PDT 24
Peak memory 218888 kb
Host smart-7b64a592-627e-40fd-9fcb-3188eb41db6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387033923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.2387033923
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.1528071709
Short name T45
Test name
Test status
Simulation time 306520432 ps
CPU time 12.19 seconds
Started May 02 12:48:10 PM PDT 24
Finished May 02 12:48:25 PM PDT 24
Peak memory 216452 kb
Host smart-fef167d9-957d-40c9-9a31-2ad7bf3ba44a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528071709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.1528071709
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.1932969138
Short name T333
Test name
Test status
Simulation time 264323667 ps
CPU time 14.91 seconds
Started May 02 12:49:02 PM PDT 24
Finished May 02 12:49:22 PM PDT 24
Peak memory 215152 kb
Host smart-63ef0332-24b5-46f1-bd63-2930da67c686
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1932969138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.1932969138
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.1357274937
Short name T25
Test name
Test status
Simulation time 531927228 ps
CPU time 6.47 seconds
Started May 02 12:47:51 PM PDT 24
Finished May 02 12:48:01 PM PDT 24
Peak memory 221748 kb
Host smart-3253011b-14ef-43e4-a23c-d583eadfb013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357274937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.1357274937
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.943661102
Short name T131
Test name
Test status
Simulation time 1052376563 ps
CPU time 13.67 seconds
Started May 02 12:49:02 PM PDT 24
Finished May 02 12:49:21 PM PDT 24
Peak memory 214020 kb
Host smart-92eac99d-2026-438c-afc0-42ce413486e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=943661102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.943661102
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.68738219
Short name T4
Test name
Test status
Simulation time 890075208 ps
CPU time 4.03 seconds
Started May 02 12:47:58 PM PDT 24
Finished May 02 12:48:07 PM PDT 24
Peak memory 214548 kb
Host smart-fd35e252-8fa8-4dd3-a5d8-32289620ffd4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=68738219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.68738219
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.1505693625
Short name T271
Test name
Test status
Simulation time 453612973 ps
CPU time 16.19 seconds
Started May 02 12:48:38 PM PDT 24
Finished May 02 12:48:59 PM PDT 24
Peak memory 214076 kb
Host smart-578ff24f-f8ca-40df-b20f-96ff2ee6ad9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1505693625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.1505693625
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.3912461127
Short name T38
Test name
Test status
Simulation time 146939004 ps
CPU time 3.44 seconds
Started May 02 12:48:57 PM PDT 24
Finished May 02 12:49:05 PM PDT 24
Peak memory 209828 kb
Host smart-2ea5be38-1302-4f95-b9f6-b5f67f588b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912461127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.3912461127
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.3277313479
Short name T92
Test name
Test status
Simulation time 125794006 ps
CPU time 6.12 seconds
Started May 02 12:48:19 PM PDT 24
Finished May 02 12:48:27 PM PDT 24
Peak memory 221240 kb
Host smart-2e6b799c-a6b7-4301-9337-effda6a056bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277313479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.3277313479
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.75993047
Short name T112
Test name
Test status
Simulation time 551547233 ps
CPU time 16.25 seconds
Started May 02 12:47:02 PM PDT 24
Finished May 02 12:47:20 PM PDT 24
Peak memory 214488 kb
Host smart-76ec18ca-d2b4-4bd8-94c1-0e6659250843
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75993047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.k
eymgr_shadow_reg_errors_with_csr_rw.75993047
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.2374383756
Short name T411
Test name
Test status
Simulation time 276470117 ps
CPU time 14.85 seconds
Started May 02 12:48:57 PM PDT 24
Finished May 02 12:49:16 PM PDT 24
Peak memory 215364 kb
Host smart-d0d34a6f-e061-431d-a54d-63ab90481739
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2374383756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.2374383756
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.3525788991
Short name T71
Test name
Test status
Simulation time 844924312 ps
CPU time 22.57 seconds
Started May 02 12:49:00 PM PDT 24
Finished May 02 12:49:28 PM PDT 24
Peak memory 222348 kb
Host smart-92fa8c53-2e62-46eb-a5e7-1a62b4461ee4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525788991 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.3525788991
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.3087287996
Short name T40
Test name
Test status
Simulation time 587764262 ps
CPU time 3.2 seconds
Started May 02 12:48:22 PM PDT 24
Finished May 02 12:48:27 PM PDT 24
Peak memory 209080 kb
Host smart-a22d31d9-29e1-49c6-b36f-f51507f840b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087287996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.3087287996
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.1765653641
Short name T425
Test name
Test status
Simulation time 14093292 ps
CPU time 0.75 seconds
Started May 02 12:47:46 PM PDT 24
Finished May 02 12:47:50 PM PDT 24
Peak memory 205576 kb
Host smart-4d6d9297-e473-4e0b-9fcf-fc48c1f0824d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765653641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.1765653641
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.3125176969
Short name T73
Test name
Test status
Simulation time 212706019 ps
CPU time 8.28 seconds
Started May 02 12:48:15 PM PDT 24
Finished May 02 12:48:26 PM PDT 24
Peak memory 217072 kb
Host smart-d0da9836-5663-44ab-81dd-f49426a29073
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125176969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.3125176969
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.2608645116
Short name T33
Test name
Test status
Simulation time 120882917 ps
CPU time 3.44 seconds
Started May 02 12:47:41 PM PDT 24
Finished May 02 12:47:48 PM PDT 24
Peak memory 207420 kb
Host smart-da957ee4-1ad8-4909-8c0b-46c3c33e6774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608645116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.2608645116
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.2391257137
Short name T144
Test name
Test status
Simulation time 299364792 ps
CPU time 10.61 seconds
Started May 02 12:47:51 PM PDT 24
Finished May 02 12:48:06 PM PDT 24
Peak memory 217464 kb
Host smart-960c7f96-d912-46ca-ab28-f08730504a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391257137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.2391257137
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.344781520
Short name T95
Test name
Test status
Simulation time 109849688 ps
CPU time 4.44 seconds
Started May 02 12:49:04 PM PDT 24
Finished May 02 12:49:14 PM PDT 24
Peak memory 213900 kb
Host smart-0c7e6d1b-cf84-4409-82ff-3de5b39f1a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344781520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.344781520
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.1912742044
Short name T129
Test name
Test status
Simulation time 251779128 ps
CPU time 12.64 seconds
Started May 02 12:48:13 PM PDT 24
Finished May 02 12:48:29 PM PDT 24
Peak memory 214972 kb
Host smart-6c150705-fcb1-4026-88d3-86069011a98d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1912742044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.1912742044
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.3272065996
Short name T383
Test name
Test status
Simulation time 186655393 ps
CPU time 3.95 seconds
Started May 02 12:48:37 PM PDT 24
Finished May 02 12:48:46 PM PDT 24
Peak memory 213916 kb
Host smart-104bf18f-2817-4a01-bf2d-04030b25fc22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3272065996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.3272065996
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.562852015
Short name T220
Test name
Test status
Simulation time 4738502485 ps
CPU time 35.33 seconds
Started May 02 12:48:58 PM PDT 24
Finished May 02 12:49:38 PM PDT 24
Peak memory 222300 kb
Host smart-32ea55ec-842b-4d40-9785-515ccc632364
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562852015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.562852015
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.3858194639
Short name T232
Test name
Test status
Simulation time 25547461797 ps
CPU time 108.73 seconds
Started May 02 12:49:30 PM PDT 24
Finished May 02 12:51:23 PM PDT 24
Peak memory 222184 kb
Host smart-d6d11c00-e782-42b6-829a-d27649411ba4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858194639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.3858194639
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.1361435778
Short name T250
Test name
Test status
Simulation time 4078658823 ps
CPU time 59.93 seconds
Started May 02 12:49:03 PM PDT 24
Finished May 02 12:50:08 PM PDT 24
Peak memory 222176 kb
Host smart-ced5e48d-0d2a-4f09-a258-f1649f158a54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361435778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.1361435778
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.3932626598
Short name T57
Test name
Test status
Simulation time 124334460 ps
CPU time 4.06 seconds
Started May 02 12:48:37 PM PDT 24
Finished May 02 12:48:46 PM PDT 24
Peak memory 214276 kb
Host smart-abc472bc-78b3-4cd4-9049-dc7191afd95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932626598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.3932626598
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.93731603
Short name T68
Test name
Test status
Simulation time 336021525 ps
CPU time 14.72 seconds
Started May 02 12:49:04 PM PDT 24
Finished May 02 12:49:23 PM PDT 24
Peak memory 220828 kb
Host smart-7f604b70-e905-4697-b550-fdd107531eb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93731603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.93731603
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.1731382937
Short name T163
Test name
Test status
Simulation time 426914802 ps
CPU time 8.95 seconds
Started May 02 12:46:49 PM PDT 24
Finished May 02 12:47:00 PM PDT 24
Peak memory 209572 kb
Host smart-90372ffe-4eba-41a8-a54d-6475e6023979
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731382937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.1731382937
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.4090569270
Short name T390
Test name
Test status
Simulation time 315441779 ps
CPU time 3.56 seconds
Started May 02 12:48:57 PM PDT 24
Finished May 02 12:49:05 PM PDT 24
Peak memory 214000 kb
Host smart-d5e016cd-f04d-4309-bf2f-5302bc5582e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090569270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.4090569270
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.3578945325
Short name T350
Test name
Test status
Simulation time 437470669 ps
CPU time 12.24 seconds
Started May 02 12:47:58 PM PDT 24
Finished May 02 12:48:14 PM PDT 24
Peak memory 214940 kb
Host smart-ba6190c3-f94c-4462-b881-9ec0336b0886
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3578945325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.3578945325
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.2803022854
Short name T193
Test name
Test status
Simulation time 2375692181 ps
CPU time 8.28 seconds
Started May 02 12:49:08 PM PDT 24
Finished May 02 12:49:23 PM PDT 24
Peak memory 209104 kb
Host smart-f90066ba-6336-4534-8e5e-201462841f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803022854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.2803022854
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.1234598411
Short name T87
Test name
Test status
Simulation time 2569274543 ps
CPU time 67.21 seconds
Started May 02 12:48:06 PM PDT 24
Finished May 02 12:49:17 PM PDT 24
Peak memory 214144 kb
Host smart-f93c1fcb-e7ac-40ce-aa15-81f5e9a55a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234598411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.1234598411
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.1658170459
Short name T264
Test name
Test status
Simulation time 1350386350 ps
CPU time 47.14 seconds
Started May 02 12:47:18 PM PDT 24
Finished May 02 12:48:09 PM PDT 24
Peak memory 222268 kb
Host smart-948ee51e-583b-4489-a0aa-1a3fd41b0f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658170459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.1658170459
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.232181854
Short name T371
Test name
Test status
Simulation time 197927554 ps
CPU time 4.36 seconds
Started May 02 12:47:40 PM PDT 24
Finished May 02 12:47:47 PM PDT 24
Peak memory 215056 kb
Host smart-7da54348-0f04-440c-b78d-3715e4455a3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=232181854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.232181854
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.120844882
Short name T154
Test name
Test status
Simulation time 196992418 ps
CPU time 4.82 seconds
Started May 02 12:46:32 PM PDT 24
Finished May 02 12:46:40 PM PDT 24
Peak memory 209104 kb
Host smart-1f0e6f89-fe96-4971-aab4-2af5fa1c5b3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120844882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err.
120844882
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.1254408819
Short name T148
Test name
Test status
Simulation time 60315846 ps
CPU time 3.95 seconds
Started May 02 12:47:15 PM PDT 24
Finished May 02 12:47:22 PM PDT 24
Peak memory 218232 kb
Host smart-89f3b9bc-6327-48a3-9817-fb291041b3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254408819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.1254408819
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.797538975
Short name T252
Test name
Test status
Simulation time 3155126868 ps
CPU time 33.32 seconds
Started May 02 12:48:11 PM PDT 24
Finished May 02 12:48:46 PM PDT 24
Peak memory 222232 kb
Host smart-3bebc324-c533-470a-98dd-a870de16f51e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797538975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.797538975
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.2040258222
Short name T345
Test name
Test status
Simulation time 6916742330 ps
CPU time 68.49 seconds
Started May 02 12:47:44 PM PDT 24
Finished May 02 12:48:56 PM PDT 24
Peak memory 222204 kb
Host smart-1c2e5b51-49b4-4fff-ac47-4ba2a2bf3309
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040258222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.2040258222
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.2395128528
Short name T91
Test name
Test status
Simulation time 44182605 ps
CPU time 3.23 seconds
Started May 02 12:48:53 PM PDT 24
Finished May 02 12:49:01 PM PDT 24
Peak memory 213876 kb
Host smart-352c857d-aeb9-48fc-81af-0391a7ea3a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395128528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.2395128528
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.2493855871
Short name T22
Test name
Test status
Simulation time 823388706 ps
CPU time 2.89 seconds
Started May 02 12:49:17 PM PDT 24
Finished May 02 12:49:23 PM PDT 24
Peak memory 208296 kb
Host smart-86aa64f6-96cb-41bd-8290-3663fcfc01a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493855871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.2493855871
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.3181149945
Short name T147
Test name
Test status
Simulation time 764563078 ps
CPU time 21.73 seconds
Started May 02 12:48:33 PM PDT 24
Finished May 02 12:48:58 PM PDT 24
Peak memory 217252 kb
Host smart-d7a73a0c-8cb7-4db0-90e7-82b6102cb940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181149945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.3181149945
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.1912700357
Short name T405
Test name
Test status
Simulation time 69519320 ps
CPU time 4.22 seconds
Started May 02 12:48:40 PM PDT 24
Finished May 02 12:48:50 PM PDT 24
Peak memory 214000 kb
Host smart-0388b3c4-3f0c-4f11-9bcd-bfbadce73e31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1912700357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.1912700357
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.62232413
Short name T166
Test name
Test status
Simulation time 621210556 ps
CPU time 9.51 seconds
Started May 02 12:48:13 PM PDT 24
Finished May 02 12:48:26 PM PDT 24
Peak memory 209928 kb
Host smart-9edff371-6110-4d8d-872d-8539edfadfee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62232413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.62232413
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.3263737257
Short name T171
Test name
Test status
Simulation time 216513869 ps
CPU time 2.51 seconds
Started May 02 12:48:13 PM PDT 24
Finished May 02 12:48:18 PM PDT 24
Peak memory 209512 kb
Host smart-e18affd3-f438-4ca2-a24d-b056c109c957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263737257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.3263737257
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.2056209824
Short name T1004
Test name
Test status
Simulation time 242111774 ps
CPU time 7.01 seconds
Started May 02 12:46:18 PM PDT 24
Finished May 02 12:46:27 PM PDT 24
Peak memory 214568 kb
Host smart-69035e07-1161-4855-9d08-a033e165d445
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056209824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.2056209824
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.3627955504
Short name T153
Test name
Test status
Simulation time 1861217172 ps
CPU time 10.74 seconds
Started May 02 12:46:22 PM PDT 24
Finished May 02 12:46:35 PM PDT 24
Peak memory 209580 kb
Host smart-f22c26a1-4a8b-4ea7-8e2a-3e7c5b512be0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627955504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.3627955504
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.1043466030
Short name T149
Test name
Test status
Simulation time 526037918 ps
CPU time 5.54 seconds
Started May 02 12:46:29 PM PDT 24
Finished May 02 12:46:38 PM PDT 24
Peak memory 209544 kb
Host smart-19de0568-a65f-4fd4-8561-b6b77e4cce2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043466030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.1043466030
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.2189653880
Short name T158
Test name
Test status
Simulation time 1847740691 ps
CPU time 47.18 seconds
Started May 02 12:46:52 PM PDT 24
Finished May 02 12:47:43 PM PDT 24
Peak memory 222412 kb
Host smart-6a0615d1-66e2-4c7a-bd32-fbce95616e70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189653880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.2189653880
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.3306687831
Short name T249
Test name
Test status
Simulation time 29561490 ps
CPU time 2.28 seconds
Started May 02 12:47:51 PM PDT 24
Finished May 02 12:47:57 PM PDT 24
Peak memory 208596 kb
Host smart-18f49048-db34-4fbb-a57a-fc8fb761b2dc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306687831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.3306687831
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.3469305199
Short name T121
Test name
Test status
Simulation time 1270044288 ps
CPU time 22.63 seconds
Started May 02 12:48:04 PM PDT 24
Finished May 02 12:48:31 PM PDT 24
Peak memory 222328 kb
Host smart-f5a23265-4216-4881-a047-395beb54b5e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469305199 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.3469305199
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.1678834862
Short name T351
Test name
Test status
Simulation time 90747397 ps
CPU time 4.52 seconds
Started May 02 12:48:16 PM PDT 24
Finished May 02 12:48:23 PM PDT 24
Peak memory 214436 kb
Host smart-c68f28fd-621b-4967-b407-75bd41f0a5ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1678834862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.1678834862
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.2562480501
Short name T285
Test name
Test status
Simulation time 58421141 ps
CPU time 3.46 seconds
Started May 02 12:48:12 PM PDT 24
Finished May 02 12:48:19 PM PDT 24
Peak memory 222120 kb
Host smart-b2f115b6-cac1-40c7-ad5f-69615f25af89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562480501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2562480501
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_random.612372984
Short name T125
Test name
Test status
Simulation time 770861527 ps
CPU time 9.76 seconds
Started May 02 12:47:22 PM PDT 24
Finished May 02 12:47:36 PM PDT 24
Peak memory 209812 kb
Host smart-c37f5a58-b38b-4f4d-931b-463e2892bedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612372984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.612372984
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.3861675540
Short name T284
Test name
Test status
Simulation time 77628129 ps
CPU time 3.83 seconds
Started May 02 12:48:38 PM PDT 24
Finished May 02 12:48:46 PM PDT 24
Peak memory 210836 kb
Host smart-a9f2d1c4-11e1-4a30-9225-733801307751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861675540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.3861675540
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.2062874088
Short name T408
Test name
Test status
Simulation time 2542882604 ps
CPU time 36.78 seconds
Started May 02 12:49:08 PM PDT 24
Finished May 02 12:49:50 PM PDT 24
Peak memory 214012 kb
Host smart-3515c5ea-1152-4ffc-9825-23752e37b3b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2062874088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.2062874088
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.714641889
Short name T165
Test name
Test status
Simulation time 138392913 ps
CPU time 3.13 seconds
Started May 02 12:48:39 PM PDT 24
Finished May 02 12:48:47 PM PDT 24
Peak memory 209536 kb
Host smart-a2586360-125e-4e95-9f23-e178f2d82176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714641889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.714641889
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.3481288456
Short name T145
Test name
Test status
Simulation time 64299441 ps
CPU time 2.96 seconds
Started May 02 12:49:23 PM PDT 24
Finished May 02 12:49:29 PM PDT 24
Peak memory 217412 kb
Host smart-f8d66483-9005-4055-94cd-6a66b3fd50e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481288456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.3481288456
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.1625568290
Short name T105
Test name
Test status
Simulation time 438569100 ps
CPU time 16.44 seconds
Started May 02 12:47:42 PM PDT 24
Finished May 02 12:48:01 PM PDT 24
Peak memory 215188 kb
Host smart-9987e701-cd4f-450a-a380-c7a9a42adb8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625568290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.1625568290
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.1051338429
Short name T389
Test name
Test status
Simulation time 186089432 ps
CPU time 4.69 seconds
Started May 02 12:47:49 PM PDT 24
Finished May 02 12:47:58 PM PDT 24
Peak memory 213988 kb
Host smart-24491d63-bee9-4e2a-b6dd-dd6a0e7e0c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051338429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.1051338429
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.2814933626
Short name T492
Test name
Test status
Simulation time 763097132 ps
CPU time 6.12 seconds
Started May 02 12:47:55 PM PDT 24
Finished May 02 12:48:04 PM PDT 24
Peak memory 208216 kb
Host smart-26d7d631-7509-4fc0-8ec3-a8bc72284a04
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814933626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.2814933626
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.3745361502
Short name T368
Test name
Test status
Simulation time 2335245348 ps
CPU time 32.57 seconds
Started May 02 12:47:57 PM PDT 24
Finished May 02 12:48:33 PM PDT 24
Peak memory 216588 kb
Host smart-1fae5bfa-2b20-4581-a239-585aad821449
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745361502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.3745361502
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.2177275180
Short name T241
Test name
Test status
Simulation time 77728337 ps
CPU time 3.99 seconds
Started May 02 12:47:44 PM PDT 24
Finished May 02 12:47:51 PM PDT 24
Peak memory 222116 kb
Host smart-d4323471-d862-4cf3-a343-4b46b493837f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177275180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.2177275180
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.3039954031
Short name T348
Test name
Test status
Simulation time 178532826 ps
CPU time 2.44 seconds
Started May 02 12:48:09 PM PDT 24
Finished May 02 12:48:14 PM PDT 24
Peak memory 209364 kb
Host smart-d96c1cf1-a596-4465-a55c-d78b84292136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039954031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.3039954031
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.1867753959
Short name T225
Test name
Test status
Simulation time 843578207 ps
CPU time 36.1 seconds
Started May 02 12:48:02 PM PDT 24
Finished May 02 12:48:43 PM PDT 24
Peak memory 221072 kb
Host smart-c0cb8d0d-697f-48ab-8220-87d20ca5bbba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867753959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.1867753959
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.2647054164
Short name T309
Test name
Test status
Simulation time 276766051 ps
CPU time 4.49 seconds
Started May 02 12:48:02 PM PDT 24
Finished May 02 12:48:11 PM PDT 24
Peak memory 210056 kb
Host smart-65d5487e-3dab-4fc7-a6b2-a0e9e31514df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647054164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.2647054164
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.3582736460
Short name T98
Test name
Test status
Simulation time 356815337 ps
CPU time 4.66 seconds
Started May 02 12:47:43 PM PDT 24
Finished May 02 12:47:51 PM PDT 24
Peak memory 213884 kb
Host smart-2f64c692-c197-4871-9c13-e05868e24325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582736460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.3582736460
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.2086627250
Short name T61
Test name
Test status
Simulation time 345748885 ps
CPU time 11.67 seconds
Started May 02 12:48:49 PM PDT 24
Finished May 02 12:49:05 PM PDT 24
Peak memory 222132 kb
Host smart-bb8cbbf8-fecd-459b-8eab-e8718dfa74bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086627250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.2086627250
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.1238003901
Short name T227
Test name
Test status
Simulation time 443352809 ps
CPU time 22.48 seconds
Started May 02 12:49:17 PM PDT 24
Finished May 02 12:49:43 PM PDT 24
Peak memory 215364 kb
Host smart-4dda77a7-e865-498c-9240-6f888bd22b7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238003901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.1238003901
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1917113082
Short name T151
Test name
Test status
Simulation time 808322257 ps
CPU time 8.99 seconds
Started May 02 12:46:55 PM PDT 24
Finished May 02 12:47:08 PM PDT 24
Peak memory 214240 kb
Host smart-64c796e0-db01-4ecc-9977-ef878f029e91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917113082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.1917113082
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.3870308968
Short name T164
Test name
Test status
Simulation time 1542163958 ps
CPU time 10.2 seconds
Started May 02 12:46:45 PM PDT 24
Finished May 02 12:46:57 PM PDT 24
Peak memory 214244 kb
Host smart-a4b4ac50-1dd1-464e-83d6-37c2a1768ff8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870308968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.3870308968
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.785120384
Short name T157
Test name
Test status
Simulation time 246004951 ps
CPU time 5.21 seconds
Started May 02 12:46:49 PM PDT 24
Finished May 02 12:46:56 PM PDT 24
Peak memory 214264 kb
Host smart-d358d0fd-3b26-4553-8427-9ee8d7c98ddc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785120384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.
785120384
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.2638225514
Short name T143
Test name
Test status
Simulation time 363202323 ps
CPU time 4.05 seconds
Started May 02 12:48:09 PM PDT 24
Finished May 02 12:48:15 PM PDT 24
Peak memory 218212 kb
Host smart-35c9688f-6a06-43b2-8d8b-5973141331e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638225514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.2638225514
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.710208577
Short name T146
Test name
Test status
Simulation time 55891163 ps
CPU time 2.87 seconds
Started May 02 12:47:58 PM PDT 24
Finished May 02 12:48:05 PM PDT 24
Peak memory 217024 kb
Host smart-6b9a7db8-f75e-47e1-9d4e-bdea9cff88ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710208577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.710208577
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.3735838217
Short name T328
Test name
Test status
Simulation time 141225485 ps
CPU time 1.8 seconds
Started May 02 12:47:55 PM PDT 24
Finished May 02 12:48:00 PM PDT 24
Peak memory 209152 kb
Host smart-74af697c-ad98-418d-846d-f30ba3083ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735838217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.3735838217
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.248726469
Short name T343
Test name
Test status
Simulation time 54015316 ps
CPU time 3.18 seconds
Started May 02 12:47:52 PM PDT 24
Finished May 02 12:47:59 PM PDT 24
Peak memory 208056 kb
Host smart-c844c8d9-13ce-4240-95a5-ee54e2e041fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248726469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.248726469
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.193918687
Short name T315
Test name
Test status
Simulation time 26410780 ps
CPU time 2.06 seconds
Started May 02 12:47:45 PM PDT 24
Finished May 02 12:47:51 PM PDT 24
Peak memory 207232 kb
Host smart-f9d70a98-be21-420c-8c87-8d579b461beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193918687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.193918687
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.3526869190
Short name T369
Test name
Test status
Simulation time 201794478 ps
CPU time 4.72 seconds
Started May 02 12:48:01 PM PDT 24
Finished May 02 12:48:10 PM PDT 24
Peak memory 213984 kb
Host smart-deb6e742-3d5c-4bfc-8cd6-795e3dac8dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526869190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.3526869190
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.2207734722
Short name T180
Test name
Test status
Simulation time 135490223 ps
CPU time 2.08 seconds
Started May 02 12:48:02 PM PDT 24
Finished May 02 12:48:08 PM PDT 24
Peak memory 209376 kb
Host smart-6a6fddc3-0864-49b6-8db9-571fac72b247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207734722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.2207734722
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.3404167742
Short name T16
Test name
Test status
Simulation time 347325585 ps
CPU time 4.82 seconds
Started May 02 12:48:00 PM PDT 24
Finished May 02 12:48:09 PM PDT 24
Peak memory 214024 kb
Host smart-2fcb5c2f-6cd4-4b6e-aa81-d05ddcfae85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404167742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.3404167742
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.843956494
Short name T290
Test name
Test status
Simulation time 1131026962 ps
CPU time 10.09 seconds
Started May 02 12:48:11 PM PDT 24
Finished May 02 12:48:23 PM PDT 24
Peak memory 222240 kb
Host smart-beee3264-80d9-4144-a7ec-1e4dfd20e9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843956494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.843956494
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.910649737
Short name T294
Test name
Test status
Simulation time 255119144 ps
CPU time 4.03 seconds
Started May 02 12:48:02 PM PDT 24
Finished May 02 12:48:11 PM PDT 24
Peak memory 208004 kb
Host smart-014bbc3a-dc29-49d8-bc85-2ebae063805b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910649737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.910649737
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.2299704684
Short name T313
Test name
Test status
Simulation time 2795684319 ps
CPU time 10.99 seconds
Started May 02 12:47:58 PM PDT 24
Finished May 02 12:48:13 PM PDT 24
Peak memory 218332 kb
Host smart-30c69784-95fc-485c-811e-3655e734b541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299704684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.2299704684
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.1097789205
Short name T362
Test name
Test status
Simulation time 1550019315 ps
CPU time 22.13 seconds
Started May 02 12:48:19 PM PDT 24
Finished May 02 12:48:43 PM PDT 24
Peak memory 210360 kb
Host smart-d4905705-d061-48d7-80a8-894b6ad17524
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097789205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.1097789205
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.206881102
Short name T218
Test name
Test status
Simulation time 445238931 ps
CPU time 12.95 seconds
Started May 02 12:48:11 PM PDT 24
Finished May 02 12:48:26 PM PDT 24
Peak memory 214044 kb
Host smart-b8c60665-e1b0-46f6-bf57-7c5601aa9e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206881102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.206881102
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.3673387714
Short name T24
Test name
Test status
Simulation time 118420941 ps
CPU time 3.15 seconds
Started May 02 12:48:25 PM PDT 24
Finished May 02 12:48:32 PM PDT 24
Peak memory 222424 kb
Host smart-0558cd96-3f2b-4f66-8be8-e6e45030ad92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673387714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.3673387714
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_random.3557724982
Short name T298
Test name
Test status
Simulation time 516337792 ps
CPU time 2.93 seconds
Started May 02 12:48:37 PM PDT 24
Finished May 02 12:48:45 PM PDT 24
Peak memory 207092 kb
Host smart-9530241d-1a80-46fd-a1fb-2b6e8f7a0ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557724982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.3557724982
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.946177116
Short name T416
Test name
Test status
Simulation time 226275334 ps
CPU time 4.06 seconds
Started May 02 12:48:37 PM PDT 24
Finished May 02 12:48:46 PM PDT 24
Peak memory 214088 kb
Host smart-136d9d2a-e266-44c7-a08a-75fc3f4ae06f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=946177116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.946177116
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.1765146384
Short name T304
Test name
Test status
Simulation time 364812338 ps
CPU time 3.93 seconds
Started May 02 12:48:38 PM PDT 24
Finished May 02 12:48:47 PM PDT 24
Peak memory 210788 kb
Host smart-c7cfb499-1261-42de-bd27-9a2e992619ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765146384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.1765146384
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.5927859
Short name T222
Test name
Test status
Simulation time 178435202 ps
CPU time 3.25 seconds
Started May 02 12:48:24 PM PDT 24
Finished May 02 12:48:30 PM PDT 24
Peak memory 213924 kb
Host smart-cb232f90-0b37-4724-b641-a00f4590be8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5927859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.5927859
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.3344661883
Short name T58
Test name
Test status
Simulation time 95613976 ps
CPU time 2.78 seconds
Started May 02 12:48:37 PM PDT 24
Finished May 02 12:48:45 PM PDT 24
Peak memory 214164 kb
Host smart-78db887f-09b1-4dc2-80c6-2cec31e429a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344661883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.3344661883
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.178918387
Short name T8
Test name
Test status
Simulation time 581319126 ps
CPU time 5.22 seconds
Started May 02 12:48:49 PM PDT 24
Finished May 02 12:48:58 PM PDT 24
Peak memory 222368 kb
Host smart-49521e75-f598-49f8-9b97-d6e76ea07175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178918387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.178918387
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.3886893675
Short name T43
Test name
Test status
Simulation time 312486188 ps
CPU time 2.69 seconds
Started May 02 12:48:59 PM PDT 24
Finished May 02 12:49:07 PM PDT 24
Peak memory 214240 kb
Host smart-5ccabcc7-da0a-47fe-af2c-c0b99a189361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886893675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.3886893675
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.1643778249
Short name T9
Test name
Test status
Simulation time 105271232 ps
CPU time 4.53 seconds
Started May 02 12:48:54 PM PDT 24
Finished May 02 12:49:03 PM PDT 24
Peak memory 222376 kb
Host smart-5c945541-777b-4efa-bf5a-09fd161dc373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643778249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.1643778249
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.493710331
Short name T229
Test name
Test status
Simulation time 102045062 ps
CPU time 6 seconds
Started May 02 12:49:12 PM PDT 24
Finished May 02 12:49:23 PM PDT 24
Peak memory 214784 kb
Host smart-10297676-2f5c-46d3-a429-8732e6462639
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=493710331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.493710331
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.3188733254
Short name T266
Test name
Test status
Simulation time 143598449 ps
CPU time 2.79 seconds
Started May 02 12:47:42 PM PDT 24
Finished May 02 12:47:47 PM PDT 24
Peak memory 214876 kb
Host smart-74b8fc7d-394d-401c-97ef-d4200135cd65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3188733254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.3188733254
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.1121132676
Short name T13
Test name
Test status
Simulation time 445410560 ps
CPU time 9.61 seconds
Started May 02 12:47:21 PM PDT 24
Finished May 02 12:47:34 PM PDT 24
Peak memory 233212 kb
Host smart-f25b2739-44ca-4c9f-8795-12214f4c4a6f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121132676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.1121132676
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.1747993334
Short name T55
Test name
Test status
Simulation time 2429909991 ps
CPU time 5.12 seconds
Started May 02 12:48:40 PM PDT 24
Finished May 02 12:48:52 PM PDT 24
Peak memory 217464 kb
Host smart-e72c01ce-e9f5-4226-b576-1c85b7b1fa9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747993334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.1747993334
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.808056340
Short name T990
Test name
Test status
Simulation time 2054454964 ps
CPU time 11.04 seconds
Started May 02 12:46:19 PM PDT 24
Finished May 02 12:46:33 PM PDT 24
Peak memory 206028 kb
Host smart-309b760f-9cc0-4fd8-9351-832564b5792a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808056340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.808056340
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.1589506979
Short name T1001
Test name
Test status
Simulation time 1005074862 ps
CPU time 12.8 seconds
Started May 02 12:46:30 PM PDT 24
Finished May 02 12:46:46 PM PDT 24
Peak memory 206000 kb
Host smart-67f71b34-77e8-4a4c-92db-fa9944ebe04c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589506979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.1
589506979
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.1116880969
Short name T1062
Test name
Test status
Simulation time 212226392 ps
CPU time 1.21 seconds
Started May 02 12:46:38 PM PDT 24
Finished May 02 12:46:43 PM PDT 24
Peak memory 206028 kb
Host smart-8d639e55-ac90-4e68-b02b-be74221ac077
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116880969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.1
116880969
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.1543437314
Short name T1028
Test name
Test status
Simulation time 203690773 ps
CPU time 2.31 seconds
Started May 02 12:46:17 PM PDT 24
Finished May 02 12:46:22 PM PDT 24
Peak memory 214364 kb
Host smart-328131c1-19cd-4765-8938-e080db931bea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543437314 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.1543437314
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.3115713724
Short name T1073
Test name
Test status
Simulation time 25754776 ps
CPU time 0.92 seconds
Started May 02 12:46:22 PM PDT 24
Finished May 02 12:46:25 PM PDT 24
Peak memory 205728 kb
Host smart-84b130de-828e-4681-8333-04a28fe62bc4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115713724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.3115713724
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.241915817
Short name T1074
Test name
Test status
Simulation time 84342920 ps
CPU time 0.76 seconds
Started May 02 12:46:43 PM PDT 24
Finished May 02 12:46:46 PM PDT 24
Peak memory 205724 kb
Host smart-e5b7d736-612e-4d2c-a99f-66e8cbd07522
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241915817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.241915817
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3526989636
Short name T133
Test name
Test status
Simulation time 333964653 ps
CPU time 1.54 seconds
Started May 02 12:46:23 PM PDT 24
Finished May 02 12:46:27 PM PDT 24
Peak memory 205968 kb
Host smart-29dd5316-2516-47f0-b7d4-daf382090ad4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526989636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.3526989636
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.2315010065
Short name T943
Test name
Test status
Simulation time 332205841 ps
CPU time 4.84 seconds
Started May 02 12:46:37 PM PDT 24
Finished May 02 12:46:45 PM PDT 24
Peak memory 214544 kb
Host smart-c2e58301-c4fe-47bc-aaa4-5a6875bad3ff
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315010065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.2315010065
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.2860739619
Short name T1076
Test name
Test status
Simulation time 1109364419 ps
CPU time 6.15 seconds
Started May 02 12:46:29 PM PDT 24
Finished May 02 12:46:39 PM PDT 24
Peak memory 217488 kb
Host smart-c4c69ea7-2779-41d8-9da4-096edae1c15c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860739619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.2860739619
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.696385624
Short name T156
Test name
Test status
Simulation time 3045020324 ps
CPU time 17.85 seconds
Started May 02 12:46:25 PM PDT 24
Finished May 02 12:46:45 PM PDT 24
Peak memory 209752 kb
Host smart-552b7945-a066-4011-9ae2-c86eb4023885
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696385624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.
696385624
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.323730057
Short name T992
Test name
Test status
Simulation time 7178682364 ps
CPU time 9.77 seconds
Started May 02 12:46:33 PM PDT 24
Finished May 02 12:46:46 PM PDT 24
Peak memory 206204 kb
Host smart-1a4172d0-f01d-4bd4-ba0c-75c1ebbd387b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323730057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.323730057
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.1239175490
Short name T931
Test name
Test status
Simulation time 3165248302 ps
CPU time 17.5 seconds
Started May 02 12:46:21 PM PDT 24
Finished May 02 12:46:40 PM PDT 24
Peak memory 206116 kb
Host smart-8d0a0c47-b3af-43f9-ac3b-212b309c3ef4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239175490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.1
239175490
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.1141220002
Short name T925
Test name
Test status
Simulation time 16122233 ps
CPU time 1.05 seconds
Started May 02 12:46:20 PM PDT 24
Finished May 02 12:46:24 PM PDT 24
Peak memory 205936 kb
Host smart-d884c484-3428-4246-a17a-27f353f1a6f4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141220002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.1
141220002
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.2878539300
Short name T978
Test name
Test status
Simulation time 89361528 ps
CPU time 2.19 seconds
Started May 02 12:46:47 PM PDT 24
Finished May 02 12:46:51 PM PDT 24
Peak memory 214392 kb
Host smart-1beb6215-0f4d-45ba-a223-ffdf55d795f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878539300 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.2878539300
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.85915354
Short name T1014
Test name
Test status
Simulation time 21040284 ps
CPU time 0.99 seconds
Started May 02 12:46:22 PM PDT 24
Finished May 02 12:46:25 PM PDT 24
Peak memory 205776 kb
Host smart-f13c6434-5f0b-4049-80c0-c3cc1e88eac8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85915354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.85915354
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.3279009614
Short name T910
Test name
Test status
Simulation time 27861534 ps
CPU time 0.76 seconds
Started May 02 12:46:28 PM PDT 24
Finished May 02 12:46:31 PM PDT 24
Peak memory 205772 kb
Host smart-33ac22c7-5ff0-4dfb-8e87-6ec0387a2881
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279009614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.3279009614
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.3436785356
Short name T984
Test name
Test status
Simulation time 92487528 ps
CPU time 3.73 seconds
Started May 02 12:46:44 PM PDT 24
Finished May 02 12:46:50 PM PDT 24
Peak memory 206124 kb
Host smart-04d51072-b526-4232-9ec1-752481fb68ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436785356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.3436785356
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3126305112
Short name T940
Test name
Test status
Simulation time 101334743 ps
CPU time 2.82 seconds
Started May 02 12:46:31 PM PDT 24
Finished May 02 12:46:37 PM PDT 24
Peak memory 214500 kb
Host smart-0db8e0b3-061a-44ab-b9a0-6b8f4962f58b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126305112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.3126305112
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.253441250
Short name T1015
Test name
Test status
Simulation time 483478884 ps
CPU time 8.66 seconds
Started May 02 12:46:31 PM PDT 24
Finished May 02 12:46:43 PM PDT 24
Peak memory 214556 kb
Host smart-bf6e830b-f24b-432c-855e-3e18176aa74e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253441250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.k
eymgr_shadow_reg_errors_with_csr_rw.253441250
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.2094622226
Short name T953
Test name
Test status
Simulation time 50749145 ps
CPU time 1.66 seconds
Started May 02 12:46:42 PM PDT 24
Finished May 02 12:46:47 PM PDT 24
Peak memory 216704 kb
Host smart-45125108-691b-476d-a3dd-03d905e75d20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094622226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.2094622226
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1131673173
Short name T1016
Test name
Test status
Simulation time 19604019 ps
CPU time 1.22 seconds
Started May 02 12:46:50 PM PDT 24
Finished May 02 12:46:55 PM PDT 24
Peak memory 214444 kb
Host smart-8b4e10b3-3ca3-4a8a-810f-75dfba12abee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131673173 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.1131673173
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.187125729
Short name T942
Test name
Test status
Simulation time 160025583 ps
CPU time 1.65 seconds
Started May 02 12:46:34 PM PDT 24
Finished May 02 12:46:38 PM PDT 24
Peak memory 206036 kb
Host smart-f694a57d-a43f-4cdf-9ff7-bf6788919de7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187125729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.187125729
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.638136725
Short name T1009
Test name
Test status
Simulation time 16922947 ps
CPU time 0.72 seconds
Started May 02 12:46:43 PM PDT 24
Finished May 02 12:46:47 PM PDT 24
Peak memory 205716 kb
Host smart-88c1ad8c-f0c7-4562-abdf-703a6cef28c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638136725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.638136725
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2093248466
Short name T935
Test name
Test status
Simulation time 380536684 ps
CPU time 2.78 seconds
Started May 02 12:46:28 PM PDT 24
Finished May 02 12:46:33 PM PDT 24
Peak memory 206132 kb
Host smart-6ee65e46-8aa8-4af6-b181-2c64f3d61a0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093248466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.2093248466
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.2614167580
Short name T1057
Test name
Test status
Simulation time 246851859 ps
CPU time 2.03 seconds
Started May 02 12:46:50 PM PDT 24
Finished May 02 12:46:55 PM PDT 24
Peak memory 214516 kb
Host smart-2e763d54-469a-4ebb-b5ab-c810cdd89de2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614167580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.2614167580
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.2250440635
Short name T945
Test name
Test status
Simulation time 306950098 ps
CPU time 6.56 seconds
Started May 02 12:46:33 PM PDT 24
Finished May 02 12:46:42 PM PDT 24
Peak memory 214476 kb
Host smart-55c42bff-0960-452e-a959-dc8df5b4c8e6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250440635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.2250440635
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1673160551
Short name T1055
Test name
Test status
Simulation time 128435542 ps
CPU time 3.19 seconds
Started May 02 12:46:49 PM PDT 24
Finished May 02 12:46:54 PM PDT 24
Peak memory 216344 kb
Host smart-d594c810-7f6f-4ac7-8645-d5c7afa43382
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673160551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.1673160551
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.866751589
Short name T970
Test name
Test status
Simulation time 63983813 ps
CPU time 1.26 seconds
Started May 02 12:46:25 PM PDT 24
Finished May 02 12:46:28 PM PDT 24
Peak memory 214320 kb
Host smart-f970663c-95f7-4855-9021-e300c3f3c1f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866751589 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.866751589
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.3826868950
Short name T1041
Test name
Test status
Simulation time 113860595 ps
CPU time 1.23 seconds
Started May 02 12:46:48 PM PDT 24
Finished May 02 12:46:51 PM PDT 24
Peak memory 205952 kb
Host smart-273fcdac-a87e-4831-b44b-6ef017c61c9e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826868950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.3826868950
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.924170222
Short name T1008
Test name
Test status
Simulation time 20795073 ps
CPU time 0.73 seconds
Started May 02 12:46:43 PM PDT 24
Finished May 02 12:46:46 PM PDT 24
Peak memory 205784 kb
Host smart-36d4e9c8-59ca-4582-8c9b-807e3f677f7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924170222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.924170222
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.2218117141
Short name T1046
Test name
Test status
Simulation time 416406667 ps
CPU time 3.73 seconds
Started May 02 12:46:31 PM PDT 24
Finished May 02 12:46:38 PM PDT 24
Peak memory 206052 kb
Host smart-69e36864-4f1f-4bb1-9a0b-cfec0ee41576
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218117141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.2218117141
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.794959531
Short name T951
Test name
Test status
Simulation time 157142955 ps
CPU time 2.95 seconds
Started May 02 12:46:50 PM PDT 24
Finished May 02 12:46:56 PM PDT 24
Peak memory 214660 kb
Host smart-d8ee443a-13fa-4402-b517-e5b3ef160da2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794959531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shado
w_reg_errors.794959531
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.769398268
Short name T979
Test name
Test status
Simulation time 39368536 ps
CPU time 2.52 seconds
Started May 02 12:46:47 PM PDT 24
Finished May 02 12:46:52 PM PDT 24
Peak memory 214240 kb
Host smart-f0a584a5-ddcc-483e-9650-31cd090186e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769398268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.769398268
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.3302505030
Short name T161
Test name
Test status
Simulation time 532567197 ps
CPU time 12.97 seconds
Started May 02 12:46:46 PM PDT 24
Finished May 02 12:47:01 PM PDT 24
Peak memory 214364 kb
Host smart-dae84ae5-51a7-48d8-bef9-e214a7c6e87b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302505030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.3302505030
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.2818479513
Short name T934
Test name
Test status
Simulation time 96261832 ps
CPU time 1.67 seconds
Started May 02 12:46:52 PM PDT 24
Finished May 02 12:46:57 PM PDT 24
Peak memory 214376 kb
Host smart-af87de81-8d5f-4c87-8820-8c0305efbbe6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818479513 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.2818479513
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.548885414
Short name T928
Test name
Test status
Simulation time 62058231 ps
CPU time 0.95 seconds
Started May 02 12:46:45 PM PDT 24
Finished May 02 12:46:49 PM PDT 24
Peak memory 205804 kb
Host smart-62e8771d-5673-4c6d-83bd-37671e1a0be0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548885414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.548885414
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.3773651606
Short name T1036
Test name
Test status
Simulation time 104221927 ps
CPU time 0.75 seconds
Started May 02 12:46:30 PM PDT 24
Finished May 02 12:46:34 PM PDT 24
Peak memory 205760 kb
Host smart-17c76faf-48fd-437a-a2fa-b2dff628b69c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773651606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.3773651606
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.1637511842
Short name T1006
Test name
Test status
Simulation time 122686815 ps
CPU time 2.97 seconds
Started May 02 12:46:36 PM PDT 24
Finished May 02 12:46:42 PM PDT 24
Peak memory 206048 kb
Host smart-b1b0ed6f-3f20-41c0-99b2-7a83980b9f10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637511842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.1637511842
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2181942612
Short name T115
Test name
Test status
Simulation time 823703570 ps
CPU time 4.64 seconds
Started May 02 12:46:36 PM PDT 24
Finished May 02 12:46:43 PM PDT 24
Peak memory 214536 kb
Host smart-83df7aee-585c-43bc-880e-decc8539ae6b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181942612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.2181942612
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.2965572470
Short name T1050
Test name
Test status
Simulation time 662264993 ps
CPU time 5.12 seconds
Started May 02 12:46:30 PM PDT 24
Finished May 02 12:46:38 PM PDT 24
Peak memory 214244 kb
Host smart-5ffff299-91a8-4d42-a434-aec6e16600dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965572470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.2965572470
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2537637206
Short name T384
Test name
Test status
Simulation time 270240005 ps
CPU time 5.41 seconds
Started May 02 12:46:43 PM PDT 24
Finished May 02 12:46:51 PM PDT 24
Peak memory 209768 kb
Host smart-71a8f25c-6052-47e0-8271-3aaedb34de06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537637206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.2537637206
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.186565228
Short name T1023
Test name
Test status
Simulation time 54802924 ps
CPU time 1.62 seconds
Started May 02 12:46:51 PM PDT 24
Finished May 02 12:46:56 PM PDT 24
Peak memory 216416 kb
Host smart-bc1dd1e5-7eab-4c64-9da2-59aa4e0e58ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186565228 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.186565228
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.1147015792
Short name T924
Test name
Test status
Simulation time 27005335 ps
CPU time 1.24 seconds
Started May 02 12:46:36 PM PDT 24
Finished May 02 12:46:41 PM PDT 24
Peak memory 205924 kb
Host smart-fbe0a52e-1fd5-4b80-899f-c5e94e52ff34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147015792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.1147015792
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.1465750341
Short name T1013
Test name
Test status
Simulation time 18591658 ps
CPU time 0.85 seconds
Started May 02 12:46:52 PM PDT 24
Finished May 02 12:46:57 PM PDT 24
Peak memory 205796 kb
Host smart-76a01b49-3fc1-432a-9ea8-6780e4f6b635
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465750341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.1465750341
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.1390012515
Short name T947
Test name
Test status
Simulation time 22220938 ps
CPU time 1.35 seconds
Started May 02 12:47:22 PM PDT 24
Finished May 02 12:47:27 PM PDT 24
Peak memory 205968 kb
Host smart-e8d8213a-f274-419e-8d6b-2e4f2615a6ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390012515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.1390012515
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.83729765
Short name T1024
Test name
Test status
Simulation time 2386878600 ps
CPU time 10.25 seconds
Started May 02 12:46:48 PM PDT 24
Finished May 02 12:47:01 PM PDT 24
Peak memory 214676 kb
Host smart-a1fcb6b0-dd82-4e46-9501-2fe77be087ba
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83729765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shadow
_reg_errors.83729765
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.1317878665
Short name T1019
Test name
Test status
Simulation time 419307906 ps
CPU time 5.26 seconds
Started May 02 12:46:54 PM PDT 24
Finished May 02 12:47:04 PM PDT 24
Peak memory 214544 kb
Host smart-69ca0207-f8e1-4f41-9755-17f50b52449b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317878665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.1317878665
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.180123650
Short name T1049
Test name
Test status
Simulation time 82793653 ps
CPU time 3.19 seconds
Started May 02 12:46:49 PM PDT 24
Finished May 02 12:46:54 PM PDT 24
Peak memory 214216 kb
Host smart-3a72ab7f-91d7-4549-b666-9c21a5256faf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180123650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.180123650
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.2823150797
Short name T159
Test name
Test status
Simulation time 549899790 ps
CPU time 15.47 seconds
Started May 02 12:46:33 PM PDT 24
Finished May 02 12:46:51 PM PDT 24
Peak memory 209220 kb
Host smart-06e461e8-5542-47b8-af31-b29eea1ae115
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823150797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.2823150797
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.1637941741
Short name T936
Test name
Test status
Simulation time 95075539 ps
CPU time 1.43 seconds
Started May 02 12:46:36 PM PDT 24
Finished May 02 12:46:41 PM PDT 24
Peak memory 205960 kb
Host smart-3a289f18-d177-438f-9799-913e72fcdaca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637941741 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.1637941741
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.1535744830
Short name T1021
Test name
Test status
Simulation time 54125407 ps
CPU time 1.46 seconds
Started May 02 12:47:12 PM PDT 24
Finished May 02 12:47:17 PM PDT 24
Peak memory 205996 kb
Host smart-2764cf2d-d6f0-4dfb-b8ef-3292dfec4141
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535744830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.1535744830
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2186669395
Short name T971
Test name
Test status
Simulation time 37727110 ps
CPU time 0.81 seconds
Started May 02 12:46:36 PM PDT 24
Finished May 02 12:46:39 PM PDT 24
Peak memory 205640 kb
Host smart-b9011e9f-9ba6-4e92-8fae-df7dfd645150
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186669395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.2186669395
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.3445186964
Short name T965
Test name
Test status
Simulation time 45557890 ps
CPU time 2.19 seconds
Started May 02 12:46:36 PM PDT 24
Finished May 02 12:46:41 PM PDT 24
Peak memory 206092 kb
Host smart-64c7000c-9260-441d-a167-d60bb4d83574
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445186964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.3445186964
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3664119527
Short name T1056
Test name
Test status
Simulation time 174025103 ps
CPU time 2.08 seconds
Started May 02 12:46:35 PM PDT 24
Finished May 02 12:46:39 PM PDT 24
Peak memory 214608 kb
Host smart-d60d53f0-4dd4-4b9c-b6ce-ecb91e7d9f63
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664119527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.3664119527
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.849821170
Short name T119
Test name
Test status
Simulation time 1614917359 ps
CPU time 10.74 seconds
Started May 02 12:46:57 PM PDT 24
Finished May 02 12:47:11 PM PDT 24
Peak memory 214556 kb
Host smart-e339af8e-d7de-46f5-bc03-45f39e1a038d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849821170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
keymgr_shadow_reg_errors_with_csr_rw.849821170
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.2092608235
Short name T1031
Test name
Test status
Simulation time 209925702 ps
CPU time 3.4 seconds
Started May 02 12:46:55 PM PDT 24
Finished May 02 12:47:03 PM PDT 24
Peak memory 214232 kb
Host smart-de1638f6-f948-44a3-91ab-08109bdaf05a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092608235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.2092608235
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.277660956
Short name T1064
Test name
Test status
Simulation time 229496830 ps
CPU time 1.74 seconds
Started May 02 12:46:36 PM PDT 24
Finished May 02 12:46:41 PM PDT 24
Peak memory 214292 kb
Host smart-17091724-de4d-449a-a198-f6df6ebd15f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277660956 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.277660956
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.3023383522
Short name T136
Test name
Test status
Simulation time 34865702 ps
CPU time 0.98 seconds
Started May 02 12:47:10 PM PDT 24
Finished May 02 12:47:14 PM PDT 24
Peak memory 205784 kb
Host smart-70f24fae-1d3d-4002-afe7-2f0eea6620a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023383522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.3023383522
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.459808076
Short name T950
Test name
Test status
Simulation time 19739291 ps
CPU time 0.81 seconds
Started May 02 12:47:20 PM PDT 24
Finished May 02 12:47:25 PM PDT 24
Peak memory 205772 kb
Host smart-7b92b7d5-82fb-4f99-a589-ff9b98d72493
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459808076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.459808076
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.338226999
Short name T976
Test name
Test status
Simulation time 61272323 ps
CPU time 2.28 seconds
Started May 02 12:47:38 PM PDT 24
Finished May 02 12:47:42 PM PDT 24
Peak memory 206084 kb
Host smart-690b18a8-63e2-41a7-b052-96f3b2a73739
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338226999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_sa
me_csr_outstanding.338226999
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.4178402232
Short name T958
Test name
Test status
Simulation time 362257581 ps
CPU time 3.24 seconds
Started May 02 12:46:51 PM PDT 24
Finished May 02 12:46:58 PM PDT 24
Peak memory 214596 kb
Host smart-ebda1a89-9057-4cc3-93cf-f9759eda0c6f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178402232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.4178402232
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.2119936487
Short name T962
Test name
Test status
Simulation time 2511232429 ps
CPU time 7.15 seconds
Started May 02 12:46:35 PM PDT 24
Finished May 02 12:46:45 PM PDT 24
Peak memory 214640 kb
Host smart-7460d339-4cb1-4f54-8fc2-cb55c3822cb6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119936487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.2119936487
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.888744897
Short name T999
Test name
Test status
Simulation time 164369412 ps
CPU time 2.66 seconds
Started May 02 12:46:51 PM PDT 24
Finished May 02 12:46:57 PM PDT 24
Peak memory 216872 kb
Host smart-4d92f20b-c7e8-4fd2-a1c2-84068f2ebe71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888744897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.888744897
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.2500062035
Short name T168
Test name
Test status
Simulation time 68275238 ps
CPU time 3.62 seconds
Started May 02 12:46:46 PM PDT 24
Finished May 02 12:46:52 PM PDT 24
Peak memory 214268 kb
Host smart-a1bfbee0-d628-4199-9738-c7bb14995a59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500062035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.2500062035
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.3432635565
Short name T981
Test name
Test status
Simulation time 73300685 ps
CPU time 1.38 seconds
Started May 02 12:46:38 PM PDT 24
Finished May 02 12:46:43 PM PDT 24
Peak memory 222468 kb
Host smart-68852894-b55e-4663-be0e-f4421df0bf05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432635565 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.3432635565
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.4035691250
Short name T972
Test name
Test status
Simulation time 14435639 ps
CPU time 1.22 seconds
Started May 02 12:47:22 PM PDT 24
Finished May 02 12:47:27 PM PDT 24
Peak memory 206084 kb
Host smart-ee005269-0234-4e09-a529-b702d18f88c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035691250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.4035691250
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1068851025
Short name T912
Test name
Test status
Simulation time 46500841 ps
CPU time 0.7 seconds
Started May 02 12:46:38 PM PDT 24
Finished May 02 12:46:43 PM PDT 24
Peak memory 205676 kb
Host smart-2dcffd26-f028-4386-bd5e-d998198d726d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068851025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.1068851025
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.2028944456
Short name T1039
Test name
Test status
Simulation time 240620408 ps
CPU time 4.57 seconds
Started May 02 12:46:53 PM PDT 24
Finished May 02 12:47:02 PM PDT 24
Peak memory 206092 kb
Host smart-d1c05021-c132-48b0-9143-9521e60d23bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028944456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.2028944456
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.1853838294
Short name T991
Test name
Test status
Simulation time 420880737 ps
CPU time 4.09 seconds
Started May 02 12:46:36 PM PDT 24
Finished May 02 12:46:43 PM PDT 24
Peak memory 214536 kb
Host smart-62e27459-1bcc-4f63-bcce-0cfb42081751
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853838294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.1853838294
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.965543291
Short name T1017
Test name
Test status
Simulation time 202084853 ps
CPU time 5.25 seconds
Started May 02 12:46:35 PM PDT 24
Finished May 02 12:46:43 PM PDT 24
Peak memory 214568 kb
Host smart-ba0af0f0-eab0-4f6b-a33c-a02a8fa819d4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965543291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
keymgr_shadow_reg_errors_with_csr_rw.965543291
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.3510644012
Short name T938
Test name
Test status
Simulation time 53122337 ps
CPU time 1.95 seconds
Started May 02 12:46:38 PM PDT 24
Finished May 02 12:46:43 PM PDT 24
Peak memory 214880 kb
Host smart-f7b5bc3b-396f-438a-90e1-1ab83bc2eecf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510644012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.3510644012
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.1413796062
Short name T167
Test name
Test status
Simulation time 5228519867 ps
CPU time 32.17 seconds
Started May 02 12:46:34 PM PDT 24
Finished May 02 12:47:08 PM PDT 24
Peak memory 214500 kb
Host smart-3f6f8e92-9567-4c98-bea8-c814e7854420
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413796062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.1413796062
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.4210990647
Short name T973
Test name
Test status
Simulation time 89503683 ps
CPU time 1.43 seconds
Started May 02 12:46:36 PM PDT 24
Finished May 02 12:46:41 PM PDT 24
Peak memory 214304 kb
Host smart-7540185b-aefe-4a41-b888-af8f2788b3cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210990647 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.4210990647
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.446468808
Short name T1018
Test name
Test status
Simulation time 65411213 ps
CPU time 0.97 seconds
Started May 02 12:46:41 PM PDT 24
Finished May 02 12:46:45 PM PDT 24
Peak memory 205960 kb
Host smart-22416d6f-a319-45fd-a075-acf1fb749a93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446468808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.446468808
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.377223625
Short name T920
Test name
Test status
Simulation time 12969247 ps
CPU time 0.74 seconds
Started May 02 12:46:52 PM PDT 24
Finished May 02 12:46:57 PM PDT 24
Peak memory 205752 kb
Host smart-18556865-5c5d-4211-8c10-a8c427afa288
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377223625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.377223625
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.613324077
Short name T134
Test name
Test status
Simulation time 39883751 ps
CPU time 2.17 seconds
Started May 02 12:46:52 PM PDT 24
Finished May 02 12:46:59 PM PDT 24
Peak memory 206056 kb
Host smart-a30fa48f-e821-4473-a374-c440b5d38e5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613324077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_sa
me_csr_outstanding.613324077
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.461640304
Short name T118
Test name
Test status
Simulation time 136528863 ps
CPU time 2.48 seconds
Started May 02 12:46:35 PM PDT 24
Finished May 02 12:46:40 PM PDT 24
Peak memory 214464 kb
Host smart-a81a0e94-864d-424d-94c5-4531920a1586
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461640304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shado
w_reg_errors.461640304
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.783704324
Short name T982
Test name
Test status
Simulation time 196590923 ps
CPU time 4.75 seconds
Started May 02 12:46:38 PM PDT 24
Finished May 02 12:46:46 PM PDT 24
Peak memory 214512 kb
Host smart-d8cb28d2-499c-4de4-a000-1b0901fec716
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783704324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
keymgr_shadow_reg_errors_with_csr_rw.783704324
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.370740156
Short name T939
Test name
Test status
Simulation time 48429327 ps
CPU time 2.02 seconds
Started May 02 12:46:38 PM PDT 24
Finished May 02 12:46:43 PM PDT 24
Peak memory 215264 kb
Host smart-8a7fa9c7-0489-41f6-82a6-ea2612801e39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370740156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.370740156
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.1122407625
Short name T1045
Test name
Test status
Simulation time 186535053 ps
CPU time 4.82 seconds
Started May 02 12:47:25 PM PDT 24
Finished May 02 12:47:33 PM PDT 24
Peak memory 214344 kb
Host smart-dfed3976-73ba-4dd6-99ea-3e2d9574fa98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122407625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.1122407625
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.3428139762
Short name T1040
Test name
Test status
Simulation time 56020067 ps
CPU time 2.1 seconds
Started May 02 12:46:36 PM PDT 24
Finished May 02 12:46:40 PM PDT 24
Peak memory 214200 kb
Host smart-a0adfd9b-3509-4711-8af9-c29f5addad97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428139762 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.3428139762
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.1826772546
Short name T1011
Test name
Test status
Simulation time 80352821 ps
CPU time 0.93 seconds
Started May 02 12:46:52 PM PDT 24
Finished May 02 12:46:56 PM PDT 24
Peak memory 205708 kb
Host smart-eb077834-69a7-4d86-9eb8-2a930945e669
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826772546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.1826772546
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.1338924788
Short name T927
Test name
Test status
Simulation time 14630572 ps
CPU time 0.78 seconds
Started May 02 12:46:51 PM PDT 24
Finished May 02 12:46:55 PM PDT 24
Peak memory 205728 kb
Host smart-2e495e4a-5765-48a0-a33b-85f8ea90338d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338924788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.1338924788
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.11716361
Short name T1048
Test name
Test status
Simulation time 199891484 ps
CPU time 1.82 seconds
Started May 02 12:46:52 PM PDT 24
Finished May 02 12:46:57 PM PDT 24
Peak memory 205932 kb
Host smart-bf5f69ce-c0ea-4bfa-86b3-1adf9ba337b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11716361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_sam
e_csr_outstanding.11716361
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.4062989509
Short name T1034
Test name
Test status
Simulation time 57305651 ps
CPU time 2.44 seconds
Started May 02 12:46:38 PM PDT 24
Finished May 02 12:46:44 PM PDT 24
Peak memory 214524 kb
Host smart-38439f2d-81f1-499d-8b6d-a5570d450e12
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062989509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.4062989509
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2821391393
Short name T1047
Test name
Test status
Simulation time 844222073 ps
CPU time 7.41 seconds
Started May 02 12:46:50 PM PDT 24
Finished May 02 12:47:01 PM PDT 24
Peak memory 220472 kb
Host smart-6aa78abb-02dc-4c84-869f-b641dac3a457
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821391393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.2821391393
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.1725998618
Short name T1005
Test name
Test status
Simulation time 126505655 ps
CPU time 3.65 seconds
Started May 02 12:46:37 PM PDT 24
Finished May 02 12:46:43 PM PDT 24
Peak memory 217404 kb
Host smart-bcdd37a7-9284-4ef9-9fd6-2582f0c848d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725998618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.1725998618
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1277512865
Short name T959
Test name
Test status
Simulation time 27923572 ps
CPU time 1.18 seconds
Started May 02 12:46:44 PM PDT 24
Finished May 02 12:46:48 PM PDT 24
Peak memory 206084 kb
Host smart-f6d29996-83f6-4676-a6c5-02eed779b955
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277512865 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.1277512865
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.2164890082
Short name T952
Test name
Test status
Simulation time 13103346 ps
CPU time 1.15 seconds
Started May 02 12:46:43 PM PDT 24
Finished May 02 12:46:47 PM PDT 24
Peak memory 205984 kb
Host smart-0e6f2593-827d-4052-b2ad-dfbe5b3c978f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164890082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.2164890082
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.3426193927
Short name T918
Test name
Test status
Simulation time 42547158 ps
CPU time 0.75 seconds
Started May 02 12:46:52 PM PDT 24
Finished May 02 12:46:56 PM PDT 24
Peak memory 205688 kb
Host smart-764d9d5b-b622-4a5f-85fb-07c42d8aed28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426193927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.3426193927
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.2716283955
Short name T1035
Test name
Test status
Simulation time 74387337 ps
CPU time 2.18 seconds
Started May 02 12:47:07 PM PDT 24
Finished May 02 12:47:11 PM PDT 24
Peak memory 206000 kb
Host smart-86a56aa9-2e60-43cd-a2e0-94ad8f554646
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716283955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.2716283955
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3665185783
Short name T1022
Test name
Test status
Simulation time 316173014 ps
CPU time 2.75 seconds
Started May 02 12:46:52 PM PDT 24
Finished May 02 12:46:58 PM PDT 24
Peak memory 214484 kb
Host smart-1048062e-d2e1-4b08-b88a-0bade045172a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665185783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.3665185783
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1367756039
Short name T964
Test name
Test status
Simulation time 350545818 ps
CPU time 5.03 seconds
Started May 02 12:46:46 PM PDT 24
Finished May 02 12:46:53 PM PDT 24
Peak memory 214548 kb
Host smart-ffcedd4c-94c0-403c-9c0a-f995ce697e02
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367756039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.1367756039
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.705360114
Short name T1052
Test name
Test status
Simulation time 236729898 ps
CPU time 2.57 seconds
Started May 02 12:46:42 PM PDT 24
Finished May 02 12:46:48 PM PDT 24
Peak memory 222436 kb
Host smart-01a6eee5-5888-4d11-8a66-56a2643b66f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705360114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.705360114
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.4212036778
Short name T1078
Test name
Test status
Simulation time 509455853 ps
CPU time 8.83 seconds
Started May 02 12:46:43 PM PDT 24
Finished May 02 12:46:55 PM PDT 24
Peak memory 205992 kb
Host smart-361e1fa3-6d4a-4596-a684-5236a4f6e788
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212036778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.4
212036778
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.3929761580
Short name T1053
Test name
Test status
Simulation time 436999588 ps
CPU time 12.73 seconds
Started May 02 12:46:22 PM PDT 24
Finished May 02 12:46:37 PM PDT 24
Peak memory 205988 kb
Host smart-f38df476-0962-4744-b0a5-6c6e1a5a7990
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929761580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.3
929761580
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.4162036983
Short name T1026
Test name
Test status
Simulation time 20776196 ps
CPU time 0.91 seconds
Started May 02 12:46:40 PM PDT 24
Finished May 02 12:46:44 PM PDT 24
Peak memory 205836 kb
Host smart-ed1c17ff-9085-4eb1-b5a9-5e5e69005ea1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162036983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.4
162036983
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1688813952
Short name T960
Test name
Test status
Simulation time 25162492 ps
CPU time 1.55 seconds
Started May 02 12:46:25 PM PDT 24
Finished May 02 12:46:29 PM PDT 24
Peak memory 214200 kb
Host smart-b4e37b6e-c04a-49ff-9540-86ef05698d12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688813952 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.1688813952
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.170858322
Short name T1033
Test name
Test status
Simulation time 33895951 ps
CPU time 1.13 seconds
Started May 02 12:46:37 PM PDT 24
Finished May 02 12:46:41 PM PDT 24
Peak memory 205824 kb
Host smart-f21d94dd-09d8-46e6-a7b7-a95a4e278be9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170858322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.170858322
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.3238842328
Short name T933
Test name
Test status
Simulation time 60512623 ps
CPU time 0.73 seconds
Started May 02 12:46:38 PM PDT 24
Finished May 02 12:46:43 PM PDT 24
Peak memory 205668 kb
Host smart-159e1acc-e854-4b82-9347-7dcd6293823a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238842328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.3238842328
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.1082701886
Short name T1037
Test name
Test status
Simulation time 144590826 ps
CPU time 2.56 seconds
Started May 02 12:46:25 PM PDT 24
Finished May 02 12:46:29 PM PDT 24
Peak memory 206052 kb
Host smart-f3ad7d59-e33c-463e-923b-c46b780d6eb1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082701886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.1082701886
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.1652761259
Short name T117
Test name
Test status
Simulation time 294550408 ps
CPU time 2.59 seconds
Started May 02 12:46:51 PM PDT 24
Finished May 02 12:46:57 PM PDT 24
Peak memory 222696 kb
Host smart-877dc915-7750-495c-bc66-d3969f98e3b0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652761259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.1652761259
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.3185545546
Short name T995
Test name
Test status
Simulation time 185725887 ps
CPU time 4.62 seconds
Started May 02 12:46:21 PM PDT 24
Finished May 02 12:46:28 PM PDT 24
Peak memory 220308 kb
Host smart-e9213762-b919-4fdc-8c89-9ef7fef7bcc4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185545546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.3185545546
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.78268098
Short name T908
Test name
Test status
Simulation time 368631234 ps
CPU time 2.16 seconds
Started May 02 12:46:36 PM PDT 24
Finished May 02 12:46:41 PM PDT 24
Peak memory 214168 kb
Host smart-7ef949c0-4845-4aeb-bdc3-9e4ef590aa98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78268098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.78268098
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.3963488583
Short name T173
Test name
Test status
Simulation time 269193420 ps
CPU time 5.43 seconds
Started May 02 12:46:27 PM PDT 24
Finished May 02 12:46:35 PM PDT 24
Peak memory 214320 kb
Host smart-6e0d1152-d4ad-4793-8204-db02dc23c0ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963488583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.3963488583
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.1754031589
Short name T926
Test name
Test status
Simulation time 13947090 ps
CPU time 0.88 seconds
Started May 02 12:46:43 PM PDT 24
Finished May 02 12:46:46 PM PDT 24
Peak memory 205916 kb
Host smart-0064af7b-d667-4163-b421-c41792258a55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754031589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.1754031589
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1688324870
Short name T1027
Test name
Test status
Simulation time 28990622 ps
CPU time 0.75 seconds
Started May 02 12:46:46 PM PDT 24
Finished May 02 12:46:49 PM PDT 24
Peak memory 205764 kb
Host smart-bebf1ffb-9b52-4b8c-9e7d-02a759643925
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688324870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.1688324870
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.308539577
Short name T907
Test name
Test status
Simulation time 9834093 ps
CPU time 0.82 seconds
Started May 02 12:46:53 PM PDT 24
Finished May 02 12:46:58 PM PDT 24
Peak memory 205648 kb
Host smart-528caea0-8922-445d-900d-68452043dc62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308539577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.308539577
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.4043561907
Short name T961
Test name
Test status
Simulation time 22233307 ps
CPU time 0.84 seconds
Started May 02 12:46:43 PM PDT 24
Finished May 02 12:46:47 PM PDT 24
Peak memory 205724 kb
Host smart-ca1d6733-6595-4c1b-9499-b2482cc02448
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043561907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.4043561907
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.3032540283
Short name T937
Test name
Test status
Simulation time 34526376 ps
CPU time 0.81 seconds
Started May 02 12:46:55 PM PDT 24
Finished May 02 12:47:00 PM PDT 24
Peak memory 205720 kb
Host smart-e5b1359c-987a-4878-8bf7-0921aca886d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032540283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.3032540283
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.1168063404
Short name T980
Test name
Test status
Simulation time 32230017 ps
CPU time 0.73 seconds
Started May 02 12:47:04 PM PDT 24
Finished May 02 12:47:06 PM PDT 24
Peak memory 205676 kb
Host smart-e08f507d-bf60-4fe3-8e2a-69163732a2de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168063404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.1168063404
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.216720053
Short name T1012
Test name
Test status
Simulation time 13257390 ps
CPU time 0.87 seconds
Started May 02 12:47:15 PM PDT 24
Finished May 02 12:47:20 PM PDT 24
Peak memory 205772 kb
Host smart-2cf63fc0-ea2c-4b60-96e8-bd96b579ff4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216720053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.216720053
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.3565892553
Short name T1038
Test name
Test status
Simulation time 12202310 ps
CPU time 0.78 seconds
Started May 02 12:46:53 PM PDT 24
Finished May 02 12:46:58 PM PDT 24
Peak memory 205672 kb
Host smart-931e7783-b8a2-4c40-b620-de4532c80c05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565892553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.3565892553
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.2112036500
Short name T987
Test name
Test status
Simulation time 8280165 ps
CPU time 0.81 seconds
Started May 02 12:47:06 PM PDT 24
Finished May 02 12:47:09 PM PDT 24
Peak memory 205860 kb
Host smart-eb3b71d1-e52f-4306-8b2c-aa08ef80477f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112036500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.2112036500
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.1138996246
Short name T917
Test name
Test status
Simulation time 41118251 ps
CPU time 0.74 seconds
Started May 02 12:47:04 PM PDT 24
Finished May 02 12:47:06 PM PDT 24
Peak memory 205728 kb
Host smart-530ccf77-c1e0-4485-8c28-88c6506c9f83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138996246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.1138996246
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.3047038021
Short name T923
Test name
Test status
Simulation time 472657218 ps
CPU time 11.28 seconds
Started May 02 12:46:25 PM PDT 24
Finished May 02 12:46:38 PM PDT 24
Peak memory 205968 kb
Host smart-ed46401c-1cc3-4b69-b4b7-3f1f79843cc8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047038021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.3
047038021
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.726714967
Short name T946
Test name
Test status
Simulation time 519724573 ps
CPU time 12.5 seconds
Started May 02 12:46:39 PM PDT 24
Finished May 02 12:46:55 PM PDT 24
Peak memory 205964 kb
Host smart-cb053ee8-a51d-4104-b265-29b44467b453
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726714967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.726714967
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.2749875196
Short name T911
Test name
Test status
Simulation time 12108485 ps
CPU time 1 seconds
Started May 02 12:46:48 PM PDT 24
Finished May 02 12:46:50 PM PDT 24
Peak memory 205996 kb
Host smart-73dd0383-b625-4f32-8c9a-9e0833b92648
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749875196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.2
749875196
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.386129238
Short name T1007
Test name
Test status
Simulation time 37681578 ps
CPU time 1.31 seconds
Started May 02 12:46:24 PM PDT 24
Finished May 02 12:46:27 PM PDT 24
Peak memory 206148 kb
Host smart-bce49bbc-a6d0-4241-9439-d4d52f72559a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386129238 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.386129238
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.3498841045
Short name T132
Test name
Test status
Simulation time 135885509 ps
CPU time 1.62 seconds
Started May 02 12:46:27 PM PDT 24
Finished May 02 12:46:31 PM PDT 24
Peak memory 205984 kb
Host smart-3c879aed-8d3e-47eb-b790-0551a480c1cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498841045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.3498841045
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.718125665
Short name T988
Test name
Test status
Simulation time 17812562 ps
CPU time 0.73 seconds
Started May 02 12:46:52 PM PDT 24
Finished May 02 12:46:57 PM PDT 24
Peak memory 205712 kb
Host smart-aaa03365-c84f-4a22-9f72-a3434cb554eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718125665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.718125665
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.1522311402
Short name T1025
Test name
Test status
Simulation time 107404505 ps
CPU time 2.94 seconds
Started May 02 12:46:26 PM PDT 24
Finished May 02 12:46:31 PM PDT 24
Peak memory 206048 kb
Host smart-98d273f1-4fb9-4776-8403-66398827236d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522311402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.1522311402
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1574630099
Short name T1000
Test name
Test status
Simulation time 1515007326 ps
CPU time 4.43 seconds
Started May 02 12:46:41 PM PDT 24
Finished May 02 12:46:49 PM PDT 24
Peak memory 214532 kb
Host smart-52fe7700-09e5-4174-8592-031fae30ab48
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574630099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.1574630099
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.3500950993
Short name T983
Test name
Test status
Simulation time 290577434 ps
CPU time 3.75 seconds
Started May 02 12:46:23 PM PDT 24
Finished May 02 12:46:29 PM PDT 24
Peak memory 214588 kb
Host smart-313ce81a-bce7-4c2e-8c9b-17a9915106dd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500950993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.3500950993
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.3932040551
Short name T1075
Test name
Test status
Simulation time 201515752 ps
CPU time 3.67 seconds
Started May 02 12:46:24 PM PDT 24
Finished May 02 12:46:30 PM PDT 24
Peak memory 216868 kb
Host smart-e4d9ced1-a3da-469d-bc73-472014bf9486
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932040551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.3932040551
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.185703125
Short name T1068
Test name
Test status
Simulation time 15475743 ps
CPU time 0.82 seconds
Started May 02 12:46:47 PM PDT 24
Finished May 02 12:46:50 PM PDT 24
Peak memory 205764 kb
Host smart-982772db-ffa2-461a-92af-f223a407ce6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185703125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.185703125
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.1376997897
Short name T919
Test name
Test status
Simulation time 16944401 ps
CPU time 0.87 seconds
Started May 02 12:46:52 PM PDT 24
Finished May 02 12:46:57 PM PDT 24
Peak memory 205760 kb
Host smart-1191f936-4f77-4a11-909c-80834ba28241
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376997897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.1376997897
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.703302955
Short name T949
Test name
Test status
Simulation time 12652254 ps
CPU time 0.72 seconds
Started May 02 12:46:52 PM PDT 24
Finished May 02 12:46:57 PM PDT 24
Peak memory 205720 kb
Host smart-1818e7b9-c270-4f3c-a41e-9b0428e71a22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703302955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.703302955
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.2318792515
Short name T1003
Test name
Test status
Simulation time 11005047 ps
CPU time 0.86 seconds
Started May 02 12:46:50 PM PDT 24
Finished May 02 12:46:54 PM PDT 24
Peak memory 205684 kb
Host smart-119dbe1b-f1cf-4207-a0fe-11570da29ac2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318792515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.2318792515
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1259603630
Short name T909
Test name
Test status
Simulation time 13045551 ps
CPU time 0.76 seconds
Started May 02 12:47:20 PM PDT 24
Finished May 02 12:47:25 PM PDT 24
Peak memory 205748 kb
Host smart-e46b9b3f-fcf2-4693-8afd-75315c3dec07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259603630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.1259603630
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.3961248760
Short name T993
Test name
Test status
Simulation time 55843485 ps
CPU time 0.78 seconds
Started May 02 12:46:55 PM PDT 24
Finished May 02 12:47:00 PM PDT 24
Peak memory 205732 kb
Host smart-a99a1ac0-d787-4213-982f-fac249ea5c0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961248760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.3961248760
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.1698993308
Short name T994
Test name
Test status
Simulation time 34849883 ps
CPU time 0.77 seconds
Started May 02 12:46:43 PM PDT 24
Finished May 02 12:46:47 PM PDT 24
Peak memory 205764 kb
Host smart-38baeb32-c40c-4f24-b3c0-a45da2a61133
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698993308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.1698993308
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.2462685608
Short name T914
Test name
Test status
Simulation time 43874724 ps
CPU time 0.8 seconds
Started May 02 12:46:43 PM PDT 24
Finished May 02 12:46:46 PM PDT 24
Peak memory 205784 kb
Host smart-9190147b-62a2-45e5-a797-10b4980de70e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462685608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.2462685608
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.541981005
Short name T932
Test name
Test status
Simulation time 17359606 ps
CPU time 0.8 seconds
Started May 02 12:46:52 PM PDT 24
Finished May 02 12:46:57 PM PDT 24
Peak memory 205672 kb
Host smart-11ddc6da-edeb-48b0-9428-b3f2aa5e6240
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541981005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.541981005
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.2747561269
Short name T966
Test name
Test status
Simulation time 38509932 ps
CPU time 0.86 seconds
Started May 02 12:46:45 PM PDT 24
Finished May 02 12:46:48 PM PDT 24
Peak memory 205760 kb
Host smart-d54eddf7-a953-4f35-8100-9c3ea143067d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747561269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.2747561269
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.4010947934
Short name T1044
Test name
Test status
Simulation time 183422342 ps
CPU time 6.9 seconds
Started May 02 12:46:51 PM PDT 24
Finished May 02 12:47:02 PM PDT 24
Peak memory 205996 kb
Host smart-ad1fa8bb-d3ba-4195-8c7b-72d1e9814f11
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010947934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.4
010947934
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1459100142
Short name T985
Test name
Test status
Simulation time 7221511417 ps
CPU time 11.81 seconds
Started May 02 12:46:50 PM PDT 24
Finished May 02 12:47:05 PM PDT 24
Peak memory 206136 kb
Host smart-e64df36d-deb5-44cf-985b-cba4d749d415
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459100142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.1
459100142
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.2836471649
Short name T930
Test name
Test status
Simulation time 33187132 ps
CPU time 1.1 seconds
Started May 02 12:46:24 PM PDT 24
Finished May 02 12:46:27 PM PDT 24
Peak memory 205944 kb
Host smart-6907f885-8e06-4853-9bd7-ff3ada09a18f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836471649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.2
836471649
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.254747204
Short name T1010
Test name
Test status
Simulation time 114537630 ps
CPU time 1.18 seconds
Started May 02 12:46:36 PM PDT 24
Finished May 02 12:46:40 PM PDT 24
Peak memory 206180 kb
Host smart-ef7f05cb-c3d4-4a6c-a292-e9b4f21c47d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254747204 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.254747204
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.1498773165
Short name T968
Test name
Test status
Simulation time 110132830 ps
CPU time 1.26 seconds
Started May 02 12:46:29 PM PDT 24
Finished May 02 12:46:34 PM PDT 24
Peak memory 205956 kb
Host smart-a0edd0a7-0be3-4935-8da2-dec196f4a009
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498773165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.1498773165
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.2788336468
Short name T922
Test name
Test status
Simulation time 35821290 ps
CPU time 0.8 seconds
Started May 02 12:46:30 PM PDT 24
Finished May 02 12:46:34 PM PDT 24
Peak memory 205688 kb
Host smart-1891b112-5612-4b0e-a13d-6c1b7050bd3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788336468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.2788336468
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2682660343
Short name T135
Test name
Test status
Simulation time 89000945 ps
CPU time 3.48 seconds
Started May 02 12:46:28 PM PDT 24
Finished May 02 12:46:34 PM PDT 24
Peak memory 206044 kb
Host smart-e684b422-9714-40f6-9291-a76e1301a3a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682660343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.2682660343
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.2031149930
Short name T974
Test name
Test status
Simulation time 219586287 ps
CPU time 4.81 seconds
Started May 02 12:46:50 PM PDT 24
Finished May 02 12:46:58 PM PDT 24
Peak memory 214564 kb
Host smart-8118041c-ad02-4593-8832-3e34abc3d8d3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031149930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.2031149930
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.2171399165
Short name T1058
Test name
Test status
Simulation time 421527861 ps
CPU time 14.67 seconds
Started May 02 12:46:41 PM PDT 24
Finished May 02 12:46:59 PM PDT 24
Peak memory 214488 kb
Host smart-93121151-c1e9-4605-aea6-ea8afd517c26
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171399165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.2171399165
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.2433190270
Short name T1069
Test name
Test status
Simulation time 49235186 ps
CPU time 2.72 seconds
Started May 02 12:46:40 PM PDT 24
Finished May 02 12:46:47 PM PDT 24
Peak memory 214280 kb
Host smart-b6d9f3e0-5257-44aa-927f-b055449b19f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433190270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.2433190270
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.708988075
Short name T944
Test name
Test status
Simulation time 224116035 ps
CPU time 6.1 seconds
Started May 02 12:46:24 PM PDT 24
Finished May 02 12:46:32 PM PDT 24
Peak memory 209248 kb
Host smart-81bcb1e6-f7da-41e2-956b-29bf89972e93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708988075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err.
708988075
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.141020668
Short name T1032
Test name
Test status
Simulation time 9785849 ps
CPU time 0.79 seconds
Started May 02 12:46:52 PM PDT 24
Finished May 02 12:46:56 PM PDT 24
Peak memory 205768 kb
Host smart-9de905ae-d8d1-4fa2-87d2-39416843eff0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141020668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.141020668
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.1680941717
Short name T913
Test name
Test status
Simulation time 10081563 ps
CPU time 0.74 seconds
Started May 02 12:46:54 PM PDT 24
Finished May 02 12:46:59 PM PDT 24
Peak memory 205668 kb
Host smart-67c8b977-c7da-41e2-a2f9-72ea08f87d54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680941717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.1680941717
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.3207156626
Short name T1072
Test name
Test status
Simulation time 27930053 ps
CPU time 0.76 seconds
Started May 02 12:46:52 PM PDT 24
Finished May 02 12:46:56 PM PDT 24
Peak memory 205760 kb
Host smart-ca27653c-01aa-4f16-be83-66441f50f63a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207156626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.3207156626
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.2419932652
Short name T1060
Test name
Test status
Simulation time 24759271 ps
CPU time 0.78 seconds
Started May 02 12:46:58 PM PDT 24
Finished May 02 12:47:02 PM PDT 24
Peak memory 205700 kb
Host smart-6b66f693-5572-47d7-9de6-69811558cd47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419932652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.2419932652
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1573940463
Short name T929
Test name
Test status
Simulation time 39051185 ps
CPU time 0.82 seconds
Started May 02 12:47:12 PM PDT 24
Finished May 02 12:47:16 PM PDT 24
Peak memory 205720 kb
Host smart-a3a92d82-02fe-4316-9446-66e607a2cc75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573940463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.1573940463
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.1534683649
Short name T1059
Test name
Test status
Simulation time 33375161 ps
CPU time 0.73 seconds
Started May 02 12:46:45 PM PDT 24
Finished May 02 12:46:48 PM PDT 24
Peak memory 205692 kb
Host smart-bdefb201-0a6c-450f-899d-bffc3670c4ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534683649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.1534683649
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.4134793671
Short name T1043
Test name
Test status
Simulation time 53470909 ps
CPU time 0.75 seconds
Started May 02 12:46:46 PM PDT 24
Finished May 02 12:46:49 PM PDT 24
Peak memory 205748 kb
Host smart-ad8b1a6f-6974-466e-9090-8a642cae09d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134793671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.4134793671
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.4228183649
Short name T975
Test name
Test status
Simulation time 8918664 ps
CPU time 0.71 seconds
Started May 02 12:46:53 PM PDT 24
Finished May 02 12:46:59 PM PDT 24
Peak memory 205756 kb
Host smart-a80c671b-2326-4ef9-9a28-3f8663570653
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228183649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.4228183649
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.566241487
Short name T997
Test name
Test status
Simulation time 9415024 ps
CPU time 0.69 seconds
Started May 02 12:47:03 PM PDT 24
Finished May 02 12:47:05 PM PDT 24
Peak memory 205812 kb
Host smart-67ec4ded-2505-4231-9642-73fd5cfe3ed2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566241487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.566241487
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.4181682583
Short name T954
Test name
Test status
Simulation time 11500195 ps
CPU time 0.71 seconds
Started May 02 12:46:54 PM PDT 24
Finished May 02 12:46:59 PM PDT 24
Peak memory 205692 kb
Host smart-ef05549a-3867-4292-b242-982f0ddd3d2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181682583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.4181682583
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3198400611
Short name T1077
Test name
Test status
Simulation time 94300627 ps
CPU time 1.19 seconds
Started May 02 12:46:27 PM PDT 24
Finished May 02 12:46:30 PM PDT 24
Peak memory 206124 kb
Host smart-b1d3937d-3c63-40d5-836c-da3b8d3df4ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198400611 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.3198400611
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.2768897310
Short name T963
Test name
Test status
Simulation time 22759828 ps
CPU time 1.08 seconds
Started May 02 12:46:49 PM PDT 24
Finished May 02 12:46:52 PM PDT 24
Peak memory 205836 kb
Host smart-7ea47259-080d-4ac3-8804-060972dbb7e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768897310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.2768897310
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.3326817218
Short name T977
Test name
Test status
Simulation time 39213181 ps
CPU time 0.83 seconds
Started May 02 12:46:54 PM PDT 24
Finished May 02 12:47:00 PM PDT 24
Peak memory 205728 kb
Host smart-347934b5-ce01-42f1-851d-36e351c0d434
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326817218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.3326817218
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.2023817650
Short name T986
Test name
Test status
Simulation time 340353194 ps
CPU time 2.67 seconds
Started May 02 12:46:45 PM PDT 24
Finished May 02 12:46:50 PM PDT 24
Peak memory 206112 kb
Host smart-92d67cbb-27a2-45c6-943b-456012b7f16e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023817650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.2023817650
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.2385154511
Short name T969
Test name
Test status
Simulation time 110818764 ps
CPU time 2.4 seconds
Started May 02 12:46:33 PM PDT 24
Finished May 02 12:46:38 PM PDT 24
Peak memory 222696 kb
Host smart-9b951333-d6bc-4494-999b-c8bb117cc68f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385154511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.2385154511
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.1013890359
Short name T138
Test name
Test status
Simulation time 963674860 ps
CPU time 5.36 seconds
Started May 02 12:46:49 PM PDT 24
Finished May 02 12:46:57 PM PDT 24
Peak memory 214500 kb
Host smart-0857f3ae-b569-418c-8daa-01c52e9aa905
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013890359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.1013890359
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.1823102110
Short name T1067
Test name
Test status
Simulation time 468291094 ps
CPU time 2.26 seconds
Started May 02 12:46:31 PM PDT 24
Finished May 02 12:46:37 PM PDT 24
Peak memory 214252 kb
Host smart-81565ae9-c766-43a6-8412-455666bee8f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823102110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.1823102110
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.2538818002
Short name T170
Test name
Test status
Simulation time 4212312122 ps
CPU time 39.78 seconds
Started May 02 12:46:49 PM PDT 24
Finished May 02 12:47:31 PM PDT 24
Peak memory 214396 kb
Host smart-f9ad4a23-d37f-4a9b-8972-ea07c3c35082
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538818002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.2538818002
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1569962884
Short name T1029
Test name
Test status
Simulation time 61332488 ps
CPU time 2.2 seconds
Started May 02 12:46:50 PM PDT 24
Finished May 02 12:46:55 PM PDT 24
Peak memory 214328 kb
Host smart-e7c91e80-2b97-4b75-b68e-ebf32d8f40ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569962884 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.1569962884
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.2207171334
Short name T1054
Test name
Test status
Simulation time 13246411 ps
CPU time 0.9 seconds
Started May 02 12:46:38 PM PDT 24
Finished May 02 12:46:42 PM PDT 24
Peak memory 205716 kb
Host smart-6903e49f-2d6d-4343-9333-22d10ed44b5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207171334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.2207171334
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.1183923433
Short name T1066
Test name
Test status
Simulation time 32078234 ps
CPU time 0.72 seconds
Started May 02 12:46:25 PM PDT 24
Finished May 02 12:46:27 PM PDT 24
Peak memory 205676 kb
Host smart-f866dd1c-1c5d-4e31-aba9-904c7864f6f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183923433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.1183923433
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.3395785815
Short name T1079
Test name
Test status
Simulation time 193220006 ps
CPU time 1.57 seconds
Started May 02 12:46:29 PM PDT 24
Finished May 02 12:46:33 PM PDT 24
Peak memory 206012 kb
Host smart-e7817096-9d50-48a3-b6b3-4bcd7854fa0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395785815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.3395785815
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.860102837
Short name T1065
Test name
Test status
Simulation time 326782876 ps
CPU time 3.29 seconds
Started May 02 12:46:24 PM PDT 24
Finished May 02 12:46:29 PM PDT 24
Peak memory 214532 kb
Host smart-f8adfa76-99c5-4e63-a6d8-4675324b9152
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860102837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow
_reg_errors.860102837
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.2987837873
Short name T1002
Test name
Test status
Simulation time 170703572 ps
CPU time 8.93 seconds
Started May 02 12:46:26 PM PDT 24
Finished May 02 12:46:37 PM PDT 24
Peak memory 214520 kb
Host smart-e2b012dc-6f6f-4248-af21-4898e3cdc8fa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987837873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.2987837873
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.1443505860
Short name T1061
Test name
Test status
Simulation time 583896340 ps
CPU time 5.08 seconds
Started May 02 12:46:24 PM PDT 24
Finished May 02 12:46:31 PM PDT 24
Peak memory 214156 kb
Host smart-fd210c32-ab9b-4c82-a979-4f24b844eb63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443505860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.1443505860
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2379438054
Short name T1070
Test name
Test status
Simulation time 482474361 ps
CPU time 12.05 seconds
Started May 02 12:46:47 PM PDT 24
Finished May 02 12:47:01 PM PDT 24
Peak memory 209608 kb
Host smart-18339a7c-0476-44ed-8d5a-45f94a6abaec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379438054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.2379438054
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.479050784
Short name T1063
Test name
Test status
Simulation time 122744004 ps
CPU time 1.61 seconds
Started May 02 12:46:38 PM PDT 24
Finished May 02 12:46:43 PM PDT 24
Peak memory 214212 kb
Host smart-54ca5f53-2334-4602-a0ea-3c84306ad970
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479050784 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.479050784
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.3005314267
Short name T955
Test name
Test status
Simulation time 99517916 ps
CPU time 1.04 seconds
Started May 02 12:46:40 PM PDT 24
Finished May 02 12:46:44 PM PDT 24
Peak memory 205820 kb
Host smart-20c82d5b-8334-48a7-93f0-2b8c40efe7ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005314267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.3005314267
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.1353902114
Short name T996
Test name
Test status
Simulation time 141938649 ps
CPU time 0.76 seconds
Started May 02 12:46:44 PM PDT 24
Finished May 02 12:46:47 PM PDT 24
Peak memory 205760 kb
Host smart-35f7168a-d47f-4387-8850-6b577eb3b14b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353902114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.1353902114
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2062089377
Short name T956
Test name
Test status
Simulation time 251825897 ps
CPU time 2.73 seconds
Started May 02 12:46:49 PM PDT 24
Finished May 02 12:46:53 PM PDT 24
Peak memory 206008 kb
Host smart-fdf48ec4-1ac7-4de7-a371-911f671ff18d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062089377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.2062089377
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.2169693164
Short name T113
Test name
Test status
Simulation time 1046006392 ps
CPU time 10.04 seconds
Started May 02 12:46:43 PM PDT 24
Finished May 02 12:46:55 PM PDT 24
Peak memory 214504 kb
Host smart-7276854e-14b5-459a-830d-fece65360303
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169693164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.2169693164
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.2578437022
Short name T1071
Test name
Test status
Simulation time 418343779 ps
CPU time 7.52 seconds
Started May 02 12:46:21 PM PDT 24
Finished May 02 12:46:31 PM PDT 24
Peak memory 214580 kb
Host smart-c737cdaa-da17-4071-bac9-32926dea196f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578437022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.2578437022
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.2961034677
Short name T1042
Test name
Test status
Simulation time 126746005 ps
CPU time 4.43 seconds
Started May 02 12:46:24 PM PDT 24
Finished May 02 12:46:30 PM PDT 24
Peak memory 214144 kb
Host smart-a5640584-95d5-4c90-82fd-e8e6a04340e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961034677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.2961034677
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.456906761
Short name T998
Test name
Test status
Simulation time 85253869 ps
CPU time 1.04 seconds
Started May 02 12:46:51 PM PDT 24
Finished May 02 12:46:56 PM PDT 24
Peak memory 205888 kb
Host smart-b53c5bbb-9232-47ba-abe4-365ee606c567
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456906761 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.456906761
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.731709963
Short name T941
Test name
Test status
Simulation time 53923035 ps
CPU time 1.11 seconds
Started May 02 12:46:46 PM PDT 24
Finished May 02 12:46:49 PM PDT 24
Peak memory 205852 kb
Host smart-78454678-ed40-43b2-aaa9-7c4462f705b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731709963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.731709963
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.1843098152
Short name T916
Test name
Test status
Simulation time 44253395 ps
CPU time 0.87 seconds
Started May 02 12:46:39 PM PDT 24
Finished May 02 12:46:44 PM PDT 24
Peak memory 205672 kb
Host smart-43dba2d4-0e49-4f9f-9f65-08a84314168a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843098152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.1843098152
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.213624669
Short name T989
Test name
Test status
Simulation time 233519181 ps
CPU time 3.38 seconds
Started May 02 12:46:29 PM PDT 24
Finished May 02 12:46:36 PM PDT 24
Peak memory 206104 kb
Host smart-be9baf66-dae1-48e8-86bf-88e36239fe1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213624669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sam
e_csr_outstanding.213624669
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2262234102
Short name T967
Test name
Test status
Simulation time 100034938 ps
CPU time 3.29 seconds
Started May 02 12:46:28 PM PDT 24
Finished May 02 12:46:33 PM PDT 24
Peak memory 222640 kb
Host smart-3d814a3e-b811-452b-b188-ae48a124f9c4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262234102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.2262234102
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.3332003549
Short name T116
Test name
Test status
Simulation time 330992961 ps
CPU time 4.61 seconds
Started May 02 12:46:49 PM PDT 24
Finished May 02 12:46:55 PM PDT 24
Peak memory 214572 kb
Host smart-48ec8a86-0c29-4eb8-b5ab-84f5f72e7d70
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332003549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.3332003549
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.496711398
Short name T1020
Test name
Test status
Simulation time 264149745 ps
CPU time 2.14 seconds
Started May 02 12:46:31 PM PDT 24
Finished May 02 12:46:37 PM PDT 24
Peak memory 214196 kb
Host smart-7b5e3d0d-dc81-4b66-99ca-eaf9b0fc14cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496711398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.496711398
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2907617748
Short name T1051
Test name
Test status
Simulation time 97773582 ps
CPU time 1.38 seconds
Started May 02 12:46:48 PM PDT 24
Finished May 02 12:46:51 PM PDT 24
Peak memory 214352 kb
Host smart-7a5a7199-85de-4cc2-851d-671f933c39fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907617748 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.2907617748
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.214668144
Short name T137
Test name
Test status
Simulation time 23723477 ps
CPU time 1.43 seconds
Started May 02 12:46:48 PM PDT 24
Finished May 02 12:46:51 PM PDT 24
Peak memory 205860 kb
Host smart-854076ee-3cba-4f24-8e2d-874d8f5476ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214668144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.214668144
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.121924901
Short name T921
Test name
Test status
Simulation time 19140764 ps
CPU time 0.74 seconds
Started May 02 12:46:32 PM PDT 24
Finished May 02 12:46:36 PM PDT 24
Peak memory 205772 kb
Host smart-9644459b-e6f8-44f3-aaf8-287704856226
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121924901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.121924901
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.3912629237
Short name T957
Test name
Test status
Simulation time 326235806 ps
CPU time 2.63 seconds
Started May 02 12:46:32 PM PDT 24
Finished May 02 12:46:37 PM PDT 24
Peak memory 206064 kb
Host smart-ebebef66-da5e-4b20-9305-25df2f5a9458
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912629237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.3912629237
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.565546522
Short name T1030
Test name
Test status
Simulation time 609592081 ps
CPU time 4.76 seconds
Started May 02 12:46:53 PM PDT 24
Finished May 02 12:47:03 PM PDT 24
Peak memory 219492 kb
Host smart-69f25324-5483-4a07-adb2-ec51552a3096
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565546522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow
_reg_errors.565546522
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1653833460
Short name T948
Test name
Test status
Simulation time 2805255340 ps
CPU time 4.98 seconds
Started May 02 12:46:56 PM PDT 24
Finished May 02 12:47:05 PM PDT 24
Peak memory 214728 kb
Host smart-9cc02ec8-15ba-46fd-a1be-a8df30f04254
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653833460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.1653833460
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.231610903
Short name T915
Test name
Test status
Simulation time 84253495 ps
CPU time 1.79 seconds
Started May 02 12:46:47 PM PDT 24
Finished May 02 12:46:50 PM PDT 24
Peak memory 216408 kb
Host smart-b63e1803-1c82-46f4-9fa1-346f8c521854
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231610903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.231610903
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.2989888099
Short name T152
Test name
Test status
Simulation time 279111150 ps
CPU time 5.07 seconds
Started May 02 12:46:52 PM PDT 24
Finished May 02 12:47:02 PM PDT 24
Peak memory 209188 kb
Host smart-8d405895-541d-46e0-ae57-7a8bc64203ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989888099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.2989888099
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.3664209874
Short name T448
Test name
Test status
Simulation time 17694005 ps
CPU time 0.95 seconds
Started May 02 12:47:18 PM PDT 24
Finished May 02 12:47:23 PM PDT 24
Peak memory 205768 kb
Host smart-602c0af2-32f3-40e7-b81d-28778ed98ff3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664209874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.3664209874
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.2943710557
Short name T422
Test name
Test status
Simulation time 46386202 ps
CPU time 3.27 seconds
Started May 02 12:47:19 PM PDT 24
Finished May 02 12:47:26 PM PDT 24
Peak memory 214956 kb
Host smart-2e263319-704b-4a7d-a6a5-fefbeef61411
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2943710557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.2943710557
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.2149984431
Short name T278
Test name
Test status
Simulation time 184378028 ps
CPU time 3.21 seconds
Started May 02 12:47:41 PM PDT 24
Finished May 02 12:47:47 PM PDT 24
Peak memory 209936 kb
Host smart-94083a16-dc9e-4227-9d8a-5306182ece6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149984431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.2149984431
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.2766677307
Short name T96
Test name
Test status
Simulation time 135984552 ps
CPU time 6.6 seconds
Started May 02 12:47:30 PM PDT 24
Finished May 02 12:47:39 PM PDT 24
Peak memory 222100 kb
Host smart-c3d365e5-2bef-43b2-847c-f012039ad7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766677307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.2766677307
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.4190227097
Short name T710
Test name
Test status
Simulation time 70902196 ps
CPU time 3.54 seconds
Started May 02 12:47:32 PM PDT 24
Finished May 02 12:47:38 PM PDT 24
Peak memory 209148 kb
Host smart-f92bef96-108f-41ec-883c-59598a26818f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190227097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.4190227097
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.1039223288
Short name T615
Test name
Test status
Simulation time 454885376 ps
CPU time 5.51 seconds
Started May 02 12:47:21 PM PDT 24
Finished May 02 12:47:30 PM PDT 24
Peak memory 208688 kb
Host smart-7dd76029-17e9-4eca-b81e-51381716b73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039223288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.1039223288
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload.1300980862
Short name T746
Test name
Test status
Simulation time 143255729 ps
CPU time 2.91 seconds
Started May 02 12:47:16 PM PDT 24
Finished May 02 12:47:23 PM PDT 24
Peak memory 207976 kb
Host smart-dc6dc141-b1c9-466f-a295-f5a9eeae9bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300980862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.1300980862
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.1594182340
Short name T693
Test name
Test status
Simulation time 1050919936 ps
CPU time 11.64 seconds
Started May 02 12:47:43 PM PDT 24
Finished May 02 12:47:57 PM PDT 24
Peak memory 207524 kb
Host smart-94a842dc-1b55-4c4a-88f7-4a88cd53ced4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594182340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.1594182340
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.901540552
Short name T455
Test name
Test status
Simulation time 43146309 ps
CPU time 2.38 seconds
Started May 02 12:47:44 PM PDT 24
Finished May 02 12:47:49 PM PDT 24
Peak memory 206476 kb
Host smart-5a1d83e0-b070-41dd-9979-9ce93608fd28
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901540552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.901540552
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.1549948803
Short name T525
Test name
Test status
Simulation time 59992002 ps
CPU time 2.33 seconds
Started May 02 12:47:16 PM PDT 24
Finished May 02 12:47:22 PM PDT 24
Peak memory 206380 kb
Host smart-f4bb82db-f897-450e-9010-eb1fa096ca8d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549948803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.1549948803
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.1593842150
Short name T247
Test name
Test status
Simulation time 266260321 ps
CPU time 3.49 seconds
Started May 02 12:47:26 PM PDT 24
Finished May 02 12:47:33 PM PDT 24
Peak memory 209532 kb
Host smart-9fe59b07-af8d-4eb3-a64a-7f84eeeb6002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593842150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.1593842150
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.3462201211
Short name T14
Test name
Test status
Simulation time 109199968 ps
CPU time 1.78 seconds
Started May 02 12:47:16 PM PDT 24
Finished May 02 12:47:22 PM PDT 24
Peak memory 206260 kb
Host smart-2267f49c-1f3c-4cbb-91e8-bd32a6b4a54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462201211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.3462201211
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.4172414734
Short name T274
Test name
Test status
Simulation time 3236416230 ps
CPU time 30.14 seconds
Started May 02 12:47:27 PM PDT 24
Finished May 02 12:48:00 PM PDT 24
Peak memory 222212 kb
Host smart-12959243-20fb-4915-a1bb-eadd32475fc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172414734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.4172414734
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.291419924
Short name T60
Test name
Test status
Simulation time 153470602 ps
CPU time 6.03 seconds
Started May 02 12:47:27 PM PDT 24
Finished May 02 12:47:36 PM PDT 24
Peak memory 219560 kb
Host smart-60cc77f8-7076-4441-bc33-54a3bf659735
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291419924 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.291419924
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.1584213300
Short name T897
Test name
Test status
Simulation time 107805133 ps
CPU time 5.11 seconds
Started May 02 12:47:26 PM PDT 24
Finished May 02 12:47:34 PM PDT 24
Peak memory 209348 kb
Host smart-1fd37a17-bcec-4052-bdef-1b4a54dae077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584213300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.1584213300
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.1310084166
Short name T183
Test name
Test status
Simulation time 148100544 ps
CPU time 1.94 seconds
Started May 02 12:47:16 PM PDT 24
Finished May 02 12:47:22 PM PDT 24
Peak memory 209352 kb
Host smart-f199266a-9e63-4ec4-9730-07beea722c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310084166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.1310084166
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.864075967
Short name T740
Test name
Test status
Simulation time 25210169 ps
CPU time 0.74 seconds
Started May 02 12:47:23 PM PDT 24
Finished May 02 12:47:27 PM PDT 24
Peak memory 205532 kb
Host smart-7d0edc08-c587-4d0b-85c2-72dd3b169ee8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864075967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.864075967
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.2952986274
Short name T79
Test name
Test status
Simulation time 145344465 ps
CPU time 2.97 seconds
Started May 02 12:47:16 PM PDT 24
Finished May 02 12:47:23 PM PDT 24
Peak memory 215316 kb
Host smart-d73197db-9db2-45c5-ae10-15af9841f23a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2952986274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.2952986274
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.1666550606
Short name T34
Test name
Test status
Simulation time 264226128 ps
CPU time 7.39 seconds
Started May 02 12:47:22 PM PDT 24
Finished May 02 12:47:33 PM PDT 24
Peak memory 221684 kb
Host smart-d7b4a71f-20ed-486b-81ea-2e855f74d025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666550606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.1666550606
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.1283897017
Short name T562
Test name
Test status
Simulation time 48908694 ps
CPU time 2.48 seconds
Started May 02 12:47:22 PM PDT 24
Finished May 02 12:47:28 PM PDT 24
Peak memory 206736 kb
Host smart-f202b80a-f7ba-4795-916a-9c236444395d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283897017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.1283897017
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.2256656329
Short name T870
Test name
Test status
Simulation time 3787001519 ps
CPU time 39.79 seconds
Started May 02 12:47:19 PM PDT 24
Finished May 02 12:48:04 PM PDT 24
Peak memory 214044 kb
Host smart-24a5ed78-f969-4199-acf1-6e0c550d5200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256656329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.2256656329
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.1415998395
Short name T289
Test name
Test status
Simulation time 2406355609 ps
CPU time 7.27 seconds
Started May 02 12:47:24 PM PDT 24
Finished May 02 12:47:34 PM PDT 24
Peak memory 214016 kb
Host smart-2303c765-ef12-4aa7-9aa6-1526f1d8e5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415998395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.1415998395
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.1789800272
Short name T702
Test name
Test status
Simulation time 230496054 ps
CPU time 3.16 seconds
Started May 02 12:47:39 PM PDT 24
Finished May 02 12:47:45 PM PDT 24
Peak memory 214884 kb
Host smart-f245f255-c14a-4b10-a285-a93fbc0f73a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789800272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.1789800272
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.3245733509
Short name T605
Test name
Test status
Simulation time 1684412189 ps
CPU time 11.16 seconds
Started May 02 12:47:19 PM PDT 24
Finished May 02 12:47:34 PM PDT 24
Peak memory 207760 kb
Host smart-f062bc11-ce39-4aac-9954-0f1e6116b612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245733509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.3245733509
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sideload.3796100809
Short name T482
Test name
Test status
Simulation time 45630373 ps
CPU time 1.87 seconds
Started May 02 12:47:19 PM PDT 24
Finished May 02 12:47:25 PM PDT 24
Peak memory 206836 kb
Host smart-14cb440e-a629-4c39-9cf6-c66b0f76feac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796100809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.3796100809
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.816656971
Short name T434
Test name
Test status
Simulation time 641339221 ps
CPU time 3.62 seconds
Started May 02 12:47:43 PM PDT 24
Finished May 02 12:47:50 PM PDT 24
Peak memory 206584 kb
Host smart-faf50f46-448e-4ed1-9488-0565c7085f7e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816656971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.816656971
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.3795109011
Short name T546
Test name
Test status
Simulation time 2852257397 ps
CPU time 11.11 seconds
Started May 02 12:47:29 PM PDT 24
Finished May 02 12:47:42 PM PDT 24
Peak memory 208140 kb
Host smart-c8a355fe-395b-4cc9-b3b5-75824b6646ab
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795109011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.3795109011
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.1784111917
Short name T206
Test name
Test status
Simulation time 227083445 ps
CPU time 5.72 seconds
Started May 02 12:47:24 PM PDT 24
Finished May 02 12:47:33 PM PDT 24
Peak memory 207964 kb
Host smart-71e81fcf-fba0-48a1-af40-c5c8a9820aa2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784111917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.1784111917
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.230178818
Short name T864
Test name
Test status
Simulation time 442637470 ps
CPU time 3.02 seconds
Started May 02 12:47:32 PM PDT 24
Finished May 02 12:47:37 PM PDT 24
Peak memory 208648 kb
Host smart-4aa75c93-6e34-48db-b79b-57ba0ea9f0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230178818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.230178818
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.2606071721
Short name T567
Test name
Test status
Simulation time 531168404 ps
CPU time 4.16 seconds
Started May 02 12:47:19 PM PDT 24
Finished May 02 12:47:28 PM PDT 24
Peak memory 208020 kb
Host smart-19e9f0ed-ae0f-4af6-9b5c-34309612e922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606071721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.2606071721
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.303403846
Short name T532
Test name
Test status
Simulation time 123744708 ps
CPU time 4.88 seconds
Started May 02 12:47:22 PM PDT 24
Finished May 02 12:47:30 PM PDT 24
Peak memory 217648 kb
Host smart-ba1d6d7c-6afd-4309-9493-08f6877767f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303403846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.303403846
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.3055581139
Short name T126
Test name
Test status
Simulation time 505673094 ps
CPU time 3.33 seconds
Started May 02 12:47:35 PM PDT 24
Finished May 02 12:47:40 PM PDT 24
Peak memory 209248 kb
Host smart-753ad576-551c-481d-ba82-6b031b6afccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055581139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.3055581139
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.1946960184
Short name T404
Test name
Test status
Simulation time 189043976 ps
CPU time 5.85 seconds
Started May 02 12:47:43 PM PDT 24
Finished May 02 12:47:52 PM PDT 24
Peak memory 222200 kb
Host smart-0d1f57be-4c94-4d2c-9a49-b530a6ae99af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1946960184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.1946960184
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.3607232851
Short name T36
Test name
Test status
Simulation time 57701810 ps
CPU time 3.16 seconds
Started May 02 12:47:47 PM PDT 24
Finished May 02 12:47:53 PM PDT 24
Peak memory 220980 kb
Host smart-7417bc5b-4356-44f9-b9bc-9bf1a5e58f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607232851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.3607232851
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.3970410898
Short name T603
Test name
Test status
Simulation time 45601571 ps
CPU time 2.06 seconds
Started May 02 12:47:50 PM PDT 24
Finished May 02 12:47:56 PM PDT 24
Peak memory 208484 kb
Host smart-01102e81-098c-433b-a1d7-18af0ec8e413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970410898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.3970410898
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.2185534071
Short name T342
Test name
Test status
Simulation time 301268300 ps
CPU time 5.4 seconds
Started May 02 12:47:49 PM PDT 24
Finished May 02 12:47:58 PM PDT 24
Peak memory 210232 kb
Host smart-7ffa226a-9587-4345-822e-a163be511bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185534071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.2185534071
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.4159818229
Short name T208
Test name
Test status
Simulation time 421017135 ps
CPU time 3.41 seconds
Started May 02 12:47:51 PM PDT 24
Finished May 02 12:47:58 PM PDT 24
Peak memory 209344 kb
Host smart-47c38d19-3ad0-4758-afd7-9c307f25603a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159818229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.4159818229
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.2708995826
Short name T526
Test name
Test status
Simulation time 293788381 ps
CPU time 6.12 seconds
Started May 02 12:47:56 PM PDT 24
Finished May 02 12:48:06 PM PDT 24
Peak memory 215208 kb
Host smart-66841d4a-e8b7-4c77-9a03-5a10f92a817c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708995826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.2708995826
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.4002910185
Short name T854
Test name
Test status
Simulation time 1841434266 ps
CPU time 40.65 seconds
Started May 02 12:48:00 PM PDT 24
Finished May 02 12:48:45 PM PDT 24
Peak memory 207596 kb
Host smart-019edaf3-e80f-4e97-b8e1-1ddc1abb13bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002910185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.4002910185
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.2551082180
Short name T887
Test name
Test status
Simulation time 76026413 ps
CPU time 3.66 seconds
Started May 02 12:47:49 PM PDT 24
Finished May 02 12:47:57 PM PDT 24
Peak memory 208116 kb
Host smart-2a82b257-1aad-4a9c-8a0a-716f96afca04
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551082180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.2551082180
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.1232776260
Short name T556
Test name
Test status
Simulation time 6177871763 ps
CPU time 43.76 seconds
Started May 02 12:47:45 PM PDT 24
Finished May 02 12:48:33 PM PDT 24
Peak memory 208284 kb
Host smart-1bf5d7f9-7500-4b12-8d1b-7617f455a78a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232776260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.1232776260
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_smoke.737234101
Short name T736
Test name
Test status
Simulation time 102244974 ps
CPU time 2.83 seconds
Started May 02 12:47:51 PM PDT 24
Finished May 02 12:47:57 PM PDT 24
Peak memory 207736 kb
Host smart-6ba4fb7e-260e-4c24-b035-5adfb6fc5e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737234101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.737234101
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.3103893188
Short name T675
Test name
Test status
Simulation time 2685074568 ps
CPU time 23.82 seconds
Started May 02 12:48:01 PM PDT 24
Finished May 02 12:48:29 PM PDT 24
Peak memory 221912 kb
Host smart-53ffe9c9-233f-49ec-8d24-ac48d01e66a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103893188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.3103893188
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.1982239843
Short name T344
Test name
Test status
Simulation time 170344459 ps
CPU time 5.52 seconds
Started May 02 12:47:55 PM PDT 24
Finished May 02 12:48:04 PM PDT 24
Peak memory 217760 kb
Host smart-39061ec9-000f-4165-abdb-45c545a1b2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982239843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.1982239843
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.596582675
Short name T747
Test name
Test status
Simulation time 355027642 ps
CPU time 4.19 seconds
Started May 02 12:47:44 PM PDT 24
Finished May 02 12:47:52 PM PDT 24
Peak memory 209936 kb
Host smart-4c08db39-2552-436d-9ff9-5d9d388e76d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596582675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.596582675
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.2177290840
Short name T632
Test name
Test status
Simulation time 29502372 ps
CPU time 0.96 seconds
Started May 02 12:47:58 PM PDT 24
Finished May 02 12:48:03 PM PDT 24
Peak memory 205812 kb
Host smart-6db80ab2-0123-4b1d-ad8f-28b30365226b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177290840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.2177290840
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.2781289730
Short name T409
Test name
Test status
Simulation time 171135235 ps
CPU time 9.17 seconds
Started May 02 12:47:38 PM PDT 24
Finished May 02 12:47:49 PM PDT 24
Peak memory 214944 kb
Host smart-1fec0cfd-aee7-4d1e-8a0a-6e3cc3a4c86e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2781289730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.2781289730
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.1930878853
Short name T23
Test name
Test status
Simulation time 81628286 ps
CPU time 3.64 seconds
Started May 02 12:47:52 PM PDT 24
Finished May 02 12:48:00 PM PDT 24
Peak memory 207988 kb
Host smart-5dec8dd6-a513-4152-ba5a-fe41bc76d80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930878853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.1930878853
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.2264795601
Short name T544
Test name
Test status
Simulation time 65198212 ps
CPU time 1.39 seconds
Started May 02 12:47:51 PM PDT 24
Finished May 02 12:47:56 PM PDT 24
Peak memory 206964 kb
Host smart-5a68e9dd-0e7f-4cc5-b28e-dc16bc9febec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264795601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.2264795601
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.440475605
Short name T773
Test name
Test status
Simulation time 164250175 ps
CPU time 8.73 seconds
Started May 02 12:47:45 PM PDT 24
Finished May 02 12:47:57 PM PDT 24
Peak memory 209836 kb
Host smart-82f8d72a-6039-4fe0-a49d-c79110d277a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440475605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.440475605
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.3680794558
Short name T235
Test name
Test status
Simulation time 108981015 ps
CPU time 5.14 seconds
Started May 02 12:47:51 PM PDT 24
Finished May 02 12:47:59 PM PDT 24
Peak memory 209704 kb
Host smart-b132425b-7fae-423c-bebc-ad3cd9e8089a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680794558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.3680794558
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.1490980954
Short name T574
Test name
Test status
Simulation time 118011362 ps
CPU time 2.41 seconds
Started May 02 12:47:53 PM PDT 24
Finished May 02 12:47:59 PM PDT 24
Peak memory 206428 kb
Host smart-aa1f3778-ff62-4582-8fae-a8100d272e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490980954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.1490980954
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.2799576057
Short name T629
Test name
Test status
Simulation time 4377118808 ps
CPU time 29.96 seconds
Started May 02 12:47:46 PM PDT 24
Finished May 02 12:48:20 PM PDT 24
Peak memory 207688 kb
Host smart-05c5ef20-2370-45e4-a903-8bea51beff15
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799576057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.2799576057
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.2291373128
Short name T643
Test name
Test status
Simulation time 1044897713 ps
CPU time 11.2 seconds
Started May 02 12:47:55 PM PDT 24
Finished May 02 12:48:10 PM PDT 24
Peak memory 207540 kb
Host smart-bf71dfd7-31b0-4003-a4d4-2bed6c1e0761
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291373128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.2291373128
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.1088442428
Short name T760
Test name
Test status
Simulation time 211828810 ps
CPU time 2.72 seconds
Started May 02 12:47:54 PM PDT 24
Finished May 02 12:48:01 PM PDT 24
Peak memory 209036 kb
Host smart-1da6dc67-f3d5-4ab8-92ec-3f584b9fad82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088442428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.1088442428
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.2221010654
Short name T506
Test name
Test status
Simulation time 24730890 ps
CPU time 1.88 seconds
Started May 02 12:47:55 PM PDT 24
Finished May 02 12:48:00 PM PDT 24
Peak memory 208052 kb
Host smart-ea958efb-4e53-486a-9ed4-1467b983905f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221010654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.2221010654
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.1800003949
Short name T192
Test name
Test status
Simulation time 45848426 ps
CPU time 2.62 seconds
Started May 02 12:48:02 PM PDT 24
Finished May 02 12:48:09 PM PDT 24
Peak memory 218112 kb
Host smart-a2097d4b-9faf-4365-949c-ce4c32ddcf56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800003949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.1800003949
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.2361191808
Short name T122
Test name
Test status
Simulation time 1858729009 ps
CPU time 15.37 seconds
Started May 02 12:47:46 PM PDT 24
Finished May 02 12:48:04 PM PDT 24
Peak memory 222248 kb
Host smart-6239c2c1-6c28-4865-a9fe-5bd0ad5427c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361191808 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.2361191808
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.1596673501
Short name T37
Test name
Test status
Simulation time 33691463 ps
CPU time 1.82 seconds
Started May 02 12:47:59 PM PDT 24
Finished May 02 12:48:05 PM PDT 24
Peak memory 209876 kb
Host smart-7069448c-9ec5-4374-a163-f7791a832800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596673501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.1596673501
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.497569346
Short name T499
Test name
Test status
Simulation time 13493709 ps
CPU time 0.78 seconds
Started May 02 12:48:02 PM PDT 24
Finished May 02 12:48:07 PM PDT 24
Peak memory 205500 kb
Host smart-e51b27c3-80b0-4e5a-ab37-f132e1d42966
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497569346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.497569346
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.3598671168
Short name T420
Test name
Test status
Simulation time 481700416 ps
CPU time 3.81 seconds
Started May 02 12:47:45 PM PDT 24
Finished May 02 12:47:52 PM PDT 24
Peak memory 213960 kb
Host smart-a2e0658a-ac5c-452f-b272-98204618579e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3598671168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.3598671168
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.3007211804
Short name T610
Test name
Test status
Simulation time 557090032 ps
CPU time 4.17 seconds
Started May 02 12:47:56 PM PDT 24
Finished May 02 12:48:04 PM PDT 24
Peak memory 218580 kb
Host smart-3a2cb92a-cb6b-4936-a9d7-e4c4c87c96fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007211804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.3007211804
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.2978973189
Short name T770
Test name
Test status
Simulation time 35436697 ps
CPU time 1.94 seconds
Started May 02 12:47:47 PM PDT 24
Finished May 02 12:47:52 PM PDT 24
Peak memory 207732 kb
Host smart-7c5981e1-03e8-4eb8-a3cd-56140179430b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978973189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.2978973189
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.2416915807
Short name T286
Test name
Test status
Simulation time 388627965 ps
CPU time 4.86 seconds
Started May 02 12:47:51 PM PDT 24
Finished May 02 12:48:00 PM PDT 24
Peak memory 222120 kb
Host smart-35ef9ee0-d64a-4771-af78-990d4d710481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416915807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.2416915807
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.2927326403
Short name T52
Test name
Test status
Simulation time 1335588378 ps
CPU time 5.32 seconds
Started May 02 12:47:54 PM PDT 24
Finished May 02 12:48:03 PM PDT 24
Peak memory 219880 kb
Host smart-798f9e70-5952-4f8a-9279-0cb956b890c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927326403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.2927326403
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.2904262077
Short name T307
Test name
Test status
Simulation time 795960125 ps
CPU time 5.04 seconds
Started May 02 12:47:40 PM PDT 24
Finished May 02 12:47:48 PM PDT 24
Peak memory 209384 kb
Host smart-5f79f6a0-ad53-44e8-87cd-f7715b56f89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904262077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.2904262077
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.1433106799
Short name T766
Test name
Test status
Simulation time 1413778491 ps
CPU time 6.38 seconds
Started May 02 12:47:52 PM PDT 24
Finished May 02 12:48:02 PM PDT 24
Peak memory 208108 kb
Host smart-608164b7-14c1-4623-925f-798f12b1a755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433106799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.1433106799
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.1591128625
Short name T553
Test name
Test status
Simulation time 874002820 ps
CPU time 5.64 seconds
Started May 02 12:47:53 PM PDT 24
Finished May 02 12:48:02 PM PDT 24
Peak memory 206440 kb
Host smart-0b70ee12-854e-40c0-817a-383019a6ca8e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591128625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.1591128625
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.1837326621
Short name T895
Test name
Test status
Simulation time 127348123 ps
CPU time 4.27 seconds
Started May 02 12:47:53 PM PDT 24
Finished May 02 12:48:01 PM PDT 24
Peak memory 206468 kb
Host smart-7e42e6c8-82e5-47e6-b091-abd7b802cbf5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837326621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.1837326621
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.3961300069
Short name T639
Test name
Test status
Simulation time 212537285 ps
CPU time 4.79 seconds
Started May 02 12:47:47 PM PDT 24
Finished May 02 12:47:55 PM PDT 24
Peak memory 207964 kb
Host smart-3cabbdb4-a374-4edf-b871-d86a2ddb3e96
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961300069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.3961300069
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.538467430
Short name T549
Test name
Test status
Simulation time 252861761 ps
CPU time 3.76 seconds
Started May 02 12:47:51 PM PDT 24
Finished May 02 12:47:58 PM PDT 24
Peak memory 217872 kb
Host smart-c99703a6-a093-4d4c-b53d-560e240431bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538467430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.538467430
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.916047324
Short name T798
Test name
Test status
Simulation time 547638786 ps
CPU time 3.37 seconds
Started May 02 12:47:43 PM PDT 24
Finished May 02 12:47:50 PM PDT 24
Peak memory 207864 kb
Host smart-dfef827a-b79e-4b37-8d03-d3b148c80a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916047324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.916047324
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.876932956
Short name T611
Test name
Test status
Simulation time 648442109 ps
CPU time 21.43 seconds
Started May 02 12:47:51 PM PDT 24
Finished May 02 12:48:16 PM PDT 24
Peak memory 222288 kb
Host smart-d4bf653b-13e5-44d2-a294-2cb484f78524
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876932956 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.876932956
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.3558598042
Short name T29
Test name
Test status
Simulation time 313309529 ps
CPU time 6.96 seconds
Started May 02 12:48:15 PM PDT 24
Finished May 02 12:48:25 PM PDT 24
Peak memory 218060 kb
Host smart-8b01953a-6fa3-4f5f-bb1a-ab64a88df01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558598042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.3558598042
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.1674409230
Short name T457
Test name
Test status
Simulation time 12224391 ps
CPU time 0.88 seconds
Started May 02 12:47:46 PM PDT 24
Finished May 02 12:47:50 PM PDT 24
Peak memory 205576 kb
Host smart-8987cde5-7a96-4afc-aea4-b78620109e93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674409230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.1674409230
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.150186493
Short name T696
Test name
Test status
Simulation time 275663880 ps
CPU time 3.5 seconds
Started May 02 12:48:14 PM PDT 24
Finished May 02 12:48:21 PM PDT 24
Peak memory 209912 kb
Host smart-8761f68c-b860-4911-8cd3-ab7793a4ea57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150186493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.150186493
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.303103631
Short name T792
Test name
Test status
Simulation time 389118768 ps
CPU time 4.62 seconds
Started May 02 12:48:02 PM PDT 24
Finished May 02 12:48:11 PM PDT 24
Peak memory 208552 kb
Host smart-28731bb7-42df-4037-afd5-b06d4f20456b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303103631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.303103631
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.4023241703
Short name T287
Test name
Test status
Simulation time 53046364 ps
CPU time 3.98 seconds
Started May 02 12:47:56 PM PDT 24
Finished May 02 12:48:04 PM PDT 24
Peak memory 222224 kb
Host smart-1e192084-5337-4281-9052-e313a0965f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023241703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.4023241703
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.3117636453
Short name T5
Test name
Test status
Simulation time 427774670 ps
CPU time 2.75 seconds
Started May 02 12:47:54 PM PDT 24
Finished May 02 12:47:59 PM PDT 24
Peak memory 214280 kb
Host smart-cb60d99f-4a75-4240-a756-a66ee02e296f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117636453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.3117636453
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.3183696248
Short name T620
Test name
Test status
Simulation time 67487248 ps
CPU time 3.18 seconds
Started May 02 12:47:48 PM PDT 24
Finished May 02 12:47:55 PM PDT 24
Peak memory 208948 kb
Host smart-cf6ff230-bef2-44d4-ad32-34a071789a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183696248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.3183696248
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.3686811577
Short name T394
Test name
Test status
Simulation time 104689677 ps
CPU time 2.73 seconds
Started May 02 12:47:51 PM PDT 24
Finished May 02 12:47:57 PM PDT 24
Peak memory 206412 kb
Host smart-b958967b-e65b-4a1a-a020-3184fe0d4623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686811577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.3686811577
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.587481743
Short name T592
Test name
Test status
Simulation time 94299540 ps
CPU time 2.71 seconds
Started May 02 12:48:04 PM PDT 24
Finished May 02 12:48:10 PM PDT 24
Peak memory 206496 kb
Host smart-e382ad7a-cd91-4e4a-bea6-2a5a31eec5dd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587481743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.587481743
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.955204732
Short name T734
Test name
Test status
Simulation time 849533272 ps
CPU time 10.41 seconds
Started May 02 12:47:45 PM PDT 24
Finished May 02 12:47:59 PM PDT 24
Peak memory 208772 kb
Host smart-0095a4bd-1bc6-4804-b8a0-fa0798ae8692
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955204732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.955204732
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.2956005181
Short name T473
Test name
Test status
Simulation time 68325440 ps
CPU time 3.45 seconds
Started May 02 12:47:48 PM PDT 24
Finished May 02 12:47:55 PM PDT 24
Peak memory 208068 kb
Host smart-4ff9ebf9-ea94-4080-a5b8-d20fda753a0f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956005181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.2956005181
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.259927386
Short name T256
Test name
Test status
Simulation time 176594069 ps
CPU time 2.98 seconds
Started May 02 12:47:57 PM PDT 24
Finished May 02 12:48:09 PM PDT 24
Peak memory 209316 kb
Host smart-836a028e-4141-4619-b526-02528f9e47fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259927386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.259927386
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.1645651365
Short name T438
Test name
Test status
Simulation time 510242946 ps
CPU time 7.24 seconds
Started May 02 12:48:02 PM PDT 24
Finished May 02 12:48:13 PM PDT 24
Peak memory 207908 kb
Host smart-81356c92-113e-4db6-8c42-375083bec13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645651365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.1645651365
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.1180045705
Short name T356
Test name
Test status
Simulation time 654021345 ps
CPU time 10.06 seconds
Started May 02 12:47:59 PM PDT 24
Finished May 02 12:48:13 PM PDT 24
Peak memory 214612 kb
Host smart-ebdc6e52-9c42-42d8-b958-19318053eaf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180045705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.1180045705
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.533843757
Short name T862
Test name
Test status
Simulation time 287233137 ps
CPU time 14.96 seconds
Started May 02 12:47:49 PM PDT 24
Finished May 02 12:48:08 PM PDT 24
Peak memory 220164 kb
Host smart-915f33c8-5a59-4e53-b901-f411e182bd0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533843757 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.533843757
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.2309669950
Short name T576
Test name
Test status
Simulation time 345831990 ps
CPU time 4.06 seconds
Started May 02 12:47:45 PM PDT 24
Finished May 02 12:47:52 PM PDT 24
Peak memory 208936 kb
Host smart-29a9d5de-e233-449d-8421-bf61ae4ca7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309669950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.2309669950
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.3381408130
Short name T742
Test name
Test status
Simulation time 94368927 ps
CPU time 4.28 seconds
Started May 02 12:48:01 PM PDT 24
Finished May 02 12:48:10 PM PDT 24
Peak memory 209568 kb
Host smart-e8ddf067-8599-43e2-ad4b-c33662c914e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381408130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.3381408130
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.2145405012
Short name T440
Test name
Test status
Simulation time 25245289 ps
CPU time 0.91 seconds
Started May 02 12:47:57 PM PDT 24
Finished May 02 12:48:01 PM PDT 24
Peak memory 205728 kb
Host smart-0974f502-c68e-4663-9865-31732cd8f379
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145405012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.2145405012
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.3344848600
Short name T141
Test name
Test status
Simulation time 104315402 ps
CPU time 3.8 seconds
Started May 02 12:47:52 PM PDT 24
Finished May 02 12:47:59 PM PDT 24
Peak memory 214580 kb
Host smart-c7edf9cd-3f7f-4f33-ac64-12fc7390d62d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3344848600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.3344848600
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.1610068576
Short name T32
Test name
Test status
Simulation time 219088662 ps
CPU time 2.89 seconds
Started May 02 12:47:57 PM PDT 24
Finished May 02 12:48:03 PM PDT 24
Peak memory 209656 kb
Host smart-dc8f5d67-c7a3-41ec-99ab-ace10534ce71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610068576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.1610068576
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.802342241
Short name T78
Test name
Test status
Simulation time 58827303 ps
CPU time 2.26 seconds
Started May 02 12:47:58 PM PDT 24
Finished May 02 12:48:04 PM PDT 24
Peak memory 217872 kb
Host smart-7707a899-1281-4b27-b773-89c20165d7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802342241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.802342241
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.1093382682
Short name T602
Test name
Test status
Simulation time 111292342 ps
CPU time 4.99 seconds
Started May 02 12:47:59 PM PDT 24
Finished May 02 12:48:09 PM PDT 24
Peak memory 207788 kb
Host smart-a0302ec0-3a6a-4af1-aeab-a2551789b68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093382682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.1093382682
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.4206685914
Short name T550
Test name
Test status
Simulation time 372614046 ps
CPU time 4.81 seconds
Started May 02 12:47:54 PM PDT 24
Finished May 02 12:48:03 PM PDT 24
Peak memory 220204 kb
Host smart-3f9a023e-7556-4767-ba5c-eaaaa7fc2c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206685914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.4206685914
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.3749939931
Short name T863
Test name
Test status
Simulation time 169409101 ps
CPU time 2.95 seconds
Started May 02 12:47:59 PM PDT 24
Finished May 02 12:48:06 PM PDT 24
Peak memory 207244 kb
Host smart-fac4f88f-44d5-4d33-940e-d95d11e3ff19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749939931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.3749939931
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.3906024404
Short name T751
Test name
Test status
Simulation time 61530525 ps
CPU time 2.19 seconds
Started May 02 12:47:50 PM PDT 24
Finished May 02 12:47:56 PM PDT 24
Peak memory 206396 kb
Host smart-50396462-e9c6-4fc5-bab4-576034325b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906024404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.3906024404
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.4094884368
Short name T814
Test name
Test status
Simulation time 135497357 ps
CPU time 2.47 seconds
Started May 02 12:47:51 PM PDT 24
Finished May 02 12:47:57 PM PDT 24
Peak memory 206444 kb
Host smart-8ae87dee-e637-4cc7-9b54-2b195a734775
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094884368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.4094884368
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.1321994428
Short name T559
Test name
Test status
Simulation time 639703087 ps
CPU time 3.48 seconds
Started May 02 12:47:49 PM PDT 24
Finished May 02 12:47:57 PM PDT 24
Peak memory 206352 kb
Host smart-a1dbcf83-7b4f-4096-8be3-19c259730e53
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321994428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.1321994428
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.3099386743
Short name T589
Test name
Test status
Simulation time 188963105 ps
CPU time 2.5 seconds
Started May 02 12:47:52 PM PDT 24
Finished May 02 12:47:58 PM PDT 24
Peak memory 206448 kb
Host smart-ee207bd1-cb6e-4960-8d84-1cd95458d350
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099386743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.3099386743
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.216902217
Short name T280
Test name
Test status
Simulation time 606182917 ps
CPU time 19.61 seconds
Started May 02 12:47:49 PM PDT 24
Finished May 02 12:48:17 PM PDT 24
Peak memory 208784 kb
Host smart-4dc8a969-2564-4959-8ae9-104c982eebb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216902217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.216902217
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.2947695687
Short name T711
Test name
Test status
Simulation time 119393652 ps
CPU time 3.39 seconds
Started May 02 12:47:50 PM PDT 24
Finished May 02 12:47:57 PM PDT 24
Peak memory 206404 kb
Host smart-4aecde81-9c9c-47d7-9437-434bba9cd144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947695687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.2947695687
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.198788075
Short name T337
Test name
Test status
Simulation time 713723892 ps
CPU time 16.17 seconds
Started May 02 12:47:57 PM PDT 24
Finished May 02 12:48:16 PM PDT 24
Peak memory 214604 kb
Host smart-7ca0022e-7d47-4689-bca5-fe1343b7534e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198788075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.198788075
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.1640482641
Short name T677
Test name
Test status
Simulation time 2684262758 ps
CPU time 26.88 seconds
Started May 02 12:48:01 PM PDT 24
Finished May 02 12:48:32 PM PDT 24
Peak memory 218100 kb
Host smart-726e5e5c-5853-4152-97f0-ea9e3bff4031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640482641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.1640482641
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.111541280
Short name T162
Test name
Test status
Simulation time 29942655 ps
CPU time 1.63 seconds
Started May 02 12:47:52 PM PDT 24
Finished May 02 12:47:57 PM PDT 24
Peak memory 209280 kb
Host smart-3dafbbbe-cad7-4403-a056-bea748f18190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111541280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.111541280
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.904791171
Short name T778
Test name
Test status
Simulation time 16325392 ps
CPU time 0.86 seconds
Started May 02 12:47:57 PM PDT 24
Finished May 02 12:48:02 PM PDT 24
Peak memory 205516 kb
Host smart-864fd9d2-9401-4c29-9e2c-7de822af00ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904791171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.904791171
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.3207626963
Short name T336
Test name
Test status
Simulation time 916304023 ps
CPU time 4.09 seconds
Started May 02 12:47:51 PM PDT 24
Finished May 02 12:47:59 PM PDT 24
Peak memory 213956 kb
Host smart-fc578f18-0105-4eb1-9101-3eaf6d33770b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3207626963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.3207626963
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.1147969839
Short name T797
Test name
Test status
Simulation time 608284800 ps
CPU time 5.42 seconds
Started May 02 12:47:55 PM PDT 24
Finished May 02 12:48:04 PM PDT 24
Peak memory 208648 kb
Host smart-1b583305-3c39-4a0b-82b8-9e7672928d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147969839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.1147969839
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.2152820122
Short name T712
Test name
Test status
Simulation time 2001162135 ps
CPU time 10.68 seconds
Started May 02 12:47:59 PM PDT 24
Finished May 02 12:48:15 PM PDT 24
Peak memory 208536 kb
Host smart-a1453b65-950b-49b1-b4b2-3d1b43076543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152820122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.2152820122
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.1284503833
Short name T399
Test name
Test status
Simulation time 211353476 ps
CPU time 2.59 seconds
Started May 02 12:47:57 PM PDT 24
Finished May 02 12:48:09 PM PDT 24
Peak memory 218764 kb
Host smart-21fe324d-d107-4a2b-8852-adf75814a822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284503833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.1284503833
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.3944153083
Short name T262
Test name
Test status
Simulation time 2312098691 ps
CPU time 7.61 seconds
Started May 02 12:47:59 PM PDT 24
Finished May 02 12:48:11 PM PDT 24
Peak memory 222184 kb
Host smart-546e57b1-4a03-4760-896d-3997b2ca8439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944153083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.3944153083
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.2738252324
Short name T83
Test name
Test status
Simulation time 290144209 ps
CPU time 2.89 seconds
Started May 02 12:47:57 PM PDT 24
Finished May 02 12:48:03 PM PDT 24
Peak memory 205748 kb
Host smart-5cc0afce-1c0e-4264-a7db-f79bd3e0d7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738252324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.2738252324
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.2621155246
Short name T329
Test name
Test status
Simulation time 127663234 ps
CPU time 2.51 seconds
Started May 02 12:48:00 PM PDT 24
Finished May 02 12:48:11 PM PDT 24
Peak memory 207676 kb
Host smart-91e47e0c-32b0-47c9-a08a-6da102609667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621155246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.2621155246
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.2805708003
Short name T893
Test name
Test status
Simulation time 321977986 ps
CPU time 3.11 seconds
Started May 02 12:47:54 PM PDT 24
Finished May 02 12:48:01 PM PDT 24
Peak memory 207968 kb
Host smart-ef64b407-cba9-46a6-9e8e-db30aa45fb05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805708003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.2805708003
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.1477603043
Short name T537
Test name
Test status
Simulation time 88669963 ps
CPU time 1.9 seconds
Started May 02 12:48:15 PM PDT 24
Finished May 02 12:48:20 PM PDT 24
Peak memory 206976 kb
Host smart-24ca33a2-aaae-403e-99dc-c84d23e46f85
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477603043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.1477603043
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.1979010513
Short name T317
Test name
Test status
Simulation time 1392521883 ps
CPU time 9.07 seconds
Started May 02 12:47:49 PM PDT 24
Finished May 02 12:48:02 PM PDT 24
Peak memory 207468 kb
Host smart-641885c8-4be8-4d61-b147-43895b1dda34
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979010513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.1979010513
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.1458037399
Short name T793
Test name
Test status
Simulation time 78821214 ps
CPU time 3.41 seconds
Started May 02 12:47:58 PM PDT 24
Finished May 02 12:48:06 PM PDT 24
Peak memory 207592 kb
Host smart-8da55232-b275-4535-b50b-96bf281e9f87
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458037399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.1458037399
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.3043210964
Short name T727
Test name
Test status
Simulation time 65359379 ps
CPU time 2.83 seconds
Started May 02 12:48:12 PM PDT 24
Finished May 02 12:48:18 PM PDT 24
Peak memory 207868 kb
Host smart-c186a6e5-50e6-4491-9a46-f4f3985d8263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043210964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.3043210964
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.2249409845
Short name T453
Test name
Test status
Simulation time 105245340 ps
CPU time 2.74 seconds
Started May 02 12:47:53 PM PDT 24
Finished May 02 12:47:59 PM PDT 24
Peak memory 207876 kb
Host smart-afa8b3ce-a55f-4e51-a307-0281ac752771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249409845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.2249409845
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.4095485091
Short name T224
Test name
Test status
Simulation time 619518278 ps
CPU time 29.11 seconds
Started May 02 12:47:59 PM PDT 24
Finished May 02 12:48:32 PM PDT 24
Peak memory 216280 kb
Host smart-c6be8778-e55b-4f9d-8604-11f132af1d56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095485091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.4095485091
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.50895152
Short name T800
Test name
Test status
Simulation time 1329356032 ps
CPU time 12.12 seconds
Started May 02 12:47:56 PM PDT 24
Finished May 02 12:48:11 PM PDT 24
Peak memory 220440 kb
Host smart-90042e08-1df3-47df-b032-df5ce50df36e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50895152 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.50895152
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.3905963287
Short name T662
Test name
Test status
Simulation time 128948747 ps
CPU time 5 seconds
Started May 02 12:47:57 PM PDT 24
Finished May 02 12:48:06 PM PDT 24
Peak memory 213916 kb
Host smart-fcb082e3-3741-4980-b8c9-9888730fe62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905963287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.3905963287
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.2121520573
Short name T765
Test name
Test status
Simulation time 171094054 ps
CPU time 2.17 seconds
Started May 02 12:48:00 PM PDT 24
Finished May 02 12:48:07 PM PDT 24
Peak memory 209980 kb
Host smart-320ade50-365e-4b57-8b46-92f7f8ad86ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121520573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.2121520573
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.3003760288
Short name T682
Test name
Test status
Simulation time 53343573 ps
CPU time 1.09 seconds
Started May 02 12:48:04 PM PDT 24
Finished May 02 12:48:09 PM PDT 24
Peak memory 205680 kb
Host smart-9314b888-e35c-4eb9-91b7-62867f771daa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003760288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.3003760288
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.3649160167
Short name T388
Test name
Test status
Simulation time 110198497 ps
CPU time 2.51 seconds
Started May 02 12:48:00 PM PDT 24
Finished May 02 12:48:07 PM PDT 24
Peak memory 213996 kb
Host smart-fe70cad1-6211-44f4-bae4-c81a332b0dda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3649160167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.3649160167
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.4096777681
Short name T484
Test name
Test status
Simulation time 6362719237 ps
CPU time 32.77 seconds
Started May 02 12:48:01 PM PDT 24
Finished May 02 12:48:38 PM PDT 24
Peak memory 222056 kb
Host smart-bfca9cd7-e200-4487-9917-4664f7a06398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096777681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.4096777681
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.2940803589
Short name T672
Test name
Test status
Simulation time 400176381 ps
CPU time 1.96 seconds
Started May 02 12:47:59 PM PDT 24
Finished May 02 12:48:05 PM PDT 24
Peak memory 207296 kb
Host smart-9b4e7723-af05-424f-bb57-9189f4d60016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940803589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.2940803589
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.28742021
Short name T391
Test name
Test status
Simulation time 7556459519 ps
CPU time 69.07 seconds
Started May 02 12:48:01 PM PDT 24
Finished May 02 12:49:14 PM PDT 24
Peak memory 213996 kb
Host smart-bac75fc6-05c6-4ab6-b9ec-f9cb74b5c272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28742021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.28742021
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.4238838721
Short name T678
Test name
Test status
Simulation time 364197087 ps
CPU time 3.09 seconds
Started May 02 12:48:00 PM PDT 24
Finished May 02 12:48:07 PM PDT 24
Peak memory 208892 kb
Host smart-f616a13d-2fff-44f3-bf6a-d923ea6653d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238838721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.4238838721
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.2290324515
Short name T698
Test name
Test status
Simulation time 115270614 ps
CPU time 4.64 seconds
Started May 02 12:48:17 PM PDT 24
Finished May 02 12:48:24 PM PDT 24
Peak memory 208884 kb
Host smart-884cd372-50be-4691-94b9-1ca89bf40459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290324515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.2290324515
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.92001602
Short name T538
Test name
Test status
Simulation time 357100424 ps
CPU time 3.19 seconds
Started May 02 12:47:47 PM PDT 24
Finished May 02 12:47:53 PM PDT 24
Peak memory 206356 kb
Host smart-b9d21444-8da0-43e9-81d0-31d4f2cde420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92001602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.92001602
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.1530594847
Short name T900
Test name
Test status
Simulation time 131149147 ps
CPU time 2.41 seconds
Started May 02 12:48:05 PM PDT 24
Finished May 02 12:48:11 PM PDT 24
Peak memory 206780 kb
Host smart-410485ad-2a74-4d17-8835-fe079a3e2716
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530594847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.1530594847
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.3018479614
Short name T622
Test name
Test status
Simulation time 682523869 ps
CPU time 8.22 seconds
Started May 02 12:48:08 PM PDT 24
Finished May 02 12:48:19 PM PDT 24
Peak memory 208696 kb
Host smart-b42b6773-9d47-4e99-a640-a3679177f6a1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018479614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.3018479614
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.1984247837
Short name T107
Test name
Test status
Simulation time 78622574 ps
CPU time 1.85 seconds
Started May 02 12:48:04 PM PDT 24
Finished May 02 12:48:10 PM PDT 24
Peak memory 206292 kb
Host smart-cc3cc766-c829-480a-b04d-c4fd1a58cf18
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984247837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.1984247837
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.2751884012
Short name T485
Test name
Test status
Simulation time 41276303 ps
CPU time 2.38 seconds
Started May 02 12:48:10 PM PDT 24
Finished May 02 12:48:15 PM PDT 24
Peak memory 209428 kb
Host smart-86384b9b-90e7-4143-87c5-53c2b057cb88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751884012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.2751884012
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.1412693555
Short name T881
Test name
Test status
Simulation time 530860469 ps
CPU time 6.49 seconds
Started May 02 12:47:59 PM PDT 24
Finished May 02 12:48:10 PM PDT 24
Peak memory 208064 kb
Host smart-3d8820f8-4811-444b-a020-b48b60f98de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412693555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.1412693555
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.2216233167
Short name T714
Test name
Test status
Simulation time 305125108 ps
CPU time 8.41 seconds
Started May 02 12:48:03 PM PDT 24
Finished May 02 12:48:20 PM PDT 24
Peak memory 214644 kb
Host smart-bf82b680-ab3c-4834-b29d-24471be82bd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216233167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.2216233167
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.4222888665
Short name T733
Test name
Test status
Simulation time 5301863421 ps
CPU time 8.78 seconds
Started May 02 12:47:56 PM PDT 24
Finished May 02 12:48:08 PM PDT 24
Peak memory 214044 kb
Host smart-d5d1e254-3969-42bc-9b61-da6e459b7367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222888665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.4222888665
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.3836913153
Short name T566
Test name
Test status
Simulation time 123513597 ps
CPU time 2.85 seconds
Started May 02 12:48:00 PM PDT 24
Finished May 02 12:48:08 PM PDT 24
Peak memory 209928 kb
Host smart-81b326e7-3167-4e2f-adc4-9120f7753fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836913153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.3836913153
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.5001396
Short name T705
Test name
Test status
Simulation time 38113102 ps
CPU time 0.75 seconds
Started May 02 12:48:02 PM PDT 24
Finished May 02 12:48:07 PM PDT 24
Peak memory 205668 kb
Host smart-c9ff59db-dc24-46d8-bcd9-fed3c80946a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5001396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.5001396
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.1106930658
Short name T899
Test name
Test status
Simulation time 1154373288 ps
CPU time 38.81 seconds
Started May 02 12:47:59 PM PDT 24
Finished May 02 12:48:42 PM PDT 24
Peak memory 222504 kb
Host smart-3e85be2a-9f23-45d3-941a-004c41702d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106930658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.1106930658
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.1024319805
Short name T584
Test name
Test status
Simulation time 129947663 ps
CPU time 2.44 seconds
Started May 02 12:48:03 PM PDT 24
Finished May 02 12:48:09 PM PDT 24
Peak memory 208856 kb
Host smart-b2b6a596-cea9-4386-81d6-23abe5bbba24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024319805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.1024319805
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.1307680182
Short name T901
Test name
Test status
Simulation time 422987996 ps
CPU time 4.56 seconds
Started May 02 12:48:02 PM PDT 24
Finished May 02 12:48:11 PM PDT 24
Peak memory 211176 kb
Host smart-2ea12c6d-ca2a-4923-a321-89a0338ead83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307680182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.1307680182
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.1422125669
Short name T400
Test name
Test status
Simulation time 239151858 ps
CPU time 3.87 seconds
Started May 02 12:48:02 PM PDT 24
Finished May 02 12:48:10 PM PDT 24
Peak memory 207388 kb
Host smart-b7d04eda-ae38-49fe-bce5-960072192fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422125669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.1422125669
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.1145487863
Short name T593
Test name
Test status
Simulation time 1027170181 ps
CPU time 8.35 seconds
Started May 02 12:47:59 PM PDT 24
Finished May 02 12:48:11 PM PDT 24
Peak memory 214004 kb
Host smart-12069d42-168a-4204-8983-041b3a8917c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145487863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.1145487863
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.3305014887
Short name T707
Test name
Test status
Simulation time 13598626760 ps
CPU time 59.06 seconds
Started May 02 12:48:04 PM PDT 24
Finished May 02 12:49:07 PM PDT 24
Peak memory 207852 kb
Host smart-d3ea3c9c-e6e0-4693-8263-c69fd58d38a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305014887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.3305014887
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.3291777274
Short name T202
Test name
Test status
Simulation time 928862793 ps
CPU time 12.31 seconds
Started May 02 12:47:59 PM PDT 24
Finished May 02 12:48:16 PM PDT 24
Peak memory 208148 kb
Host smart-72aff247-cccd-492f-9d6d-570f136368ef
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291777274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.3291777274
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.3559106992
Short name T18
Test name
Test status
Simulation time 263503323 ps
CPU time 5.47 seconds
Started May 02 12:48:07 PM PDT 24
Finished May 02 12:48:16 PM PDT 24
Peak memory 207416 kb
Host smart-fd936ee7-bb92-4600-ae26-c89837946a42
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559106992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.3559106992
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.153739230
Short name T476
Test name
Test status
Simulation time 270011472 ps
CPU time 6.09 seconds
Started May 02 12:48:08 PM PDT 24
Finished May 02 12:48:17 PM PDT 24
Peak memory 208556 kb
Host smart-cc25329b-eed1-4d43-92ed-68d42eb3fc2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153739230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.153739230
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.2999504506
Short name T510
Test name
Test status
Simulation time 219064293 ps
CPU time 7.36 seconds
Started May 02 12:48:01 PM PDT 24
Finished May 02 12:48:13 PM PDT 24
Peak memory 207908 kb
Host smart-e279b2a2-c779-41ba-b000-9c7a1858f314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999504506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.2999504506
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.1759435288
Short name T120
Test name
Test status
Simulation time 354067448 ps
CPU time 10.41 seconds
Started May 02 12:47:51 PM PDT 24
Finished May 02 12:48:05 PM PDT 24
Peak memory 218656 kb
Host smart-73f2e085-6081-484c-b408-b0300516ef44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759435288 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.1759435288
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.726445457
Short name T844
Test name
Test status
Simulation time 189460267 ps
CPU time 1.55 seconds
Started May 02 12:48:02 PM PDT 24
Finished May 02 12:48:08 PM PDT 24
Peak memory 209596 kb
Host smart-92737cb5-2349-4e87-82cb-0e2ee45ac029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726445457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.726445457
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.3846778178
Short name T582
Test name
Test status
Simulation time 30604862 ps
CPU time 0.76 seconds
Started May 02 12:48:05 PM PDT 24
Finished May 02 12:48:09 PM PDT 24
Peak memory 205584 kb
Host smart-e2069f13-61a7-42e7-8e14-c1a93ad39fba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846778178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.3846778178
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.4158554633
Short name T524
Test name
Test status
Simulation time 2619557084 ps
CPU time 12.82 seconds
Started May 02 12:48:12 PM PDT 24
Finished May 02 12:48:28 PM PDT 24
Peak memory 209212 kb
Host smart-099ed40d-bfe9-4a15-8623-06291368d44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158554633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.4158554633
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.3759060120
Short name T86
Test name
Test status
Simulation time 325172879 ps
CPU time 8.68 seconds
Started May 02 12:48:07 PM PDT 24
Finished May 02 12:48:18 PM PDT 24
Peak memory 209360 kb
Host smart-43ddd0e7-259a-429c-9a35-1ea6bd88e072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759060120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.3759060120
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.1613076262
Short name T755
Test name
Test status
Simulation time 184410219 ps
CPU time 2.67 seconds
Started May 02 12:48:15 PM PDT 24
Finished May 02 12:48:25 PM PDT 24
Peak memory 215936 kb
Host smart-64dbd11e-7c76-4f44-b0ef-6db52016acc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613076262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.1613076262
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.1691427752
Short name T762
Test name
Test status
Simulation time 71679595 ps
CPU time 3.48 seconds
Started May 02 12:48:11 PM PDT 24
Finished May 02 12:48:16 PM PDT 24
Peak memory 207608 kb
Host smart-8e757020-19ce-4dfe-a7dc-dc6b69f01cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691427752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.1691427752
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.1311268562
Short name T239
Test name
Test status
Simulation time 257340145 ps
CPU time 4.55 seconds
Started May 02 12:48:07 PM PDT 24
Finished May 02 12:48:14 PM PDT 24
Peak memory 208000 kb
Host smart-276fe0b2-0270-40d5-80ff-3d473c425c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311268562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.1311268562
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.3013682066
Short name T869
Test name
Test status
Simulation time 481557226 ps
CPU time 4.56 seconds
Started May 02 12:47:59 PM PDT 24
Finished May 02 12:48:08 PM PDT 24
Peak memory 206364 kb
Host smart-60c9b24c-7822-4909-9071-e9557750ba23
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013682066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.3013682066
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.3910467616
Short name T201
Test name
Test status
Simulation time 195549817 ps
CPU time 7.19 seconds
Started May 02 12:48:16 PM PDT 24
Finished May 02 12:48:26 PM PDT 24
Peak memory 207708 kb
Host smart-4169d5e9-2a05-46df-90cb-d748111d49c1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910467616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.3910467616
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.1416132861
Short name T647
Test name
Test status
Simulation time 79141032 ps
CPU time 3.9 seconds
Started May 02 12:48:18 PM PDT 24
Finished May 02 12:48:24 PM PDT 24
Peak memory 208612 kb
Host smart-b89efee3-c8df-4036-bdd1-97ecf6282ebf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416132861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.1416132861
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.1665003327
Short name T548
Test name
Test status
Simulation time 579906485 ps
CPU time 6.79 seconds
Started May 02 12:48:13 PM PDT 24
Finished May 02 12:48:22 PM PDT 24
Peak memory 209412 kb
Host smart-8f73d09c-b39f-4465-a911-2786382ef0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665003327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.1665003327
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.791600165
Short name T80
Test name
Test status
Simulation time 320740282 ps
CPU time 3.41 seconds
Started May 02 12:48:00 PM PDT 24
Finished May 02 12:48:08 PM PDT 24
Peak memory 208120 kb
Host smart-2823428a-b86c-405e-9397-117439242845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791600165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.791600165
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.4023811516
Short name T234
Test name
Test status
Simulation time 755387104 ps
CPU time 5.62 seconds
Started May 02 12:48:16 PM PDT 24
Finished May 02 12:48:24 PM PDT 24
Peak memory 208196 kb
Host smart-1363cecc-1086-4db4-a0a5-e66dd11a69ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023811516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.4023811516
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.865884101
Short name T380
Test name
Test status
Simulation time 100043374 ps
CPU time 2.07 seconds
Started May 02 12:48:16 PM PDT 24
Finished May 02 12:48:20 PM PDT 24
Peak memory 209556 kb
Host smart-0cff2434-9886-4942-91f4-0875369058e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865884101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.865884101
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.146133753
Short name T99
Test name
Test status
Simulation time 52808663 ps
CPU time 0.71 seconds
Started May 02 12:48:08 PM PDT 24
Finished May 02 12:48:12 PM PDT 24
Peak memory 205508 kb
Host smart-42567912-ee58-48f0-a97a-c54b89869426
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146133753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.146133753
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.3908839683
Short name T799
Test name
Test status
Simulation time 1129138899 ps
CPU time 16.02 seconds
Started May 02 12:48:05 PM PDT 24
Finished May 02 12:48:24 PM PDT 24
Peak memory 222324 kb
Host smart-59841c01-418a-4949-aca9-fe745ae458f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908839683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.3908839683
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.1828414631
Short name T282
Test name
Test status
Simulation time 82227736 ps
CPU time 3.99 seconds
Started May 02 12:48:37 PM PDT 24
Finished May 02 12:48:46 PM PDT 24
Peak memory 214056 kb
Host smart-d9dea09f-838a-4e81-bd59-94303eaff4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828414631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.1828414631
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.3656100277
Short name T93
Test name
Test status
Simulation time 230257370 ps
CPU time 5.63 seconds
Started May 02 12:48:00 PM PDT 24
Finished May 02 12:48:10 PM PDT 24
Peak memory 213972 kb
Host smart-1bb59784-f9c7-4888-ac1c-3e927c88d843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656100277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.3656100277
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.3678630465
Short name T195
Test name
Test status
Simulation time 2019708447 ps
CPU time 11.69 seconds
Started May 02 12:48:12 PM PDT 24
Finished May 02 12:48:26 PM PDT 24
Peak memory 213964 kb
Host smart-96d308cd-af41-4c02-b8d3-a3b585c9e0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678630465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.3678630465
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.1764991967
Short name T17
Test name
Test status
Simulation time 368720893 ps
CPU time 4.55 seconds
Started May 02 12:48:20 PM PDT 24
Finished May 02 12:48:26 PM PDT 24
Peak memory 209440 kb
Host smart-de905214-16a8-4dd7-98e5-8830457cfa1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764991967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.1764991967
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.1301742598
Short name T301
Test name
Test status
Simulation time 204628264 ps
CPU time 3.22 seconds
Started May 02 12:48:03 PM PDT 24
Finished May 02 12:48:11 PM PDT 24
Peak memory 207740 kb
Host smart-3e403f9b-880a-446e-ad75-ac697583f2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301742598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.1301742598
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.3584951378
Short name T785
Test name
Test status
Simulation time 123944165 ps
CPU time 2.41 seconds
Started May 02 12:48:06 PM PDT 24
Finished May 02 12:48:12 PM PDT 24
Peak memory 206272 kb
Host smart-d446475f-5879-4802-ab37-2efcbe981c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584951378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.3584951378
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.942483498
Short name T883
Test name
Test status
Simulation time 433322397 ps
CPU time 3.96 seconds
Started May 02 12:47:59 PM PDT 24
Finished May 02 12:48:07 PM PDT 24
Peak memory 206436 kb
Host smart-15db3df8-0d1b-4bff-9082-386cce9fa84c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942483498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.942483498
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.1872317634
Short name T460
Test name
Test status
Simulation time 272122496 ps
CPU time 6.89 seconds
Started May 02 12:48:02 PM PDT 24
Finished May 02 12:48:13 PM PDT 24
Peak memory 206484 kb
Host smart-157fb9ec-d523-4031-a0f9-fb42bba70880
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872317634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.1872317634
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.1965500714
Short name T557
Test name
Test status
Simulation time 315857260 ps
CPU time 4.28 seconds
Started May 02 12:48:02 PM PDT 24
Finished May 02 12:48:11 PM PDT 24
Peak memory 208364 kb
Host smart-8fc9824c-79cf-44cc-a7a3-8a3adab5b794
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965500714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.1965500714
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.516169827
Short name T889
Test name
Test status
Simulation time 139116345 ps
CPU time 2.97 seconds
Started May 02 12:48:16 PM PDT 24
Finished May 02 12:48:22 PM PDT 24
Peak memory 207628 kb
Host smart-b6696f4e-d63b-410e-b505-5a6c890cd39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516169827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.516169827
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.1087678521
Short name T486
Test name
Test status
Simulation time 116307176 ps
CPU time 3.07 seconds
Started May 02 12:48:06 PM PDT 24
Finished May 02 12:48:13 PM PDT 24
Peak memory 206420 kb
Host smart-2adecc78-77d6-4371-b880-70b6d1585403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087678521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.1087678521
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.3223973056
Short name T904
Test name
Test status
Simulation time 706218969 ps
CPU time 11.35 seconds
Started May 02 12:48:01 PM PDT 24
Finished May 02 12:48:16 PM PDT 24
Peak memory 222316 kb
Host smart-e0570f86-f387-4571-aa19-3da430a87d72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223973056 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.3223973056
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.3430152325
Short name T184
Test name
Test status
Simulation time 443119123 ps
CPU time 2.88 seconds
Started May 02 12:48:11 PM PDT 24
Finished May 02 12:48:16 PM PDT 24
Peak memory 209444 kb
Host smart-e93fb617-b95b-4d29-a588-0bba4d0bdf42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430152325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.3430152325
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.3981999412
Short name T808
Test name
Test status
Simulation time 26600667 ps
CPU time 0.77 seconds
Started May 02 12:47:32 PM PDT 24
Finished May 02 12:47:35 PM PDT 24
Peak memory 205532 kb
Host smart-8331667f-6318-4df7-8c4c-0ca2625c2581
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981999412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.3981999412
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.3298437165
Short name T258
Test name
Test status
Simulation time 155428453 ps
CPU time 9.09 seconds
Started May 02 12:47:18 PM PDT 24
Finished May 02 12:47:32 PM PDT 24
Peak memory 214436 kb
Host smart-14ab321e-3010-4487-9fe8-c87ac3a2cecc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3298437165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.3298437165
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.1845593296
Short name T730
Test name
Test status
Simulation time 200057550 ps
CPU time 2.49 seconds
Started May 02 12:47:33 PM PDT 24
Finished May 02 12:47:38 PM PDT 24
Peak memory 217044 kb
Host smart-343cd3d2-4327-4ce6-b313-852d14966249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845593296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.1845593296
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.99603481
Short name T316
Test name
Test status
Simulation time 123357844 ps
CPU time 3.13 seconds
Started May 02 12:47:20 PM PDT 24
Finished May 02 12:47:27 PM PDT 24
Peak memory 208844 kb
Host smart-47efbc9b-b44e-4332-ba92-4734e1de5b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99603481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.99603481
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.127865393
Short name T365
Test name
Test status
Simulation time 1030087572 ps
CPU time 29.79 seconds
Started May 02 12:47:21 PM PDT 24
Finished May 02 12:47:54 PM PDT 24
Peak memory 218172 kb
Host smart-cf1c01de-410a-43b3-99c7-d282ec39885c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127865393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.127865393
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.3701946386
Short name T601
Test name
Test status
Simulation time 113950167 ps
CPU time 3.27 seconds
Started May 02 12:47:24 PM PDT 24
Finished May 02 12:47:30 PM PDT 24
Peak memory 208392 kb
Host smart-b37b2712-4784-43dc-8990-eb10117f051e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701946386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.3701946386
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.943392016
Short name T367
Test name
Test status
Simulation time 203204858 ps
CPU time 3.5 seconds
Started May 02 12:47:25 PM PDT 24
Finished May 02 12:47:31 PM PDT 24
Peak memory 208920 kb
Host smart-d9160964-5586-4358-b663-e2d5a075824f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943392016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.943392016
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.2802011895
Short name T12
Test name
Test status
Simulation time 5063015251 ps
CPU time 30.82 seconds
Started May 02 12:47:18 PM PDT 24
Finished May 02 12:47:52 PM PDT 24
Peak memory 243128 kb
Host smart-e6b383a3-4a0d-4b50-a3bb-0940bcd5028f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802011895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.2802011895
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.2111498780
Short name T259
Test name
Test status
Simulation time 128619074 ps
CPU time 4.06 seconds
Started May 02 12:47:19 PM PDT 24
Finished May 02 12:47:28 PM PDT 24
Peak memory 207900 kb
Host smart-a45da088-4522-4676-9801-a61ef022454f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111498780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.2111498780
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.1880723459
Short name T260
Test name
Test status
Simulation time 207188017 ps
CPU time 6.05 seconds
Started May 02 12:47:34 PM PDT 24
Finished May 02 12:47:42 PM PDT 24
Peak memory 207188 kb
Host smart-0065648a-4476-40a7-8d17-02633f2ffa9a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880723459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.1880723459
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.2296010432
Short name T771
Test name
Test status
Simulation time 288970026 ps
CPU time 4.72 seconds
Started May 02 12:47:35 PM PDT 24
Finished May 02 12:47:41 PM PDT 24
Peak memory 206548 kb
Host smart-c8c2a79d-5286-483b-9a87-c2002dcccb42
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296010432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.2296010432
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.1012466394
Short name T768
Test name
Test status
Simulation time 1663573079 ps
CPU time 16.92 seconds
Started May 02 12:47:20 PM PDT 24
Finished May 02 12:47:41 PM PDT 24
Peak memory 207788 kb
Host smart-f21935f2-4b37-4ee9-ad7c-f30df15312a8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012466394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.1012466394
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.1598676188
Short name T867
Test name
Test status
Simulation time 189937101 ps
CPU time 2.53 seconds
Started May 02 12:47:45 PM PDT 24
Finished May 02 12:47:51 PM PDT 24
Peak memory 218064 kb
Host smart-8addbbdd-77fe-4bda-9168-d2b33daf341b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598676188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.1598676188
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.1017529768
Short name T697
Test name
Test status
Simulation time 85782321 ps
CPU time 1.86 seconds
Started May 02 12:47:25 PM PDT 24
Finished May 02 12:47:29 PM PDT 24
Peak memory 206372 kb
Host smart-0a5605f3-730f-4c07-9678-45ba9ffe4ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017529768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.1017529768
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.1313623497
Short name T74
Test name
Test status
Simulation time 4060095269 ps
CPU time 42.08 seconds
Started May 02 12:47:33 PM PDT 24
Finished May 02 12:48:17 PM PDT 24
Peak memory 222068 kb
Host smart-a5bfc1ed-d282-42ec-9cb8-7ca1ef8635b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313623497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.1313623497
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.3887805741
Short name T726
Test name
Test status
Simulation time 1101888023 ps
CPU time 23.99 seconds
Started May 02 12:47:20 PM PDT 24
Finished May 02 12:47:48 PM PDT 24
Peak memory 208512 kb
Host smart-083e3535-a443-46f8-b872-c6c56894b1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887805741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.3887805741
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.1077531924
Short name T39
Test name
Test status
Simulation time 97946305 ps
CPU time 2.41 seconds
Started May 02 12:47:17 PM PDT 24
Finished May 02 12:47:23 PM PDT 24
Peak memory 209528 kb
Host smart-0d07b882-5e7f-40d9-918d-5d308f3ffa39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077531924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.1077531924
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.395634452
Short name T474
Test name
Test status
Simulation time 43323606 ps
CPU time 0.82 seconds
Started May 02 12:48:31 PM PDT 24
Finished May 02 12:48:35 PM PDT 24
Peak memory 205540 kb
Host smart-13aefc88-6be2-4ffd-badc-0c31a8ba985f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395634452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.395634452
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.1201523142
Short name T577
Test name
Test status
Simulation time 28818338 ps
CPU time 2.03 seconds
Started May 02 12:48:08 PM PDT 24
Finished May 02 12:48:13 PM PDT 24
Peak memory 209272 kb
Host smart-cf2c27f5-a164-4f32-9b8c-bf818afdfe1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201523142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.1201523142
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.4151831416
Short name T320
Test name
Test status
Simulation time 30321758 ps
CPU time 2.26 seconds
Started May 02 12:48:02 PM PDT 24
Finished May 02 12:48:08 PM PDT 24
Peak memory 217856 kb
Host smart-3833b48d-0b3f-4f80-a26d-a5a4cfdda021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151831416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.4151831416
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.3469273485
Short name T505
Test name
Test status
Simulation time 671476554 ps
CPU time 5.58 seconds
Started May 02 12:48:06 PM PDT 24
Finished May 02 12:48:15 PM PDT 24
Peak memory 214656 kb
Host smart-52c3cd3e-4ed6-4a60-a26e-380a76a91985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469273485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.3469273485
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.2254696938
Short name T839
Test name
Test status
Simulation time 836922966 ps
CPU time 11.3 seconds
Started May 02 12:48:02 PM PDT 24
Finished May 02 12:48:18 PM PDT 24
Peak memory 213988 kb
Host smart-0a81403c-ac46-4d0e-b278-6d41509e5fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254696938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.2254696938
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.3118512346
Short name T15
Test name
Test status
Simulation time 156684430 ps
CPU time 3.47 seconds
Started May 02 12:48:05 PM PDT 24
Finished May 02 12:48:12 PM PDT 24
Peak memory 207952 kb
Host smart-c7129c6e-d9ac-4b16-a5db-08a82b74eac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118512346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.3118512346
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.3094159036
Short name T563
Test name
Test status
Simulation time 235445035 ps
CPU time 3.35 seconds
Started May 02 12:48:08 PM PDT 24
Finished May 02 12:48:14 PM PDT 24
Peak memory 208348 kb
Host smart-0325c6b4-430c-47a5-b5ac-c5d383649f52
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094159036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.3094159036
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.4169135659
Short name T837
Test name
Test status
Simulation time 51048583 ps
CPU time 2.7 seconds
Started May 02 12:48:00 PM PDT 24
Finished May 02 12:48:07 PM PDT 24
Peak memory 207652 kb
Host smart-da97e4bc-5880-431e-9a13-1de50fd3683a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169135659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.4169135659
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.2008224180
Short name T338
Test name
Test status
Simulation time 3714148021 ps
CPU time 39.68 seconds
Started May 02 12:48:14 PM PDT 24
Finished May 02 12:48:57 PM PDT 24
Peak memory 207740 kb
Host smart-13679558-39ec-4b3c-85bf-e05509ea8244
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008224180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.2008224180
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.3730779543
Short name T244
Test name
Test status
Simulation time 445534589 ps
CPU time 3.82 seconds
Started May 02 12:48:04 PM PDT 24
Finished May 02 12:48:12 PM PDT 24
Peak memory 208352 kb
Host smart-180d90e8-c2d0-42c9-b1dd-136d24912757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730779543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.3730779543
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.741047055
Short name T871
Test name
Test status
Simulation time 52450797 ps
CPU time 2.03 seconds
Started May 02 12:48:07 PM PDT 24
Finished May 02 12:48:12 PM PDT 24
Peak memory 207888 kb
Host smart-3b3a1528-2966-4f61-a034-316a95da3e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741047055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.741047055
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.1037211532
Short name T613
Test name
Test status
Simulation time 408358958 ps
CPU time 16.32 seconds
Started May 02 12:48:07 PM PDT 24
Finished May 02 12:48:26 PM PDT 24
Peak memory 219600 kb
Host smart-eeab1b7f-9c48-4445-a0c0-0c76d77f8290
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037211532 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.1037211532
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.1646452584
Short name T334
Test name
Test status
Simulation time 80120702 ps
CPU time 3.59 seconds
Started May 02 12:48:14 PM PDT 24
Finished May 02 12:48:20 PM PDT 24
Peak memory 208364 kb
Host smart-89330be3-87de-48a7-8505-f38a935be669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646452584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.1646452584
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.1283228776
Short name T490
Test name
Test status
Simulation time 50576151 ps
CPU time 2.45 seconds
Started May 02 12:48:12 PM PDT 24
Finished May 02 12:48:17 PM PDT 24
Peak memory 209368 kb
Host smart-1b145656-e0f8-4f1c-adf4-74dbe1b6fb19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283228776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.1283228776
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.2023492923
Short name T802
Test name
Test status
Simulation time 11250651 ps
CPU time 0.79 seconds
Started May 02 12:48:13 PM PDT 24
Finished May 02 12:48:17 PM PDT 24
Peak memory 205688 kb
Host smart-a249abcd-1939-4bdc-9737-55c7f6d4cd9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023492923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.2023492923
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.4237565146
Short name T212
Test name
Test status
Simulation time 283054084 ps
CPU time 4.43 seconds
Started May 02 12:48:10 PM PDT 24
Finished May 02 12:48:17 PM PDT 24
Peak memory 208280 kb
Host smart-e5d1b6f2-2608-47ac-81a9-8764c08b9f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237565146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.4237565146
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.3915456420
Short name T522
Test name
Test status
Simulation time 161293777 ps
CPU time 3.79 seconds
Started May 02 12:48:14 PM PDT 24
Finished May 02 12:48:21 PM PDT 24
Peak memory 214088 kb
Host smart-42a68565-ce10-47e9-a5e9-7286c5627562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915456420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.3915456420
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.1578829308
Short name T684
Test name
Test status
Simulation time 1439871507 ps
CPU time 4.54 seconds
Started May 02 12:48:05 PM PDT 24
Finished May 02 12:48:13 PM PDT 24
Peak memory 208564 kb
Host smart-2738f418-dbd5-4cc5-9a19-82fa7f57eccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578829308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.1578829308
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.3516403790
Short name T273
Test name
Test status
Simulation time 1538031081 ps
CPU time 50.14 seconds
Started May 02 12:48:18 PM PDT 24
Finished May 02 12:49:10 PM PDT 24
Peak memory 213400 kb
Host smart-8b891e76-e4f7-4334-bb7e-ec41e6f28407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516403790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.3516403790
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_random.1017713876
Short name T597
Test name
Test status
Simulation time 716559624 ps
CPU time 3.76 seconds
Started May 02 12:48:24 PM PDT 24
Finished May 02 12:48:31 PM PDT 24
Peak memory 214016 kb
Host smart-6e6c21f8-fb94-44ff-8872-c3701b8b2286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017713876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.1017713876
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.4227638197
Short name T717
Test name
Test status
Simulation time 27772649 ps
CPU time 2.03 seconds
Started May 02 12:48:21 PM PDT 24
Finished May 02 12:48:25 PM PDT 24
Peak memory 208328 kb
Host smart-d4f4ce9c-1655-45e1-bccd-2cb1bc2d7fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227638197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.4227638197
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.1358943679
Short name T880
Test name
Test status
Simulation time 210606477 ps
CPU time 2.96 seconds
Started May 02 12:48:11 PM PDT 24
Finished May 02 12:48:16 PM PDT 24
Peak memory 206396 kb
Host smart-1bf25361-8803-42eb-a821-53f6f36d67dc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358943679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.1358943679
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.2438092684
Short name T331
Test name
Test status
Simulation time 110259745 ps
CPU time 2.8 seconds
Started May 02 12:48:31 PM PDT 24
Finished May 02 12:48:36 PM PDT 24
Peak memory 207420 kb
Host smart-a1c91140-9af7-489f-ae81-581b4fd9089c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438092684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.2438092684
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.3627817148
Short name T481
Test name
Test status
Simulation time 1077814293 ps
CPU time 26.61 seconds
Started May 02 12:48:21 PM PDT 24
Finished May 02 12:48:49 PM PDT 24
Peak memory 207580 kb
Host smart-a42b328f-3068-4744-94ad-848268770f42
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627817148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.3627817148
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.4035929003
Short name T659
Test name
Test status
Simulation time 127218017 ps
CPU time 3.65 seconds
Started May 02 12:48:25 PM PDT 24
Finished May 02 12:48:32 PM PDT 24
Peak memory 214000 kb
Host smart-d84539db-6c7b-45d8-8903-050f6dc0be75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035929003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.4035929003
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.1708701727
Short name T853
Test name
Test status
Simulation time 118829280 ps
CPU time 4.65 seconds
Started May 02 12:48:07 PM PDT 24
Finished May 02 12:48:15 PM PDT 24
Peak memory 208224 kb
Host smart-2dca723c-b45d-490b-b676-2884c2ff7cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708701727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.1708701727
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.292400537
Short name T251
Test name
Test status
Simulation time 707051021 ps
CPU time 3.9 seconds
Started May 02 12:48:36 PM PDT 24
Finished May 02 12:48:43 PM PDT 24
Peak memory 207620 kb
Host smart-3853b551-3779-433b-9ffa-32b534a1b018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292400537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.292400537
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.35913090
Short name T540
Test name
Test status
Simulation time 98606231 ps
CPU time 3.39 seconds
Started May 02 12:48:13 PM PDT 24
Finished May 02 12:48:19 PM PDT 24
Peak memory 210012 kb
Host smart-042e291b-475e-4e59-b575-9d372709fc8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35913090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.35913090
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.4063417632
Short name T435
Test name
Test status
Simulation time 17090712 ps
CPU time 0.74 seconds
Started May 02 12:48:10 PM PDT 24
Finished May 02 12:48:13 PM PDT 24
Peak memory 205500 kb
Host smart-6373047e-ede4-4cd5-9fd3-ad09272dd660
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063417632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.4063417632
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.764860001
Short name T421
Test name
Test status
Simulation time 33885973 ps
CPU time 2.73 seconds
Started May 02 12:48:36 PM PDT 24
Finished May 02 12:48:42 PM PDT 24
Peak memory 214916 kb
Host smart-8f5c1cbd-9cc7-4d4d-bd87-d784f5578fa7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=764860001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.764860001
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.3260543956
Short name T777
Test name
Test status
Simulation time 1013757363 ps
CPU time 11.6 seconds
Started May 02 12:48:22 PM PDT 24
Finished May 02 12:48:36 PM PDT 24
Peak memory 208784 kb
Host smart-b6d99f50-f587-498f-bc33-42c43d9b1ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260543956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.3260543956
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.278468031
Short name T310
Test name
Test status
Simulation time 105791635 ps
CPU time 3.62 seconds
Started May 02 12:48:07 PM PDT 24
Finished May 02 12:48:14 PM PDT 24
Peak memory 222228 kb
Host smart-e3062dc2-8a12-4cf2-a1be-d070ea66396c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278468031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.278468031
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.646081933
Short name T821
Test name
Test status
Simulation time 159238921 ps
CPU time 4.06 seconds
Started May 02 12:48:16 PM PDT 24
Finished May 02 12:48:23 PM PDT 24
Peak memory 216644 kb
Host smart-1bb156dd-5633-48b5-9444-922f104532ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646081933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.646081933
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.632422271
Short name T477
Test name
Test status
Simulation time 484086855 ps
CPU time 6.37 seconds
Started May 02 12:48:11 PM PDT 24
Finished May 02 12:48:20 PM PDT 24
Peak memory 213940 kb
Host smart-f8b8b1b7-0d34-4ab3-aedb-0f4199553553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632422271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.632422271
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.4135449879
Short name T454
Test name
Test status
Simulation time 182079878 ps
CPU time 5.64 seconds
Started May 02 12:48:26 PM PDT 24
Finished May 02 12:48:35 PM PDT 24
Peak memory 207484 kb
Host smart-7c072132-cb10-4cb3-8a65-3b16a87bd8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135449879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.4135449879
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.1909271348
Short name T665
Test name
Test status
Simulation time 1071317701 ps
CPU time 8.01 seconds
Started May 02 12:48:10 PM PDT 24
Finished May 02 12:48:20 PM PDT 24
Peak memory 208032 kb
Host smart-3cd2351a-9812-4e72-b0be-7f3749845e9e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909271348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.1909271348
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.289869265
Short name T621
Test name
Test status
Simulation time 31911180 ps
CPU time 1.97 seconds
Started May 02 12:48:26 PM PDT 24
Finished May 02 12:48:31 PM PDT 24
Peak memory 207772 kb
Host smart-e1f556d2-537e-4844-8abb-6c8fac65379d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289869265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.289869265
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.3499520448
Short name T651
Test name
Test status
Simulation time 606965011 ps
CPU time 4.42 seconds
Started May 02 12:48:18 PM PDT 24
Finished May 02 12:48:25 PM PDT 24
Peak memory 206448 kb
Host smart-efec38ec-652d-4d27-bae9-05ed4f61f41f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499520448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.3499520448
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.115551491
Short name T198
Test name
Test status
Simulation time 623697641 ps
CPU time 3.9 seconds
Started May 02 12:48:29 PM PDT 24
Finished May 02 12:48:37 PM PDT 24
Peak memory 214760 kb
Host smart-cac604f2-3fbb-4a4b-9914-899589f7e8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115551491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.115551491
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.1125942758
Short name T475
Test name
Test status
Simulation time 721867788 ps
CPU time 5.35 seconds
Started May 02 12:48:10 PM PDT 24
Finished May 02 12:48:18 PM PDT 24
Peak memory 206256 kb
Host smart-a58d1d12-12b8-456e-8831-dcb5f3453f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125942758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.1125942758
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.335457989
Short name T649
Test name
Test status
Simulation time 129205749 ps
CPU time 5.26 seconds
Started May 02 12:48:15 PM PDT 24
Finished May 02 12:48:23 PM PDT 24
Peak memory 208392 kb
Host smart-574d6f5c-6581-442e-bed0-ae51280062c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335457989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.335457989
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.972300434
Short name T160
Test name
Test status
Simulation time 877663869 ps
CPU time 7.34 seconds
Started May 02 12:48:23 PM PDT 24
Finished May 02 12:48:34 PM PDT 24
Peak memory 210484 kb
Host smart-d6c859bc-6956-4b56-ae97-b13e0d78510b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972300434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.972300434
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.852573328
Short name T769
Test name
Test status
Simulation time 29789978 ps
CPU time 0.75 seconds
Started May 02 12:48:39 PM PDT 24
Finished May 02 12:48:45 PM PDT 24
Peak memory 205464 kb
Host smart-3a04445a-4dbf-4974-bf57-6415f890e175
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852573328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.852573328
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.843684284
Short name T387
Test name
Test status
Simulation time 1025675409 ps
CPU time 8.89 seconds
Started May 02 12:48:22 PM PDT 24
Finished May 02 12:48:33 PM PDT 24
Peak memory 214088 kb
Host smart-e7120db1-5b3a-4b05-8054-b1e6a70ef319
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=843684284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.843684284
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.3325511721
Short name T569
Test name
Test status
Simulation time 2208548838 ps
CPU time 24.67 seconds
Started May 02 12:48:36 PM PDT 24
Finished May 02 12:49:04 PM PDT 24
Peak memory 214380 kb
Host smart-89882111-9626-477c-b53b-6b863d4392da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325511721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.3325511721
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.2582867125
Short name T500
Test name
Test status
Simulation time 971514651 ps
CPU time 29.96 seconds
Started May 02 12:48:17 PM PDT 24
Finished May 02 12:48:49 PM PDT 24
Peak memory 213988 kb
Host smart-5fcea515-3294-47a2-846f-b7443f24b0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582867125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.2582867125
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.1143509262
Short name T363
Test name
Test status
Simulation time 513489576 ps
CPU time 5.3 seconds
Started May 02 12:48:14 PM PDT 24
Finished May 02 12:48:23 PM PDT 24
Peak memory 213968 kb
Host smart-9a7677fd-bca2-426a-8b02-d5fcadc8b4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143509262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.1143509262
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.2731556449
Short name T868
Test name
Test status
Simulation time 38681787 ps
CPU time 2.86 seconds
Started May 02 12:48:36 PM PDT 24
Finished May 02 12:48:43 PM PDT 24
Peak memory 208552 kb
Host smart-9e46af62-6b43-415d-b9d6-b162c6863204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731556449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.2731556449
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.4080900577
Short name T221
Test name
Test status
Simulation time 140535465 ps
CPU time 2.6 seconds
Started May 02 12:48:14 PM PDT 24
Finished May 02 12:48:20 PM PDT 24
Peak memory 218584 kb
Host smart-a35775a7-2174-43cf-b595-c4d40e0b2cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080900577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.4080900577
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.3162148119
Short name T813
Test name
Test status
Simulation time 74905168 ps
CPU time 3.57 seconds
Started May 02 12:48:34 PM PDT 24
Finished May 02 12:48:40 PM PDT 24
Peak memory 208624 kb
Host smart-adca909a-ebfe-4cec-9af8-9d2664189d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162148119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.3162148119
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.343024339
Short name T257
Test name
Test status
Simulation time 199867517 ps
CPU time 3.19 seconds
Started May 02 12:48:20 PM PDT 24
Finished May 02 12:48:25 PM PDT 24
Peak memory 206188 kb
Host smart-0b2f6dc5-5af4-4aff-803f-b459ff61d2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343024339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.343024339
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.3343765288
Short name T516
Test name
Test status
Simulation time 513502543 ps
CPU time 4.06 seconds
Started May 02 12:48:36 PM PDT 24
Finished May 02 12:48:44 PM PDT 24
Peak memory 208420 kb
Host smart-20da35f5-5a5d-48a0-b423-f5299c902460
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343765288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.3343765288
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.555169754
Short name T519
Test name
Test status
Simulation time 72722171 ps
CPU time 2.25 seconds
Started May 02 12:48:20 PM PDT 24
Finished May 02 12:48:24 PM PDT 24
Peak memory 206376 kb
Host smart-e69054e1-0762-485a-b262-8f7ad7005741
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555169754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.555169754
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.2587523630
Short name T804
Test name
Test status
Simulation time 565597136 ps
CPU time 4.91 seconds
Started May 02 12:48:31 PM PDT 24
Finished May 02 12:48:39 PM PDT 24
Peak memory 208164 kb
Host smart-116df35a-1ed6-43d4-88c7-c0321b30ab13
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587523630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.2587523630
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.3319202682
Short name T465
Test name
Test status
Simulation time 855428425 ps
CPU time 4.34 seconds
Started May 02 12:48:14 PM PDT 24
Finished May 02 12:48:22 PM PDT 24
Peak memory 208916 kb
Host smart-53b7f7be-a882-4b00-abc9-2836c6b81885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319202682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.3319202682
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.1512871308
Short name T398
Test name
Test status
Simulation time 2523918343 ps
CPU time 7.35 seconds
Started May 02 12:48:14 PM PDT 24
Finished May 02 12:48:24 PM PDT 24
Peak memory 208184 kb
Host smart-335d93fa-7bfe-4d8b-950a-255b37e92f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512871308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.1512871308
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.1120712468
Short name T50
Test name
Test status
Simulation time 790741700 ps
CPU time 16.63 seconds
Started May 02 12:48:32 PM PDT 24
Finished May 02 12:48:51 PM PDT 24
Peak memory 215140 kb
Host smart-74bb629f-3cdc-4e39-a468-02eed54a8169
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120712468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.1120712468
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.1935626299
Short name T178
Test name
Test status
Simulation time 715590656 ps
CPU time 13.26 seconds
Started May 02 12:48:39 PM PDT 24
Finished May 02 12:48:58 PM PDT 24
Peak memory 222292 kb
Host smart-cb5b9e72-efb3-4626-be83-ffd04d3d2201
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935626299 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.1935626299
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.4071985444
Short name T245
Test name
Test status
Simulation time 710294779 ps
CPU time 5.8 seconds
Started May 02 12:48:19 PM PDT 24
Finished May 02 12:48:27 PM PDT 24
Peak memory 217720 kb
Host smart-2a2ea459-3531-4e0d-bf41-1e909d004bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071985444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.4071985444
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.3521904996
Short name T539
Test name
Test status
Simulation time 283431678 ps
CPU time 2.79 seconds
Started May 02 12:48:04 PM PDT 24
Finished May 02 12:48:10 PM PDT 24
Peak memory 209752 kb
Host smart-94e8b8ef-abae-48bb-8d3d-cacc8aeb4100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521904996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.3521904996
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.43489487
Short name T469
Test name
Test status
Simulation time 29289729 ps
CPU time 0.81 seconds
Started May 02 12:48:25 PM PDT 24
Finished May 02 12:48:30 PM PDT 24
Peak memory 205464 kb
Host smart-534a2366-354b-4801-bd59-3c5cd57a3c98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43489487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.43489487
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.3466446984
Short name T414
Test name
Test status
Simulation time 100795622 ps
CPU time 3.84 seconds
Started May 02 12:48:13 PM PDT 24
Finished May 02 12:48:20 PM PDT 24
Peak memory 215128 kb
Host smart-5e55da85-02d5-4987-8d3d-fcf4ac9d0808
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3466446984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.3466446984
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.2324164409
Short name T478
Test name
Test status
Simulation time 93178572 ps
CPU time 3.27 seconds
Started May 02 12:48:33 PM PDT 24
Finished May 02 12:48:39 PM PDT 24
Peak memory 209456 kb
Host smart-26e7d45c-b2fc-42f5-a73a-cd93502e2064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324164409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.2324164409
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.3277879401
Short name T28
Test name
Test status
Simulation time 906968966 ps
CPU time 9.03 seconds
Started May 02 12:48:12 PM PDT 24
Finished May 02 12:48:24 PM PDT 24
Peak memory 218908 kb
Host smart-f12904c3-e6fc-4265-bfa5-7be23aed8fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277879401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.3277879401
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.792196169
Short name T261
Test name
Test status
Simulation time 213958166 ps
CPU time 6.59 seconds
Started May 02 12:48:21 PM PDT 24
Finished May 02 12:48:29 PM PDT 24
Peak memory 222088 kb
Host smart-7f2796bf-95e0-4f09-96ef-e818a33bedee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792196169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.792196169
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.2874280383
Short name T882
Test name
Test status
Simulation time 1101625379 ps
CPU time 6.2 seconds
Started May 02 12:48:17 PM PDT 24
Finished May 02 12:48:26 PM PDT 24
Peak memory 219920 kb
Host smart-33114268-5651-4d63-ac27-07696bfd968f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874280383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.2874280383
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.2130160913
Short name T514
Test name
Test status
Simulation time 631552570 ps
CPU time 3.83 seconds
Started May 02 12:48:28 PM PDT 24
Finished May 02 12:48:35 PM PDT 24
Peak memory 206688 kb
Host smart-848f7de0-c541-4d1d-84a9-787ec750ec02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130160913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.2130160913
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.1607925902
Short name T321
Test name
Test status
Simulation time 171901499 ps
CPU time 6.96 seconds
Started May 02 12:48:12 PM PDT 24
Finished May 02 12:48:21 PM PDT 24
Peak memory 208088 kb
Host smart-33da89f9-d4b3-40b3-a1b7-8c8df39da28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607925902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.1607925902
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.4045500819
Short name T891
Test name
Test status
Simulation time 66005607 ps
CPU time 3.28 seconds
Started May 02 12:48:19 PM PDT 24
Finished May 02 12:48:24 PM PDT 24
Peak memory 208380 kb
Host smart-c35da4f5-def8-4873-9b4e-6f596cf6db0c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045500819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.4045500819
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.2823212615
Short name T470
Test name
Test status
Simulation time 82921053 ps
CPU time 1.94 seconds
Started May 02 12:48:34 PM PDT 24
Finished May 02 12:48:39 PM PDT 24
Peak memory 206904 kb
Host smart-6d18442b-c27b-4dbf-9a15-4066ae77ff18
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823212615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.2823212615
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.569571877
Short name T624
Test name
Test status
Simulation time 18472236080 ps
CPU time 52.07 seconds
Started May 02 12:48:11 PM PDT 24
Finished May 02 12:49:05 PM PDT 24
Peak memory 207764 kb
Host smart-413c4a4d-52ef-46c9-b924-2f60b69fae33
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569571877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.569571877
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.1313525250
Short name T471
Test name
Test status
Simulation time 74392762 ps
CPU time 3.4 seconds
Started May 02 12:48:23 PM PDT 24
Finished May 02 12:48:30 PM PDT 24
Peak memory 217924 kb
Host smart-a98c88fd-544f-448c-baba-647f26dd1c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313525250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.1313525250
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.2887193531
Short name T568
Test name
Test status
Simulation time 381727614 ps
CPU time 2.72 seconds
Started May 02 12:48:13 PM PDT 24
Finished May 02 12:48:19 PM PDT 24
Peak memory 206324 kb
Host smart-175b791d-31f5-428c-97a6-6eecda47fabb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887193531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.2887193531
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.2446404677
Short name T324
Test name
Test status
Simulation time 241026474 ps
CPU time 9.8 seconds
Started May 02 12:48:12 PM PDT 24
Finished May 02 12:48:25 PM PDT 24
Peak memory 208096 kb
Host smart-5bf552c4-d893-40bb-85f5-69d69e493055
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446404677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.2446404677
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.3192845484
Short name T718
Test name
Test status
Simulation time 217190987 ps
CPU time 9.07 seconds
Started May 02 12:48:10 PM PDT 24
Finished May 02 12:48:21 PM PDT 24
Peak memory 219388 kb
Host smart-3743b07e-db2c-476c-8478-08365a4808e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192845484 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.3192845484
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.3208910784
Short name T534
Test name
Test status
Simulation time 110361884 ps
CPU time 5.55 seconds
Started May 02 12:48:11 PM PDT 24
Finished May 02 12:48:19 PM PDT 24
Peak memory 208452 kb
Host smart-06ae75a7-716b-4376-8db6-b5a5aa0d1b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208910784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.3208910784
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.3100400350
Short name T708
Test name
Test status
Simulation time 11170177 ps
CPU time 0.75 seconds
Started May 02 12:48:40 PM PDT 24
Finished May 02 12:48:47 PM PDT 24
Peak memory 205696 kb
Host smart-e4dc6206-8109-4407-890d-716bb9548fa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100400350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.3100400350
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.2734313952
Short name T413
Test name
Test status
Simulation time 2529510678 ps
CPU time 11.76 seconds
Started May 02 12:48:33 PM PDT 24
Finished May 02 12:48:48 PM PDT 24
Peak memory 215296 kb
Host smart-a6a2b757-8176-4d64-a6e6-6ef6cd254d53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2734313952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.2734313952
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.3958900685
Short name T272
Test name
Test status
Simulation time 180451039 ps
CPU time 3.02 seconds
Started May 02 12:48:33 PM PDT 24
Finished May 02 12:48:39 PM PDT 24
Peak memory 209408 kb
Host smart-ce65469e-6034-441d-afc2-db6e07c4f3c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958900685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.3958900685
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.1759316461
Short name T791
Test name
Test status
Simulation time 738729985 ps
CPU time 18.5 seconds
Started May 02 12:48:12 PM PDT 24
Finished May 02 12:48:34 PM PDT 24
Peak memory 218696 kb
Host smart-cecc3bce-379d-48d7-85ae-7eaa94478509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759316461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.1759316461
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.1851529600
Short name T377
Test name
Test status
Simulation time 191615490 ps
CPU time 3.14 seconds
Started May 02 12:48:37 PM PDT 24
Finished May 02 12:48:43 PM PDT 24
Peak memory 207832 kb
Host smart-cb502183-09cf-4b31-88fa-8f3996bbb3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851529600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.1851529600
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.3575840302
Short name T633
Test name
Test status
Simulation time 495731075 ps
CPU time 11.79 seconds
Started May 02 12:48:12 PM PDT 24
Finished May 02 12:48:27 PM PDT 24
Peak memory 208620 kb
Host smart-80302fdb-f7cf-4c83-bed1-efc9cf48c471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575840302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.3575840302
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.2027360177
Short name T542
Test name
Test status
Simulation time 1009470301 ps
CPU time 3.46 seconds
Started May 02 12:48:22 PM PDT 24
Finished May 02 12:48:27 PM PDT 24
Peak memory 206544 kb
Host smart-7fdc871d-6f5c-4ddc-875f-de100a7a0a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027360177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.2027360177
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.1182136895
Short name T104
Test name
Test status
Simulation time 86993327 ps
CPU time 1.78 seconds
Started May 02 12:48:16 PM PDT 24
Finished May 02 12:48:20 PM PDT 24
Peak memory 206452 kb
Host smart-ab3ef4e2-cf00-4ec9-b006-acc4c7f930d7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182136895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.1182136895
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.2712572201
Short name T834
Test name
Test status
Simulation time 1926711855 ps
CPU time 48.18 seconds
Started May 02 12:48:12 PM PDT 24
Finished May 02 12:49:04 PM PDT 24
Peak memory 207688 kb
Host smart-96944570-07ee-4376-bb84-82531c3b61d5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712572201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.2712572201
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.2015574727
Short name T515
Test name
Test status
Simulation time 54285616 ps
CPU time 2.85 seconds
Started May 02 12:48:27 PM PDT 24
Finished May 02 12:48:33 PM PDT 24
Peak memory 206480 kb
Host smart-5c6976fd-4b2b-4f2d-a14e-d99a1921dd68
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015574727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.2015574727
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.3529199000
Short name T683
Test name
Test status
Simulation time 247921340 ps
CPU time 2.6 seconds
Started May 02 12:48:12 PM PDT 24
Finished May 02 12:48:17 PM PDT 24
Peak memory 207424 kb
Host smart-483948b4-13bf-4f2a-9ad6-3713a4b8da87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529199000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.3529199000
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.1846085191
Short name T713
Test name
Test status
Simulation time 65308169 ps
CPU time 2.98 seconds
Started May 02 12:48:36 PM PDT 24
Finished May 02 12:48:43 PM PDT 24
Peak memory 207596 kb
Host smart-34dda431-8402-4db1-b0a9-a30651542556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846085191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.1846085191
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.296711530
Short name T65
Test name
Test status
Simulation time 2632613715 ps
CPU time 15.03 seconds
Started May 02 12:48:17 PM PDT 24
Finished May 02 12:48:35 PM PDT 24
Peak memory 220880 kb
Host smart-2c4123ca-106d-4fbd-92dd-437d538a9671
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296711530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.296711530
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.3319704343
Short name T312
Test name
Test status
Simulation time 212444723 ps
CPU time 5.26 seconds
Started May 02 12:48:18 PM PDT 24
Finished May 02 12:48:25 PM PDT 24
Peak memory 217908 kb
Host smart-426f0490-4c65-47e8-8231-6882c4873f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319704343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.3319704343
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.3066717547
Short name T172
Test name
Test status
Simulation time 110328374 ps
CPU time 2.06 seconds
Started May 02 12:48:27 PM PDT 24
Finished May 02 12:48:33 PM PDT 24
Peak memory 209604 kb
Host smart-41973af7-95db-4799-a782-fd852fd6ff15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066717547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.3066717547
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.4243574688
Short name T432
Test name
Test status
Simulation time 52569714 ps
CPU time 0.77 seconds
Started May 02 12:48:35 PM PDT 24
Finished May 02 12:48:39 PM PDT 24
Peak memory 205652 kb
Host smart-279b3e5d-a643-41d0-a836-bb92ce6ecb05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243574688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.4243574688
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.2154131125
Short name T296
Test name
Test status
Simulation time 694651202 ps
CPU time 3.49 seconds
Started May 02 12:48:31 PM PDT 24
Finished May 02 12:48:37 PM PDT 24
Peak memory 214016 kb
Host smart-5cc84087-4508-46ab-830c-ae1779632b7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2154131125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.2154131125
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.352999434
Short name T694
Test name
Test status
Simulation time 663550237 ps
CPU time 9.89 seconds
Started May 02 12:48:35 PM PDT 24
Finished May 02 12:48:47 PM PDT 24
Peak memory 221312 kb
Host smart-b5c9bc75-0bff-4bbb-a461-cc81ce1237e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352999434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.352999434
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.3329596718
Short name T600
Test name
Test status
Simulation time 67812561 ps
CPU time 3.26 seconds
Started May 02 12:48:37 PM PDT 24
Finished May 02 12:48:44 PM PDT 24
Peak memory 208952 kb
Host smart-11c130d5-df50-4c31-ae64-4cab2f649fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329596718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.3329596718
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.3052434346
Short name T695
Test name
Test status
Simulation time 125881377 ps
CPU time 4.96 seconds
Started May 02 12:48:19 PM PDT 24
Finished May 02 12:48:26 PM PDT 24
Peak memory 222108 kb
Host smart-8e69415e-58bf-4970-86c2-2d1583983e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052434346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.3052434346
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.487184329
Short name T761
Test name
Test status
Simulation time 76607407 ps
CPU time 3.89 seconds
Started May 02 12:48:28 PM PDT 24
Finished May 02 12:48:36 PM PDT 24
Peak memory 214024 kb
Host smart-8a972b26-4d40-49f5-a1cc-6ba8b7b86b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487184329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.487184329
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.1920377064
Short name T109
Test name
Test status
Simulation time 125756129 ps
CPU time 1.82 seconds
Started May 02 12:48:37 PM PDT 24
Finished May 02 12:48:42 PM PDT 24
Peak memory 205836 kb
Host smart-0f58b973-2f8d-4267-8b19-789556046609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920377064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.1920377064
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.1551713711
Short name T668
Test name
Test status
Simulation time 242357606 ps
CPU time 5.35 seconds
Started May 02 12:48:12 PM PDT 24
Finished May 02 12:48:20 PM PDT 24
Peak memory 209560 kb
Host smart-4f4c4eff-6e81-4810-ad40-cd001e8a2049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551713711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.1551713711
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.2269444331
Short name T676
Test name
Test status
Simulation time 129848214 ps
CPU time 4.8 seconds
Started May 02 12:48:36 PM PDT 24
Finished May 02 12:48:44 PM PDT 24
Peak memory 206444 kb
Host smart-83cfbb25-9f36-4238-90c5-5d3487841548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269444331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.2269444331
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.4158617786
Short name T709
Test name
Test status
Simulation time 113841174 ps
CPU time 2.4 seconds
Started May 02 12:48:12 PM PDT 24
Finished May 02 12:48:17 PM PDT 24
Peak memory 208420 kb
Host smart-6cdbf5b4-8335-4d2d-bbff-1e8f81e46794
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158617786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.4158617786
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.42908917
Short name T520
Test name
Test status
Simulation time 7134409916 ps
CPU time 64.07 seconds
Started May 02 12:48:14 PM PDT 24
Finished May 02 12:49:21 PM PDT 24
Peak memory 207532 kb
Host smart-0e780e40-aecc-4614-b97f-8a0e28035b57
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42908917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.42908917
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.3931287299
Short name T596
Test name
Test status
Simulation time 513717623 ps
CPU time 6.85 seconds
Started May 02 12:48:45 PM PDT 24
Finished May 02 12:48:58 PM PDT 24
Peak memory 208244 kb
Host smart-58a43935-5d1a-428c-8986-6bbb4e6a4df9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931287299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.3931287299
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.1422615364
Short name T495
Test name
Test status
Simulation time 91197308 ps
CPU time 3.49 seconds
Started May 02 12:48:11 PM PDT 24
Finished May 02 12:48:17 PM PDT 24
Peak memory 220032 kb
Host smart-e9dc84bd-b7cf-45ec-858f-0b249ee190e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422615364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.1422615364
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.3231590819
Short name T452
Test name
Test status
Simulation time 1017253158 ps
CPU time 22.46 seconds
Started May 02 12:48:12 PM PDT 24
Finished May 02 12:48:37 PM PDT 24
Peak memory 207956 kb
Host smart-1713ac96-407e-424f-abf7-9b81e818a426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231590819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.3231590819
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.3319700658
Short name T322
Test name
Test status
Simulation time 2222510012 ps
CPU time 24.33 seconds
Started May 02 12:48:14 PM PDT 24
Finished May 02 12:48:41 PM PDT 24
Peak memory 221436 kb
Host smart-fbcd90e8-74b0-497d-842d-36adf160730c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319700658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.3319700658
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.2571699761
Short name T346
Test name
Test status
Simulation time 644054296 ps
CPU time 22.63 seconds
Started May 02 12:48:13 PM PDT 24
Finished May 02 12:48:38 PM PDT 24
Peak memory 222300 kb
Host smart-be50c486-a111-4a42-a025-75afa2f47664
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571699761 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.2571699761
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.1152621995
Short name T719
Test name
Test status
Simulation time 174993568 ps
CPU time 4.14 seconds
Started May 02 12:48:38 PM PDT 24
Finished May 02 12:48:47 PM PDT 24
Peak memory 208032 kb
Host smart-428b8bf1-1dac-40a6-a488-fa4755b4fe31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152621995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.1152621995
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.1476653785
Short name T462
Test name
Test status
Simulation time 13730083 ps
CPU time 0.91 seconds
Started May 02 12:48:31 PM PDT 24
Finished May 02 12:48:35 PM PDT 24
Peak memory 205664 kb
Host smart-593d8cd8-5b62-4e14-a095-7060109566c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476653785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.1476653785
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.2872006808
Short name T270
Test name
Test status
Simulation time 270499556 ps
CPU time 6.26 seconds
Started May 02 12:48:24 PM PDT 24
Finished May 02 12:48:33 PM PDT 24
Peak memory 214656 kb
Host smart-4a2c7f23-bdce-42a9-ac1c-b41bce1b78a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2872006808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.2872006808
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.851450668
Short name T402
Test name
Test status
Simulation time 100184006 ps
CPU time 3.38 seconds
Started May 02 12:48:21 PM PDT 24
Finished May 02 12:48:27 PM PDT 24
Peak memory 209136 kb
Host smart-76a75a63-4992-47c7-b9eb-fd4abe6f3474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851450668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.851450668
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.1647682519
Short name T878
Test name
Test status
Simulation time 369343041 ps
CPU time 10.73 seconds
Started May 02 12:48:43 PM PDT 24
Finished May 02 12:49:00 PM PDT 24
Peak memory 209096 kb
Host smart-8522ec80-a1a7-4f86-bccb-d531c9253a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647682519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.1647682519
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.3367010007
Short name T616
Test name
Test status
Simulation time 143129990 ps
CPU time 2.44 seconds
Started May 02 12:48:20 PM PDT 24
Finished May 02 12:48:24 PM PDT 24
Peak memory 213924 kb
Host smart-99670315-8870-4dee-ae55-d84fa6732a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367010007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.3367010007
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_sideload.316309540
Short name T805
Test name
Test status
Simulation time 112092186 ps
CPU time 3.46 seconds
Started May 02 12:48:37 PM PDT 24
Finished May 02 12:48:44 PM PDT 24
Peak memory 206296 kb
Host smart-89689871-2f05-436b-881b-42e59eaf854f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316309540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.316309540
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.2895722272
Short name T612
Test name
Test status
Simulation time 1141096622 ps
CPU time 28.55 seconds
Started May 02 12:48:20 PM PDT 24
Finished May 02 12:48:50 PM PDT 24
Peak memory 207504 kb
Host smart-58158325-5ecf-4230-9368-74fa8c77c9fb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895722272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.2895722272
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.2652838313
Short name T845
Test name
Test status
Simulation time 368295340 ps
CPU time 7.62 seconds
Started May 02 12:48:27 PM PDT 24
Finished May 02 12:48:38 PM PDT 24
Peak memory 208552 kb
Host smart-b02107af-43c8-4491-8fff-b59042c3e51c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652838313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.2652838313
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.52762379
Short name T355
Test name
Test status
Simulation time 603244778 ps
CPU time 12.13 seconds
Started May 02 12:48:21 PM PDT 24
Finished May 02 12:48:35 PM PDT 24
Peak memory 208172 kb
Host smart-fd5b8461-e6ad-4eb4-9f25-06f9a84779d7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52762379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.52762379
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.2003671320
Short name T521
Test name
Test status
Simulation time 1390446356 ps
CPU time 2.77 seconds
Started May 02 12:48:37 PM PDT 24
Finished May 02 12:48:44 PM PDT 24
Peak memory 208952 kb
Host smart-9d52ae8d-2033-4e82-b548-05b542651df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003671320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.2003671320
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.2490017767
Short name T190
Test name
Test status
Simulation time 1690461972 ps
CPU time 3.03 seconds
Started May 02 12:48:27 PM PDT 24
Finished May 02 12:48:34 PM PDT 24
Peak memory 206384 kb
Host smart-dd8fd351-e651-4d57-81b0-67f392d3425a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490017767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.2490017767
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.2485420319
Short name T211
Test name
Test status
Simulation time 9254536607 ps
CPU time 115.96 seconds
Started May 02 12:48:25 PM PDT 24
Finished May 02 12:50:25 PM PDT 24
Peak memory 216312 kb
Host smart-19279415-fe34-4ab0-be6f-6480c58fd4f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485420319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.2485420319
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.398328369
Short name T866
Test name
Test status
Simulation time 286050211 ps
CPU time 8.51 seconds
Started May 02 12:48:35 PM PDT 24
Finished May 02 12:48:47 PM PDT 24
Peak memory 217996 kb
Host smart-9e054a41-aa72-4f41-bca5-6b0c8d978d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398328369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.398328369
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.1188770098
Short name T441
Test name
Test status
Simulation time 98594244 ps
CPU time 2.97 seconds
Started May 02 12:48:44 PM PDT 24
Finished May 02 12:48:53 PM PDT 24
Peak memory 209940 kb
Host smart-7732351c-72e3-40fc-9644-d97aaa5486c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188770098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.1188770098
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.521353901
Short name T431
Test name
Test status
Simulation time 41634993 ps
CPU time 0.74 seconds
Started May 02 12:48:23 PM PDT 24
Finished May 02 12:48:27 PM PDT 24
Peak memory 205580 kb
Host smart-b46c26ef-b8b7-47d9-bf35-700eca1b1faf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521353901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.521353901
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.167116651
Short name T41
Test name
Test status
Simulation time 170819781 ps
CPU time 6.59 seconds
Started May 02 12:48:21 PM PDT 24
Finished May 02 12:48:30 PM PDT 24
Peak memory 214012 kb
Host smart-b5c23615-9041-4805-be0a-b7bff170f129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167116651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.167116651
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.1134998273
Short name T509
Test name
Test status
Simulation time 55981512 ps
CPU time 1.67 seconds
Started May 02 12:48:40 PM PDT 24
Finished May 02 12:48:48 PM PDT 24
Peak memory 209340 kb
Host smart-12d49d6d-b265-4493-b669-87dddb6eb6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134998273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.1134998273
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.3647176826
Short name T801
Test name
Test status
Simulation time 75003584 ps
CPU time 2.72 seconds
Started May 02 12:48:23 PM PDT 24
Finished May 02 12:48:29 PM PDT 24
Peak memory 208304 kb
Host smart-43a58ebf-6ebf-4842-8d9b-f90744796d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647176826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.3647176826
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_random.3857251688
Short name T691
Test name
Test status
Simulation time 19017311262 ps
CPU time 127.16 seconds
Started May 02 12:48:23 PM PDT 24
Finished May 02 12:50:33 PM PDT 24
Peak memory 208916 kb
Host smart-1cad690b-1441-42de-bfdc-e6d3fcef0204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857251688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.3857251688
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.933530315
Short name T340
Test name
Test status
Simulation time 71328492 ps
CPU time 2.87 seconds
Started May 02 12:48:38 PM PDT 24
Finished May 02 12:48:45 PM PDT 24
Peak memory 206160 kb
Host smart-4da1cff0-2d11-4b95-aadf-4534ff510ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933530315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.933530315
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.3148725516
Short name T851
Test name
Test status
Simulation time 419120851 ps
CPU time 5.24 seconds
Started May 02 12:48:34 PM PDT 24
Finished May 02 12:48:42 PM PDT 24
Peak memory 206416 kb
Host smart-8ed1e32d-e3a2-4a15-9c59-e84aa0e391b7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148725516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.3148725516
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.3322362117
Short name T752
Test name
Test status
Simulation time 323876361 ps
CPU time 4.78 seconds
Started May 02 12:48:47 PM PDT 24
Finished May 02 12:48:57 PM PDT 24
Peak memory 207292 kb
Host smart-2de23a59-36fa-40be-ace4-f779ece048d2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322362117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.3322362117
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.977023647
Short name T745
Test name
Test status
Simulation time 24775962 ps
CPU time 1.99 seconds
Started May 02 12:48:24 PM PDT 24
Finished May 02 12:48:29 PM PDT 24
Peak memory 206508 kb
Host smart-e57789e7-21ce-440f-98a0-5e1059d3c29a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977023647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.977023647
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.2950390914
Short name T849
Test name
Test status
Simulation time 955326760 ps
CPU time 3.02 seconds
Started May 02 12:48:25 PM PDT 24
Finished May 02 12:48:31 PM PDT 24
Peak memory 208840 kb
Host smart-cc0f7be9-7ca2-4fbf-aa81-7d7edc332cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950390914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.2950390914
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.325776952
Short name T775
Test name
Test status
Simulation time 1513482220 ps
CPU time 23.69 seconds
Started May 02 12:48:24 PM PDT 24
Finished May 02 12:48:51 PM PDT 24
Peak memory 207784 kb
Host smart-ee0fc8a5-6d27-4617-8dcf-3226439ef2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325776952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.325776952
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.1576535678
Short name T327
Test name
Test status
Simulation time 8594405860 ps
CPU time 35.86 seconds
Started May 02 12:48:39 PM PDT 24
Finished May 02 12:49:26 PM PDT 24
Peak memory 222292 kb
Host smart-1fddbbdd-4e90-43f5-a49a-f3ed4722f2fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576535678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.1576535678
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.668111359
Short name T750
Test name
Test status
Simulation time 190388303 ps
CPU time 9.38 seconds
Started May 02 12:48:38 PM PDT 24
Finished May 02 12:48:52 PM PDT 24
Peak memory 222320 kb
Host smart-a78fd61a-5637-4535-95b2-0253c48af6da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668111359 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.668111359
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.3235135287
Short name T493
Test name
Test status
Simulation time 432350292 ps
CPU time 5.41 seconds
Started May 02 12:48:21 PM PDT 24
Finished May 02 12:48:29 PM PDT 24
Peak memory 209468 kb
Host smart-3594c51a-ba64-4ab6-8068-5dd3b598ae38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235135287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.3235135287
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.1313765461
Short name T155
Test name
Test status
Simulation time 126657717 ps
CPU time 2.67 seconds
Started May 02 12:48:41 PM PDT 24
Finished May 02 12:48:50 PM PDT 24
Peak memory 209772 kb
Host smart-54d8b79b-34d4-4598-973d-951f4a3ec04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313765461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.1313765461
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.2904133204
Short name T598
Test name
Test status
Simulation time 12828406 ps
CPU time 0.88 seconds
Started May 02 12:48:27 PM PDT 24
Finished May 02 12:48:32 PM PDT 24
Peak memory 205556 kb
Host smart-e12301e2-43ef-4ba4-9031-21361355b8a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904133204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.2904133204
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.3592481608
Short name T423
Test name
Test status
Simulation time 153240107 ps
CPU time 2.79 seconds
Started May 02 12:48:26 PM PDT 24
Finished May 02 12:48:32 PM PDT 24
Peak memory 214016 kb
Host smart-6a42d311-86ec-4102-b777-686e160796f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3592481608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.3592481608
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.1688002429
Short name T42
Test name
Test status
Simulation time 1548789328 ps
CPU time 12.75 seconds
Started May 02 12:48:28 PM PDT 24
Finished May 02 12:48:44 PM PDT 24
Peak memory 210000 kb
Host smart-6404f4e2-a6d9-4e64-ab3b-d536d9bf2a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688002429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.1688002429
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.3320203428
Short name T848
Test name
Test status
Simulation time 96729624 ps
CPU time 3.16 seconds
Started May 02 12:48:36 PM PDT 24
Finished May 02 12:48:43 PM PDT 24
Peak memory 209584 kb
Host smart-82630100-440e-44d6-a6d9-d50fa50c9248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320203428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.3320203428
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.91239027
Short name T535
Test name
Test status
Simulation time 242465297 ps
CPU time 5.66 seconds
Started May 02 12:48:21 PM PDT 24
Finished May 02 12:48:28 PM PDT 24
Peak memory 214000 kb
Host smart-ebcd2cf5-30d3-4390-95f2-f121a46269af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91239027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.91239027
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.1783882080
Short name T263
Test name
Test status
Simulation time 54935069 ps
CPU time 3.43 seconds
Started May 02 12:48:40 PM PDT 24
Finished May 02 12:48:50 PM PDT 24
Peak memory 210756 kb
Host smart-53a7a9bb-909d-4840-8cf5-35e41a198ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783882080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.1783882080
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.1316683350
Short name T723
Test name
Test status
Simulation time 599702196 ps
CPU time 3.96 seconds
Started May 02 12:48:40 PM PDT 24
Finished May 02 12:48:51 PM PDT 24
Peak memory 208764 kb
Host smart-c85cb39e-4e93-4a0b-8a6d-8b87a65494d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316683350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.1316683350
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.3218591583
Short name T101
Test name
Test status
Simulation time 382084259 ps
CPU time 4.92 seconds
Started May 02 12:48:22 PM PDT 24
Finished May 02 12:48:29 PM PDT 24
Peak memory 206968 kb
Host smart-3403fada-5cb9-4e65-9a59-e83cfa85f007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218591583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.3218591583
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.3252432728
Short name T812
Test name
Test status
Simulation time 1627105524 ps
CPU time 17.24 seconds
Started May 02 12:48:21 PM PDT 24
Finished May 02 12:48:40 PM PDT 24
Peak memory 208432 kb
Host smart-4385dfc7-6983-4b18-b622-57d7e1868577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252432728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.3252432728
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.2725727284
Short name T599
Test name
Test status
Simulation time 153116904 ps
CPU time 4.58 seconds
Started May 02 12:48:33 PM PDT 24
Finished May 02 12:48:40 PM PDT 24
Peak memory 208232 kb
Host smart-7dd4e750-844e-4861-af58-7039585f0666
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725727284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.2725727284
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.3465789002
Short name T656
Test name
Test status
Simulation time 226764685 ps
CPU time 1.8 seconds
Started May 02 12:48:25 PM PDT 24
Finished May 02 12:48:31 PM PDT 24
Peak memory 206384 kb
Host smart-059fa382-2cfe-4406-b71d-5b062aa84383
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465789002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.3465789002
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.3159967538
Short name T795
Test name
Test status
Simulation time 282274922 ps
CPU time 6.47 seconds
Started May 02 12:48:36 PM PDT 24
Finished May 02 12:48:46 PM PDT 24
Peak memory 208056 kb
Host smart-0403fce7-aae2-4655-815c-5248dda21f65
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159967538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.3159967538
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.1183715362
Short name T833
Test name
Test status
Simulation time 92769197 ps
CPU time 1.78 seconds
Started May 02 12:48:39 PM PDT 24
Finished May 02 12:48:46 PM PDT 24
Peak memory 215312 kb
Host smart-cb6648b6-7afe-489d-ac0d-10418f0e617a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183715362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.1183715362
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.630586927
Short name T199
Test name
Test status
Simulation time 46100980 ps
CPU time 1.95 seconds
Started May 02 12:48:37 PM PDT 24
Finished May 02 12:48:43 PM PDT 24
Peak memory 207888 kb
Host smart-f21b2d3c-d5c0-427e-afc6-e71bb433b890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630586927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.630586927
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.3864793793
Short name T817
Test name
Test status
Simulation time 11165561372 ps
CPU time 265.58 seconds
Started May 02 12:48:27 PM PDT 24
Finished May 02 12:52:56 PM PDT 24
Peak memory 222292 kb
Host smart-12cef12a-b2b0-4091-b334-24fc828ef785
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864793793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.3864793793
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.3611078259
Short name T176
Test name
Test status
Simulation time 1407051328 ps
CPU time 16.91 seconds
Started May 02 12:48:24 PM PDT 24
Finished May 02 12:48:44 PM PDT 24
Peak memory 222228 kb
Host smart-28f5eeab-fc71-46dd-85d9-a7de818374d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611078259 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.3611078259
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.3694111788
Short name T776
Test name
Test status
Simulation time 260763685 ps
CPU time 2.68 seconds
Started May 02 12:48:37 PM PDT 24
Finished May 02 12:48:43 PM PDT 24
Peak memory 214084 kb
Host smart-60906b78-4a84-4139-9a8f-137822956b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694111788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.3694111788
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.2919670267
Short name T169
Test name
Test status
Simulation time 72842662 ps
CPU time 3.34 seconds
Started May 02 12:48:40 PM PDT 24
Finished May 02 12:48:49 PM PDT 24
Peak memory 209944 kb
Host smart-4a195a3d-fc03-4950-9165-6ad08ba59395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919670267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.2919670267
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.1019246300
Short name T456
Test name
Test status
Simulation time 31785378 ps
CPU time 0.74 seconds
Started May 02 12:47:50 PM PDT 24
Finished May 02 12:47:55 PM PDT 24
Peak memory 205660 kb
Host smart-19456bdb-6b49-4838-94a7-13f2ac53ba43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019246300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.1019246300
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.137809819
Short name T689
Test name
Test status
Simulation time 50944870 ps
CPU time 1.6 seconds
Started May 02 12:47:22 PM PDT 24
Finished May 02 12:47:27 PM PDT 24
Peak memory 215808 kb
Host smart-834472e1-3141-487a-a30a-bda0bd594cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137809819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.137809819
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.1539775250
Short name T69
Test name
Test status
Simulation time 85286243 ps
CPU time 3.47 seconds
Started May 02 12:47:37 PM PDT 24
Finished May 02 12:47:43 PM PDT 24
Peak memory 207684 kb
Host smart-cfe4d6c7-94d7-4b15-9124-89b9f74ec1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539775250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.1539775250
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.1841746552
Short name T794
Test name
Test status
Simulation time 3232903714 ps
CPU time 10.05 seconds
Started May 02 12:47:21 PM PDT 24
Finished May 02 12:47:35 PM PDT 24
Peak memory 209324 kb
Host smart-8a8dd945-52d0-4621-9cb2-1c05c15d2bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841746552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.1841746552
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.1331525269
Short name T6
Test name
Test status
Simulation time 230000554 ps
CPU time 5.23 seconds
Started May 02 12:47:25 PM PDT 24
Finished May 02 12:47:33 PM PDT 24
Peak memory 209504 kb
Host smart-a7db4e37-9a7e-469a-8eb0-16319097ffff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331525269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.1331525269
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.1051938590
Short name T44
Test name
Test status
Simulation time 2292503753 ps
CPU time 18.97 seconds
Started May 02 12:47:46 PM PDT 24
Finished May 02 12:48:08 PM PDT 24
Peak memory 232276 kb
Host smart-263c547a-341a-41fc-a7a0-2c23b71f7fdf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051938590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.1051938590
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.4003602701
Short name T838
Test name
Test status
Simulation time 54140963 ps
CPU time 2.76 seconds
Started May 02 12:47:18 PM PDT 24
Finished May 02 12:47:25 PM PDT 24
Peak memory 207456 kb
Host smart-fecfc466-b3ea-4afc-a8d7-95a248e27290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003602701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.4003602701
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.3924442048
Short name T807
Test name
Test status
Simulation time 1497187690 ps
CPU time 21.62 seconds
Started May 02 12:47:21 PM PDT 24
Finished May 02 12:47:46 PM PDT 24
Peak memory 208084 kb
Host smart-6d3656c4-82de-4e16-95fe-a0ca174239de
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924442048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.3924442048
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.3749643520
Short name T205
Test name
Test status
Simulation time 101615512 ps
CPU time 2.13 seconds
Started May 02 12:47:30 PM PDT 24
Finished May 02 12:47:34 PM PDT 24
Peak memory 208464 kb
Host smart-1018c3e8-9845-4bc6-b3d2-aea56b58890c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749643520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.3749643520
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.4210391054
Short name T308
Test name
Test status
Simulation time 708809440 ps
CPU time 5.29 seconds
Started May 02 12:47:18 PM PDT 24
Finished May 02 12:47:27 PM PDT 24
Peak memory 208308 kb
Host smart-808afd7e-cba3-49b6-8721-73b415a19ffd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210391054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.4210391054
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.951802254
Short name T902
Test name
Test status
Simulation time 36094839 ps
CPU time 2.37 seconds
Started May 02 12:47:23 PM PDT 24
Finished May 02 12:47:28 PM PDT 24
Peak memory 209288 kb
Host smart-047323a4-9938-4b42-b57f-519db5bb563a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951802254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.951802254
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.1267766275
Short name T445
Test name
Test status
Simulation time 664612496 ps
CPU time 4.05 seconds
Started May 02 12:47:36 PM PDT 24
Finished May 02 12:47:42 PM PDT 24
Peak memory 207976 kb
Host smart-2144adf8-eee6-4d73-9729-3b0eff86e2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267766275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.1267766275
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.1162273001
Short name T181
Test name
Test status
Simulation time 17456333 ps
CPU time 0.96 seconds
Started May 02 12:47:29 PM PDT 24
Finished May 02 12:47:32 PM PDT 24
Peak memory 205604 kb
Host smart-d69b9dd1-fa86-4822-91b8-1a5913d9779e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162273001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.1162273001
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.2519388935
Short name T625
Test name
Test status
Simulation time 216434400 ps
CPU time 9.69 seconds
Started May 02 12:47:48 PM PDT 24
Finished May 02 12:48:01 PM PDT 24
Peak memory 222324 kb
Host smart-3cb1db5a-3121-4a27-bc37-2f8e521b02a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519388935 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.2519388935
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.634354095
Short name T635
Test name
Test status
Simulation time 749546582 ps
CPU time 4.74 seconds
Started May 02 12:47:42 PM PDT 24
Finished May 02 12:47:49 PM PDT 24
Peak memory 208952 kb
Host smart-719bdf4b-df4e-4084-a821-2b30d2f23710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634354095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.634354095
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.3448600830
Short name T827
Test name
Test status
Simulation time 90116294 ps
CPU time 2.6 seconds
Started May 02 12:47:27 PM PDT 24
Finished May 02 12:47:32 PM PDT 24
Peak memory 209528 kb
Host smart-ea205738-02b6-43b4-acc4-405bf883cf83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448600830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.3448600830
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.2525700531
Short name T645
Test name
Test status
Simulation time 89431464 ps
CPU time 0.8 seconds
Started May 02 12:48:33 PM PDT 24
Finished May 02 12:48:36 PM PDT 24
Peak memory 205580 kb
Host smart-a66ca2d5-6f26-41f5-8568-70d922bf5dbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525700531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.2525700531
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.479214481
Short name T424
Test name
Test status
Simulation time 50480525 ps
CPU time 3.59 seconds
Started May 02 12:48:39 PM PDT 24
Finished May 02 12:48:47 PM PDT 24
Peak memory 213932 kb
Host smart-827f2d33-bd3a-43f3-a15d-2f353d344428
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=479214481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.479214481
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.1889326485
Short name T511
Test name
Test status
Simulation time 218571081 ps
CPU time 2.7 seconds
Started May 02 12:48:40 PM PDT 24
Finished May 02 12:48:49 PM PDT 24
Peak memory 207620 kb
Host smart-e31d4b77-5c32-4923-a183-6fc1fb5487eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889326485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.1889326485
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.3127686261
Short name T347
Test name
Test status
Simulation time 240954672 ps
CPU time 6.1 seconds
Started May 02 12:48:34 PM PDT 24
Finished May 02 12:48:43 PM PDT 24
Peak memory 207816 kb
Host smart-d3a5b493-4bc5-43fa-82d6-006509888257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127686261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.3127686261
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.791304879
Short name T366
Test name
Test status
Simulation time 48648502 ps
CPU time 2.88 seconds
Started May 02 12:48:23 PM PDT 24
Finished May 02 12:48:30 PM PDT 24
Peak memory 213992 kb
Host smart-c41ccd6d-8ddf-41c1-a818-d941f16e448b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791304879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.791304879
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.85463398
Short name T663
Test name
Test status
Simulation time 616977026 ps
CPU time 3.09 seconds
Started May 02 12:48:23 PM PDT 24
Finished May 02 12:48:28 PM PDT 24
Peak memory 219300 kb
Host smart-fd6f42af-6ba0-4ef8-93ba-6c33b3f3de34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85463398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.85463398
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.1694152116
Short name T2
Test name
Test status
Simulation time 3238884168 ps
CPU time 59.87 seconds
Started May 02 12:48:35 PM PDT 24
Finished May 02 12:49:38 PM PDT 24
Peak memory 217728 kb
Host smart-fdb4e554-9395-4b1c-898e-dbed44862b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694152116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.1694152116
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.952190118
Short name T364
Test name
Test status
Simulation time 124973193 ps
CPU time 3.71 seconds
Started May 02 12:48:41 PM PDT 24
Finished May 02 12:48:51 PM PDT 24
Peak memory 208344 kb
Host smart-3c4dcd5c-f852-400a-b690-32f203e1a5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952190118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.952190118
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.4188996636
Short name T360
Test name
Test status
Simulation time 207618437 ps
CPU time 3.22 seconds
Started May 02 12:48:23 PM PDT 24
Finished May 02 12:48:28 PM PDT 24
Peak memory 208724 kb
Host smart-67da9ded-1875-404d-aa3f-04104ad2db7d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188996636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.4188996636
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.1998887875
Short name T706
Test name
Test status
Simulation time 421672384 ps
CPU time 6.7 seconds
Started May 02 12:48:23 PM PDT 24
Finished May 02 12:48:33 PM PDT 24
Peak memory 207604 kb
Host smart-26f34765-27ff-4d79-8ac0-f00c343f12b9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998887875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.1998887875
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.2988220771
Short name T503
Test name
Test status
Simulation time 138224516 ps
CPU time 3.52 seconds
Started May 02 12:48:25 PM PDT 24
Finished May 02 12:48:32 PM PDT 24
Peak memory 206348 kb
Host smart-bce4443f-df0d-4c8f-8f0e-ad3a683a8889
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988220771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.2988220771
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.868446722
Short name T483
Test name
Test status
Simulation time 391854698 ps
CPU time 2.32 seconds
Started May 02 12:48:26 PM PDT 24
Finished May 02 12:48:32 PM PDT 24
Peak memory 208768 kb
Host smart-c07bd2e8-47f7-42d3-82d8-020d1455ef3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868446722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.868446722
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.1469592617
Short name T429
Test name
Test status
Simulation time 157273545 ps
CPU time 4.04 seconds
Started May 02 12:48:27 PM PDT 24
Finished May 02 12:48:35 PM PDT 24
Peak memory 208044 kb
Host smart-c11d12d3-24d4-4458-90bb-7f27ff8f6932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469592617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.1469592617
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.2546173507
Short name T763
Test name
Test status
Simulation time 2971088855 ps
CPU time 73.28 seconds
Started May 02 12:48:43 PM PDT 24
Finished May 02 12:50:02 PM PDT 24
Peak memory 220784 kb
Host smart-e216cf3c-c612-4ac9-b739-1196a239121d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546173507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.2546173507
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.3710414035
Short name T123
Test name
Test status
Simulation time 293471029 ps
CPU time 18.17 seconds
Started May 02 12:48:37 PM PDT 24
Finished May 02 12:48:58 PM PDT 24
Peak memory 219896 kb
Host smart-561e0ccc-f36a-4338-9369-d79e6bcd6c2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710414035 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.3710414035
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.3128875790
Short name T690
Test name
Test status
Simulation time 8643924971 ps
CPU time 55.8 seconds
Started May 02 12:48:37 PM PDT 24
Finished May 02 12:49:37 PM PDT 24
Peak memory 210068 kb
Host smart-aa8d512b-a907-424a-b69b-1425d4ad5de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128875790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.3128875790
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.346902945
Short name T62
Test name
Test status
Simulation time 74880060 ps
CPU time 1.74 seconds
Started May 02 12:48:46 PM PDT 24
Finished May 02 12:48:53 PM PDT 24
Peak memory 209500 kb
Host smart-7aee3122-8bdf-4c2b-9683-b9e29aabc389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346902945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.346902945
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.2372864990
Short name T788
Test name
Test status
Simulation time 40313158 ps
CPU time 0.76 seconds
Started May 02 12:48:40 PM PDT 24
Finished May 02 12:48:47 PM PDT 24
Peak memory 205468 kb
Host smart-567d57be-c325-43c0-991c-f84f8fc83a78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372864990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.2372864990
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.3595705555
Short name T385
Test name
Test status
Simulation time 138520842 ps
CPU time 2.91 seconds
Started May 02 12:48:39 PM PDT 24
Finished May 02 12:48:48 PM PDT 24
Peak memory 214008 kb
Host smart-3e7402a4-88b3-4edc-b9a4-e9eb7a7c30b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3595705555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.3595705555
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.1330825258
Short name T631
Test name
Test status
Simulation time 241169788 ps
CPU time 4.42 seconds
Started May 02 12:48:43 PM PDT 24
Finished May 02 12:48:54 PM PDT 24
Peak memory 214264 kb
Host smart-f56b47a0-3861-4bdf-beff-1f11661596a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330825258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.1330825258
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.4193457394
Short name T670
Test name
Test status
Simulation time 168878068 ps
CPU time 3.86 seconds
Started May 02 12:48:43 PM PDT 24
Finished May 02 12:48:53 PM PDT 24
Peak memory 209908 kb
Host smart-5907fbf9-69a7-4b08-84ea-75a24df5f112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193457394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.4193457394
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.2336491322
Short name T243
Test name
Test status
Simulation time 361939438 ps
CPU time 4.27 seconds
Started May 02 12:48:38 PM PDT 24
Finished May 02 12:48:47 PM PDT 24
Peak memory 222168 kb
Host smart-17427ab4-48fa-4f9f-9831-0b3950782b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336491322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2336491322
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.3448446298
Short name T240
Test name
Test status
Simulation time 408075153 ps
CPU time 5.59 seconds
Started May 02 12:48:39 PM PDT 24
Finished May 02 12:48:50 PM PDT 24
Peak memory 213920 kb
Host smart-bc175456-9731-4489-bf24-907a77bf323e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448446298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.3448446298
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_random.1229529936
Short name T554
Test name
Test status
Simulation time 405009002 ps
CPU time 10.39 seconds
Started May 02 12:48:35 PM PDT 24
Finished May 02 12:48:48 PM PDT 24
Peak memory 217860 kb
Host smart-5c298d39-4385-463a-af20-6c80718a9d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229529936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.1229529936
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.1242283749
Short name T786
Test name
Test status
Simulation time 5671449788 ps
CPU time 40.33 seconds
Started May 02 12:48:32 PM PDT 24
Finished May 02 12:49:15 PM PDT 24
Peak memory 207608 kb
Host smart-314f0347-275d-45e1-a098-763d12ea8286
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242283749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.1242283749
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.1484061420
Short name T796
Test name
Test status
Simulation time 146858791 ps
CPU time 4.75 seconds
Started May 02 12:48:38 PM PDT 24
Finished May 02 12:48:48 PM PDT 24
Peak memory 206436 kb
Host smart-80fd4e17-258c-450d-817d-9245c8e1a120
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484061420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.1484061420
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.2843031444
Short name T772
Test name
Test status
Simulation time 29742278 ps
CPU time 2.22 seconds
Started May 02 12:48:35 PM PDT 24
Finished May 02 12:48:40 PM PDT 24
Peak memory 208376 kb
Host smart-ba8aad49-5d43-456f-a142-d4787f571501
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843031444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.2843031444
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.1270714228
Short name T295
Test name
Test status
Simulation time 56847283 ps
CPU time 2.54 seconds
Started May 02 12:48:38 PM PDT 24
Finished May 02 12:48:45 PM PDT 24
Peak memory 217940 kb
Host smart-2273cfa1-bb4e-4810-a58f-ed831cdd79e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270714228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.1270714228
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.1821962562
Short name T200
Test name
Test status
Simulation time 37342901 ps
CPU time 2.24 seconds
Started May 02 12:48:43 PM PDT 24
Finished May 02 12:48:51 PM PDT 24
Peak memory 206376 kb
Host smart-77194b80-03b5-4897-b904-7dd39ccbc4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821962562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.1821962562
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.2582671911
Short name T228
Test name
Test status
Simulation time 714212532 ps
CPU time 31.52 seconds
Started May 02 12:48:34 PM PDT 24
Finished May 02 12:49:09 PM PDT 24
Peak memory 221208 kb
Host smart-16bb3734-219a-4fe8-9e1f-abd99e93ab13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582671911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.2582671911
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.2128921286
Short name T685
Test name
Test status
Simulation time 332603384 ps
CPU time 3.97 seconds
Started May 02 12:48:48 PM PDT 24
Finished May 02 12:48:57 PM PDT 24
Peak memory 207180 kb
Host smart-b3119461-04c9-4fa3-84f0-9e57d99d5717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128921286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.2128921286
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.2661541353
Short name T531
Test name
Test status
Simulation time 15351299 ps
CPU time 0.76 seconds
Started May 02 12:48:37 PM PDT 24
Finished May 02 12:48:43 PM PDT 24
Peak memory 205592 kb
Host smart-b911b070-4e13-4cbb-91f2-43d44998d8d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661541353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.2661541353
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.367484494
Short name T561
Test name
Test status
Simulation time 38354525 ps
CPU time 2.34 seconds
Started May 02 12:48:40 PM PDT 24
Finished May 02 12:48:48 PM PDT 24
Peak memory 214108 kb
Host smart-94c4c6bc-e428-417c-95f3-b59cd9f0e565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367484494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.367484494
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.4041126675
Short name T26
Test name
Test status
Simulation time 1099794855 ps
CPU time 6.87 seconds
Started May 02 12:48:33 PM PDT 24
Finished May 02 12:48:43 PM PDT 24
Peak memory 219788 kb
Host smart-e7f94c67-41bd-4c7e-b6dd-3ce0c11c2b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041126675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.4041126675
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.634167303
Short name T332
Test name
Test status
Simulation time 121154738 ps
CPU time 4.21 seconds
Started May 02 12:48:55 PM PDT 24
Finished May 02 12:49:04 PM PDT 24
Peak memory 219780 kb
Host smart-1ad94c25-6ff8-467f-8be7-e5c52dd840a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634167303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.634167303
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.2654539788
Short name T459
Test name
Test status
Simulation time 251063582 ps
CPU time 3.41 seconds
Started May 02 12:48:37 PM PDT 24
Finished May 02 12:48:45 PM PDT 24
Peak memory 208804 kb
Host smart-f92da2f9-dd7b-47e1-968a-7bd9ab1a9081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654539788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.2654539788
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.1315773150
Short name T253
Test name
Test status
Simulation time 305257717 ps
CPU time 2.73 seconds
Started May 02 12:48:47 PM PDT 24
Finished May 02 12:48:55 PM PDT 24
Peak memory 206540 kb
Host smart-917bd979-0971-4b06-b4ab-48fd0f690bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315773150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.1315773150
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.561360193
Short name T648
Test name
Test status
Simulation time 153063889 ps
CPU time 3.4 seconds
Started May 02 12:48:49 PM PDT 24
Finished May 02 12:48:57 PM PDT 24
Peak memory 208160 kb
Host smart-9c37cc30-fe42-4588-b78d-88fd23cfce94
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561360193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.561360193
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.3786413696
Short name T472
Test name
Test status
Simulation time 67637323 ps
CPU time 2.41 seconds
Started May 02 12:48:39 PM PDT 24
Finished May 02 12:48:47 PM PDT 24
Peak memory 206444 kb
Host smart-01ac009d-1ba5-4d02-a194-07d2a925e6e3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786413696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.3786413696
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.2748539664
Short name T203
Test name
Test status
Simulation time 637431583 ps
CPU time 6.85 seconds
Started May 02 12:48:39 PM PDT 24
Finished May 02 12:48:51 PM PDT 24
Peak memory 208224 kb
Host smart-eccb2766-a15c-48f4-a2da-2075f1de43b6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748539664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.2748539664
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.213520072
Short name T512
Test name
Test status
Simulation time 20262316 ps
CPU time 1.77 seconds
Started May 02 12:48:34 PM PDT 24
Finished May 02 12:48:39 PM PDT 24
Peak memory 207208 kb
Host smart-632fb9df-4605-48fb-8d1d-6ce1f7498235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213520072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.213520072
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.2577831371
Short name T551
Test name
Test status
Simulation time 580545360 ps
CPU time 4.14 seconds
Started May 02 12:48:38 PM PDT 24
Finished May 02 12:48:47 PM PDT 24
Peak memory 206156 kb
Host smart-6d6ea4a5-c2f5-48e6-94c0-ba39ea8f6c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577831371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.2577831371
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.3138268116
Short name T552
Test name
Test status
Simulation time 11240691233 ps
CPU time 48.58 seconds
Started May 02 12:48:38 PM PDT 24
Finished May 02 12:49:31 PM PDT 24
Peak memory 216864 kb
Host smart-ec3a03ff-2bb4-46de-b79e-d2fde86dc79f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138268116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.3138268116
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.694156926
Short name T275
Test name
Test status
Simulation time 5865465783 ps
CPU time 20.16 seconds
Started May 02 12:48:34 PM PDT 24
Finished May 02 12:48:57 PM PDT 24
Peak memory 222700 kb
Host smart-b7c76270-7bf7-4e08-8bb2-d03189f221ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694156926 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.694156926
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.2412819884
Short name T608
Test name
Test status
Simulation time 757849052 ps
CPU time 3.34 seconds
Started May 02 12:48:36 PM PDT 24
Finished May 02 12:48:43 PM PDT 24
Peak memory 207160 kb
Host smart-ae719250-461a-49e4-956f-85f8b9c671a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412819884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.2412819884
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.4219788350
Short name T888
Test name
Test status
Simulation time 101297344 ps
CPU time 1.33 seconds
Started May 02 12:48:46 PM PDT 24
Finished May 02 12:48:53 PM PDT 24
Peak memory 209300 kb
Host smart-64c4162d-5c15-4ade-9ef7-c5ef02e9bc81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219788350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.4219788350
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.1862118653
Short name T502
Test name
Test status
Simulation time 11192930 ps
CPU time 0.88 seconds
Started May 02 12:48:42 PM PDT 24
Finished May 02 12:48:49 PM PDT 24
Peak memory 205580 kb
Host smart-8567af24-d828-4ef5-89a8-54c3eea7e559
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862118653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.1862118653
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.2306843185
Short name T896
Test name
Test status
Simulation time 175645382 ps
CPU time 1.92 seconds
Started May 02 12:48:39 PM PDT 24
Finished May 02 12:48:47 PM PDT 24
Peak memory 208312 kb
Host smart-458e3a9e-8eaf-4780-bd1a-007d5f58d189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306843185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.2306843185
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.3717583961
Short name T780
Test name
Test status
Simulation time 212772393 ps
CPU time 5.06 seconds
Started May 02 12:48:48 PM PDT 24
Finished May 02 12:48:57 PM PDT 24
Peak memory 218208 kb
Host smart-383b9ea6-c3dc-4c54-9e9f-9aa762d14464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717583961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.3717583961
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.2427106452
Short name T305
Test name
Test status
Simulation time 4630889670 ps
CPU time 75.21 seconds
Started May 02 12:48:57 PM PDT 24
Finished May 02 12:50:17 PM PDT 24
Peak memory 233320 kb
Host smart-4eeedf25-f589-437d-b87d-69afd7debc4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427106452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.2427106452
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.3703784061
Short name T7
Test name
Test status
Simulation time 989090025 ps
CPU time 29.93 seconds
Started May 02 12:48:44 PM PDT 24
Finished May 02 12:49:20 PM PDT 24
Peak memory 209196 kb
Host smart-31f91f40-10da-483c-b759-bbde89dcaf6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703784061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.3703784061
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.278553259
Short name T835
Test name
Test status
Simulation time 74612353 ps
CPU time 3.23 seconds
Started May 02 12:48:37 PM PDT 24
Finished May 02 12:48:43 PM PDT 24
Peak memory 206952 kb
Host smart-0725ac7f-9923-406c-96c3-53d6c12a6987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278553259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.278553259
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.456287216
Short name T789
Test name
Test status
Simulation time 8442128929 ps
CPU time 40.39 seconds
Started May 02 12:48:30 PM PDT 24
Finished May 02 12:49:14 PM PDT 24
Peak memory 207488 kb
Host smart-9d2dc633-a3be-487d-a853-3861280d104d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456287216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.456287216
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.3126149984
Short name T204
Test name
Test status
Simulation time 42956705 ps
CPU time 2.36 seconds
Started May 02 12:48:43 PM PDT 24
Finished May 02 12:48:51 PM PDT 24
Peak memory 206440 kb
Host smart-4bdf7a61-6d94-4bb8-986b-b839363f815a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126149984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.3126149984
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.320251013
Short name T779
Test name
Test status
Simulation time 240224696 ps
CPU time 6.33 seconds
Started May 02 12:48:41 PM PDT 24
Finished May 02 12:48:53 PM PDT 24
Peak memory 208112 kb
Host smart-7ceca80a-2d6b-48f8-9246-62a0fa873694
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320251013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.320251013
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.1287256265
Short name T664
Test name
Test status
Simulation time 69073342 ps
CPU time 3.34 seconds
Started May 02 12:48:35 PM PDT 24
Finished May 02 12:48:42 PM PDT 24
Peak memory 208436 kb
Host smart-c1b009d4-32cd-4443-8755-d44053ea7409
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287256265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.1287256265
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.3255170059
Short name T741
Test name
Test status
Simulation time 76718764 ps
CPU time 1.61 seconds
Started May 02 12:49:03 PM PDT 24
Finished May 02 12:49:09 PM PDT 24
Peak memory 207196 kb
Host smart-f635c286-36fb-4faa-8060-e2ce8c1e04f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255170059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.3255170059
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.2389955711
Short name T781
Test name
Test status
Simulation time 62448993 ps
CPU time 2.21 seconds
Started May 02 12:48:38 PM PDT 24
Finished May 02 12:48:45 PM PDT 24
Peak memory 206684 kb
Host smart-5e0c7d8e-83af-4703-8927-a9df809b225d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389955711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.2389955711
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.965059154
Short name T623
Test name
Test status
Simulation time 627742203 ps
CPU time 7.64 seconds
Started May 02 12:48:42 PM PDT 24
Finished May 02 12:48:56 PM PDT 24
Peak memory 222260 kb
Host smart-4b085832-f0af-4f7d-b12e-4b898c161316
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965059154 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.965059154
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.1420574787
Short name T341
Test name
Test status
Simulation time 5214699388 ps
CPU time 35.75 seconds
Started May 02 12:48:54 PM PDT 24
Finished May 02 12:49:34 PM PDT 24
Peak memory 208636 kb
Host smart-cfdcef2b-9bb7-4b71-9939-b2cf35869661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420574787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.1420574787
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.1241144882
Short name T207
Test name
Test status
Simulation time 2041317011 ps
CPU time 12.05 seconds
Started May 02 12:49:00 PM PDT 24
Finished May 02 12:49:16 PM PDT 24
Peak memory 211320 kb
Host smart-8be9b1b1-e0b0-40f2-9fcf-8489afe4360b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241144882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.1241144882
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.548855406
Short name T753
Test name
Test status
Simulation time 81697377 ps
CPU time 0.74 seconds
Started May 02 12:48:52 PM PDT 24
Finished May 02 12:48:57 PM PDT 24
Peak memory 205516 kb
Host smart-2742dc13-3cfe-4a46-9019-77875eb6c0ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548855406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.548855406
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.3970726199
Short name T386
Test name
Test status
Simulation time 74746849 ps
CPU time 2.8 seconds
Started May 02 12:48:48 PM PDT 24
Finished May 02 12:48:56 PM PDT 24
Peak memory 214784 kb
Host smart-292807a1-1573-4d3e-a291-b78aa28b1c0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3970726199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.3970726199
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.2702818488
Short name T885
Test name
Test status
Simulation time 116340843 ps
CPU time 5.16 seconds
Started May 02 12:48:37 PM PDT 24
Finished May 02 12:48:45 PM PDT 24
Peak memory 221264 kb
Host smart-b8cb6922-3e64-44bb-a907-9ecbb585ab4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702818488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.2702818488
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.1933959248
Short name T732
Test name
Test status
Simulation time 541676862 ps
CPU time 2.87 seconds
Started May 02 12:48:45 PM PDT 24
Finished May 02 12:48:54 PM PDT 24
Peak memory 209468 kb
Host smart-0a5d03ad-bdd6-43b2-b58b-8cc9d44a56e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933959248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.1933959248
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.3228766164
Short name T806
Test name
Test status
Simulation time 212852334 ps
CPU time 3.45 seconds
Started May 02 12:48:40 PM PDT 24
Finished May 02 12:48:50 PM PDT 24
Peak memory 208568 kb
Host smart-fbcc89b5-04a6-4451-98c4-eab0b8c46181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228766164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.3228766164
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.451085209
Short name T638
Test name
Test status
Simulation time 222319328 ps
CPU time 4.21 seconds
Started May 02 12:48:40 PM PDT 24
Finished May 02 12:48:51 PM PDT 24
Peak memory 215884 kb
Host smart-5c6e6a61-56e5-4119-8d86-0dcc078587b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451085209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.451085209
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.4019370483
Short name T583
Test name
Test status
Simulation time 649495910 ps
CPU time 9.23 seconds
Started May 02 12:48:45 PM PDT 24
Finished May 02 12:49:00 PM PDT 24
Peak memory 208112 kb
Host smart-f4a5e748-c73d-4a91-8dc0-313f2f0ce24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019370483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.4019370483
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.422857232
Short name T302
Test name
Test status
Simulation time 523796582 ps
CPU time 5.67 seconds
Started May 02 12:49:01 PM PDT 24
Finished May 02 12:49:11 PM PDT 24
Peak memory 206332 kb
Host smart-387a6fdd-28a8-41cd-a136-dc0de798b088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422857232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.422857232
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.2622671345
Short name T744
Test name
Test status
Simulation time 763676713 ps
CPU time 3.46 seconds
Started May 02 12:48:50 PM PDT 24
Finished May 02 12:48:57 PM PDT 24
Peak memory 206248 kb
Host smart-16eb519a-9639-43cd-a564-68b8ee2c28f7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622671345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.2622671345
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.3302988518
Short name T704
Test name
Test status
Simulation time 84258743 ps
CPU time 2.04 seconds
Started May 02 12:48:53 PM PDT 24
Finished May 02 12:49:00 PM PDT 24
Peak memory 207964 kb
Host smart-41d99a43-af4e-4a0f-ae8b-97d3a0a01849
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302988518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.3302988518
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.1131751415
Short name T449
Test name
Test status
Simulation time 190086637 ps
CPU time 7.36 seconds
Started May 02 12:49:11 PM PDT 24
Finished May 02 12:49:24 PM PDT 24
Peak memory 208128 kb
Host smart-2fd19a08-b9fe-40a1-85bd-94b8ac8bd65f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131751415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.1131751415
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.3021955062
Short name T187
Test name
Test status
Simulation time 133465849 ps
CPU time 2.52 seconds
Started May 02 12:48:38 PM PDT 24
Finished May 02 12:48:45 PM PDT 24
Peak memory 214032 kb
Host smart-b7be3913-dad4-4dca-96db-20d842573ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021955062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.3021955062
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.2109283649
Short name T494
Test name
Test status
Simulation time 129367244 ps
CPU time 2.4 seconds
Started May 02 12:48:54 PM PDT 24
Finished May 02 12:49:01 PM PDT 24
Peak memory 206240 kb
Host smart-52b3e6c6-e7ea-4453-938e-66881ba4bb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109283649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.2109283649
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.2157386775
Short name T790
Test name
Test status
Simulation time 1558322383 ps
CPU time 4.62 seconds
Started May 02 12:48:53 PM PDT 24
Finished May 02 12:49:01 PM PDT 24
Peak memory 207044 kb
Host smart-9d227ab9-ebd7-48d4-a6ce-5384482c7b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157386775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.2157386775
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.2463328147
Short name T381
Test name
Test status
Simulation time 297522050 ps
CPU time 3.86 seconds
Started May 02 12:49:10 PM PDT 24
Finished May 02 12:49:19 PM PDT 24
Peak memory 210084 kb
Host smart-d0de9be4-6f08-4c72-8082-9d8975b1a354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463328147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.2463328147
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.3126532055
Short name T774
Test name
Test status
Simulation time 32501960 ps
CPU time 0.91 seconds
Started May 02 12:48:47 PM PDT 24
Finished May 02 12:48:53 PM PDT 24
Peak memory 205744 kb
Host smart-4e3accfb-5f64-4c32-9a2b-058b546b3794
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126532055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.3126532055
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.82381762
Short name T417
Test name
Test status
Simulation time 670999044 ps
CPU time 15.39 seconds
Started May 02 12:48:54 PM PDT 24
Finished May 02 12:49:14 PM PDT 24
Peak memory 213984 kb
Host smart-2ecf96a2-4098-419f-add3-318f3304ce2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=82381762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.82381762
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.2209437740
Short name T31
Test name
Test status
Simulation time 245084423 ps
CPU time 6.92 seconds
Started May 02 12:48:57 PM PDT 24
Finished May 02 12:49:14 PM PDT 24
Peak memory 214264 kb
Host smart-ced49570-ef4c-44ba-a305-381438141a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209437740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.2209437740
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.1107721253
Short name T607
Test name
Test status
Simulation time 114217048 ps
CPU time 3.36 seconds
Started May 02 12:48:55 PM PDT 24
Finished May 02 12:49:03 PM PDT 24
Peak memory 209476 kb
Host smart-64f68806-8b24-4856-a106-1f530c1a9579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107721253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.1107721253
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.3494040493
Short name T855
Test name
Test status
Simulation time 443857510 ps
CPU time 9.02 seconds
Started May 02 12:48:48 PM PDT 24
Finished May 02 12:49:02 PM PDT 24
Peak memory 208060 kb
Host smart-6874682e-9b68-4d08-8faa-1c01945ea068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494040493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.3494040493
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.2590749921
Short name T30
Test name
Test status
Simulation time 886729658 ps
CPU time 8.83 seconds
Started May 02 12:48:46 PM PDT 24
Finished May 02 12:49:00 PM PDT 24
Peak memory 214044 kb
Host smart-da877959-2b99-4e38-b965-584cef1ff901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590749921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.2590749921
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.1669864705
Short name T223
Test name
Test status
Simulation time 134795846 ps
CPU time 3.98 seconds
Started May 02 12:48:53 PM PDT 24
Finished May 02 12:49:00 PM PDT 24
Peak memory 208804 kb
Host smart-39d1d80c-3d29-4626-9785-8f5c131c6e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669864705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.1669864705
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.3931776578
Short name T185
Test name
Test status
Simulation time 4138626285 ps
CPU time 90.98 seconds
Started May 02 12:49:06 PM PDT 24
Finished May 02 12:50:42 PM PDT 24
Peak memory 207736 kb
Host smart-151d0caf-85b6-4b1c-bd7b-c673e35812f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931776578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.3931776578
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.3806057281
Short name T555
Test name
Test status
Simulation time 92118376 ps
CPU time 1.98 seconds
Started May 02 12:48:44 PM PDT 24
Finished May 02 12:48:52 PM PDT 24
Peak memory 208096 kb
Host smart-1e9ce880-1cd1-4117-91fe-dfda0532acfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806057281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.3806057281
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.2197192104
Short name T890
Test name
Test status
Simulation time 188274245 ps
CPU time 6.86 seconds
Started May 02 12:48:47 PM PDT 24
Finished May 02 12:48:59 PM PDT 24
Peak memory 208644 kb
Host smart-9969204e-247a-492f-8863-eead1e8ef6f6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197192104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.2197192104
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.2911526676
Short name T335
Test name
Test status
Simulation time 124235014 ps
CPU time 4.22 seconds
Started May 02 12:48:55 PM PDT 24
Finished May 02 12:49:04 PM PDT 24
Peak memory 206452 kb
Host smart-e47d855d-70e8-4256-8e6c-d68a76a84fee
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911526676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.2911526676
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.1902463809
Short name T729
Test name
Test status
Simulation time 497095907 ps
CPU time 5.73 seconds
Started May 02 12:49:04 PM PDT 24
Finished May 02 12:49:15 PM PDT 24
Peak memory 206456 kb
Host smart-4f04bb13-eac3-45d8-8dfa-9a5d951aa367
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902463809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.1902463809
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.4124323060
Short name T467
Test name
Test status
Simulation time 42411452 ps
CPU time 2.03 seconds
Started May 02 12:48:40 PM PDT 24
Finished May 02 12:48:48 PM PDT 24
Peak memory 208576 kb
Host smart-b3b549f7-4007-418c-a4bc-4f3d9370a102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124323060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.4124323060
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.2118231494
Short name T671
Test name
Test status
Simulation time 527072428 ps
CPU time 3.22 seconds
Started May 02 12:48:55 PM PDT 24
Finished May 02 12:49:03 PM PDT 24
Peak memory 206372 kb
Host smart-a354ea59-2117-4255-9cf2-175b34db464f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118231494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.2118231494
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.1234981713
Short name T182
Test name
Test status
Simulation time 3812994048 ps
CPU time 25.77 seconds
Started May 02 12:48:51 PM PDT 24
Finished May 02 12:49:21 PM PDT 24
Peak memory 216024 kb
Host smart-c36ace3a-1aa4-49cb-8fe6-b0b20dd4db11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234981713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.1234981713
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.4117393701
Short name T64
Test name
Test status
Simulation time 1442654273 ps
CPU time 15.36 seconds
Started May 02 12:48:45 PM PDT 24
Finished May 02 12:49:06 PM PDT 24
Peak memory 222268 kb
Host smart-e5b65d06-64a4-444e-9ff8-32aa52968218
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117393701 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.4117393701
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.4154896216
Short name T894
Test name
Test status
Simulation time 123101198 ps
CPU time 3.35 seconds
Started May 02 12:48:37 PM PDT 24
Finished May 02 12:48:44 PM PDT 24
Peak memory 207336 kb
Host smart-7b47082d-5090-4d10-8703-2493921f02b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154896216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.4154896216
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.975170425
Short name T558
Test name
Test status
Simulation time 100592142 ps
CPU time 2.77 seconds
Started May 02 12:48:40 PM PDT 24
Finished May 02 12:48:49 PM PDT 24
Peak memory 209616 kb
Host smart-bf25af68-fb4b-4114-875d-78c2cdbc6b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975170425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.975170425
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.15935992
Short name T436
Test name
Test status
Simulation time 8479695 ps
CPU time 0.71 seconds
Started May 02 12:48:53 PM PDT 24
Finished May 02 12:48:58 PM PDT 24
Peak memory 205556 kb
Host smart-0c16ca26-e12e-4144-9018-3acb06e91e54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15935992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.15935992
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.1267848672
Short name T213
Test name
Test status
Simulation time 257119791 ps
CPU time 8.84 seconds
Started May 02 12:48:38 PM PDT 24
Finished May 02 12:48:52 PM PDT 24
Peak memory 208980 kb
Host smart-0ce7882c-1f6e-42c6-9d4f-e30068acf38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267848672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.1267848672
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.3446559960
Short name T48
Test name
Test status
Simulation time 74834616 ps
CPU time 2.2 seconds
Started May 02 12:49:03 PM PDT 24
Finished May 02 12:49:10 PM PDT 24
Peak memory 207124 kb
Host smart-9ef06fbc-1c56-46f5-b8d7-a584baad33ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446559960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.3446559960
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.1076161520
Short name T443
Test name
Test status
Simulation time 218012077 ps
CPU time 3.33 seconds
Started May 02 12:48:56 PM PDT 24
Finished May 02 12:49:04 PM PDT 24
Peak memory 209156 kb
Host smart-0dd3971d-64b5-4069-a69d-a826e10330c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076161520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.1076161520
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.2772184126
Short name T783
Test name
Test status
Simulation time 119443231 ps
CPU time 2.63 seconds
Started May 02 12:48:41 PM PDT 24
Finished May 02 12:48:50 PM PDT 24
Peak memory 208928 kb
Host smart-b299c8a7-58e4-45c9-976c-af351a6b17a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772184126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.2772184126
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.159254747
Short name T782
Test name
Test status
Simulation time 203143755 ps
CPU time 2.08 seconds
Started May 02 12:49:08 PM PDT 24
Finished May 02 12:49:15 PM PDT 24
Peak memory 208256 kb
Host smart-ca6ac809-ae7a-4306-8f69-a3583e083ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159254747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.159254747
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.2799690760
Short name T85
Test name
Test status
Simulation time 147083129 ps
CPU time 3.11 seconds
Started May 02 12:48:48 PM PDT 24
Finished May 02 12:48:56 PM PDT 24
Peak memory 208404 kb
Host smart-9ef65ea3-eb1a-45aa-98aa-75ad65aca37c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799690760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.2799690760
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.3332027529
Short name T876
Test name
Test status
Simulation time 103954721 ps
CPU time 3.27 seconds
Started May 02 12:48:40 PM PDT 24
Finished May 02 12:48:49 PM PDT 24
Peak memory 206700 kb
Host smart-83fe70c1-9369-4f52-af17-fc4547275eb0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332027529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.3332027529
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.2732518972
Short name T570
Test name
Test status
Simulation time 229149018 ps
CPU time 3.34 seconds
Started May 02 12:48:40 PM PDT 24
Finished May 02 12:48:50 PM PDT 24
Peak memory 208380 kb
Host smart-1a41c06e-4f26-4a50-be3e-3b55be80389d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732518972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.2732518972
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.1430524793
Short name T699
Test name
Test status
Simulation time 224896408 ps
CPU time 1.7 seconds
Started May 02 12:48:52 PM PDT 24
Finished May 02 12:48:58 PM PDT 24
Peak memory 206964 kb
Host smart-891b09fa-e7f3-4c0c-838a-34f28bab0822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430524793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.1430524793
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.3619707211
Short name T884
Test name
Test status
Simulation time 47593141 ps
CPU time 2.48 seconds
Started May 02 12:48:36 PM PDT 24
Finished May 02 12:48:42 PM PDT 24
Peak memory 207896 kb
Host smart-d0eb4dd0-c343-413e-8293-afa98fdc67d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619707211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.3619707211
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.2409726880
Short name T372
Test name
Test status
Simulation time 1093913875 ps
CPU time 40.66 seconds
Started May 02 12:48:41 PM PDT 24
Finished May 02 12:49:28 PM PDT 24
Peak memory 222224 kb
Host smart-084acb14-a8e8-4dd4-983e-c38c4c54e075
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409726880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.2409726880
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.2187351013
Short name T114
Test name
Test status
Simulation time 101834855 ps
CPU time 6.65 seconds
Started May 02 12:48:59 PM PDT 24
Finished May 02 12:49:10 PM PDT 24
Peak memory 217672 kb
Host smart-d9bb536b-a5bf-4151-ba3c-d4c9afa4e50d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187351013 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.2187351013
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.980350769
Short name T508
Test name
Test status
Simulation time 3233974510 ps
CPU time 18.42 seconds
Started May 02 12:48:40 PM PDT 24
Finished May 02 12:49:06 PM PDT 24
Peak memory 208328 kb
Host smart-273c9c04-3522-4190-94cf-71f8af96ea4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980350769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.980350769
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.2508540334
Short name T108
Test name
Test status
Simulation time 108475404 ps
CPU time 2.27 seconds
Started May 02 12:48:38 PM PDT 24
Finished May 02 12:48:45 PM PDT 24
Peak memory 209540 kb
Host smart-73f80203-930e-473a-a65c-4186835432f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508540334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.2508540334
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.3157801277
Short name T427
Test name
Test status
Simulation time 37405919 ps
CPU time 0.88 seconds
Started May 02 12:48:54 PM PDT 24
Finished May 02 12:49:00 PM PDT 24
Peak memory 205620 kb
Host smart-7fdfdfa9-1ec0-4a03-817e-6271a0946f64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157801277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.3157801277
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.1685253766
Short name T300
Test name
Test status
Simulation time 27191101 ps
CPU time 2.12 seconds
Started May 02 12:48:52 PM PDT 24
Finished May 02 12:48:58 PM PDT 24
Peak memory 213992 kb
Host smart-fedc29d7-cbd0-4de8-936a-a5ac98b11390
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1685253766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.1685253766
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.2675711837
Short name T21
Test name
Test status
Simulation time 57861575 ps
CPU time 3.46 seconds
Started May 02 12:49:01 PM PDT 24
Finished May 02 12:49:14 PM PDT 24
Peak memory 221328 kb
Host smart-d32ec324-4b40-48ff-9f68-451d7929fd21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675711837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.2675711837
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.3849890595
Short name T463
Test name
Test status
Simulation time 177010456 ps
CPU time 2.26 seconds
Started May 02 12:48:54 PM PDT 24
Finished May 02 12:49:01 PM PDT 24
Peak memory 206484 kb
Host smart-518e3b56-5a65-4b14-a6c6-8a692e9c3f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849890595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.3849890595
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.2164420894
Short name T361
Test name
Test status
Simulation time 2429541016 ps
CPU time 10.9 seconds
Started May 02 12:49:02 PM PDT 24
Finished May 02 12:49:18 PM PDT 24
Peak memory 214064 kb
Host smart-1de5a07a-1878-4480-a971-e87aac8def08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164420894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.2164420894
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.2935183209
Short name T497
Test name
Test status
Simulation time 353726834 ps
CPU time 2.73 seconds
Started May 02 12:48:49 PM PDT 24
Finished May 02 12:48:56 PM PDT 24
Peak memory 213924 kb
Host smart-1faca55b-45b2-4485-96b6-70b53f897443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935183209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.2935183209
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.1902467942
Short name T588
Test name
Test status
Simulation time 103213145 ps
CPU time 4.61 seconds
Started May 02 12:48:52 PM PDT 24
Finished May 02 12:49:01 PM PDT 24
Peak memory 207516 kb
Host smart-30b9dd0a-417f-49e1-8330-cf06b97d8f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902467942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.1902467942
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.1917089876
Short name T604
Test name
Test status
Simulation time 356450861 ps
CPU time 2.88 seconds
Started May 02 12:48:47 PM PDT 24
Finished May 02 12:48:55 PM PDT 24
Peak memory 206488 kb
Host smart-26861a65-eba0-4d8c-8d37-46fa76e2c542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917089876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.1917089876
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.436843534
Short name T82
Test name
Test status
Simulation time 141801485 ps
CPU time 2.44 seconds
Started May 02 12:48:54 PM PDT 24
Finished May 02 12:49:01 PM PDT 24
Peak memory 206252 kb
Host smart-05dc1127-457c-4df4-b975-6e94c273b71a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436843534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.436843534
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.3957308056
Short name T594
Test name
Test status
Simulation time 159647237 ps
CPU time 3.72 seconds
Started May 02 12:48:42 PM PDT 24
Finished May 02 12:48:52 PM PDT 24
Peak memory 208264 kb
Host smart-2ea2a695-d76c-44f1-b736-af3b1e2c5b8b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957308056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.3957308056
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.2591941139
Short name T756
Test name
Test status
Simulation time 257284664 ps
CPU time 8.19 seconds
Started May 02 12:48:49 PM PDT 24
Finished May 02 12:49:01 PM PDT 24
Peak memory 208436 kb
Host smart-5177abcd-14bb-4ab7-b20a-306fec8a7ff7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591941139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.2591941139
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.1146535754
Short name T767
Test name
Test status
Simulation time 100739780 ps
CPU time 1.74 seconds
Started May 02 12:49:07 PM PDT 24
Finished May 02 12:49:14 PM PDT 24
Peak memory 208800 kb
Host smart-b892d1de-8edc-424c-b837-d2750fefe76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146535754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.1146535754
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.1157072618
Short name T748
Test name
Test status
Simulation time 7711738011 ps
CPU time 71.74 seconds
Started May 02 12:49:01 PM PDT 24
Finished May 02 12:50:17 PM PDT 24
Peak memory 208168 kb
Host smart-21175711-5312-44b3-98a1-bfb2d79dbd07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157072618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.1157072618
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.2429629386
Short name T735
Test name
Test status
Simulation time 6779281554 ps
CPU time 44.88 seconds
Started May 02 12:49:06 PM PDT 24
Finished May 02 12:49:57 PM PDT 24
Peak memory 215276 kb
Host smart-0316c5d5-ab06-470b-8be0-87813e85813e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429629386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.2429629386
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.102417794
Short name T464
Test name
Test status
Simulation time 1666206217 ps
CPU time 42.62 seconds
Started May 02 12:48:47 PM PDT 24
Finished May 02 12:49:35 PM PDT 24
Peak memory 209152 kb
Host smart-1c5e6119-9d25-46fc-8095-3e79e16a12d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102417794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.102417794
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.4064295149
Short name T66
Test name
Test status
Simulation time 69082539 ps
CPU time 3.17 seconds
Started May 02 12:48:58 PM PDT 24
Finished May 02 12:49:11 PM PDT 24
Peak memory 209516 kb
Host smart-4e280f5d-d940-4fea-b166-6c07ffaadc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064295149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.4064295149
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.1081426692
Short name T666
Test name
Test status
Simulation time 18771352 ps
CPU time 0.76 seconds
Started May 02 12:48:59 PM PDT 24
Finished May 02 12:49:05 PM PDT 24
Peak memory 205592 kb
Host smart-d45c883b-d5e8-40b0-bffd-94849213bf01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081426692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.1081426692
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.890803055
Short name T318
Test name
Test status
Simulation time 137080203 ps
CPU time 3.62 seconds
Started May 02 12:48:56 PM PDT 24
Finished May 02 12:49:04 PM PDT 24
Peak memory 218160 kb
Host smart-46c80333-c072-4900-be6a-7d0ba0eb6b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890803055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.890803055
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.2938429137
Short name T373
Test name
Test status
Simulation time 599062312 ps
CPU time 16.96 seconds
Started May 02 12:49:03 PM PDT 24
Finished May 02 12:49:25 PM PDT 24
Peak memory 209452 kb
Host smart-34c04da2-0901-4fd3-8d2e-bfeae7fc853b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938429137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.2938429137
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.1593383020
Short name T189
Test name
Test status
Simulation time 155449128 ps
CPU time 3.59 seconds
Started May 02 12:49:16 PM PDT 24
Finished May 02 12:49:23 PM PDT 24
Peak memory 210276 kb
Host smart-29cb53ec-fec0-4603-997f-d49aa042f588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593383020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.1593383020
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.3117204558
Short name T49
Test name
Test status
Simulation time 202802870 ps
CPU time 3.81 seconds
Started May 02 12:49:07 PM PDT 24
Finished May 02 12:49:17 PM PDT 24
Peak memory 219864 kb
Host smart-f35fdd43-550b-4035-8703-f25a6ea0dad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117204558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.3117204558
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.4072724406
Short name T738
Test name
Test status
Simulation time 386080978 ps
CPU time 10.42 seconds
Started May 02 12:49:00 PM PDT 24
Finished May 02 12:49:14 PM PDT 24
Peak memory 213952 kb
Host smart-4ed7b0a1-e969-463d-ba4e-cc63030417e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072724406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.4072724406
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.594506929
Short name T687
Test name
Test status
Simulation time 153285045 ps
CPU time 6.06 seconds
Started May 02 12:49:03 PM PDT 24
Finished May 02 12:49:14 PM PDT 24
Peak memory 207864 kb
Host smart-52c66e3f-02df-4355-a429-232a40bcb277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594506929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.594506929
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.909527437
Short name T430
Test name
Test status
Simulation time 27696072 ps
CPU time 1.77 seconds
Started May 02 12:48:57 PM PDT 24
Finished May 02 12:49:04 PM PDT 24
Peak memory 206412 kb
Host smart-4f75f7c2-6a57-4066-9d18-59854c6fcc9e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909527437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.909527437
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.581548643
Short name T617
Test name
Test status
Simulation time 154218563 ps
CPU time 3.8 seconds
Started May 02 12:49:05 PM PDT 24
Finished May 02 12:49:14 PM PDT 24
Peak memory 208364 kb
Host smart-fa05d268-b472-4941-a0c2-e98abec251d7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581548643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.581548643
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.3873284910
Short name T466
Test name
Test status
Simulation time 321631648 ps
CPU time 2.66 seconds
Started May 02 12:49:03 PM PDT 24
Finished May 02 12:49:10 PM PDT 24
Peak memory 206468 kb
Host smart-1edb7689-84c1-4d79-8cff-2331fb3012fa
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873284910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.3873284910
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.3027335019
Short name T276
Test name
Test status
Simulation time 333108014 ps
CPU time 3.62 seconds
Started May 02 12:49:04 PM PDT 24
Finished May 02 12:49:13 PM PDT 24
Peak memory 214088 kb
Host smart-c7ad2779-28a3-4d84-a3b4-689e64a46f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027335019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.3027335019
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.3364341677
Short name T196
Test name
Test status
Simulation time 34739202 ps
CPU time 2.43 seconds
Started May 02 12:49:01 PM PDT 24
Finished May 02 12:49:08 PM PDT 24
Peak memory 207840 kb
Host smart-28b3ac7a-9304-4e91-8c00-849c5da1ef6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364341677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.3364341677
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.1993706717
Short name T585
Test name
Test status
Simulation time 2793951442 ps
CPU time 63.1 seconds
Started May 02 12:49:11 PM PDT 24
Finished May 02 12:50:19 PM PDT 24
Peak memory 208720 kb
Host smart-ab04ccab-a760-47ab-a264-ea42c0c8cec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993706717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.1993706717
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.4012240294
Short name T661
Test name
Test status
Simulation time 762049916 ps
CPU time 4.54 seconds
Started May 02 12:48:58 PM PDT 24
Finished May 02 12:49:07 PM PDT 24
Peak memory 209968 kb
Host smart-0c1291f2-7eee-4841-8e0a-9aae522d4606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012240294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.4012240294
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.2724142096
Short name T743
Test name
Test status
Simulation time 72348047 ps
CPU time 0.89 seconds
Started May 02 12:49:12 PM PDT 24
Finished May 02 12:49:18 PM PDT 24
Peak memory 205584 kb
Host smart-346918c2-052a-4af8-bb73-2a15f1084b1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724142096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.2724142096
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.3744076992
Short name T496
Test name
Test status
Simulation time 641845348 ps
CPU time 8.02 seconds
Started May 02 12:49:17 PM PDT 24
Finished May 02 12:49:28 PM PDT 24
Peak memory 217676 kb
Host smart-11afe6b1-7c4e-4815-bd76-f3d4041a2cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744076992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.3744076992
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.3408818149
Short name T846
Test name
Test status
Simulation time 49880206 ps
CPU time 1.37 seconds
Started May 02 12:49:16 PM PDT 24
Finished May 02 12:49:21 PM PDT 24
Peak memory 208024 kb
Host smart-cc6cc033-466e-4cb7-8121-0c3c2c48b5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408818149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.3408818149
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.970665815
Short name T97
Test name
Test status
Simulation time 485893282 ps
CPU time 6.31 seconds
Started May 02 12:48:56 PM PDT 24
Finished May 02 12:49:08 PM PDT 24
Peak memory 222164 kb
Host smart-6179aab0-a88d-43ec-980d-c3b52eb28828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970665815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.970665815
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.4150358393
Short name T375
Test name
Test status
Simulation time 552893817 ps
CPU time 5.16 seconds
Started May 02 12:48:57 PM PDT 24
Finished May 02 12:49:07 PM PDT 24
Peak memory 214020 kb
Host smart-3d10b34d-f4de-42c8-a691-da7068115a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150358393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.4150358393
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.3621792117
Short name T46
Test name
Test status
Simulation time 103409812 ps
CPU time 5.05 seconds
Started May 02 12:49:03 PM PDT 24
Finished May 02 12:49:18 PM PDT 24
Peak memory 220184 kb
Host smart-25dc3df6-5afc-4e27-9e8d-9638655c8e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621792117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.3621792117
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.2077972343
Short name T188
Test name
Test status
Simulation time 111502381 ps
CPU time 4.48 seconds
Started May 02 12:49:02 PM PDT 24
Finished May 02 12:49:11 PM PDT 24
Peak memory 209844 kb
Host smart-ab34913e-cc40-47d8-8472-8e35767180d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077972343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.2077972343
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.2370967120
Short name T679
Test name
Test status
Simulation time 1268210960 ps
CPU time 35.99 seconds
Started May 02 12:48:56 PM PDT 24
Finished May 02 12:49:36 PM PDT 24
Peak memory 207624 kb
Host smart-d18c9040-980a-4ebc-a5a6-8e9e3926a6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370967120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.2370967120
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.307044902
Short name T479
Test name
Test status
Simulation time 160187671 ps
CPU time 4.6 seconds
Started May 02 12:49:05 PM PDT 24
Finished May 02 12:49:16 PM PDT 24
Peak memory 207744 kb
Host smart-588a2d52-932a-461e-a9f7-1e5099ec70d5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307044902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.307044902
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.1532655686
Short name T803
Test name
Test status
Simulation time 2037478269 ps
CPU time 36.98 seconds
Started May 02 12:49:12 PM PDT 24
Finished May 02 12:49:54 PM PDT 24
Peak memory 207408 kb
Host smart-06593451-ce8c-4a83-8896-3a4a2a00517a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532655686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.1532655686
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.3997870305
Short name T861
Test name
Test status
Simulation time 101208101 ps
CPU time 2.73 seconds
Started May 02 12:49:04 PM PDT 24
Finished May 02 12:49:12 PM PDT 24
Peak memory 208184 kb
Host smart-44202443-ca98-4139-87f9-5f3022eda78c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997870305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.3997870305
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.1458231180
Short name T504
Test name
Test status
Simulation time 27142967 ps
CPU time 2.25 seconds
Started May 02 12:48:55 PM PDT 24
Finished May 02 12:49:02 PM PDT 24
Peak memory 213968 kb
Host smart-36fe9140-4dba-4cef-bc7c-c5c41301515a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458231180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.1458231180
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.1150087994
Short name T433
Test name
Test status
Simulation time 52400833 ps
CPU time 2.66 seconds
Started May 02 12:49:01 PM PDT 24
Finished May 02 12:49:09 PM PDT 24
Peak memory 206300 kb
Host smart-180dfbbe-0888-470f-9451-df013b8b3b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150087994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.1150087994
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.2654401475
Short name T825
Test name
Test status
Simulation time 447956253 ps
CPU time 5.25 seconds
Started May 02 12:48:53 PM PDT 24
Finished May 02 12:49:02 PM PDT 24
Peak memory 209956 kb
Host smart-b6884c89-d1b9-45b1-be97-585c4417e344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654401475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.2654401475
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.268109276
Short name T590
Test name
Test status
Simulation time 20676876 ps
CPU time 0.75 seconds
Started May 02 12:47:27 PM PDT 24
Finished May 02 12:47:30 PM PDT 24
Peak memory 205520 kb
Host smart-e394eb6c-fc79-414f-9fe7-ed3e6110aebf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268109276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.268109276
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.280178822
Short name T267
Test name
Test status
Simulation time 127353180 ps
CPU time 7.23 seconds
Started May 02 12:47:42 PM PDT 24
Finished May 02 12:47:52 PM PDT 24
Peak memory 213924 kb
Host smart-4b965b2d-4d06-4e48-b456-2c5b9ae2fa0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=280178822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.280178822
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.3610483343
Short name T660
Test name
Test status
Simulation time 1314425727 ps
CPU time 46.33 seconds
Started May 02 12:47:42 PM PDT 24
Finished May 02 12:48:31 PM PDT 24
Peak memory 222368 kb
Host smart-4454e45d-a259-4f5a-a224-5380b970ee62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610483343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.3610483343
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.1687250209
Short name T54
Test name
Test status
Simulation time 74859894 ps
CPU time 1.81 seconds
Started May 02 12:47:42 PM PDT 24
Finished May 02 12:47:47 PM PDT 24
Peak memory 209828 kb
Host smart-75297668-5902-47e7-b493-ce8a6a3e6df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687250209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.1687250209
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.30678229
Short name T700
Test name
Test status
Simulation time 498034807 ps
CPU time 8.88 seconds
Started May 02 12:47:36 PM PDT 24
Finished May 02 12:47:46 PM PDT 24
Peak memory 214000 kb
Host smart-4f265f97-64f9-44a1-9899-8d937d861209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30678229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.30678229
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.2888604868
Short name T306
Test name
Test status
Simulation time 236583542 ps
CPU time 4.81 seconds
Started May 02 12:47:21 PM PDT 24
Finished May 02 12:47:30 PM PDT 24
Peak memory 220880 kb
Host smart-47bdc3b5-9c0b-470c-8799-e53790c7a3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888604868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.2888604868
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.1535664935
Short name T233
Test name
Test status
Simulation time 201566069 ps
CPU time 3.42 seconds
Started May 02 12:47:26 PM PDT 24
Finished May 02 12:47:33 PM PDT 24
Peak memory 209444 kb
Host smart-a9844360-15f9-4d63-86cf-fe60d222589c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535664935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.1535664935
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.821930069
Short name T281
Test name
Test status
Simulation time 189326357 ps
CPU time 2.66 seconds
Started May 02 12:47:34 PM PDT 24
Finished May 02 12:47:38 PM PDT 24
Peak memory 206932 kb
Host smart-8ac7040c-c404-4b3f-9883-655e175f7071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821930069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.821930069
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.2411919174
Short name T100
Test name
Test status
Simulation time 1098833071 ps
CPU time 10.07 seconds
Started May 02 12:47:37 PM PDT 24
Finished May 02 12:47:49 PM PDT 24
Peak memory 229960 kb
Host smart-85c2dfe6-2234-4413-9ade-0644628baddc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411919174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.2411919174
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.661018684
Short name T236
Test name
Test status
Simulation time 31539114 ps
CPU time 2.14 seconds
Started May 02 12:47:53 PM PDT 24
Finished May 02 12:47:58 PM PDT 24
Peak memory 206332 kb
Host smart-c723924a-b30c-4398-8178-3ee1cd7c895a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661018684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.661018684
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.181270287
Short name T816
Test name
Test status
Simulation time 20337117 ps
CPU time 1.7 seconds
Started May 02 12:47:43 PM PDT 24
Finished May 02 12:47:48 PM PDT 24
Peak memory 206424 kb
Host smart-d28b09cd-546b-489b-8338-470d812db891
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181270287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.181270287
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.409496485
Short name T840
Test name
Test status
Simulation time 3460440632 ps
CPU time 63.32 seconds
Started May 02 12:47:26 PM PDT 24
Finished May 02 12:48:32 PM PDT 24
Peak memory 208192 kb
Host smart-8c32cc1a-f77b-4fa4-85e8-b4c17b4da811
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409496485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.409496485
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.3755492751
Short name T831
Test name
Test status
Simulation time 157894811 ps
CPU time 5.41 seconds
Started May 02 12:47:28 PM PDT 24
Finished May 02 12:47:35 PM PDT 24
Peak memory 208252 kb
Host smart-47ed0c61-a950-432b-81a6-ac0cba7a74c5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755492751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.3755492751
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.3754137455
Short name T630
Test name
Test status
Simulation time 189667642 ps
CPU time 3.94 seconds
Started May 02 12:47:28 PM PDT 24
Finished May 02 12:47:34 PM PDT 24
Peak memory 209508 kb
Host smart-f8a0812b-3bd4-41f4-b49b-6f54bdc76390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754137455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.3754137455
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.3950948496
Short name T595
Test name
Test status
Simulation time 3971125085 ps
CPU time 37.45 seconds
Started May 02 12:47:26 PM PDT 24
Finished May 02 12:48:07 PM PDT 24
Peak memory 208536 kb
Host smart-7b92b735-ae44-491c-8069-82246b77cec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950948496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.3950948496
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.2155428085
Short name T311
Test name
Test status
Simulation time 853959658 ps
CPU time 8.85 seconds
Started May 02 12:47:45 PM PDT 24
Finished May 02 12:47:57 PM PDT 24
Peak memory 216300 kb
Host smart-410ec234-b97d-4fe7-831b-ab024956d1e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155428085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.2155428085
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.1682533602
Short name T352
Test name
Test status
Simulation time 193161459 ps
CPU time 2.58 seconds
Started May 02 12:47:59 PM PDT 24
Finished May 02 12:48:06 PM PDT 24
Peak memory 208692 kb
Host smart-fa84a6fb-a349-4ea0-be0c-ab1b949b90c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682533602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.1682533602
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.2269232135
Short name T673
Test name
Test status
Simulation time 58910617 ps
CPU time 2.27 seconds
Started May 02 12:47:44 PM PDT 24
Finished May 02 12:47:50 PM PDT 24
Peak memory 209496 kb
Host smart-000628dc-0a7e-4fae-ba37-9446fca96521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269232135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.2269232135
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.2244847304
Short name T564
Test name
Test status
Simulation time 22743374 ps
CPU time 0.87 seconds
Started May 02 12:48:53 PM PDT 24
Finished May 02 12:48:58 PM PDT 24
Peak memory 205480 kb
Host smart-83f639b6-b574-4481-b6aa-4dc6ab7702ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244847304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.2244847304
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.3124295255
Short name T758
Test name
Test status
Simulation time 345604314 ps
CPU time 4.89 seconds
Started May 02 12:48:55 PM PDT 24
Finished May 02 12:49:05 PM PDT 24
Peak memory 209360 kb
Host smart-d0e60084-3d8c-4a63-ade9-264d614c2647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124295255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.3124295255
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.2855412674
Short name T89
Test name
Test status
Simulation time 408697130 ps
CPU time 6.82 seconds
Started May 02 12:48:53 PM PDT 24
Finished May 02 12:49:04 PM PDT 24
Peak memory 213996 kb
Host smart-92117162-4099-42dc-b299-686a07b0a3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855412674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.2855412674
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.483143067
Short name T810
Test name
Test status
Simulation time 192959934 ps
CPU time 2.85 seconds
Started May 02 12:48:53 PM PDT 24
Finished May 02 12:49:00 PM PDT 24
Peak memory 220064 kb
Host smart-b879796a-2faf-43db-8c9b-8432fdcf9b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483143067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.483143067
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.732751153
Short name T246
Test name
Test status
Simulation time 2248933698 ps
CPU time 23.28 seconds
Started May 02 12:49:03 PM PDT 24
Finished May 02 12:49:31 PM PDT 24
Peak memory 214048 kb
Host smart-06124759-e432-425e-b0ff-aeab14bf329a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732751153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.732751153
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.364094458
Short name T339
Test name
Test status
Simulation time 365086220 ps
CPU time 3.53 seconds
Started May 02 12:48:58 PM PDT 24
Finished May 02 12:49:06 PM PDT 24
Peak memory 206472 kb
Host smart-58f6d760-eea8-4a69-ba73-4b6e5df7bb1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364094458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.364094458
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.2781238203
Short name T716
Test name
Test status
Simulation time 232869282 ps
CPU time 7.01 seconds
Started May 02 12:48:56 PM PDT 24
Finished May 02 12:49:07 PM PDT 24
Peak memory 206472 kb
Host smart-56e3da2f-03d4-49df-a0e2-91e9cf5d95fd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781238203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.2781238203
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.3633296778
Short name T401
Test name
Test status
Simulation time 935401837 ps
CPU time 9.97 seconds
Started May 02 12:48:51 PM PDT 24
Finished May 02 12:49:05 PM PDT 24
Peak memory 207600 kb
Host smart-147e87df-5e11-415e-918d-76901cce7530
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633296778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.3633296778
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.886392006
Short name T619
Test name
Test status
Simulation time 3651267406 ps
CPU time 39.18 seconds
Started May 02 12:48:54 PM PDT 24
Finished May 02 12:49:38 PM PDT 24
Peak memory 208072 kb
Host smart-eb1d58e6-677b-4ba1-92ef-0593cf9f6368
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886392006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.886392006
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.1191133100
Short name T654
Test name
Test status
Simulation time 1739208578 ps
CPU time 3.4 seconds
Started May 02 12:48:58 PM PDT 24
Finished May 02 12:49:05 PM PDT 24
Peak memory 213936 kb
Host smart-2f5d4ce4-489a-432a-84d6-de0eda20ce6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191133100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.1191133100
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.1441252355
Short name T487
Test name
Test status
Simulation time 412102627 ps
CPU time 3.21 seconds
Started May 02 12:49:16 PM PDT 24
Finished May 02 12:49:23 PM PDT 24
Peak memory 206380 kb
Host smart-126bf497-7926-4ab2-a076-fb0beba3ed86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441252355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.1441252355
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.3291255492
Short name T507
Test name
Test status
Simulation time 1215175804 ps
CPU time 32.02 seconds
Started May 02 12:48:57 PM PDT 24
Finished May 02 12:49:34 PM PDT 24
Peak memory 213972 kb
Host smart-41e5f392-3bac-4fdd-b80b-741a081ea536
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291255492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.3291255492
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.703885724
Short name T177
Test name
Test status
Simulation time 427725165 ps
CPU time 16.28 seconds
Started May 02 12:49:02 PM PDT 24
Finished May 02 12:49:24 PM PDT 24
Peak memory 222256 kb
Host smart-c733c4c2-db88-4e5a-a520-90fd0f132668
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703885724 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.703885724
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.2357384085
Short name T374
Test name
Test status
Simulation time 241255757 ps
CPU time 3.72 seconds
Started May 02 12:49:04 PM PDT 24
Finished May 02 12:49:13 PM PDT 24
Peak memory 206860 kb
Host smart-5b906587-cbda-4a2c-886d-4895565fdf64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357384085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.2357384085
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.3503942975
Short name T128
Test name
Test status
Simulation time 517356242 ps
CPU time 1.73 seconds
Started May 02 12:49:05 PM PDT 24
Finished May 02 12:49:12 PM PDT 24
Peak memory 209496 kb
Host smart-208ab97e-d1b3-4467-9c1a-d07ce6edc177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503942975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.3503942975
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.3506548401
Short name T498
Test name
Test status
Simulation time 177528471 ps
CPU time 0.88 seconds
Started May 02 12:49:03 PM PDT 24
Finished May 02 12:49:10 PM PDT 24
Peak memory 205536 kb
Host smart-2414c37c-1172-493a-b4e2-7ec5ac64e4c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506548401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.3506548401
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.2155143699
Short name T277
Test name
Test status
Simulation time 38002197 ps
CPU time 2.5 seconds
Started May 02 12:49:05 PM PDT 24
Finished May 02 12:49:12 PM PDT 24
Peak memory 213980 kb
Host smart-87ba575e-2b97-4927-821d-134ca1e1cb33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2155143699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.2155143699
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.2475378741
Short name T174
Test name
Test status
Simulation time 250643113 ps
CPU time 2.14 seconds
Started May 02 12:48:57 PM PDT 24
Finished May 02 12:49:04 PM PDT 24
Peak memory 209928 kb
Host smart-3c29906f-1b73-43d9-8983-f6aa00c8f14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475378741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.2475378741
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.3628356655
Short name T47
Test name
Test status
Simulation time 83200272 ps
CPU time 2.95 seconds
Started May 02 12:49:10 PM PDT 24
Finished May 02 12:49:18 PM PDT 24
Peak memory 206712 kb
Host smart-ed6c5c3b-4490-4926-89bf-9faecf538981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628356655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.3628356655
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.3681656686
Short name T392
Test name
Test status
Simulation time 2875984288 ps
CPU time 67.19 seconds
Started May 02 12:49:13 PM PDT 24
Finished May 02 12:50:25 PM PDT 24
Peak memory 213972 kb
Host smart-840e9c9b-ef79-4ca3-80f3-abdf450bbdfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681656686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.3681656686
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.2201191776
Short name T265
Test name
Test status
Simulation time 119863073 ps
CPU time 4.19 seconds
Started May 02 12:49:01 PM PDT 24
Finished May 02 12:49:10 PM PDT 24
Peak memory 209332 kb
Host smart-c2835fec-c046-44a7-b635-9a3635c02b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201191776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.2201191776
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.3895212344
Short name T573
Test name
Test status
Simulation time 50008659 ps
CPU time 2.97 seconds
Started May 02 12:49:05 PM PDT 24
Finished May 02 12:49:13 PM PDT 24
Peak memory 220108 kb
Host smart-10102740-0a0e-4bee-a12a-465426a74258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895212344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.3895212344
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.57417318
Short name T106
Test name
Test status
Simulation time 372317068 ps
CPU time 4.61 seconds
Started May 02 12:49:07 PM PDT 24
Finished May 02 12:49:19 PM PDT 24
Peak memory 208988 kb
Host smart-698bb1c3-7370-4567-b4b9-e2f9bb9a6e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57417318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.57417318
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.191541044
Short name T609
Test name
Test status
Simulation time 40873303 ps
CPU time 1.8 seconds
Started May 02 12:48:53 PM PDT 24
Finished May 02 12:49:00 PM PDT 24
Peak memory 205904 kb
Host smart-a5150e22-fd0b-4f4f-8991-e971f7add8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191541044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.191541044
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.1269949083
Short name T248
Test name
Test status
Simulation time 70082984 ps
CPU time 2.51 seconds
Started May 02 12:49:07 PM PDT 24
Finished May 02 12:49:15 PM PDT 24
Peak memory 206412 kb
Host smart-58290a33-5c5e-45ae-9508-30d8d95750ad
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269949083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.1269949083
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.3576820654
Short name T879
Test name
Test status
Simulation time 72236171 ps
CPU time 2.52 seconds
Started May 02 12:48:58 PM PDT 24
Finished May 02 12:49:05 PM PDT 24
Peak memory 206444 kb
Host smart-4630157d-7a58-45e8-aad3-a0bbe5b2b28b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576820654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.3576820654
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.600308631
Short name T873
Test name
Test status
Simulation time 75306233 ps
CPU time 3.1 seconds
Started May 02 12:48:54 PM PDT 24
Finished May 02 12:49:02 PM PDT 24
Peak memory 207348 kb
Host smart-8f3e9491-38b3-4c30-8296-cab43a0e0761
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600308631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.600308631
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.1636019579
Short name T412
Test name
Test status
Simulation time 367793675 ps
CPU time 2.74 seconds
Started May 02 12:49:11 PM PDT 24
Finished May 02 12:49:19 PM PDT 24
Peak memory 215228 kb
Host smart-5ab5809a-abb7-4684-899b-834bdac10144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636019579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.1636019579
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.4269325248
Short name T686
Test name
Test status
Simulation time 39881111 ps
CPU time 2.27 seconds
Started May 02 12:49:04 PM PDT 24
Finished May 02 12:49:11 PM PDT 24
Peak memory 206424 kb
Host smart-cb7b6e75-0323-474e-9137-ad8feeb961e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269325248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.4269325248
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.443841077
Short name T354
Test name
Test status
Simulation time 522271912 ps
CPU time 10.08 seconds
Started May 02 12:49:12 PM PDT 24
Finished May 02 12:49:27 PM PDT 24
Peak memory 214008 kb
Host smart-051bf25c-8f8b-4ab6-b28e-6b33a0b305dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443841077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.443841077
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.2001254189
Short name T382
Test name
Test status
Simulation time 176733729 ps
CPU time 1.84 seconds
Started May 02 12:49:07 PM PDT 24
Finished May 02 12:49:14 PM PDT 24
Peak memory 209516 kb
Host smart-eb01c5e5-8f66-4350-b81e-c837014c50ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001254189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.2001254189
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.3393271115
Short name T579
Test name
Test status
Simulation time 52347665 ps
CPU time 0.87 seconds
Started May 02 12:49:04 PM PDT 24
Finished May 02 12:49:10 PM PDT 24
Peak memory 205556 kb
Host smart-33cf84f1-47da-4447-80b5-b4ac9f479306
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393271115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.3393271115
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.1542793394
Short name T216
Test name
Test status
Simulation time 187753333 ps
CPU time 5.05 seconds
Started May 02 12:49:04 PM PDT 24
Finished May 02 12:49:14 PM PDT 24
Peak memory 221548 kb
Host smart-07a5caa1-4b86-493b-a551-4ce3c8caa039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542793394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.1542793394
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.3516403170
Short name T841
Test name
Test status
Simulation time 1643386691 ps
CPU time 8.62 seconds
Started May 02 12:49:07 PM PDT 24
Finished May 02 12:49:21 PM PDT 24
Peak memory 213880 kb
Host smart-471d1ddd-b92f-445a-86c7-3358ed1348f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516403170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.3516403170
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.1731662419
Short name T291
Test name
Test status
Simulation time 2042829670 ps
CPU time 43.49 seconds
Started May 02 12:48:57 PM PDT 24
Finished May 02 12:49:45 PM PDT 24
Peak memory 213968 kb
Host smart-7b304669-ca41-4e93-a381-ade1ee60cecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731662419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.1731662419
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.885763964
Short name T396
Test name
Test status
Simulation time 132485657 ps
CPU time 4.69 seconds
Started May 02 12:49:05 PM PDT 24
Finished May 02 12:49:15 PM PDT 24
Peak memory 213928 kb
Host smart-9fc78513-f0f3-46fe-98ee-311e18d925f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885763964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.885763964
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.3984042922
Short name T614
Test name
Test status
Simulation time 376298677 ps
CPU time 3.61 seconds
Started May 02 12:49:03 PM PDT 24
Finished May 02 12:49:12 PM PDT 24
Peak memory 214008 kb
Host smart-ef3c29dd-5010-4ea7-ab6e-04ca2a1d75d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984042922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.3984042922
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.2263206373
Short name T255
Test name
Test status
Simulation time 1379019110 ps
CPU time 4.16 seconds
Started May 02 12:49:13 PM PDT 24
Finished May 02 12:49:22 PM PDT 24
Peak memory 209500 kb
Host smart-a9254eac-c63f-4ef9-9476-2dc86bd6866c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263206373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2263206373
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.2475828777
Short name T488
Test name
Test status
Simulation time 287764626 ps
CPU time 4.28 seconds
Started May 02 12:49:10 PM PDT 24
Finished May 02 12:49:19 PM PDT 24
Peak memory 206380 kb
Host smart-15ed428d-d297-4cbf-9562-b084c199cdd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475828777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.2475828777
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.3944700618
Short name T575
Test name
Test status
Simulation time 121485534 ps
CPU time 2.43 seconds
Started May 02 12:49:18 PM PDT 24
Finished May 02 12:49:24 PM PDT 24
Peak memory 206388 kb
Host smart-b7cfc709-d47b-402b-bf93-095cf58ecd7d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944700618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.3944700618
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.1899762329
Short name T843
Test name
Test status
Simulation time 62261953 ps
CPU time 3.11 seconds
Started May 02 12:49:05 PM PDT 24
Finished May 02 12:49:13 PM PDT 24
Peak memory 207636 kb
Host smart-2cb12b21-0ca2-416d-b1eb-3bbf11d7e6c0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899762329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.1899762329
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.719102371
Short name T860
Test name
Test status
Simulation time 520879035 ps
CPU time 5.95 seconds
Started May 02 12:49:09 PM PDT 24
Finished May 02 12:49:20 PM PDT 24
Peak memory 207768 kb
Host smart-8387ca37-6cc2-44f2-9086-4923152d05b9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719102371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.719102371
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.3027900744
Short name T293
Test name
Test status
Simulation time 99347686 ps
CPU time 2.77 seconds
Started May 02 12:49:03 PM PDT 24
Finished May 02 12:49:11 PM PDT 24
Peak memory 209480 kb
Host smart-edb641f3-e84b-4280-a184-3240937cf479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027900744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.3027900744
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.2390044334
Short name T847
Test name
Test status
Simulation time 82865498 ps
CPU time 3.49 seconds
Started May 02 12:49:08 PM PDT 24
Finished May 02 12:49:17 PM PDT 24
Peak memory 207852 kb
Host smart-186847fd-d0af-4569-95f4-2bf5c751385b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390044334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.2390044334
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.155256491
Short name T319
Test name
Test status
Simulation time 1294466183 ps
CPU time 18.72 seconds
Started May 02 12:49:05 PM PDT 24
Finished May 02 12:49:29 PM PDT 24
Peak memory 222264 kb
Host smart-343f91aa-15f2-4b80-b8bf-27658d085133
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155256491 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.155256491
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.1284543005
Short name T186
Test name
Test status
Simulation time 178807996 ps
CPU time 4.24 seconds
Started May 02 12:49:01 PM PDT 24
Finished May 02 12:49:10 PM PDT 24
Peak memory 209428 kb
Host smart-77edddc3-7234-4f2b-9130-cfb9a7117e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284543005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.1284543005
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.1128653853
Short name T127
Test name
Test status
Simulation time 56215665 ps
CPU time 2.06 seconds
Started May 02 12:48:56 PM PDT 24
Finished May 02 12:49:03 PM PDT 24
Peak memory 209504 kb
Host smart-fb7db82a-b83b-48a5-8e3c-b91e5b369bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128653853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.1128653853
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.882745049
Short name T450
Test name
Test status
Simulation time 84527020 ps
CPU time 0.78 seconds
Started May 02 12:49:10 PM PDT 24
Finished May 02 12:49:16 PM PDT 24
Peak memory 205572 kb
Host smart-9112b567-994b-4b0f-91f4-94389d01fc3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882745049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.882745049
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.1079456246
Short name T20
Test name
Test status
Simulation time 103716139 ps
CPU time 3.91 seconds
Started May 02 12:49:03 PM PDT 24
Finished May 02 12:49:12 PM PDT 24
Peak memory 208928 kb
Host smart-d342f34c-2c8a-475a-96f2-3f0eeb939511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079456246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.1079456246
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.3699820749
Short name T59
Test name
Test status
Simulation time 50988269 ps
CPU time 2.43 seconds
Started May 02 12:49:16 PM PDT 24
Finished May 02 12:49:22 PM PDT 24
Peak memory 208348 kb
Host smart-defb214a-cb4e-4673-b0ec-19a7fe7e71d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699820749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.3699820749
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.894572680
Short name T90
Test name
Test status
Simulation time 342731739 ps
CPU time 10.01 seconds
Started May 02 12:49:03 PM PDT 24
Finished May 02 12:49:18 PM PDT 24
Peak memory 219116 kb
Host smart-0b69d5fd-095a-4a96-a1e2-8f0a97a6e695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894572680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.894572680
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.34904637
Short name T103
Test name
Test status
Simulation time 656899844 ps
CPU time 7.59 seconds
Started May 02 12:49:15 PM PDT 24
Finished May 02 12:49:27 PM PDT 24
Peak memory 218220 kb
Host smart-d381b585-b99a-4a61-ae2d-a06de0013d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34904637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.34904637
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.2903259902
Short name T543
Test name
Test status
Simulation time 88144732 ps
CPU time 4.26 seconds
Started May 02 12:49:20 PM PDT 24
Finished May 02 12:49:27 PM PDT 24
Peak memory 206828 kb
Host smart-7ee50cc9-06dc-47b0-94e2-b5effb00df9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903259902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.2903259902
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.836041363
Short name T403
Test name
Test status
Simulation time 3919261441 ps
CPU time 49.5 seconds
Started May 02 12:49:01 PM PDT 24
Finished May 02 12:49:55 PM PDT 24
Peak memory 207908 kb
Host smart-2adbfca2-9531-421a-b86e-54729121df61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836041363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.836041363
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.2862566276
Short name T657
Test name
Test status
Simulation time 509862145 ps
CPU time 5.8 seconds
Started May 02 12:49:10 PM PDT 24
Finished May 02 12:49:22 PM PDT 24
Peak memory 207792 kb
Host smart-762a9122-cba0-49a5-bd83-02d50b403aed
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862566276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.2862566276
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.1260967808
Short name T325
Test name
Test status
Simulation time 52001096 ps
CPU time 2.29 seconds
Started May 02 12:48:56 PM PDT 24
Finished May 02 12:49:08 PM PDT 24
Peak memory 207932 kb
Host smart-4262abb7-0647-45c4-a73a-33167407e7d9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260967808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.1260967808
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.329872661
Short name T642
Test name
Test status
Simulation time 215064481 ps
CPU time 2.9 seconds
Started May 02 12:49:03 PM PDT 24
Finished May 02 12:49:11 PM PDT 24
Peak memory 206372 kb
Host smart-bd946de3-bf4d-4243-9cac-7601cf27b633
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329872661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.329872661
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.835799414
Short name T480
Test name
Test status
Simulation time 369983740 ps
CPU time 3.05 seconds
Started May 02 12:49:13 PM PDT 24
Finished May 02 12:49:21 PM PDT 24
Peak memory 208052 kb
Host smart-d1bffb7e-4217-4291-b94d-80eb9300f075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835799414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.835799414
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.1262939879
Short name T669
Test name
Test status
Simulation time 867496611 ps
CPU time 8.61 seconds
Started May 02 12:49:02 PM PDT 24
Finished May 02 12:49:16 PM PDT 24
Peak memory 206360 kb
Host smart-7fb14b8c-1cf3-482b-a2d3-f6de563bd26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262939879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.1262939879
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.2645384222
Short name T865
Test name
Test status
Simulation time 529124363 ps
CPU time 9.32 seconds
Started May 02 12:49:13 PM PDT 24
Finished May 02 12:49:27 PM PDT 24
Peak memory 222236 kb
Host smart-62260c06-175a-4165-a955-02642c92b32a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645384222 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.2645384222
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.3326552050
Short name T501
Test name
Test status
Simulation time 60978253 ps
CPU time 1.76 seconds
Started May 02 12:49:02 PM PDT 24
Finished May 02 12:49:08 PM PDT 24
Peak memory 209368 kb
Host smart-2acb99d4-abc5-4fdd-b79f-a414e301701f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326552050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.3326552050
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.2511164534
Short name T442
Test name
Test status
Simulation time 12770197 ps
CPU time 0.76 seconds
Started May 02 12:49:09 PM PDT 24
Finished May 02 12:49:16 PM PDT 24
Peak memory 205588 kb
Host smart-a41252d7-c299-4b94-81ff-716713ea71f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511164534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.2511164534
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.3445541950
Short name T875
Test name
Test status
Simulation time 284899573 ps
CPU time 2.22 seconds
Started May 02 12:49:29 PM PDT 24
Finished May 02 12:49:35 PM PDT 24
Peak memory 222312 kb
Host smart-71bd760f-723b-40b5-b075-73291666af40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445541950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.3445541950
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.1994109614
Short name T102
Test name
Test status
Simulation time 93187678 ps
CPU time 3.6 seconds
Started May 02 12:49:23 PM PDT 24
Finished May 02 12:49:29 PM PDT 24
Peak memory 209144 kb
Host smart-38d00fe2-2404-44fe-b8bc-703b4a21436d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994109614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.1994109614
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.1206657570
Short name T824
Test name
Test status
Simulation time 168087328 ps
CPU time 7.1 seconds
Started May 02 12:49:06 PM PDT 24
Finished May 02 12:49:18 PM PDT 24
Peak memory 214604 kb
Host smart-cdcc1233-76e9-4edb-bfbb-ecc537e190e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206657570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.1206657570
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.1148884006
Short name T94
Test name
Test status
Simulation time 302130757 ps
CPU time 13.13 seconds
Started May 02 12:49:28 PM PDT 24
Finished May 02 12:49:44 PM PDT 24
Peak memory 209500 kb
Host smart-df6d2783-e5d1-4664-89c7-e2d220381442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148884006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.1148884006
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.3971690264
Short name T215
Test name
Test status
Simulation time 69942696 ps
CPU time 3.17 seconds
Started May 02 12:49:22 PM PDT 24
Finished May 02 12:49:29 PM PDT 24
Peak memory 213936 kb
Host smart-563049c0-a5aa-4db7-abeb-34b38afc5a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971690264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.3971690264
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.4007857255
Short name T238
Test name
Test status
Simulation time 403700447 ps
CPU time 4.47 seconds
Started May 02 12:49:13 PM PDT 24
Finished May 02 12:49:22 PM PDT 24
Peak memory 208576 kb
Host smart-dfc04d0b-7d3a-4846-b6b2-bdf7d6ae9c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007857255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.4007857255
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.2433456024
Short name T491
Test name
Test status
Simulation time 134629545 ps
CPU time 3.35 seconds
Started May 02 12:49:15 PM PDT 24
Finished May 02 12:49:22 PM PDT 24
Peak memory 208412 kb
Host smart-755c12f2-99f9-4813-af33-e194e6f8c04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433456024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.2433456024
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.4057251327
Short name T349
Test name
Test status
Simulation time 95998369 ps
CPU time 3.76 seconds
Started May 02 12:49:08 PM PDT 24
Finished May 02 12:49:17 PM PDT 24
Peak memory 207628 kb
Host smart-f07dc472-77bc-4236-85f4-b5e4ac68c18f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057251327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.4057251327
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.3427519702
Short name T572
Test name
Test status
Simulation time 171306259 ps
CPU time 3.55 seconds
Started May 02 12:49:00 PM PDT 24
Finished May 02 12:49:08 PM PDT 24
Peak memory 208248 kb
Host smart-44ca7511-2408-4ea4-946a-7bc4639ef54f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427519702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.3427519702
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.1950509334
Short name T680
Test name
Test status
Simulation time 1060038896 ps
CPU time 7.9 seconds
Started May 02 12:49:04 PM PDT 24
Finished May 02 12:49:17 PM PDT 24
Peak memory 208388 kb
Host smart-2c0b10f1-7d59-46cd-9473-54baea3f6b1b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950509334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.1950509334
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.1034200404
Short name T323
Test name
Test status
Simulation time 48788986 ps
CPU time 3.03 seconds
Started May 02 12:49:02 PM PDT 24
Finished May 02 12:49:10 PM PDT 24
Peak memory 218016 kb
Host smart-85e91662-5b12-4e20-b51e-37f56162f47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034200404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.1034200404
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.597212488
Short name T850
Test name
Test status
Simulation time 300605363 ps
CPU time 4.79 seconds
Started May 02 12:49:14 PM PDT 24
Finished May 02 12:49:24 PM PDT 24
Peak memory 206200 kb
Host smart-97bd049e-1caa-46d9-a201-75af7876d5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597212488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.597212488
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.1655514646
Short name T737
Test name
Test status
Simulation time 1568702964 ps
CPU time 56.09 seconds
Started May 02 12:49:31 PM PDT 24
Finished May 02 12:50:32 PM PDT 24
Peak memory 222192 kb
Host smart-c5a12898-061a-46ca-9cdd-ac6f09865f09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655514646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.1655514646
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.4198525997
Short name T545
Test name
Test status
Simulation time 604735604 ps
CPU time 5.01 seconds
Started May 02 12:49:17 PM PDT 24
Finished May 02 12:49:26 PM PDT 24
Peak memory 206776 kb
Host smart-12c6310a-6cc1-4ad5-9cd2-d31a0d9a8e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198525997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.4198525997
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.736226160
Short name T636
Test name
Test status
Simulation time 95965810 ps
CPU time 1.95 seconds
Started May 02 12:49:15 PM PDT 24
Finished May 02 12:49:21 PM PDT 24
Peak memory 209496 kb
Host smart-f4b67e73-4256-4235-b1bd-33ea1c0692c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736226160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.736226160
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.1240706882
Short name T437
Test name
Test status
Simulation time 49706682 ps
CPU time 0.89 seconds
Started May 02 12:49:02 PM PDT 24
Finished May 02 12:49:07 PM PDT 24
Peak memory 205648 kb
Host smart-5c103a9e-5141-4ba2-a743-2952f5598526
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240706882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.1240706882
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.1973120075
Short name T410
Test name
Test status
Simulation time 687294635 ps
CPU time 36.93 seconds
Started May 02 12:49:08 PM PDT 24
Finished May 02 12:49:50 PM PDT 24
Peak memory 215560 kb
Host smart-cd1554e3-1c7a-49ac-9dd8-6edd0b66df7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1973120075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.1973120075
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.1319996749
Short name T214
Test name
Test status
Simulation time 237607189 ps
CPU time 5.09 seconds
Started May 02 12:49:18 PM PDT 24
Finished May 02 12:49:26 PM PDT 24
Peak memory 209324 kb
Host smart-8bae13f2-6fff-4f37-b3e0-f2c576ec9cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319996749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.1319996749
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.625662386
Short name T357
Test name
Test status
Simulation time 847691371 ps
CPU time 3.16 seconds
Started May 02 12:49:18 PM PDT 24
Finished May 02 12:49:24 PM PDT 24
Peak memory 217840 kb
Host smart-108907e8-74fa-4c7f-bfe4-573d5da3751c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625662386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.625662386
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.4200214713
Short name T754
Test name
Test status
Simulation time 435196633 ps
CPU time 5.55 seconds
Started May 02 12:49:26 PM PDT 24
Finished May 02 12:49:34 PM PDT 24
Peak memory 222228 kb
Host smart-57bce9de-571e-4a55-9139-94448983edd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200214713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.4200214713
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.313489167
Short name T288
Test name
Test status
Simulation time 1672938765 ps
CPU time 11.83 seconds
Started May 02 12:49:11 PM PDT 24
Finished May 02 12:49:28 PM PDT 24
Peak memory 214020 kb
Host smart-495b4e09-8d66-4f3f-9749-1948121964a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313489167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.313489167
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.889737928
Short name T56
Test name
Test status
Simulation time 298832186 ps
CPU time 4.06 seconds
Started May 02 12:49:19 PM PDT 24
Finished May 02 12:49:26 PM PDT 24
Peak memory 220160 kb
Host smart-5e6213fc-624d-4991-801d-d6e10d5ded28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889737928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.889737928
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.3197482308
Short name T376
Test name
Test status
Simulation time 168186207 ps
CPU time 4 seconds
Started May 02 12:49:03 PM PDT 24
Finished May 02 12:49:12 PM PDT 24
Peak memory 207016 kb
Host smart-afc04be9-c74b-493f-a352-761100f102f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197482308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.3197482308
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.1812029366
Short name T231
Test name
Test status
Simulation time 108448031 ps
CPU time 2.2 seconds
Started May 02 12:49:19 PM PDT 24
Finished May 02 12:49:24 PM PDT 24
Peak memory 206444 kb
Host smart-5e8ddaf9-1bd0-46c0-b8dd-96e37ec02c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812029366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.1812029366
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.4090566233
Short name T859
Test name
Test status
Simulation time 497872124 ps
CPU time 12.59 seconds
Started May 02 12:49:05 PM PDT 24
Finished May 02 12:49:23 PM PDT 24
Peak memory 207624 kb
Host smart-388786d7-ffc7-46ab-8534-4cc1541457d3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090566233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.4090566233
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.442474843
Short name T725
Test name
Test status
Simulation time 66576253 ps
CPU time 3.46 seconds
Started May 02 12:49:11 PM PDT 24
Finished May 02 12:49:20 PM PDT 24
Peak memory 208208 kb
Host smart-e79941e3-e41a-4285-8549-744f2cf806a0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442474843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.442474843
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.1796081844
Short name T446
Test name
Test status
Simulation time 163112976 ps
CPU time 4.02 seconds
Started May 02 12:49:06 PM PDT 24
Finished May 02 12:49:16 PM PDT 24
Peak memory 206404 kb
Host smart-fc16215a-e11b-4e08-92b7-f5902d6c4303
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796081844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.1796081844
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.2835990023
Short name T439
Test name
Test status
Simulation time 176251772 ps
CPU time 2.24 seconds
Started May 02 12:49:20 PM PDT 24
Finished May 02 12:49:25 PM PDT 24
Peak memory 207172 kb
Host smart-514af3ca-70d9-4157-bae8-372c242b5d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835990023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.2835990023
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.10338240
Short name T903
Test name
Test status
Simulation time 107143379 ps
CPU time 2.51 seconds
Started May 02 12:49:01 PM PDT 24
Finished May 02 12:49:08 PM PDT 24
Peak memory 207840 kb
Host smart-faafcc88-8be9-47d7-86f3-c6d1370ccab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10338240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.10338240
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.3755342220
Short name T226
Test name
Test status
Simulation time 1455799191 ps
CPU time 29.84 seconds
Started May 02 12:49:30 PM PDT 24
Finished May 02 12:50:04 PM PDT 24
Peak memory 216284 kb
Host smart-4d88c862-ba9e-495b-bd00-49e5c0566deb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755342220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.3755342220
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.1818477266
Short name T641
Test name
Test status
Simulation time 228076341 ps
CPU time 5.38 seconds
Started May 02 12:49:07 PM PDT 24
Finished May 02 12:49:18 PM PDT 24
Peak memory 209996 kb
Host smart-59874efd-d2fe-461a-8345-867c32964e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818477266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.1818477266
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.2775969683
Short name T378
Test name
Test status
Simulation time 2232791056 ps
CPU time 13.33 seconds
Started May 02 12:49:02 PM PDT 24
Finished May 02 12:49:20 PM PDT 24
Peak memory 210532 kb
Host smart-1ec56ef4-6f19-4659-8d67-5f80d85e14bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775969683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.2775969683
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.829342406
Short name T426
Test name
Test status
Simulation time 43303651 ps
CPU time 0.87 seconds
Started May 02 12:49:16 PM PDT 24
Finished May 02 12:49:21 PM PDT 24
Peak memory 205480 kb
Host smart-b6670524-236a-4fd3-b3d9-a1ead66c58f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829342406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.829342406
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.4239869474
Short name T819
Test name
Test status
Simulation time 142933537 ps
CPU time 3.43 seconds
Started May 02 12:49:10 PM PDT 24
Finished May 02 12:49:19 PM PDT 24
Peak memory 207632 kb
Host smart-e21210e4-b433-4e89-bf16-30279579df0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239869474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.4239869474
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.3731027055
Short name T784
Test name
Test status
Simulation time 1456039492 ps
CPU time 33.02 seconds
Started May 02 12:49:32 PM PDT 24
Finished May 02 12:50:10 PM PDT 24
Peak memory 222128 kb
Host smart-c3a220b2-a1e0-445d-bd54-de89c87a6419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731027055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.3731027055
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.1704568906
Short name T823
Test name
Test status
Simulation time 3846977971 ps
CPU time 71.44 seconds
Started May 02 12:49:25 PM PDT 24
Finished May 02 12:50:39 PM PDT 24
Peak memory 222204 kb
Host smart-4c155810-3313-412b-b0c1-cd4297746bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704568906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.1704568906
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.3688635031
Short name T667
Test name
Test status
Simulation time 60390739 ps
CPU time 3.52 seconds
Started May 02 12:49:05 PM PDT 24
Finished May 02 12:49:14 PM PDT 24
Peak memory 222172 kb
Host smart-f95cef84-f95f-4dea-a543-7f9eea0bdf2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688635031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.3688635031
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.3853206713
Short name T468
Test name
Test status
Simulation time 871266098 ps
CPU time 7.64 seconds
Started May 02 12:49:07 PM PDT 24
Finished May 02 12:49:22 PM PDT 24
Peak memory 206412 kb
Host smart-d773159f-e4a9-458f-a160-e8db82f87bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853206713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.3853206713
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.2894942442
Short name T829
Test name
Test status
Simulation time 104063313 ps
CPU time 2.71 seconds
Started May 02 12:49:27 PM PDT 24
Finished May 02 12:49:32 PM PDT 24
Peak memory 206324 kb
Host smart-3530a281-a8ca-402e-ac8c-4f54c507ae5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894942442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.2894942442
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.496137530
Short name T3
Test name
Test status
Simulation time 24393833 ps
CPU time 2.03 seconds
Started May 02 12:49:07 PM PDT 24
Finished May 02 12:49:15 PM PDT 24
Peak memory 208052 kb
Host smart-b22ba13d-15f1-4b9c-b737-47601acece7e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496137530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.496137530
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.3507452025
Short name T560
Test name
Test status
Simulation time 354959379 ps
CPU time 3.59 seconds
Started May 02 12:49:05 PM PDT 24
Finished May 02 12:49:14 PM PDT 24
Peak memory 206424 kb
Host smart-49934d47-7108-4667-b929-3e3a8476bff1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507452025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.3507452025
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.1552958731
Short name T830
Test name
Test status
Simulation time 123960261 ps
CPU time 4.64 seconds
Started May 02 12:49:06 PM PDT 24
Finished May 02 12:49:16 PM PDT 24
Peak memory 207552 kb
Host smart-35520016-1b8b-48bf-89c2-b0f081c72372
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552958731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.1552958731
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.751250718
Short name T353
Test name
Test status
Simulation time 77993746 ps
CPU time 3.72 seconds
Started May 02 12:49:08 PM PDT 24
Finished May 02 12:49:17 PM PDT 24
Peak memory 209540 kb
Host smart-cca14d81-71de-4468-9eaa-d023a1335f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751250718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.751250718
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.385587961
Short name T658
Test name
Test status
Simulation time 412654001 ps
CPU time 4.85 seconds
Started May 02 12:49:13 PM PDT 24
Finished May 02 12:49:23 PM PDT 24
Peak memory 206376 kb
Host smart-73b7dc80-6338-453e-ac54-4e3f5c802470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385587961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.385587961
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.1639227353
Short name T518
Test name
Test status
Simulation time 212551721 ps
CPU time 7.61 seconds
Started May 02 12:49:19 PM PDT 24
Finished May 02 12:49:30 PM PDT 24
Peak memory 209760 kb
Host smart-c57717ce-e6b6-461c-b17b-09c150ff2a11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639227353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.1639227353
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.454047038
Short name T874
Test name
Test status
Simulation time 45323527 ps
CPU time 2.96 seconds
Started May 02 12:49:05 PM PDT 24
Finished May 02 12:49:13 PM PDT 24
Peak memory 207136 kb
Host smart-fad2c245-560c-41dd-9c14-bc62f8e343cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454047038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.454047038
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.529215305
Short name T692
Test name
Test status
Simulation time 205305612 ps
CPU time 2.35 seconds
Started May 02 12:49:09 PM PDT 24
Finished May 02 12:49:16 PM PDT 24
Peak memory 209468 kb
Host smart-4c52d358-58cc-4357-b2c0-5d9b9f421cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529215305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.529215305
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.2153868704
Short name T527
Test name
Test status
Simulation time 8238700 ps
CPU time 0.71 seconds
Started May 02 12:49:03 PM PDT 24
Finished May 02 12:49:09 PM PDT 24
Peak memory 205580 kb
Host smart-5c1f3610-cf13-4c54-aa4d-b92f75f31abb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153868704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.2153868704
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.2151955854
Short name T419
Test name
Test status
Simulation time 310439745 ps
CPU time 4.61 seconds
Started May 02 12:49:26 PM PDT 24
Finished May 02 12:49:34 PM PDT 24
Peak memory 214016 kb
Host smart-c8ccae70-2ea8-42a5-b2d6-2e3fef779733
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2151955854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.2151955854
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.264304608
Short name T415
Test name
Test status
Simulation time 195828546 ps
CPU time 5.85 seconds
Started May 02 12:49:06 PM PDT 24
Finished May 02 12:49:17 PM PDT 24
Peak memory 209504 kb
Host smart-134c72ae-2bc0-42b9-9cbe-69c13a39e1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264304608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.264304608
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.1952503120
Short name T764
Test name
Test status
Simulation time 669782539 ps
CPU time 17.74 seconds
Started May 02 12:49:19 PM PDT 24
Finished May 02 12:49:40 PM PDT 24
Peak memory 208528 kb
Host smart-e96839cd-017d-4c32-876b-0a5b29e93a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952503120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.1952503120
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.4139607174
Short name T303
Test name
Test status
Simulation time 412757242 ps
CPU time 7.22 seconds
Started May 02 12:49:15 PM PDT 24
Finished May 02 12:49:31 PM PDT 24
Peak memory 213852 kb
Host smart-8670633e-dad5-4766-be84-b0320da89fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139607174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.4139607174
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.644081150
Short name T210
Test name
Test status
Simulation time 139087456 ps
CPU time 3.68 seconds
Started May 02 12:49:15 PM PDT 24
Finished May 02 12:49:23 PM PDT 24
Peak memory 214072 kb
Host smart-93f49879-fc4b-496d-a2b1-eb879330d276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644081150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.644081150
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.2116954500
Short name T530
Test name
Test status
Simulation time 109026367 ps
CPU time 4.85 seconds
Started May 02 12:49:26 PM PDT 24
Finished May 02 12:49:33 PM PDT 24
Peak memory 209192 kb
Host smart-f0e83523-1741-4410-803e-43560778d0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116954500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.2116954500
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.1130396265
Short name T815
Test name
Test status
Simulation time 176073097 ps
CPU time 4.83 seconds
Started May 02 12:49:03 PM PDT 24
Finished May 02 12:49:12 PM PDT 24
Peak memory 208324 kb
Host smart-8e7f468a-dbf6-436e-a985-797d47df214b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130396265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.1130396265
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.2318633290
Short name T906
Test name
Test status
Simulation time 83879850 ps
CPU time 2.39 seconds
Started May 02 12:49:05 PM PDT 24
Finished May 02 12:49:13 PM PDT 24
Peak memory 206236 kb
Host smart-e1bb44ba-9e8a-4a2f-848d-8453d71f134d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318633290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.2318633290
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.1419612188
Short name T731
Test name
Test status
Simulation time 210317404 ps
CPU time 7.46 seconds
Started May 02 12:49:05 PM PDT 24
Finished May 02 12:49:17 PM PDT 24
Peak memory 207492 kb
Host smart-80bb7b7b-f995-4a73-9d15-503020b205c7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419612188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.1419612188
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.2610656123
Short name T447
Test name
Test status
Simulation time 150954718 ps
CPU time 2.49 seconds
Started May 02 12:49:05 PM PDT 24
Finished May 02 12:49:13 PM PDT 24
Peak memory 206460 kb
Host smart-6c36a753-a903-4fba-9519-6d8bd543725e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610656123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.2610656123
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.196115330
Short name T254
Test name
Test status
Simulation time 4372587649 ps
CPU time 28.45 seconds
Started May 02 12:49:07 PM PDT 24
Finished May 02 12:49:41 PM PDT 24
Peak memory 209064 kb
Host smart-c42f1fab-adbf-45f9-89fb-813a1b187d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196115330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.196115330
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.3510507222
Short name T461
Test name
Test status
Simulation time 129544131 ps
CPU time 2.38 seconds
Started May 02 12:49:25 PM PDT 24
Finished May 02 12:49:30 PM PDT 24
Peak memory 206332 kb
Host smart-a5faa746-c77d-4636-b4ad-7a16cdae0acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510507222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.3510507222
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.2367746844
Short name T175
Test name
Test status
Simulation time 447263436 ps
CPU time 17.02 seconds
Started May 02 12:49:29 PM PDT 24
Finished May 02 12:49:49 PM PDT 24
Peak memory 220704 kb
Host smart-01fe1c8d-3d43-4e4d-a027-dc962320aaa1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367746844 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.2367746844
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.1964474105
Short name T826
Test name
Test status
Simulation time 349378723 ps
CPU time 7.9 seconds
Started May 02 12:49:22 PM PDT 24
Finished May 02 12:49:32 PM PDT 24
Peak memory 218040 kb
Host smart-fe61a63b-5398-4655-8a7e-23ab1cde1a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964474105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.1964474105
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.976345435
Short name T898
Test name
Test status
Simulation time 59616597 ps
CPU time 2.64 seconds
Started May 02 12:49:20 PM PDT 24
Finished May 02 12:49:25 PM PDT 24
Peak memory 209180 kb
Host smart-c3145bd1-09cf-4a02-be55-9e9329775964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976345435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.976345435
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.3665720895
Short name T877
Test name
Test status
Simulation time 27828368 ps
CPU time 0.98 seconds
Started May 02 12:49:34 PM PDT 24
Finished May 02 12:49:41 PM PDT 24
Peak memory 205616 kb
Host smart-72edbbb1-55ed-43d5-881e-5522098c8e8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665720895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.3665720895
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.1489907813
Short name T418
Test name
Test status
Simulation time 47832186 ps
CPU time 2.89 seconds
Started May 02 12:49:22 PM PDT 24
Finished May 02 12:49:27 PM PDT 24
Peak memory 214116 kb
Host smart-6a8344f8-a4e9-4141-9d13-87fce72351d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1489907813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.1489907813
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.2782653201
Short name T77
Test name
Test status
Simulation time 348466952 ps
CPU time 4.24 seconds
Started May 02 12:49:31 PM PDT 24
Finished May 02 12:49:39 PM PDT 24
Peak memory 208456 kb
Host smart-5142ee7c-e6ef-4a17-9082-18a619c2f12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782653201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.2782653201
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.1887608000
Short name T581
Test name
Test status
Simulation time 1229842567 ps
CPU time 9.47 seconds
Started May 02 12:49:07 PM PDT 24
Finished May 02 12:49:22 PM PDT 24
Peak memory 220724 kb
Host smart-5149272e-04d8-4b7c-8516-86afece8ede4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887608000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.1887608000
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.456499028
Short name T283
Test name
Test status
Simulation time 248108071 ps
CPU time 7.97 seconds
Started May 02 12:49:09 PM PDT 24
Finished May 02 12:49:22 PM PDT 24
Peak memory 222052 kb
Host smart-e09504ac-5bb5-48b8-a063-ae18f6367ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456499028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.456499028
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.1956762482
Short name T219
Test name
Test status
Simulation time 37271177 ps
CPU time 2.62 seconds
Started May 02 12:49:17 PM PDT 24
Finished May 02 12:49:23 PM PDT 24
Peak memory 207356 kb
Host smart-46a328ce-dc02-4572-a401-b0ee19e22bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956762482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.1956762482
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.786834587
Short name T759
Test name
Test status
Simulation time 90049660 ps
CPU time 4.23 seconds
Started May 02 12:49:06 PM PDT 24
Finished May 02 12:49:16 PM PDT 24
Peak memory 207644 kb
Host smart-70baf0a0-f7ad-413a-9bd9-2ecb9b6e9853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786834587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.786834587
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.3717546781
Short name T191
Test name
Test status
Simulation time 67697188 ps
CPU time 3.28 seconds
Started May 02 12:49:15 PM PDT 24
Finished May 02 12:49:22 PM PDT 24
Peak memory 206924 kb
Host smart-f1673bad-bc04-483e-98a8-2a670f020aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717546781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.3717546781
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.3214912921
Short name T541
Test name
Test status
Simulation time 76880538 ps
CPU time 1.94 seconds
Started May 02 12:49:08 PM PDT 24
Finished May 02 12:49:16 PM PDT 24
Peak memory 207260 kb
Host smart-c5cf147d-38d6-47c2-8790-6a284fbe0247
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214912921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.3214912921
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.1966809744
Short name T536
Test name
Test status
Simulation time 21363373 ps
CPU time 1.85 seconds
Started May 02 12:49:23 PM PDT 24
Finished May 02 12:49:28 PM PDT 24
Peak memory 206496 kb
Host smart-9128688d-1bb6-4804-bc76-1c4907fd7bcc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966809744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.1966809744
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.1138969139
Short name T715
Test name
Test status
Simulation time 8934160715 ps
CPU time 51.53 seconds
Started May 02 12:49:25 PM PDT 24
Finished May 02 12:50:19 PM PDT 24
Peak memory 208176 kb
Host smart-f0e02d0f-560f-4f33-8e7e-7ba79aeb9096
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138969139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.1138969139
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.1485425286
Short name T124
Test name
Test status
Simulation time 350857429 ps
CPU time 3.56 seconds
Started May 02 12:49:27 PM PDT 24
Finished May 02 12:49:33 PM PDT 24
Peak memory 213928 kb
Host smart-1000c9af-fb50-4484-bb35-9615e8ea0d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485425286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.1485425286
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.171144752
Short name T905
Test name
Test status
Simulation time 51837350 ps
CPU time 2.6 seconds
Started May 02 12:49:13 PM PDT 24
Finished May 02 12:49:20 PM PDT 24
Peak memory 207580 kb
Host smart-d1f31dac-01cf-43eb-9337-7dc45e464619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171144752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.171144752
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.1260773828
Short name T528
Test name
Test status
Simulation time 1084947688 ps
CPU time 5.9 seconds
Started May 02 12:49:30 PM PDT 24
Finished May 02 12:49:41 PM PDT 24
Peak memory 214632 kb
Host smart-17a118a0-9888-422b-a506-44aa24f2f6e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260773828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.1260773828
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.1890633308
Short name T739
Test name
Test status
Simulation time 110946828 ps
CPU time 7.31 seconds
Started May 02 12:49:10 PM PDT 24
Finished May 02 12:49:23 PM PDT 24
Peak memory 222224 kb
Host smart-51ac3bf8-facc-401b-9a23-9c42bc276917
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890633308 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.1890633308
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.2387433316
Short name T393
Test name
Test status
Simulation time 66305395 ps
CPU time 2.6 seconds
Started May 02 12:49:06 PM PDT 24
Finished May 02 12:49:14 PM PDT 24
Peak memory 207888 kb
Host smart-1621ed0f-3394-43f1-8527-8a86aaff5d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387433316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.2387433316
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.3919760971
Short name T650
Test name
Test status
Simulation time 152211243 ps
CPU time 2.93 seconds
Started May 02 12:49:06 PM PDT 24
Finished May 02 12:49:14 PM PDT 24
Peak memory 209448 kb
Host smart-5231f2a1-40ba-46b3-a18d-8adffdfda9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919760971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.3919760971
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.4111392803
Short name T428
Test name
Test status
Simulation time 15172640 ps
CPU time 1 seconds
Started May 02 12:49:34 PM PDT 24
Finished May 02 12:49:41 PM PDT 24
Peak memory 205792 kb
Host smart-87db1d61-d9df-4b93-aeab-2d73c6065db8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111392803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.4111392803
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.2697944462
Short name T407
Test name
Test status
Simulation time 168338260 ps
CPU time 2.5 seconds
Started May 02 12:49:17 PM PDT 24
Finished May 02 12:49:23 PM PDT 24
Peak memory 214108 kb
Host smart-7f15a01f-5fa5-4b09-88e9-1c6784fb9960
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2697944462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.2697944462
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.93304461
Short name T856
Test name
Test status
Simulation time 908395204 ps
CPU time 6.54 seconds
Started May 02 12:49:15 PM PDT 24
Finished May 02 12:49:26 PM PDT 24
Peak memory 220016 kb
Host smart-9e156684-4098-49ba-9b77-17bcd85ccc7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93304461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.93304461
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.1106528311
Short name T72
Test name
Test status
Simulation time 25053258 ps
CPU time 1.89 seconds
Started May 02 12:49:11 PM PDT 24
Finished May 02 12:49:18 PM PDT 24
Peak memory 207856 kb
Host smart-9e1fa877-0e78-4c0a-a0c7-557037cb6e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106528311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.1106528311
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.4013755120
Short name T269
Test name
Test status
Simulation time 96615287 ps
CPU time 4.1 seconds
Started May 02 12:49:10 PM PDT 24
Finished May 02 12:49:19 PM PDT 24
Peak memory 209272 kb
Host smart-ec9b7fde-b92e-406e-b896-0b6ac4e4562e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013755120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.4013755120
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.2326941388
Short name T720
Test name
Test status
Simulation time 103130395 ps
CPU time 2.93 seconds
Started May 02 12:49:15 PM PDT 24
Finished May 02 12:49:22 PM PDT 24
Peak memory 206020 kb
Host smart-aba398c6-26fb-4cc6-b8ac-30655acad9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326941388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.2326941388
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.1296170493
Short name T299
Test name
Test status
Simulation time 49424152 ps
CPU time 3.21 seconds
Started May 02 12:49:19 PM PDT 24
Finished May 02 12:49:25 PM PDT 24
Peak memory 207212 kb
Host smart-eb6fb07d-1628-4b5c-b582-548fdc85521b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296170493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.1296170493
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.3419720547
Short name T857
Test name
Test status
Simulation time 164319285 ps
CPU time 6.64 seconds
Started May 02 12:49:07 PM PDT 24
Finished May 02 12:49:19 PM PDT 24
Peak memory 208448 kb
Host smart-97888f1e-10c5-4830-93a6-06882743a8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419720547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.3419720547
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.2989915858
Short name T822
Test name
Test status
Simulation time 173084129 ps
CPU time 2.88 seconds
Started May 02 12:49:18 PM PDT 24
Finished May 02 12:49:24 PM PDT 24
Peak memory 206464 kb
Host smart-d3708fd6-2c53-4d2d-85d7-ba5e91add21e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989915858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.2989915858
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.2174994962
Short name T451
Test name
Test status
Simulation time 40969605 ps
CPU time 2.45 seconds
Started May 02 12:49:34 PM PDT 24
Finished May 02 12:49:42 PM PDT 24
Peak memory 206360 kb
Host smart-ec90d826-8b57-4c03-af4b-77777b094e5d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174994962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.2174994962
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.4089175321
Short name T395
Test name
Test status
Simulation time 259620460 ps
CPU time 3.32 seconds
Started May 02 12:49:34 PM PDT 24
Finished May 02 12:49:43 PM PDT 24
Peak memory 206376 kb
Host smart-50407a6a-4aa9-4ffc-b6d9-5ca500f51a0c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089175321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.4089175321
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.1126001450
Short name T811
Test name
Test status
Simulation time 150969833 ps
CPU time 3.35 seconds
Started May 02 12:49:24 PM PDT 24
Finished May 02 12:49:30 PM PDT 24
Peak memory 209412 kb
Host smart-d14a03b6-20dd-4286-ae1b-a42e22832658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126001450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.1126001450
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.3549372116
Short name T194
Test name
Test status
Simulation time 328982626 ps
CPU time 2.62 seconds
Started May 02 12:49:27 PM PDT 24
Finished May 02 12:49:32 PM PDT 24
Peak memory 206168 kb
Host smart-5971289e-9b1b-4047-9f95-5941e93e98fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549372116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.3549372116
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.1565365368
Short name T358
Test name
Test status
Simulation time 3482723835 ps
CPU time 24.62 seconds
Started May 02 12:49:48 PM PDT 24
Finished May 02 12:50:17 PM PDT 24
Peak memory 222376 kb
Host smart-7d4db40f-0618-42a8-bffa-929dd6949934
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565365368 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.1565365368
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.1051172795
Short name T297
Test name
Test status
Simulation time 296451788 ps
CPU time 3.82 seconds
Started May 02 12:49:06 PM PDT 24
Finished May 02 12:49:18 PM PDT 24
Peak memory 206540 kb
Host smart-d43e114e-1c2b-4bee-b9ce-e9b27ad2205a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051172795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.1051172795
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.3177253135
Short name T150
Test name
Test status
Simulation time 71555730 ps
CPU time 2.85 seconds
Started May 02 12:49:17 PM PDT 24
Finished May 02 12:49:23 PM PDT 24
Peak memory 209828 kb
Host smart-692038b5-a82d-44ae-a8b6-546eef3a5f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177253135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.3177253135
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.368602665
Short name T852
Test name
Test status
Simulation time 43033699 ps
CPU time 0.88 seconds
Started May 02 12:47:42 PM PDT 24
Finished May 02 12:47:45 PM PDT 24
Peak memory 205620 kb
Host smart-73d9e0d1-c32d-4b98-bc7f-8974ecc85d2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368602665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.368602665
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.3078408084
Short name T139
Test name
Test status
Simulation time 58454138 ps
CPU time 4.26 seconds
Started May 02 12:47:39 PM PDT 24
Finished May 02 12:47:46 PM PDT 24
Peak memory 215024 kb
Host smart-1bf9637c-aaab-45f1-bd6e-1fd959e59835
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3078408084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.3078408084
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.897927326
Short name T10
Test name
Test status
Simulation time 902106670 ps
CPU time 2.63 seconds
Started May 02 12:47:49 PM PDT 24
Finished May 02 12:47:56 PM PDT 24
Peak memory 216304 kb
Host smart-fa2a54c0-86fd-415e-8bb0-339c2ee33d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897927326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.897927326
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.1202185559
Short name T75
Test name
Test status
Simulation time 30384230 ps
CPU time 1.66 seconds
Started May 02 12:47:41 PM PDT 24
Finished May 02 12:47:45 PM PDT 24
Peak memory 207792 kb
Host smart-7a3d2e7f-272b-4485-b78b-c18a62c0b7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202185559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.1202185559
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.747464586
Short name T749
Test name
Test status
Simulation time 243270715 ps
CPU time 3.31 seconds
Started May 02 12:47:36 PM PDT 24
Finished May 02 12:47:40 PM PDT 24
Peak memory 213976 kb
Host smart-d6882eb9-3d42-42ca-9031-249eb6528665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747464586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.747464586
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.1117157286
Short name T237
Test name
Test status
Simulation time 621651661 ps
CPU time 5.64 seconds
Started May 02 12:47:40 PM PDT 24
Finished May 02 12:47:49 PM PDT 24
Peak memory 222120 kb
Host smart-5c15546d-bac6-4884-a371-13846631ea54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117157286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.1117157286
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.4110768985
Short name T242
Test name
Test status
Simulation time 266034719 ps
CPU time 5.36 seconds
Started May 02 12:47:35 PM PDT 24
Finished May 02 12:47:42 PM PDT 24
Peak memory 214004 kb
Host smart-dead9065-df7c-429e-bd0b-a3df185c3143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110768985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.4110768985
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.738526545
Short name T757
Test name
Test status
Simulation time 1326335732 ps
CPU time 7.49 seconds
Started May 02 12:47:27 PM PDT 24
Finished May 02 12:47:37 PM PDT 24
Peak memory 217868 kb
Host smart-05e4a351-c3f5-44f4-9553-09836c4e434b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738526545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.738526545
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.2859701117
Short name T397
Test name
Test status
Simulation time 1377003560 ps
CPU time 41.29 seconds
Started May 02 12:47:42 PM PDT 24
Finished May 02 12:48:26 PM PDT 24
Peak memory 208556 kb
Host smart-8ea7ffc9-de36-41d8-bbb2-62ee5d6ac32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859701117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.2859701117
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.2535446410
Short name T326
Test name
Test status
Simulation time 107188304 ps
CPU time 2.14 seconds
Started May 02 12:47:26 PM PDT 24
Finished May 02 12:47:31 PM PDT 24
Peak memory 208272 kb
Host smart-3fec4d5e-1043-443a-992d-58ec0b7c3772
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535446410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.2535446410
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.2605641831
Short name T580
Test name
Test status
Simulation time 923251821 ps
CPU time 6.22 seconds
Started May 02 12:47:42 PM PDT 24
Finished May 02 12:47:51 PM PDT 24
Peak memory 207632 kb
Host smart-105e3b9d-fc63-4780-bc13-5bddaa181572
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605641831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.2605641831
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.3324472898
Short name T832
Test name
Test status
Simulation time 204897956 ps
CPU time 6.17 seconds
Started May 02 12:47:42 PM PDT 24
Finished May 02 12:47:51 PM PDT 24
Peak memory 208060 kb
Host smart-82c6be2a-e200-4edd-821d-8791d0579837
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324472898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.3324472898
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.1591534857
Short name T330
Test name
Test status
Simulation time 114255121 ps
CPU time 4.91 seconds
Started May 02 12:47:42 PM PDT 24
Finished May 02 12:47:50 PM PDT 24
Peak memory 209348 kb
Host smart-c39c8990-96fa-458b-9c89-f33323bf3b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591534857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.1591534857
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.3247301023
Short name T565
Test name
Test status
Simulation time 234886763 ps
CPU time 3.98 seconds
Started May 02 12:47:27 PM PDT 24
Finished May 02 12:47:34 PM PDT 24
Peak memory 206260 kb
Host smart-2fb08b3e-dfd0-4fc6-94a3-f3e3ec32775e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247301023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.3247301023
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.2882023071
Short name T809
Test name
Test status
Simulation time 173390050 ps
CPU time 7.24 seconds
Started May 02 12:47:27 PM PDT 24
Finished May 02 12:47:37 PM PDT 24
Peak memory 215044 kb
Host smart-c747af47-d9e4-42c4-86f6-c5ee4eca0622
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882023071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.2882023071
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.1283203752
Short name T627
Test name
Test status
Simulation time 422108017 ps
CPU time 18.4 seconds
Started May 02 12:47:25 PM PDT 24
Finished May 02 12:47:46 PM PDT 24
Peak memory 220288 kb
Host smart-e9c0fb4a-1e33-4bd3-8058-dd2ad9b9af44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283203752 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.1283203752
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.3693469918
Short name T370
Test name
Test status
Simulation time 372594998 ps
CPU time 8.73 seconds
Started May 02 12:47:27 PM PDT 24
Finished May 02 12:47:38 PM PDT 24
Peak memory 217908 kb
Host smart-dba84fe7-2a41-4a5b-8acb-5e569bce1b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693469918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.3693469918
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.2229425395
Short name T787
Test name
Test status
Simulation time 40689357 ps
CPU time 2.38 seconds
Started May 02 12:47:26 PM PDT 24
Finished May 02 12:47:31 PM PDT 24
Peak memory 209384 kb
Host smart-16f5dbd7-a2b8-4b90-9ea6-423e8f5b7d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229425395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.2229425395
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.1644212629
Short name T84
Test name
Test status
Simulation time 21844489 ps
CPU time 0.97 seconds
Started May 02 12:47:56 PM PDT 24
Finished May 02 12:48:01 PM PDT 24
Peak memory 205748 kb
Host smart-76506c85-4e93-410f-9cf6-32e2b7ae9de3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644212629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.1644212629
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.2062277708
Short name T523
Test name
Test status
Simulation time 168568380 ps
CPU time 2.35 seconds
Started May 02 12:47:37 PM PDT 24
Finished May 02 12:47:42 PM PDT 24
Peak memory 208804 kb
Host smart-a0f873a2-73fb-4cef-abc2-cb01e1258929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062277708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.2062277708
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.2244415783
Short name T268
Test name
Test status
Simulation time 3291005678 ps
CPU time 9.06 seconds
Started May 02 12:47:43 PM PDT 24
Finished May 02 12:47:55 PM PDT 24
Peak memory 214044 kb
Host smart-d65ee98e-086c-461e-8965-cede843f61a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244415783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.2244415783
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.936816029
Short name T444
Test name
Test status
Simulation time 85082008 ps
CPU time 4.06 seconds
Started May 02 12:47:28 PM PDT 24
Finished May 02 12:47:34 PM PDT 24
Peak memory 218524 kb
Host smart-9297efc6-9bcc-4fe8-b475-bd986fd28f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936816029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.936816029
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.212845634
Short name T571
Test name
Test status
Simulation time 182021518 ps
CPU time 4.25 seconds
Started May 02 12:47:31 PM PDT 24
Finished May 02 12:47:37 PM PDT 24
Peak memory 209004 kb
Host smart-4c221842-0a65-4569-ae09-3ecb3beab7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212845634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.212845634
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.2269990472
Short name T828
Test name
Test status
Simulation time 3921162931 ps
CPU time 63.14 seconds
Started May 02 12:47:22 PM PDT 24
Finished May 02 12:48:29 PM PDT 24
Peak memory 207604 kb
Host smart-527d7341-759e-4d70-9c64-b2cfa76a2eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269990472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.2269990472
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.230438253
Short name T644
Test name
Test status
Simulation time 993966959 ps
CPU time 32.07 seconds
Started May 02 12:47:32 PM PDT 24
Finished May 02 12:48:06 PM PDT 24
Peak memory 208504 kb
Host smart-3e1d9387-6c2c-468c-a9ff-ed25d4952d6a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230438253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.230438253
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.2144507879
Short name T529
Test name
Test status
Simulation time 240452579 ps
CPU time 3.22 seconds
Started May 02 12:47:24 PM PDT 24
Finished May 02 12:47:30 PM PDT 24
Peak memory 206276 kb
Host smart-9fd03841-0d22-4b75-9b4d-3e1f8466bf41
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144507879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.2144507879
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.1192991214
Short name T533
Test name
Test status
Simulation time 330210041 ps
CPU time 3.02 seconds
Started May 02 12:47:21 PM PDT 24
Finished May 02 12:47:28 PM PDT 24
Peak memory 206460 kb
Host smart-32d3ac96-4edb-42a6-be06-01f766240e4e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192991214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.1192991214
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.2255592283
Short name T586
Test name
Test status
Simulation time 330976489 ps
CPU time 5.11 seconds
Started May 02 12:47:27 PM PDT 24
Finished May 02 12:47:35 PM PDT 24
Peak memory 213924 kb
Host smart-a0d4b420-b910-4739-bd40-b2d3cb602172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255592283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.2255592283
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.3698944413
Short name T655
Test name
Test status
Simulation time 327509569 ps
CPU time 3.54 seconds
Started May 02 12:47:21 PM PDT 24
Finished May 02 12:47:28 PM PDT 24
Peak memory 207896 kb
Host smart-7c6bd501-4fb1-43c8-aa95-2ea8e973254e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698944413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.3698944413
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.592009171
Short name T634
Test name
Test status
Simulation time 1600672963 ps
CPU time 29.59 seconds
Started May 02 12:47:26 PM PDT 24
Finished May 02 12:47:59 PM PDT 24
Peak memory 215284 kb
Host smart-c66f7775-3682-47f4-a956-3f960234fb4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592009171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.592009171
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.3548273704
Short name T314
Test name
Test status
Simulation time 507427253 ps
CPU time 16.49 seconds
Started May 02 12:47:35 PM PDT 24
Finished May 02 12:47:53 PM PDT 24
Peak memory 220300 kb
Host smart-48478b33-a49c-469a-8b5a-5f74d9915ee3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548273704 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.3548273704
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.2815993156
Short name T628
Test name
Test status
Simulation time 226099504 ps
CPU time 6.52 seconds
Started May 02 12:47:45 PM PDT 24
Finished May 02 12:47:55 PM PDT 24
Peak memory 213992 kb
Host smart-b67f060e-3e9a-457a-95a1-acdcaf1087e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815993156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.2815993156
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.840929274
Short name T379
Test name
Test status
Simulation time 89788114 ps
CPU time 2.41 seconds
Started May 02 12:47:36 PM PDT 24
Finished May 02 12:47:40 PM PDT 24
Peak memory 209676 kb
Host smart-689f4011-18e1-4d3f-8add-79025f0efead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840929274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.840929274
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.909841929
Short name T701
Test name
Test status
Simulation time 12197608 ps
CPU time 0.84 seconds
Started May 02 12:47:30 PM PDT 24
Finished May 02 12:47:33 PM PDT 24
Peak memory 205604 kb
Host smart-96d25f82-f2a6-408b-9d67-dd3b5084fb09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909841929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.909841929
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.2030642894
Short name T230
Test name
Test status
Simulation time 55889197 ps
CPU time 3.98 seconds
Started May 02 12:47:52 PM PDT 24
Finished May 02 12:48:00 PM PDT 24
Peak memory 214200 kb
Host smart-cadb5660-5f18-4066-9747-eb572ec34db7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2030642894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.2030642894
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.4260976128
Short name T35
Test name
Test status
Simulation time 45724975 ps
CPU time 2.43 seconds
Started May 02 12:47:45 PM PDT 24
Finished May 02 12:47:51 PM PDT 24
Peak memory 208900 kb
Host smart-b837d748-8535-4166-b48d-7f11c5036e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260976128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.4260976128
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.3347857048
Short name T724
Test name
Test status
Simulation time 34264053 ps
CPU time 1.59 seconds
Started May 02 12:47:51 PM PDT 24
Finished May 02 12:47:57 PM PDT 24
Peak memory 208072 kb
Host smart-18857f8b-9c5e-4131-9ebc-2262c2ef1283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347857048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.3347857048
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.3543064080
Short name T88
Test name
Test status
Simulation time 683571080 ps
CPU time 7.51 seconds
Started May 02 12:47:35 PM PDT 24
Finished May 02 12:47:44 PM PDT 24
Peak memory 213908 kb
Host smart-4c147e03-4bac-4bd9-b57d-b92be8b9daa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543064080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.3543064080
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.2152485807
Short name T197
Test name
Test status
Simulation time 1444084109 ps
CPU time 45.48 seconds
Started May 02 12:47:43 PM PDT 24
Finished May 02 12:48:31 PM PDT 24
Peak memory 215488 kb
Host smart-83fa9474-e29d-4153-9b65-b61fa44a43ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152485807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.2152485807
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.3246386850
Short name T858
Test name
Test status
Simulation time 162977634 ps
CPU time 3.66 seconds
Started May 02 12:47:47 PM PDT 24
Finished May 02 12:47:53 PM PDT 24
Peak memory 209100 kb
Host smart-fa9be952-5551-4425-9dcb-7b7b5428d350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246386850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.3246386850
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.869959563
Short name T547
Test name
Test status
Simulation time 104922785 ps
CPU time 4.91 seconds
Started May 02 12:47:26 PM PDT 24
Finished May 02 12:47:34 PM PDT 24
Peak memory 208540 kb
Host smart-ec3171fc-50d5-45f5-a2f5-8edd2b6da86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869959563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.869959563
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.1859597397
Short name T359
Test name
Test status
Simulation time 269636911 ps
CPU time 7.67 seconds
Started May 02 12:47:44 PM PDT 24
Finished May 02 12:47:55 PM PDT 24
Peak memory 208144 kb
Host smart-3b7707bb-dac9-46b1-9d2b-0cc1e6314feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859597397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.1859597397
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.2610439065
Short name T513
Test name
Test status
Simulation time 75237864 ps
CPU time 3.71 seconds
Started May 02 12:47:25 PM PDT 24
Finished May 02 12:47:32 PM PDT 24
Peak memory 208336 kb
Host smart-b661825a-1f42-4c99-b911-bf8e1f6a5165
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610439065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.2610439065
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.947083188
Short name T652
Test name
Test status
Simulation time 406215499 ps
CPU time 2.86 seconds
Started May 02 12:47:31 PM PDT 24
Finished May 02 12:47:35 PM PDT 24
Peak memory 207988 kb
Host smart-fe6d6235-5870-4055-bfef-5e8ece6cb984
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947083188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.947083188
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.3719810009
Short name T618
Test name
Test status
Simulation time 3651440588 ps
CPU time 21.52 seconds
Started May 02 12:47:36 PM PDT 24
Finished May 02 12:47:58 PM PDT 24
Peak memory 207680 kb
Host smart-55f1fa06-310d-435a-a1ba-a9a13a395f26
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719810009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.3719810009
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.3277611169
Short name T653
Test name
Test status
Simulation time 92482161 ps
CPU time 3.24 seconds
Started May 02 12:47:37 PM PDT 24
Finished May 02 12:47:42 PM PDT 24
Peak memory 217936 kb
Host smart-d6511151-0b8a-4806-9979-2301f293377b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277611169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.3277611169
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.3198727961
Short name T458
Test name
Test status
Simulation time 102160628 ps
CPU time 3.12 seconds
Started May 02 12:47:48 PM PDT 24
Finished May 02 12:47:55 PM PDT 24
Peak memory 208056 kb
Host smart-a1d6f981-d1e1-4691-877e-43945d7a5888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198727961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.3198727961
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.2596738468
Short name T179
Test name
Test status
Simulation time 148324670 ps
CPU time 6.14 seconds
Started May 02 12:47:37 PM PDT 24
Finished May 02 12:47:45 PM PDT 24
Peak memory 217716 kb
Host smart-2d699b58-81cc-4e92-977a-625f64063c10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596738468 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.2596738468
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.2138010342
Short name T818
Test name
Test status
Simulation time 302140143 ps
CPU time 4.15 seconds
Started May 02 12:47:47 PM PDT 24
Finished May 02 12:47:55 PM PDT 24
Peak memory 218000 kb
Host smart-4917d8b2-8f12-4a37-8cfa-bb380f675187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138010342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2138010342
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.3128867295
Short name T703
Test name
Test status
Simulation time 156495342 ps
CPU time 2.52 seconds
Started May 02 12:47:42 PM PDT 24
Finished May 02 12:47:47 PM PDT 24
Peak memory 209792 kb
Host smart-73490278-b66e-49ab-ae6a-a1e756aad598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128867295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.3128867295
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.3347167013
Short name T81
Test name
Test status
Simulation time 13929610 ps
CPU time 0.74 seconds
Started May 02 12:47:59 PM PDT 24
Finished May 02 12:48:04 PM PDT 24
Peak memory 205508 kb
Host smart-1d815b60-e4c0-4439-96ca-2b284bf7c6f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347167013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.3347167013
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.408229497
Short name T406
Test name
Test status
Simulation time 453923038 ps
CPU time 6.62 seconds
Started May 02 12:47:46 PM PDT 24
Finished May 02 12:47:56 PM PDT 24
Peak memory 215236 kb
Host smart-211ce30d-5010-43e8-ab80-b1a256b80935
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=408229497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.408229497
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.2751598421
Short name T591
Test name
Test status
Simulation time 109356911 ps
CPU time 3.02 seconds
Started May 02 12:47:33 PM PDT 24
Finished May 02 12:47:39 PM PDT 24
Peak memory 206564 kb
Host smart-2302586d-f248-467f-88f0-bf0b449dc8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751598421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.2751598421
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.1484523079
Short name T606
Test name
Test status
Simulation time 122902612 ps
CPU time 2.45 seconds
Started May 02 12:47:46 PM PDT 24
Finished May 02 12:47:51 PM PDT 24
Peak memory 214080 kb
Host smart-29d05496-cbd6-46b5-a108-e309ed6b8a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484523079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.1484523079
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.3932599405
Short name T721
Test name
Test status
Simulation time 346423205 ps
CPU time 4.57 seconds
Started May 02 12:47:35 PM PDT 24
Finished May 02 12:47:41 PM PDT 24
Peak memory 222096 kb
Host smart-9c08f608-9ad9-4314-b0b0-1c7851009303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932599405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.3932599405
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.2400380614
Short name T217
Test name
Test status
Simulation time 176543564 ps
CPU time 3.51 seconds
Started May 02 12:47:49 PM PDT 24
Finished May 02 12:47:56 PM PDT 24
Peak memory 209508 kb
Host smart-4cfae7cb-3aa8-4395-9043-0e6491648257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400380614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.2400380614
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.2427495075
Short name T820
Test name
Test status
Simulation time 373434822 ps
CPU time 12.9 seconds
Started May 02 12:47:52 PM PDT 24
Finished May 02 12:48:09 PM PDT 24
Peak memory 213892 kb
Host smart-3a7dd459-0687-40cb-ab62-27217606a944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427495075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.2427495075
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.390975800
Short name T872
Test name
Test status
Simulation time 134304770 ps
CPU time 4.29 seconds
Started May 02 12:47:45 PM PDT 24
Finished May 02 12:47:53 PM PDT 24
Peak memory 208084 kb
Host smart-8de90b50-a35d-4909-a426-5baa6fc354e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390975800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.390975800
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.1181830978
Short name T489
Test name
Test status
Simulation time 243968287 ps
CPU time 8.75 seconds
Started May 02 12:47:28 PM PDT 24
Finished May 02 12:47:39 PM PDT 24
Peak memory 207656 kb
Host smart-f068ef73-1ad6-4b39-8f76-dba42cf97ee4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181830978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.1181830978
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.3198685822
Short name T688
Test name
Test status
Simulation time 244104247 ps
CPU time 2.75 seconds
Started May 02 12:47:37 PM PDT 24
Finished May 02 12:47:41 PM PDT 24
Peak memory 208184 kb
Host smart-08c255e0-3845-42de-a344-6c6b3c8ade07
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198685822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.3198685822
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.34001641
Short name T722
Test name
Test status
Simulation time 23122981 ps
CPU time 1.82 seconds
Started May 02 12:47:36 PM PDT 24
Finished May 02 12:47:39 PM PDT 24
Peak memory 206864 kb
Host smart-f702f072-74e0-42b2-ae12-ec2ad691d5c3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34001641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.34001641
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.1108090307
Short name T578
Test name
Test status
Simulation time 482581135 ps
CPU time 3.75 seconds
Started May 02 12:47:53 PM PDT 24
Finished May 02 12:48:00 PM PDT 24
Peak memory 209736 kb
Host smart-63cc51d3-fb1c-4049-940c-994e3fa5a1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108090307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.1108090307
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.1273187826
Short name T886
Test name
Test status
Simulation time 130719641 ps
CPU time 3.02 seconds
Started May 02 12:47:41 PM PDT 24
Finished May 02 12:47:47 PM PDT 24
Peak memory 208268 kb
Host smart-545bbbff-c87c-451d-8761-f532a65a2bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273187826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.1273187826
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.1047177688
Short name T209
Test name
Test status
Simulation time 9945320454 ps
CPU time 93.06 seconds
Started May 02 12:47:41 PM PDT 24
Finished May 02 12:49:17 PM PDT 24
Peak memory 216172 kb
Host smart-c4aea911-6c56-445a-80dd-2f5ef866885e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047177688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.1047177688
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.3360192920
Short name T279
Test name
Test status
Simulation time 635337248 ps
CPU time 4.44 seconds
Started May 02 12:47:47 PM PDT 24
Finished May 02 12:47:54 PM PDT 24
Peak memory 213980 kb
Host smart-6e96dd85-bcc7-409c-82d9-4552b768b76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360192920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.3360192920
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.1861794622
Short name T842
Test name
Test status
Simulation time 312739724 ps
CPU time 2.4 seconds
Started May 02 12:47:52 PM PDT 24
Finished May 02 12:47:58 PM PDT 24
Peak memory 209744 kb
Host smart-6db1d643-99ea-4841-940f-b78ccab2158c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861794622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.1861794622
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.2599822924
Short name T517
Test name
Test status
Simulation time 22327234 ps
CPU time 0.73 seconds
Started May 02 12:47:52 PM PDT 24
Finished May 02 12:47:56 PM PDT 24
Peak memory 205500 kb
Host smart-7e0433d0-12fe-4e47-a9f6-9610dcd5f575
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599822924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.2599822924
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.1002775706
Short name T140
Test name
Test status
Simulation time 41475837 ps
CPU time 2.66 seconds
Started May 02 12:47:47 PM PDT 24
Finished May 02 12:47:52 PM PDT 24
Peak memory 214844 kb
Host smart-f35ca3ff-162e-4430-a5d5-1e4833eeec31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1002775706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.1002775706
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.58519909
Short name T76
Test name
Test status
Simulation time 2235938570 ps
CPU time 41.74 seconds
Started May 02 12:47:43 PM PDT 24
Finished May 02 12:48:28 PM PDT 24
Peak memory 219380 kb
Host smart-38840e5c-4c2a-4ff5-844b-0d4fe89a1808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58519909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.58519909
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.1937548924
Short name T681
Test name
Test status
Simulation time 1807301458 ps
CPU time 28.72 seconds
Started May 02 12:47:46 PM PDT 24
Finished May 02 12:48:18 PM PDT 24
Peak memory 213984 kb
Host smart-25f0ad62-dc58-496b-a2ea-891d45229ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937548924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.1937548924
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.3379730311
Short name T70
Test name
Test status
Simulation time 163200981 ps
CPU time 2.87 seconds
Started May 02 12:47:39 PM PDT 24
Finished May 02 12:47:44 PM PDT 24
Peak memory 220028 kb
Host smart-0dcd9681-7a0d-4de8-8ca3-4f40dac2d75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379730311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.3379730311
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.3887588742
Short name T292
Test name
Test status
Simulation time 898579916 ps
CPU time 5.07 seconds
Started May 02 12:48:15 PM PDT 24
Finished May 02 12:48:23 PM PDT 24
Peak memory 213624 kb
Host smart-723978f5-5dbd-4a54-933e-d6ca28ccd7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887588742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.3887588742
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.4282199406
Short name T892
Test name
Test status
Simulation time 64971986 ps
CPU time 3.18 seconds
Started May 02 12:47:56 PM PDT 24
Finished May 02 12:48:02 PM PDT 24
Peak memory 208136 kb
Host smart-2b51a6df-96b2-42aa-88d3-ddb5b7b1fe01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282199406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.4282199406
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.817885972
Short name T637
Test name
Test status
Simulation time 1304359531 ps
CPU time 28.97 seconds
Started May 02 12:47:38 PM PDT 24
Finished May 02 12:48:10 PM PDT 24
Peak memory 208560 kb
Host smart-af5cca92-aba5-4bb9-8fc0-26a4bcc13241
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817885972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.817885972
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.3374444127
Short name T646
Test name
Test status
Simulation time 60975320 ps
CPU time 3.26 seconds
Started May 02 12:47:43 PM PDT 24
Finished May 02 12:47:49 PM PDT 24
Peak memory 208176 kb
Host smart-4d9585d1-31f0-40b0-8d2f-1e05ff61b3ea
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374444127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.3374444127
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.3094280540
Short name T728
Test name
Test status
Simulation time 39057956 ps
CPU time 2.52 seconds
Started May 02 12:47:43 PM PDT 24
Finished May 02 12:47:48 PM PDT 24
Peak memory 208320 kb
Host smart-fab98ede-bae4-4ab9-8a24-0fc9e4d17eba
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094280540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.3094280540
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.892227736
Short name T587
Test name
Test status
Simulation time 99593664 ps
CPU time 2.16 seconds
Started May 02 12:47:48 PM PDT 24
Finished May 02 12:47:54 PM PDT 24
Peak memory 208160 kb
Host smart-30ccfeb3-4925-460e-ae7c-4e08e6be56e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892227736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.892227736
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.2521819230
Short name T626
Test name
Test status
Simulation time 264489613 ps
CPU time 3.14 seconds
Started May 02 12:47:39 PM PDT 24
Finished May 02 12:47:45 PM PDT 24
Peak memory 208080 kb
Host smart-8df0dc23-182d-4656-b436-ad54b0a9f0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521819230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.2521819230
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.3603990955
Short name T674
Test name
Test status
Simulation time 1936692222 ps
CPU time 43.78 seconds
Started May 02 12:47:45 PM PDT 24
Finished May 02 12:48:32 PM PDT 24
Peak memory 220204 kb
Host smart-f196cf2d-1487-4168-b3bd-7a0a72f95763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603990955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.3603990955
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.1170097025
Short name T640
Test name
Test status
Simulation time 49577542 ps
CPU time 2.34 seconds
Started May 02 12:47:46 PM PDT 24
Finished May 02 12:47:51 PM PDT 24
Peak memory 209532 kb
Host smart-ab71c3f3-28a0-4f35-82b2-92d35e658932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170097025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.1170097025
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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