Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
57485 |
1 |
|
|
T1 |
33 |
|
T3 |
203 |
|
T4 |
33 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
34513 |
1 |
|
|
T3 |
153 |
|
T5 |
6 |
|
T6 |
314 |
auto[1] |
22972 |
1 |
|
|
T1 |
33 |
|
T3 |
50 |
|
T4 |
33 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
28691 |
1 |
|
|
T1 |
17 |
|
T3 |
112 |
|
T4 |
17 |
auto[1] |
28794 |
1 |
|
|
T1 |
16 |
|
T3 |
91 |
|
T4 |
16 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for intr_cg_cc
Bins
cp_intr | cp_intr_en | cp_intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
17135 |
1 |
|
|
T3 |
86 |
|
T5 |
3 |
|
T6 |
176 |
all_values[0] |
auto[0] |
auto[1] |
17378 |
1 |
|
|
T3 |
67 |
|
T5 |
3 |
|
T6 |
138 |
all_values[0] |
auto[1] |
auto[0] |
11556 |
1 |
|
|
T1 |
17 |
|
T3 |
26 |
|
T4 |
17 |
all_values[0] |
auto[1] |
auto[1] |
11416 |
1 |
|
|
T1 |
16 |
|
T3 |
24 |
|
T4 |
16 |