Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11237

1

T1

1

T3

30

T4

4

auto[Attestation]

7597

1

T1

7

T3

42

T4

4

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2668	1			T3	14		T4	2		T6	17
auto[Aes]	3394	1			T1	8		T3	11		T6	13
auto[Kmac]	3470	1			T3	15		T4	1		T5	11
auto[Otbn]	3420	1			T3	10		T4	1		T6	18

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7599	1			T1	8		T3	15		T4	8
auto[OpGenId]	5882	1			T3	22		T4	4		T6	40
auto[OpGenSwOut]	5903	1			T3	26		T4	4		T6	32
auto[OpGenHwOut]	7049	1			T1	8		T3	24		T5	11
auto[OpDisable]	142	1			T3	1		T6	4		T17	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10586

1

T1

8

T3

36

T4

8

auto[OpDoneFail]

15989

1

T1

8

T3

52

T4

8

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6531	1			T1	1		T3	43		T4	1
auto[StInit]	3774	1			T1	2		T3	17		T4	2
auto[StCreatorRootKey]	3110	1			T1	2		T3	14		T4	2
auto[StOwnerIntKey]	2835	1			T1	2		T3	6		T4	2
auto[StOwnerKey]	2466	1			T1	2		T3	5		T4	2
auto[StDisabled]	7859	1			T1	7		T3	3		T4	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	345	1			T3	3		T6	1		T18	3
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	93	1			T3	2		T17	1		T201	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	91	1			T4	1		T6	1		T60	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	70	1			T38	1		T60	1		T145	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	55	1			T3	1		T4	1		T202	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	193	1			T6	3		T86	1		T109	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	324	1			T3	3		T6	2		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	102	1			T3	1		T60	1		T28	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	85	1			T6	1		T109	1		T60	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	72	1			T39	1		T64	1		T76	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	64	1			T109	1		T201	1		T28	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	201	1			T203	1		T76	2		T204	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	322	1			T3	1		T6	1		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	94	1			T6	1		T28	1		T54	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	87	1			T3	1		T6	2		T28	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	71	1			T6	1		T60	1		T28	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	59	1			T3	1		T18	1		T60	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	262	1			T17	2		T75	1		T28	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	326	1			T17	2		T86	1		T60	7
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	105	1			T17	1		T18	1		T60	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	92	1			T3	1		T6	1		T60	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	69	1			T145	1		T64	1		T205	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	57	1			T60	2		T28	1		T59	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	213	1			T3	1		T6	1		T109	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	60	1			T6	1		T206	2		T121	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	90	1			T3	1		T60	2		T143	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	66	1			T3	1		T6	1		T145	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	66	1			T76	1		T25	1		T207	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	64	1			T6	2		T28	2		T76	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	229	1			T6	3		T17	1		T86	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	69	1			T3	1		T59	3		T206	4
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	110	1			T3	2		T6	1		T38	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	73	1			T56	1		T76	1		T129	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	62	1			T96	1		T44	1		T188	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	57	1			T6	1		T86	1		T64	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	238	1			T86	1		T109	2		T60	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	73	1			T3	2		T6	1		T59	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	110	1			T60	3		T76	1		T119	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	77	1			T17	1		T60	1		T28	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	86	1			T3	1		T60	1		T145	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	56	1			T76	1		T59	2		T121	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	224	1			T4	1		T6	1		T146	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	84	1			T3	2		T6	1		T206	4
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	103	1			T17	1		T38	1		T60	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	82	1			T6	1		T201	1		T28	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	83	1			T3	1		T4	1		T208	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	63	1			T76	4		T19	1		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	226	1			T6	4		T17	1		T60	4
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	293	1			T3	2		T18	2		T78	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	98	1			T109	1		T60	1		T143	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	86	1			T57	1		T205	1		T76	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	57	1			T6	1		T17	1		T209	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	50	1			T6	1		T119	2		T126	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	181	1			T60	1		T28	1		T209	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	479	1			T78	1		T60	1		T48	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	136	1			T210	1		T39	1		T144	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	95	1			T1	1		T38	2		T39	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	89	1			T87	1		T60	1		T144	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	96	1			T3	1		T87	1		T76	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	301	1			T6	2		T87	3		T210	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	525	1			T3	2		T5	3		T6	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	116	1			T5	1		T6	1		T37	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	97	1			T5	1		T119	1		T126	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	102	1			T3	1		T5	1		T60	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	91	1			T5	1		T6	2		T37	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	269	1			T5	2		T6	3		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	463	1			T17	2		T18	2		T78	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	120	1			T3	1		T6	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	106	1			T16	1		T211	1		T208	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	90	1			T16	1		T18	1		T211	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	85	1			T6	1		T211	1		T64	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	312	1			T6	1		T16	1		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	57	1			T3	2		T59	2		T206	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	80	1			T6	1		T109	1		T60	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	61	1			T3	2		T6	1		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	60	1			T209	2		T208	1		T205	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	56	1			T23	1		T212	1		T213	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	167	1			T6	1		T18	1		T60	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	53	1			T3	2		T60	1		T76	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	126	1			T1	1		T87	1		T27	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	122	1			T6	1		T17	1		T87	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	106	1			T1	1		T6	1		T210	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	82	1			T1	1		T109	1		T210	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	252	1			T1	4		T3	1		T6	4
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	51	1			T3	3		T6	1		T119	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	112	1			T109	2		T60	2		T75	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	117	1			T3	1		T37	1		T28	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	113	1			T3	1		T6	1		T37	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	86	1			T3	1		T17	1		T28	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	270	1			T5	2		T6	2		T37	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	67	1			T3	2		T6	1		T119	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	118	1			T6	3		T60	1		T211	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	100	1			T3	2		T60	1		T76	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	96	1			T38	2		T145	1		T76	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	85	1			T16	1		T195	1		T214	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	275	1			T6	3		T16	3		T109	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	204	1			T3	1		T4	2		T6	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	643	1			T3	5		T6	4		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	201	1			T6	1		T109	2		T201	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	647	1			T3	4		T6	2		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	200	1			T3	2		T6	3		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	695	1			T3	1		T6	2		T17	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	204	1			T3	1		T6	1		T60	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	658	1			T3	1		T6	1		T17	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	176	1			T3	1		T6	3		T145	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	399	1			T3	1		T6	4		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	187	1			T6	1		T86	1		T56	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	422	1			T3	3		T6	1		T86	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	203	1			T3	1		T17	1		T60	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	423	1			T3	2		T4	1		T6	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	213	1			T3	1		T4	1		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	428	1			T3	2		T6	5		T17	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	168	1			T6	2		T17	1		T57	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	597	1			T3	2		T18	2		T78	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	256	1			T1	1		T3	1		T87	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	940	1			T6	2		T78	1		T87	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	275	1			T3	1		T5	3		T6	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	925	1			T3	2		T5	6		T6	5
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	267	1			T6	1		T16	2		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	909	1			T3	1		T6	2		T16	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	159	1			T3	2		T6	1		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	322	1			T3	2		T6	2		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	295	1			T1	2		T6	2		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	446	1			T1	5		T3	3		T6	4
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	299	1			T3	3		T6	1		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	450	1			T3	3		T5	2		T6	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	265	1			T3	2		T16	1		T38	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	476	1			T3	2		T6	7		T16	3