Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32550

1

T1

23

T3

95

T4

19

auto[1]

270

1

T126

2

T127

1

T131

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	32560	1			T1	23		T3	95		T4	19
auto[134217728:268435455]	6	1			T184	1		T333	1		T374	1
auto[268435456:402653183]	14	1			T184	1		T133	1		T285	1
auto[402653184:536870911]	11	1			T333	1		T368	2		T315	1
auto[536870912:671088639]	6	1			T256	1		T241	1		T412	1
auto[671088640:805306367]	5	1			T285	2		T403	1		T413	1
auto[805306368:939524095]	8	1			T133	1		T135	1		T352	1
auto[939524096:1073741823]	12	1			T126	1		T132	1		T247	1
auto[1073741824:1207959551]	7	1			T352	1		T403	1		T414	1
auto[1207959552:1342177279]	11	1			T126	1		T131	1		T182	1
auto[1342177280:1476395007]	8	1			T352	2		T136	1		T403	1
auto[1476395008:1610612735]	6	1			T131	1		T352	1		T403	1
auto[1610612736:1744830463]	9	1			T257	1		T320	1		T368	1
auto[1744830464:1879048191]	9	1			T182	2		T133	1		T136	1
auto[1879048192:2013265919]	7	1			T131	1		T184	1		T244	1
auto[2013265920:2147483647]	8	1			T352	1		T285	1		T403	1
auto[2147483648:2281701375]	8	1			T184	2		T244	1		T247	1
auto[2281701376:2415919103]	10	1			T247	1		T317	1		T136	1
auto[2415919104:2550136831]	8	1			T131	1		T133	2		T136	1
auto[2550136832:2684354559]	6	1			T368	1		T374	1		T256	1
auto[2684354560:2818572287]	7	1			T182	1		T136	1		T368	1
auto[2818572288:2952790015]	8	1			T184	1		T244	1		T247	1
auto[2952790016:3087007743]	6	1			T289	1		T315	1		T415	2
auto[3087007744:3221225471]	9	1			T127	1		T184	1		T132	1
auto[3221225472:3355443199]	8	1			T333	1		T403	1		T315	1
auto[3355443200:3489660927]	12	1			T132	1		T244	1		T257	1
auto[3489660928:3623878655]	6	1			T135	1		T333	1		T416	1
auto[3623878656:3758096383]	12	1			T132	1		T133	1		T317	1
auto[3758096384:3892314111]	15	1			T244	1		T257	1		T320	1
auto[3892314112:4026531839]	5	1			T333	2		T403	1		T374	1
auto[4026531840:4160749567]	9	1			T136	1		T257	2		T259	1
auto[4160749568:4294967295]	4	1			T182	1		T184	1		T412	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	32550	1			T1	23		T3	95		T4	19
auto[0:134217727]	auto[1]	10	1			T132	1		T244	1		T247	1
auto[134217728:268435455]	auto[1]	6	1			T184	1		T333	1		T374	1
auto[268435456:402653183]	auto[1]	14	1			T184	1		T133	1		T285	1
auto[402653184:536870911]	auto[1]	11	1			T333	1		T368	2		T315	1
auto[536870912:671088639]	auto[1]	6	1			T256	1		T241	1		T412	1
auto[671088640:805306367]	auto[1]	5	1			T285	2		T403	1		T413	1
auto[805306368:939524095]	auto[1]	8	1			T133	1		T135	1		T352	1
auto[939524096:1073741823]	auto[1]	12	1			T126	1		T132	1		T247	1
auto[1073741824:1207959551]	auto[1]	7	1			T352	1		T403	1		T414	1
auto[1207959552:1342177279]	auto[1]	11	1			T126	1		T131	1		T182	1
auto[1342177280:1476395007]	auto[1]	8	1			T352	2		T136	1		T403	1
auto[1476395008:1610612735]	auto[1]	6	1			T131	1		T352	1		T403	1
auto[1610612736:1744830463]	auto[1]	9	1			T257	1		T320	1		T368	1
auto[1744830464:1879048191]	auto[1]	9	1			T182	2		T133	1		T136	1
auto[1879048192:2013265919]	auto[1]	7	1			T131	1		T184	1		T244	1
auto[2013265920:2147483647]	auto[1]	8	1			T352	1		T285	1		T403	1
auto[2147483648:2281701375]	auto[1]	8	1			T184	2		T244	1		T247	1
auto[2281701376:2415919103]	auto[1]	10	1			T247	1		T317	1		T136	1
auto[2415919104:2550136831]	auto[1]	8	1			T131	1		T133	2		T136	1
auto[2550136832:2684354559]	auto[1]	6	1			T368	1		T374	1		T256	1
auto[2684354560:2818572287]	auto[1]	7	1			T182	1		T136	1		T368	1
auto[2818572288:2952790015]	auto[1]	8	1			T184	1		T244	1		T247	1
auto[2952790016:3087007743]	auto[1]	6	1			T289	1		T315	1		T415	2
auto[3087007744:3221225471]	auto[1]	9	1			T127	1		T184	1		T132	1
auto[3221225472:3355443199]	auto[1]	8	1			T333	1		T403	1		T315	1
auto[3355443200:3489660927]	auto[1]	12	1			T132	1		T244	1		T257	1
auto[3489660928:3623878655]	auto[1]	6	1			T135	1		T333	1		T416	1
auto[3623878656:3758096383]	auto[1]	12	1			T132	1		T133	1		T317	1
auto[3758096384:3892314111]	auto[1]	15	1			T244	1		T257	1		T320	1
auto[3892314112:4026531839]	auto[1]	5	1			T333	2		T403	1		T374	1
auto[4026531840:4160749567]	auto[1]	9	1			T136	1		T257	2		T259	1
auto[4160749568:4294967295]	auto[1]	4	1			T182	1		T184	1		T412	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1538

1

T3

13

T6

8

T15

7

auto[1]

1841

1

T3

8

T6

15

T17

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	104	1			T109	1		T60	2		T28	1
auto[134217728:268435455]	106	1			T6	2		T143	1		T28	2
auto[268435456:402653183]	113	1			T3	2		T6	2		T40	1
auto[402653184:536870911]	89	1			T3	1		T48	1		T49	1
auto[536870912:671088639]	108	1			T3	2		T60	1		T76	1
auto[671088640:805306367]	101	1			T3	1		T6	1		T40	1
auto[805306368:939524095]	108	1			T3	1		T17	1		T76	1
auto[939524096:1073741823]	102	1			T6	2		T208	1		T127	1
auto[1073741824:1207959551]	103	1			T60	1		T27	1		T251	1
auto[1207959552:1342177279]	113	1			T3	1		T6	1		T27	1
auto[1342177280:1476395007]	97	1			T6	1		T251	1		T209	1
auto[1476395008:1610612735]	110	1			T27	1		T209	1		T196	1
auto[1610612736:1744830463]	104	1			T6	3		T15	1		T60	1
auto[1744830464:1879048191]	118	1			T6	2		T48	2		T49	1
auto[1879048192:2013265919]	127	1			T3	3		T6	2		T109	1
auto[2013265920:2147483647]	105	1			T3	2		T6	1		T27	1
auto[2147483648:2281701375]	96	1			T6	1		T60	2		T49	1
auto[2281701376:2415919103]	77	1			T76	1		T126	1		T399	1
auto[2415919104:2550136831]	98	1			T3	1		T6	1		T40	2
auto[2550136832:2684354559]	101	1			T6	1		T251	1		T76	1
auto[2684354560:2818572287]	88	1			T3	1		T6	1		T15	1
auto[2818572288:2952790015]	128	1			T6	1		T15	1		T60	1
auto[2952790016:3087007743]	97	1			T6	1		T109	1		T28	1
auto[3087007744:3221225471]	97	1			T3	2		T15	1		T49	1
auto[3221225472:3355443199]	118	1			T53	1		T143	1		T28	1
auto[3355443200:3489660927]	120	1			T15	1		T60	1		T49	1
auto[3489660928:3623878655]	101	1			T15	1		T60	1		T143	2
auto[3623878656:3758096383]	118	1			T3	1		T15	1		T17	1
auto[3758096384:3892314111]	118	1			T3	1		T60	1		T48	1
auto[3892314112:4026531839]	109	1			T27	1		T48	1		T49	1
auto[4026531840:4160749567]	88	1			T3	1		T17	1		T60	1
auto[4160749568:4294967295]	117	1			T3	1		T53	1		T145	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	51	1			T109	1		T58	1		T88	1
auto[0:134217727]	auto[1]	53	1			T60	2		T28	1		T76	1
auto[134217728:268435455]	auto[0]	52	1			T28	1		T76	1		T197	1
auto[134217728:268435455]	auto[1]	54	1			T6	2		T143	1		T28	1
auto[268435456:402653183]	auto[0]	55	1			T3	1		T6	1		T60	1
auto[268435456:402653183]	auto[1]	58	1			T3	1		T6	1		T40	1
auto[402653184:536870911]	auto[0]	47	1			T48	1		T49	1		T251	1
auto[402653184:536870911]	auto[1]	42	1			T3	1		T205	1		T126	1
auto[536870912:671088639]	auto[0]	42	1			T3	1		T193	1		T196	2
auto[536870912:671088639]	auto[1]	66	1			T3	1		T60	1		T76	1
auto[671088640:805306367]	auto[0]	50	1			T6	1		T60	1		T66	1
auto[671088640:805306367]	auto[1]	51	1			T3	1		T40	1		T53	1
auto[805306368:939524095]	auto[0]	48	1			T3	1		T119	1		T399	1
auto[805306368:939524095]	auto[1]	60	1			T17	1		T76	1		T196	1
auto[939524096:1073741823]	auto[0]	45	1			T6	1		T208	1		T127	1
auto[939524096:1073741823]	auto[1]	57	1			T6	1		T59	1		T188	1
auto[1073741824:1207959551]	auto[0]	47	1			T27	1		T76	1		T69	1
auto[1073741824:1207959551]	auto[1]	56	1			T60	1		T251	1		T55	1
auto[1207959552:1342177279]	auto[0]	48	1			T48	1		T28	1		T64	1
auto[1207959552:1342177279]	auto[1]	65	1			T3	1		T6	1		T27	1
auto[1342177280:1476395007]	auto[0]	44	1			T6	1		T209	1		T76	1
auto[1342177280:1476395007]	auto[1]	53	1			T251	1		T76	2		T196	1
auto[1476395008:1610612735]	auto[0]	43	1			T27	1		T209	1		T417	1
auto[1476395008:1610612735]	auto[1]	67	1			T196	1		T19	1		T278	1
auto[1610612736:1744830463]	auto[0]	50	1			T6	1		T15	1		T60	1
auto[1610612736:1744830463]	auto[1]	54	1			T6	2		T96	1		T77	1
auto[1744830464:1879048191]	auto[0]	64	1			T6	1		T48	1		T49	1
auto[1744830464:1879048191]	auto[1]	54	1			T6	1		T48	1		T209	1
auto[1879048192:2013265919]	auto[0]	56	1			T3	1		T60	1		T208	2
auto[1879048192:2013265919]	auto[1]	71	1			T3	2		T6	2		T109	1
auto[2013265920:2147483647]	auto[0]	46	1			T3	2		T27	1		T69	1
auto[2013265920:2147483647]	auto[1]	59	1			T6	1		T28	1		T54	1
auto[2147483648:2281701375]	auto[0]	38	1			T6	1		T60	2		T49	1
auto[2147483648:2281701375]	auto[1]	58	1			T101	1		T272	1		T66	1
auto[2281701376:2415919103]	auto[0]	34	1			T66	2		T185	1		T418	1
auto[2281701376:2415919103]	auto[1]	43	1			T76	1		T126	1		T399	1
auto[2415919104:2550136831]	auto[0]	39	1			T3	1		T363	1		T25	1
auto[2415919104:2550136831]	auto[1]	59	1			T6	1		T40	2		T60	1
auto[2550136832:2684354559]	auto[0]	42	1			T59	1		T121	1		T419	1
auto[2550136832:2684354559]	auto[1]	59	1			T6	1		T251	1		T76	1
auto[2684354560:2818572287]	auto[0]	46	1			T3	1		T15	1		T17	1
auto[2684354560:2818572287]	auto[1]	42	1			T6	1		T209	1		T127	1
auto[2818572288:2952790015]	auto[0]	67	1			T15	1		T60	1		T52	1
auto[2818572288:2952790015]	auto[1]	61	1			T6	1		T19	1		T330	1
auto[2952790016:3087007743]	auto[0]	44	1			T6	1		T64	1		T182	1
auto[2952790016:3087007743]	auto[1]	53	1			T109	1		T28	1		T76	1
auto[3087007744:3221225471]	auto[0]	43	1			T3	2		T15	1		T49	1
auto[3087007744:3221225471]	auto[1]	54	1			T76	1		T197	1		T25	1
auto[3221225472:3355443199]	auto[0]	53	1			T143	1		T64	1		T23	1
auto[3221225472:3355443199]	auto[1]	65	1			T53	1		T28	1		T61	1
auto[3355443200:3489660927]	auto[0]	51	1			T15	1		T49	1		T52	1
auto[3355443200:3489660927]	auto[1]	69	1			T60	1		T28	2		T251	1
auto[3489660928:3623878655]	auto[0]	45	1			T15	1		T143	1		T28	1
auto[3489660928:3623878655]	auto[1]	56	1			T60	1		T143	1		T49	1
auto[3623878656:3758096383]	auto[0]	62	1			T15	1		T60	1		T52	1
auto[3623878656:3758096383]	auto[1]	56	1			T3	1		T17	1		T143	1
auto[3758096384:3892314111]	auto[0]	58	1			T3	1		T48	1		T69	1
auto[3758096384:3892314111]	auto[1]	60	1			T60	1		T145	1		T251	1
auto[3892314112:4026531839]	auto[0]	44	1			T27	1		T49	1		T24	1
auto[3892314112:4026531839]	auto[1]	65	1			T48	1		T28	1		T76	1
auto[4026531840:4160749567]	auto[0]	33	1			T3	1		T60	1		T59	1
auto[4026531840:4160749567]	auto[1]	55	1			T17	1		T76	1		T119	1
auto[4160749568:4294967295]	auto[0]	51	1			T3	1		T363	1		T54	1
auto[4160749568:4294967295]	auto[1]	66	1			T53	1		T145	1		T208	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1575

1

T3

12

T6

10

T15

7

auto[1]

1806

1

T3

9

T6

13

T17

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	125	1			T60	1		T143	1		T49	1
auto[134217728:268435455]	92	1			T3	1		T17	1		T60	1
auto[268435456:402653183]	101	1			T6	1		T53	1		T61	1
auto[402653184:536870911]	130	1			T15	1		T40	1		T53	1
auto[536870912:671088639]	110	1			T3	1		T40	1		T28	1
auto[671088640:805306367]	111	1			T3	1		T6	1		T109	1
auto[805306368:939524095]	106	1			T3	1		T28	2		T363	1
auto[939524096:1073741823]	112	1			T3	2		T6	1		T60	1
auto[1073741824:1207959551]	112	1			T3	2		T6	1		T109	1
auto[1207959552:1342177279]	122	1			T6	1		T60	1		T49	1
auto[1342177280:1476395007]	118	1			T15	1		T17	1		T60	2
auto[1476395008:1610612735]	86	1			T3	1		T6	3		T15	1
auto[1610612736:1744830463]	112	1			T6	2		T48	1		T52	1
auto[1744830464:1879048191]	94	1			T3	2		T109	1		T60	1
auto[1879048192:2013265919]	102	1			T6	1		T49	2		T28	1
auto[2013265920:2147483647]	102	1			T6	2		T48	1		T143	1
auto[2147483648:2281701375]	98	1			T60	1		T76	1		T119	1
auto[2281701376:2415919103]	102	1			T3	1		T6	2		T17	1
auto[2415919104:2550136831]	122	1			T6	1		T15	1		T52	1
auto[2550136832:2684354559]	82	1			T17	1		T60	1		T205	1
auto[2684354560:2818572287]	102	1			T3	1		T6	1		T40	1
auto[2818572288:2952790015]	108	1			T15	1		T60	1		T27	1
auto[2952790016:3087007743]	116	1			T53	1		T145	1		T28	1
auto[3087007744:3221225471]	108	1			T3	2		T6	1		T28	1
auto[3221225472:3355443199]	99	1			T15	2		T143	1		T52	1
auto[3355443200:3489660927]	102	1			T49	2		T52	2		T28	1
auto[3489660928:3623878655]	108	1			T3	2		T6	1		T60	1
auto[3623878656:3758096383]	99	1			T3	1		T145	1		T76	1
auto[3758096384:3892314111]	97	1			T3	2		T143	1		T52	1
auto[3892314112:4026531839]	89	1			T6	1		T60	1		T64	1
auto[4026531840:4160749567]	107	1			T6	2		T208	1		T61	1
auto[4160749568:4294967295]	107	1			T3	1		T6	1		T40	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	56	1			T143	1		T49	1		T208	1
auto[0:134217727]	auto[1]	69	1			T60	1		T251	1		T119	1
auto[134217728:268435455]	auto[0]	52	1			T60	1		T27	1		T76	1
auto[134217728:268435455]	auto[1]	40	1			T3	1		T17	1		T143	1
auto[268435456:402653183]	auto[0]	42	1			T197	1		T120	1		T66	2
auto[268435456:402653183]	auto[1]	59	1			T6	1		T53	1		T61	1
auto[402653184:536870911]	auto[0]	57	1			T15	1		T48	1		T363	1
auto[402653184:536870911]	auto[1]	73	1			T40	1		T53	1		T60	1
auto[536870912:671088639]	auto[0]	43	1			T3	1		T90	1		T420	1
auto[536870912:671088639]	auto[1]	67	1			T40	1		T28	1		T126	1
auto[671088640:805306367]	auto[0]	51	1			T60	1		T27	1		T363	1
auto[671088640:805306367]	auto[1]	60	1			T3	1		T6	1		T109	1
auto[805306368:939524095]	auto[0]	44	1			T28	2		T363	1		T76	1
auto[805306368:939524095]	auto[1]	62	1			T3	1		T55	1		T76	2
auto[939524096:1073741823]	auto[0]	55	1			T3	2		T60	1		T49	1
auto[939524096:1073741823]	auto[1]	57	1			T6	1		T197	1		T25	1
auto[1073741824:1207959551]	auto[0]	50	1			T3	1		T6	1		T109	1
auto[1073741824:1207959551]	auto[1]	62	1			T3	1		T76	1		T212	1
auto[1207959552:1342177279]	auto[0]	53	1			T60	1		T49	1		T76	1
auto[1207959552:1342177279]	auto[1]	69	1			T6	1		T119	1		T126	2
auto[1342177280:1476395007]	auto[0]	55	1			T15	1		T60	2		T27	1
auto[1342177280:1476395007]	auto[1]	63	1			T17	1		T28	1		T76	1
auto[1476395008:1610612735]	auto[0]	41	1			T6	2		T15	1		T64	1
auto[1476395008:1610612735]	auto[1]	45	1			T3	1		T6	1		T60	1
auto[1610612736:1744830463]	auto[0]	51	1			T6	1		T52	1		T193	1
auto[1610612736:1744830463]	auto[1]	61	1			T6	1		T48	1		T76	1
auto[1744830464:1879048191]	auto[0]	43	1			T3	1		T27	1		T208	1
auto[1744830464:1879048191]	auto[1]	51	1			T3	1		T109	1		T60	1
auto[1879048192:2013265919]	auto[0]	48	1			T49	2		T54	1		T96	1
auto[1879048192:2013265919]	auto[1]	54	1			T6	1		T28	1		T19	1
auto[2013265920:2147483647]	auto[0]	52	1			T48	1		T330	1		T212	1
auto[2013265920:2147483647]	auto[1]	50	1			T6	2		T143	1		T69	2
auto[2147483648:2281701375]	auto[0]	57	1			T76	1		T119	1		T19	1
auto[2147483648:2281701375]	auto[1]	41	1			T60	1		T206	1		T188	1
auto[2281701376:2415919103]	auto[0]	37	1			T3	1		T6	1		T28	1
auto[2281701376:2415919103]	auto[1]	65	1			T6	1		T17	1		T60	2
auto[2415919104:2550136831]	auto[0]	59	1			T15	1		T52	1		T90	1
auto[2415919104:2550136831]	auto[1]	63	1			T6	1		T209	1		T61	1
auto[2550136832:2684354559]	auto[0]	38	1			T60	1		T205	1		T24	1
auto[2550136832:2684354559]	auto[1]	44	1			T17	1		T96	1		T275	1
auto[2684354560:2818572287]	auto[0]	54	1			T3	1		T6	1		T48	1
auto[2684354560:2818572287]	auto[1]	48	1			T40	1		T76	1		T278	1
auto[2818572288:2952790015]	auto[0]	52	1			T15	1		T60	1		T27	1
auto[2818572288:2952790015]	auto[1]	56	1			T251	1		T203	1		T204	1
auto[2952790016:3087007743]	auto[0]	56	1			T251	1		T131	1		T88	2
auto[2952790016:3087007743]	auto[1]	60	1			T53	1		T145	1		T28	1
auto[3087007744:3221225471]	auto[0]	42	1			T3	2		T6	1		T28	1
auto[3087007744:3221225471]	auto[1]	66	1			T251	1		T101	1		T206	1
auto[3221225472:3355443199]	auto[0]	52	1			T15	2		T52	1		T195	2
auto[3221225472:3355443199]	auto[1]	47	1			T143	1		T205	1		T76	1
auto[3355443200:3489660927]	auto[0]	56	1			T49	1		T52	2		T28	1
auto[3355443200:3489660927]	auto[1]	46	1			T49	1		T251	2		T55	1
auto[3489660928:3623878655]	auto[0]	40	1			T3	1		T6	1		T23	1
auto[3489660928:3623878655]	auto[1]	68	1			T3	1		T60	1		T48	1
auto[3623878656:3758096383]	auto[0]	41	1			T218	1		T66	1		T185	1
auto[3623878656:3758096383]	auto[1]	58	1			T3	1		T145	1		T76	1
auto[3758096384:3892314111]	auto[0]	47	1			T3	1		T143	1		T52	1
auto[3758096384:3892314111]	auto[1]	50	1			T3	1		T209	1		T121	1
auto[3892314112:4026531839]	auto[0]	47	1			T6	1		T60	1		T64	1
auto[3892314112:4026531839]	auto[1]	42	1			T76	1		T69	1		T131	1
auto[4026531840:4160749567]	auto[0]	53	1			T208	1		T61	1		T76	1
auto[4026531840:4160749567]	auto[1]	54	1			T6	2		T76	1		T119	1
auto[4160749568:4294967295]	auto[0]	51	1			T3	1		T6	1		T40	1
auto[4160749568:4294967295]	auto[1]	56	1			T60	1		T145	1		T28	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1565

1

T3

13

T6

10

T15

7

auto[1]

1815

1

T3

8

T6

13

T17

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	112	1			T3	1		T6	1		T76	1
auto[134217728:268435455]	113	1			T6	1		T60	1		T48	1
auto[268435456:402653183]	75	1			T6	1		T60	1		T49	1
auto[402653184:536870911]	105	1			T6	1		T145	1		T61	1
auto[536870912:671088639]	103	1			T3	1		T15	1		T109	1
auto[671088640:805306367]	128	1			T3	2		T6	2		T60	2
auto[805306368:939524095]	105	1			T3	1		T40	2		T109	1
auto[939524096:1073741823]	104	1			T3	1		T40	1		T60	1
auto[1073741824:1207959551]	115	1			T3	1		T6	1		T60	1
auto[1207959552:1342177279]	107	1			T60	2		T76	2		T131	1
auto[1342177280:1476395007]	103	1			T205	1		T126	1		T278	1
auto[1476395008:1610612735]	108	1			T3	2		T15	1		T49	1
auto[1610612736:1744830463]	127	1			T3	1		T17	1		T48	1
auto[1744830464:1879048191]	101	1			T6	1		T53	1		T60	1
auto[1879048192:2013265919]	106	1			T3	1		T6	1		T17	1
auto[2013265920:2147483647]	112	1			T6	2		T60	1		T49	1
auto[2147483648:2281701375]	92	1			T3	1		T145	1		T54	1
auto[2281701376:2415919103]	95	1			T15	1		T53	1		T28	2
auto[2415919104:2550136831]	94	1			T27	1		T28	1		T61	1
auto[2550136832:2684354559]	97	1			T3	1		T15	1		T208	1
auto[2684354560:2818572287]	109	1			T3	2		T6	1		T49	1
auto[2818572288:2952790015]	116	1			T3	2		T60	1		T27	1
auto[2952790016:3087007743]	103	1			T3	1		T6	1		T60	2
auto[3087007744:3221225471]	118	1			T6	1		T60	1		T27	1
auto[3221225472:3355443199]	99	1			T3	1		T15	1		T17	1
auto[3355443200:3489660927]	103	1			T15	1		T48	1		T143	1
auto[3489660928:3623878655]	101	1			T6	1		T40	1		T60	1
auto[3623878656:3758096383]	121	1			T3	1		T6	5		T17	1
auto[3758096384:3892314111]	101	1			T6	1		T60	1		T28	1
auto[3892314112:4026531839]	101	1			T3	1		T6	2		T15	1
auto[4026531840:4160749567]	110	1			T143	1		T54	1		T76	3
auto[4160749568:4294967295]	96	1			T109	1		T48	1		T49	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	59	1			T3	1		T25	1		T66	1
auto[0:134217727]	auto[1]	53	1			T6	1		T76	1		T399	1
auto[134217728:268435455]	auto[0]	48	1			T60	1		T48	1		T64	1
auto[134217728:268435455]	auto[1]	65	1			T6	1		T120	1		T102	1
auto[268435456:402653183]	auto[0]	37	1			T6	1		T49	1		T195	1
auto[268435456:402653183]	auto[1]	38	1			T60	1		T28	1		T251	1
auto[402653184:536870911]	auto[0]	47	1			T195	1		T399	1		T23	1
auto[402653184:536870911]	auto[1]	58	1			T6	1		T145	1		T61	1
auto[536870912:671088639]	auto[0]	48	1			T15	1		T60	1		T193	1
auto[536870912:671088639]	auto[1]	55	1			T3	1		T109	1		T60	1
auto[671088640:805306367]	auto[0]	58	1			T3	1		T6	1		T60	1
auto[671088640:805306367]	auto[1]	70	1			T3	1		T6	1		T60	1
auto[805306368:939524095]	auto[0]	47	1			T3	1		T40	1		T109	1
auto[805306368:939524095]	auto[1]	58	1			T40	1		T48	1		T209	1
auto[939524096:1073741823]	auto[0]	48	1			T3	1		T60	1		T52	1
auto[939524096:1073741823]	auto[1]	56	1			T40	1		T48	1		T145	1
auto[1073741824:1207959551]	auto[0]	47	1			T3	1		T60	1		T209	1
auto[1073741824:1207959551]	auto[1]	68	1			T6	1		T251	1		T58	1
auto[1207959552:1342177279]	auto[0]	58	1			T60	1		T76	1		T23	1
auto[1207959552:1342177279]	auto[1]	49	1			T60	1		T76	1		T131	1
auto[1342177280:1476395007]	auto[0]	35	1			T205	1		T101	1		T66	1
auto[1342177280:1476395007]	auto[1]	68	1			T126	1		T278	1		T59	1
auto[1476395008:1610612735]	auto[0]	53	1			T3	1		T15	1		T49	1
auto[1476395008:1610612735]	auto[1]	55	1			T3	1		T196	1		T71	1
auto[1610612736:1744830463]	auto[0]	59	1			T48	1		T363	1		T193	1
auto[1610612736:1744830463]	auto[1]	68	1			T3	1		T17	1		T28	1
auto[1744830464:1879048191]	auto[0]	55	1			T60	1		T143	1		T76	1
auto[1744830464:1879048191]	auto[1]	46	1			T6	1		T53	1		T49	1
auto[1879048192:2013265919]	auto[0]	46	1			T3	1		T6	1		T60	1
auto[1879048192:2013265919]	auto[1]	60	1			T17	1		T205	1		T399	1
auto[2013265920:2147483647]	auto[0]	46	1			T6	1		T90	1		T19	1
auto[2013265920:2147483647]	auto[1]	66	1			T6	1		T60	1		T49	1
auto[2147483648:2281701375]	auto[0]	35	1			T145	1		T61	1		T79	1
auto[2147483648:2281701375]	auto[1]	57	1			T3	1		T54	1		T61	1
auto[2281701376:2415919103]	auto[0]	42	1			T15	1		T76	1		T204	1
auto[2281701376:2415919103]	auto[1]	53	1			T53	1		T28	2		T209	1
auto[2415919104:2550136831]	auto[0]	51	1			T27	1		T28	1		T23	1
auto[2415919104:2550136831]	auto[1]	43	1			T61	1		T76	1		T69	1
auto[2550136832:2684354559]	auto[0]	44	1			T15	1		T208	1		T25	1
auto[2550136832:2684354559]	auto[1]	53	1			T3	1		T196	1		T206	2
auto[2684354560:2818572287]	auto[0]	46	1			T3	2		T58	1		T88	1
auto[2684354560:2818572287]	auto[1]	63	1			T6	1		T49	1		T205	1
auto[2818572288:2952790015]	auto[0]	56	1			T3	1		T27	1		T52	1
auto[2818572288:2952790015]	auto[1]	60	1			T3	1		T60	1		T143	1
auto[2952790016:3087007743]	auto[0]	49	1			T3	1		T6	1		T27	1
auto[2952790016:3087007743]	auto[1]	54	1			T60	2		T209	1		T54	1
auto[3087007744:3221225471]	auto[0]	56	1			T6	1		T60	1		T27	1
auto[3087007744:3221225471]	auto[1]	62	1			T143	1		T52	1		T203	1
auto[3221225472:3355443199]	auto[0]	48	1			T15	1		T28	1		T90	1
auto[3221225472:3355443199]	auto[1]	51	1			T3	1		T17	1		T53	1
auto[3355443200:3489660927]	auto[0]	48	1			T15	1		T143	1		T52	1
auto[3355443200:3489660927]	auto[1]	55	1			T48	1		T76	1		T119	1
auto[3489660928:3623878655]	auto[0]	46	1			T27	1		T28	1		T363	1
auto[3489660928:3623878655]	auto[1]	55	1			T6	1		T40	1		T60	1
auto[3623878656:3758096383]	auto[0]	55	1			T3	1		T6	3		T251	2
auto[3623878656:3758096383]	auto[1]	66	1			T6	2		T17	1		T76	2
auto[3758096384:3892314111]	auto[0]	49	1			T60	1		T76	1		T71	1
auto[3758096384:3892314111]	auto[1]	52	1			T6	1		T28	1		T208	1
auto[3892314112:4026531839]	auto[0]	48	1			T3	1		T6	1		T15	1
auto[3892314112:4026531839]	auto[1]	53	1			T6	1		T28	1		T59	1
auto[4026531840:4160749567]	auto[0]	58	1			T143	1		T54	1		T76	1
auto[4026531840:4160749567]	auto[1]	52	1			T76	2		T204	1		T25	1
auto[4160749568:4294967295]	auto[0]	43	1			T48	1		T49	1		T52	1
auto[4160749568:4294967295]	auto[1]	53	1			T109	1		T28	1		T19	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1572

1

T3

15

T6

9

T15

7

auto[1]

1807

1

T3

6

T6

14

T17

4