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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4561 1 T3 22 T6 24 T15 12
auto[1] 2198 1 T3 20 T6 22 T15 2



Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 200 1 T6 2 T53 2 T60 2
auto[134217728:268435455] 242 1 T6 4 T15 2 T17 2
auto[268435456:402653183] 206 1 T28 2 T197 2 T127 2
auto[402653184:536870911] 228 1 T15 2 T49 2 T28 2
auto[536870912:671088639] 192 1 T3 4 T76 2 T70 2
auto[671088640:805306367] 200 1 T3 2 T197 2 T330 2
auto[805306368:939524095] 202 1 T3 2 T15 2 T40 2
auto[939524096:1073741823] 222 1 T53 2 T27 4 T49 2
auto[1073741824:1207959551] 218 1 T15 2 T40 2 T28 4
auto[1207959552:1342177279] 194 1 T3 2 T6 2 T61 2
auto[1342177280:1476395007] 222 1 T6 2 T60 4 T143 4
auto[1476395008:1610612735] 222 1 T3 2 T6 4 T15 2
auto[1610612736:1744830463] 224 1 T6 4 T48 2 T28 2
auto[1744830464:1879048191] 210 1 T3 2 T15 2 T109 2
auto[1879048192:2013265919] 168 1 T3 2 T60 2 T251 2
auto[2013265920:2147483647] 234 1 T6 4 T17 2 T60 2
auto[2147483648:2281701375] 206 1 T3 2 T6 2 T60 2
auto[2281701376:2415919103] 240 1 T3 2 T6 4 T145 2
auto[2415919104:2550136831] 232 1 T3 2 T48 2 T49 2
auto[2550136832:2684354559] 204 1 T3 2 T48 2 T55 2
auto[2684354560:2818572287] 224 1 T3 2 T60 2 T49 2
auto[2818572288:2952790015] 205 1 T3 2 T109 2 T60 4
auto[2952790016:3087007743] 184 1 T3 2 T6 2 T60 2
auto[3087007744:3221225471] 208 1 T6 2 T40 2 T60 6
auto[3221225472:3355443199] 184 1 T3 4 T6 2 T251 2
auto[3355443200:3489660927] 202 1 T3 2 T109 2 T27 2
auto[3489660928:3623878655] 222 1 T6 2 T27 2 T48 2
auto[3623878656:3758096383] 200 1 T3 4 T6 2 T60 4
auto[3758096384:3892314111] 222 1 T6 2 T17 4 T48 2
auto[3892314112:4026531839] 216 1 T6 4 T52 2 T363 2
auto[4026531840:4160749567] 222 1 T3 2 T6 2 T60 4
auto[4160749568:4294967295] 204 1 T15 2 T52 2 T54 2



Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 140 1 T6 2 T53 2 T61 4
auto[0:134217727] auto[1] 60 1 T60 2 T102 2 T284 2
auto[134217728:268435455] auto[0] 162 1 T6 4 T40 2 T60 2
auto[134217728:268435455] auto[1] 80 1 T15 2 T17 2 T28 2
auto[268435456:402653183] auto[0] 144 1 T127 2 T131 2 T252 2
auto[268435456:402653183] auto[1] 62 1 T28 2 T197 2 T244 2
auto[402653184:536870911] auto[0] 166 1 T15 2 T49 2 T28 2
auto[402653184:536870911] auto[1] 62 1 T76 2 T127 2 T58 2
auto[536870912:671088639] auto[0] 128 1 T3 2 T76 2 T70 2
auto[536870912:671088639] auto[1] 64 1 T3 2 T108 2 T66 2
auto[671088640:805306367] auto[0] 138 1 T330 2 T59 4 T212 2
auto[671088640:805306367] auto[1] 62 1 T3 2 T197 2 T58 2
auto[805306368:939524095] auto[0] 142 1 T15 2 T40 2 T61 2
auto[805306368:939524095] auto[1] 60 1 T3 2 T25 2 T29 2
auto[939524096:1073741823] auto[0] 164 1 T53 2 T27 4 T49 2
auto[939524096:1073741823] auto[1] 58 1 T208 2 T71 2 T184 2
auto[1073741824:1207959551] auto[0] 138 1 T15 2 T40 2 T28 4
auto[1073741824:1207959551] auto[1] 80 1 T76 2 T127 2 T23 2
auto[1207959552:1342177279] auto[0] 130 1 T3 2 T61 2 T76 2
auto[1207959552:1342177279] auto[1] 64 1 T6 2 T64 2 T88 2
auto[1342177280:1476395007] auto[0] 146 1 T60 2 T143 4 T205 2
auto[1342177280:1476395007] auto[1] 76 1 T6 2 T60 2 T76 2
auto[1476395008:1610612735] auto[0] 170 1 T3 2 T6 4 T15 2
auto[1476395008:1610612735] auto[1] 52 1 T52 2 T275 2 T206 2
auto[1610612736:1744830463] auto[0] 140 1 T6 2 T48 2 T28 2
auto[1610612736:1744830463] auto[1] 84 1 T6 2 T59 2 T101 2
auto[1744830464:1879048191] auto[0] 140 1 T15 2 T109 2 T69 2
auto[1744830464:1879048191] auto[1] 70 1 T3 2 T53 2 T60 2
auto[1879048192:2013265919] auto[0] 122 1 T3 2 T330 2 T24 2
auto[1879048192:2013265919] auto[1] 46 1 T60 2 T251 2 T363 2
auto[2013265920:2147483647] auto[0] 158 1 T6 4 T60 2 T28 2
auto[2013265920:2147483647] auto[1] 76 1 T17 2 T77 2 T23 2
auto[2147483648:2281701375] auto[0] 146 1 T3 2 T6 2 T60 2
auto[2147483648:2281701375] auto[1] 60 1 T28 2 T197 2 T19 2
auto[2281701376:2415919103] auto[0] 144 1 T3 2 T28 4 T251 2
auto[2281701376:2415919103] auto[1] 96 1 T6 4 T145 2 T363 2
auto[2415919104:2550136831] auto[0] 158 1 T48 2 T49 2 T64 2
auto[2415919104:2550136831] auto[1] 74 1 T3 2 T76 4 T399 2
auto[2550136832:2684354559] auto[0] 136 1 T48 2 T55 2 T96 2
auto[2550136832:2684354559] auto[1] 68 1 T3 2 T76 2 T420 2
auto[2684354560:2818572287] auto[0] 158 1 T3 2 T60 2 T49 2
auto[2684354560:2818572287] auto[1] 66 1 T145 2 T76 2 T96 2
auto[2818572288:2952790015] auto[0] 133 1 T109 2 T60 2 T54 2
auto[2818572288:2952790015] auto[1] 72 1 T3 2 T60 2 T76 2
auto[2952790016:3087007743] auto[0] 118 1 T60 2 T119 2 T126 2
auto[2952790016:3087007743] auto[1] 66 1 T3 2 T6 2 T28 2
auto[3087007744:3221225471] auto[0] 140 1 T40 2 T60 2 T363 2
auto[3087007744:3221225471] auto[1] 68 1 T6 2 T60 4 T48 2
auto[3221225472:3355443199] auto[0] 120 1 T3 4 T55 2 T69 2
auto[3221225472:3355443199] auto[1] 64 1 T6 2 T251 2 T399 2
auto[3355443200:3489660927] auto[0] 132 1 T3 2 T109 2 T27 2
auto[3355443200:3489660927] auto[1] 70 1 T49 2 T66 2 T186 2
auto[3489660928:3623878655] auto[0] 142 1 T6 2 T27 2 T48 2
auto[3489660928:3623878655] auto[1] 80 1 T49 2 T52 2 T145 2
auto[3623878656:3758096383] auto[0] 130 1 T3 2 T143 2 T28 2
auto[3623878656:3758096383] auto[1] 70 1 T3 2 T6 2 T60 4
auto[3758096384:3892314111] auto[0] 160 1 T48 2 T76 2 T59 2
auto[3758096384:3892314111] auto[1] 62 1 T6 2 T17 4 T52 2
auto[3892314112:4026531839] auto[0] 128 1 T6 2 T363 2 T208 2
auto[3892314112:4026531839] auto[1] 88 1 T6 2 T52 2 T76 2
auto[4026531840:4160749567] auto[0] 142 1 T6 2 T60 2 T48 2
auto[4026531840:4160749567] auto[1] 80 1 T3 2 T60 2 T27 2
auto[4160749568:4294967295] auto[0] 146 1 T15 2 T54 2 T19 2
auto[4160749568:4294967295] auto[1] 58 1 T52 2 T76 2 T120 2

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