Unified Coverage Report :: Group Instance : salt_7

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2967

1

T3

18

T6

18

T15

7

auto[1]

281

1

T126

1

T127

4

T131

9

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	100	1			T6	1		T64	1		T76	1
auto[134217728:268435455]	116	1			T109	1		T60	2		T27	1
auto[268435456:402653183]	103	1			T3	1		T15	2		T28	1
auto[402653184:536870911]	101	1			T6	1		T60	1		T48	1
auto[536870912:671088639]	95	1			T6	1		T40	1		T28	1
auto[671088640:805306367]	100	1			T3	1		T6	1		T15	1
auto[805306368:939524095]	83	1			T3	1		T6	1		T15	1
auto[939524096:1073741823]	107	1			T3	1		T6	1		T60	1
auto[1073741824:1207959551]	84	1			T40	2		T209	1		T54	1
auto[1207959552:1342177279]	106	1			T3	2		T109	1		T209	1
auto[1342177280:1476395007]	128	1			T3	3		T6	1		T52	1
auto[1476395008:1610612735]	95	1			T3	1		T17	1		T27	1
auto[1610612736:1744830463]	108	1			T6	1		T49	1		T52	1
auto[1744830464:1879048191]	99	1			T6	2		T109	1		T52	1
auto[1879048192:2013265919]	116	1			T49	1		T145	1		T28	1
auto[2013265920:2147483647]	106	1			T15	1		T60	1		T48	1
auto[2147483648:2281701375]	93	1			T60	2		T49	1		T28	1
auto[2281701376:2415919103]	112	1			T3	2		T6	1		T60	1
auto[2415919104:2550136831]	104	1			T60	1		T49	1		T195	1
auto[2550136832:2684354559]	110	1			T3	1		T60	1		T27	1
auto[2684354560:2818572287]	105	1			T6	2		T60	1		T76	1
auto[2818572288:2952790015]	86	1			T3	1		T76	1		T127	1
auto[2952790016:3087007743]	76	1			T3	1		T6	1		T15	1
auto[3087007744:3221225471]	104	1			T15	1		T17	1		T363	1
auto[3221225472:3355443199]	93	1			T40	1		T27	1		T76	2
auto[3355443200:3489660927]	100	1			T49	1		T28	1		T76	1
auto[3489660928:3623878655]	113	1			T60	2		T52	1		T19	1
auto[3623878656:3758096383]	99	1			T6	1		T208	1		T64	1
auto[3758096384:3892314111]	103	1			T3	1		T6	1		T60	1
auto[3892314112:4026531839]	110	1			T3	1		T6	1		T60	2
auto[4026531840:4160749567]	94	1			T60	1		T52	1		T76	1
auto[4160749568:4294967295]	99	1			T3	1		T6	1		T17	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	96	1			T6	1		T64	1		T76	1
auto[0:134217727]	auto[1]	4	1			T244	1		T247	1		T368	2
auto[134217728:268435455]	auto[0]	110	1			T109	1		T60	2		T27	1
auto[134217728:268435455]	auto[1]	6	1			T184	1		T134	1		T257	1
auto[268435456:402653183]	auto[0]	91	1			T3	1		T15	2		T28	1
auto[268435456:402653183]	auto[1]	12	1			T134	1		T289	2		T368	1
auto[402653184:536870911]	auto[0]	93	1			T6	1		T60	1		T48	1
auto[402653184:536870911]	auto[1]	8	1			T133	1		T285	2		T315	1
auto[536870912:671088639]	auto[0]	84	1			T6	1		T40	1		T28	1
auto[536870912:671088639]	auto[1]	11	1			T127	2		T403	1		T315	1
auto[671088640:805306367]	auto[0]	89	1			T3	1		T6	1		T15	1
auto[671088640:805306367]	auto[1]	11	1			T131	1		T184	1		T244	2
auto[805306368:939524095]	auto[0]	78	1			T3	1		T6	1		T15	1
auto[805306368:939524095]	auto[1]	5	1			T257	1		T320	1		T424	1
auto[939524096:1073741823]	auto[0]	99	1			T3	1		T6	1		T60	1
auto[939524096:1073741823]	auto[1]	8	1			T131	1		T244	2		T247	1
auto[1073741824:1207959551]	auto[0]	77	1			T40	2		T209	1		T54	1
auto[1073741824:1207959551]	auto[1]	7	1			T127	1		T136	1		T257	1
auto[1207959552:1342177279]	auto[0]	95	1			T3	2		T109	1		T209	1
auto[1207959552:1342177279]	auto[1]	11	1			T132	1		T133	2		T259	1
auto[1342177280:1476395007]	auto[0]	119	1			T3	3		T6	1		T52	1
auto[1342177280:1476395007]	auto[1]	9	1			T182	1		T289	1		T333	1
auto[1476395008:1610612735]	auto[0]	89	1			T3	1		T17	1		T27	1
auto[1476395008:1610612735]	auto[1]	6	1			T131	1		T244	1		T317	1
auto[1610612736:1744830463]	auto[0]	97	1			T6	1		T49	1		T52	1
auto[1610612736:1744830463]	auto[1]	11	1			T131	1		T184	1		T317	1
auto[1744830464:1879048191]	auto[0]	92	1			T6	2		T109	1		T52	1
auto[1744830464:1879048191]	auto[1]	7	1			T184	1		T320	3		T368	1
auto[1879048192:2013265919]	auto[0]	104	1			T49	1		T145	1		T28	1
auto[1879048192:2013265919]	auto[1]	12	1			T184	1		T352	2		T257	1
auto[2013265920:2147483647]	auto[0]	94	1			T15	1		T60	1		T48	1
auto[2013265920:2147483647]	auto[1]	12	1			T131	2		T244	1		T352	1
auto[2147483648:2281701375]	auto[0]	82	1			T60	2		T49	1		T28	1
auto[2147483648:2281701375]	auto[1]	11	1			T131	1		T135	1		T257	1
auto[2281701376:2415919103]	auto[0]	103	1			T3	2		T6	1		T60	1
auto[2281701376:2415919103]	auto[1]	9	1			T244	1		T317	1		T352	1
auto[2415919104:2550136831]	auto[0]	96	1			T60	1		T49	1		T195	1
auto[2415919104:2550136831]	auto[1]	8	1			T317	1		T308	1		T257	1
auto[2550136832:2684354559]	auto[0]	99	1			T3	1		T60	1		T27	1
auto[2550136832:2684354559]	auto[1]	11	1			T247	1		T403	1		T315	1
auto[2684354560:2818572287]	auto[0]	95	1			T6	2		T60	1		T76	1
auto[2684354560:2818572287]	auto[1]	10	1			T257	3		T368	1		T315	1
auto[2818572288:2952790015]	auto[0]	78	1			T3	1		T76	1		T127	1
auto[2818572288:2952790015]	auto[1]	8	1			T315	1		T256	2		T424	1
auto[2952790016:3087007743]	auto[0]	70	1			T3	1		T6	1		T15	1
auto[2952790016:3087007743]	auto[1]	6	1			T374	1		T256	1		T432	1
auto[3087007744:3221225471]	auto[0]	95	1			T15	1		T17	1		T363	1
auto[3087007744:3221225471]	auto[1]	9	1			T126	1		T368	1		T256	2
auto[3221225472:3355443199]	auto[0]	81	1			T40	1		T27	1		T76	2
auto[3221225472:3355443199]	auto[1]	12	1			T184	1		T244	1		T247	1
auto[3355443200:3489660927]	auto[0]	91	1			T49	1		T28	1		T76	1
auto[3355443200:3489660927]	auto[1]	9	1			T184	1		T368	2		T403	1
auto[3489660928:3623878655]	auto[0]	101	1			T60	2		T52	1		T19	1
auto[3489660928:3623878655]	auto[1]	12	1			T127	1		T134	1		T136	1
auto[3623878656:3758096383]	auto[0]	88	1			T6	1		T208	1		T64	1
auto[3623878656:3758096383]	auto[1]	11	1			T184	1		T403	3		T374	2
auto[3758096384:3892314111]	auto[0]	94	1			T3	1		T6	1		T60	1
auto[3758096384:3892314111]	auto[1]	9	1			T131	1		T247	1		T352	1
auto[3892314112:4026531839]	auto[0]	105	1			T3	1		T6	1		T60	2
auto[3892314112:4026531839]	auto[1]	5	1			T131	1		T374	1		T241	1
auto[4026531840:4160749567]	auto[0]	87	1			T60	1		T52	1		T76	1
auto[4026531840:4160749567]	auto[1]	7	1			T257	1		T289	1		T403	1
auto[4160749568:4294967295]	auto[0]	95	1			T3	1		T6	1		T17	1
auto[4160749568:4294967295]	auto[1]	4	1			T244	1		T368	1		T277	1