Unified Coverage Report :: Group Instance : attest_sw_binding_7

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1553

1

T3

13

T6

10

T15

7

auto[1]

1827

1

T3

8

T6

13

T17

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	121	1			T6	2		T53	1		T60	1
auto[134217728:268435455]	95	1			T3	2		T15	1		T40	1
auto[268435456:402653183]	104	1			T3	1		T6	2		T15	1
auto[402653184:536870911]	87	1			T3	1		T6	2		T76	2
auto[536870912:671088639]	111	1			T3	2		T143	1		T76	1
auto[671088640:805306367]	105	1			T6	1		T60	1		T48	1
auto[805306368:939524095]	123	1			T3	1		T6	1		T54	1
auto[939524096:1073741823]	87	1			T48	1		T55	1		T205	1
auto[1073741824:1207959551]	127	1			T60	1		T27	1		T143	1
auto[1207959552:1342177279]	100	1			T6	1		T251	1		T76	1
auto[1342177280:1476395007]	87	1			T6	1		T17	1		T109	1
auto[1476395008:1610612735]	114	1			T3	1		T6	1		T145	1
auto[1610612736:1744830463]	110	1			T3	2		T28	2		T208	1
auto[1744830464:1879048191]	126	1			T3	1		T6	1		T60	1
auto[1879048192:2013265919]	108	1			T3	1		T17	1		T60	1
auto[2013265920:2147483647]	104	1			T3	1		T6	1		T15	1
auto[2147483648:2281701375]	90	1			T27	1		T52	1		T363	1
auto[2281701376:2415919103]	108	1			T6	1		T60	1		T28	1
auto[2415919104:2550136831]	89	1			T3	1		T6	1		T208	1
auto[2550136832:2684354559]	103	1			T3	2		T53	1		T48	1
auto[2684354560:2818572287]	100	1			T6	1		T40	1		T60	1
auto[2818572288:2952790015]	101	1			T3	1		T60	1		T195	1
auto[2952790016:3087007743]	110	1			T3	1		T15	1		T27	1
auto[3087007744:3221225471]	90	1			T17	1		T48	1		T49	1
auto[3221225472:3355443199]	112	1			T6	3		T60	2		T28	1
auto[3355443200:3489660927]	102	1			T60	1		T27	1		T49	1
auto[3489660928:3623878655]	106	1			T60	1		T28	1		T251	1
auto[3623878656:3758096383]	108	1			T3	1		T6	1		T17	1
auto[3758096384:3892314111]	108	1			T3	1		T143	2		T206	1
auto[3892314112:4026531839]	121	1			T6	1		T40	1		T60	1
auto[4026531840:4160749567]	112	1			T15	2		T60	2		T52	1
auto[4160749568:4294967295]	111	1			T3	1		T6	2		T15	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	68	1			T6	2		T28	1		T193	1
auto[0:134217727]	auto[1]	53	1			T53	1		T60	1		T28	1
auto[134217728:268435455]	auto[0]	43	1			T3	1		T15	1		T205	1
auto[134217728:268435455]	auto[1]	52	1			T3	1		T40	1		T145	1
auto[268435456:402653183]	auto[0]	50	1			T3	1		T6	1		T15	1
auto[268435456:402653183]	auto[1]	54	1			T6	1		T53	1		T60	1
auto[402653184:536870911]	auto[0]	43	1			T6	1		T76	2		T275	2
auto[402653184:536870911]	auto[1]	44	1			T3	1		T6	1		T131	1
auto[536870912:671088639]	auto[0]	54	1			T3	1		T23	1		T59	1
auto[536870912:671088639]	auto[1]	57	1			T3	1		T143	1		T76	1
auto[671088640:805306367]	auto[0]	45	1			T48	1		T69	1		T59	1
auto[671088640:805306367]	auto[1]	60	1			T6	1		T60	1		T251	1
auto[805306368:939524095]	auto[0]	52	1			T54	1		T66	1		T123	1
auto[805306368:939524095]	auto[1]	71	1			T3	1		T6	1		T55	1
auto[939524096:1073741823]	auto[0]	39	1			T205	1		T76	1		T197	1
auto[939524096:1073741823]	auto[1]	48	1			T48	1		T55	1		T19	1
auto[1073741824:1207959551]	auto[0]	61	1			T27	1		T143	1		T49	2
auto[1073741824:1207959551]	auto[1]	66	1			T60	1		T28	1		T119	1
auto[1207959552:1342177279]	auto[0]	43	1			T88	1		T120	2		T185	1
auto[1207959552:1342177279]	auto[1]	57	1			T6	1		T251	1		T76	1
auto[1342177280:1476395007]	auto[0]	36	1			T28	1		T208	2		T67	1
auto[1342177280:1476395007]	auto[1]	51	1			T6	1		T17	1		T109	1
auto[1476395008:1610612735]	auto[0]	56	1			T3	1		T54	1		T66	1
auto[1476395008:1610612735]	auto[1]	58	1			T6	1		T145	1		T212	1
auto[1610612736:1744830463]	auto[0]	53	1			T3	1		T208	1		T101	1
auto[1610612736:1744830463]	auto[1]	57	1			T3	1		T28	2		T61	1
auto[1744830464:1879048191]	auto[0]	49	1			T3	1		T6	1		T52	1
auto[1744830464:1879048191]	auto[1]	77	1			T60	1		T251	1		T363	1
auto[1879048192:2013265919]	auto[0]	50	1			T3	1		T251	1		T209	1
auto[1879048192:2013265919]	auto[1]	58	1			T17	1		T60	1		T49	1
auto[2013265920:2147483647]	auto[0]	44	1			T15	1		T49	1		T52	1
auto[2013265920:2147483647]	auto[1]	60	1			T3	1		T6	1		T28	1
auto[2147483648:2281701375]	auto[0]	38	1			T27	1		T52	1		T363	1
auto[2147483648:2281701375]	auto[1]	52	1			T25	1		T66	1		T337	1
auto[2281701376:2415919103]	auto[0]	54	1			T6	1		T90	1		T25	1
auto[2281701376:2415919103]	auto[1]	54	1			T60	1		T28	1		T61	1
auto[2415919104:2550136831]	auto[0]	41	1			T3	1		T69	1		T58	1
auto[2415919104:2550136831]	auto[1]	48	1			T6	1		T208	1		T204	1
auto[2550136832:2684354559]	auto[0]	42	1			T3	2		T49	2		T54	1
auto[2550136832:2684354559]	auto[1]	61	1			T53	1		T48	1		T28	1
auto[2684354560:2818572287]	auto[0]	54	1			T6	1		T60	1		T127	1
auto[2684354560:2818572287]	auto[1]	46	1			T40	1		T126	1		T71	1
auto[2818572288:2952790015]	auto[0]	39	1			T60	1		T195	1		T58	1
auto[2818572288:2952790015]	auto[1]	62	1			T3	1		T104	1		T121	1
auto[2952790016:3087007743]	auto[0]	59	1			T15	1		T27	1		T48	1
auto[2952790016:3087007743]	auto[1]	51	1			T3	1		T204	1		T126	1
auto[3087007744:3221225471]	auto[0]	35	1			T49	1		T28	1		T76	1
auto[3087007744:3221225471]	auto[1]	55	1			T17	1		T48	1		T131	1
auto[3221225472:3355443199]	auto[0]	47	1			T6	2		T60	1		T28	1
auto[3221225472:3355443199]	auto[1]	65	1			T6	1		T60	1		T196	1
auto[3355443200:3489660927]	auto[0]	52	1			T27	1		T49	1		T363	1
auto[3355443200:3489660927]	auto[1]	50	1			T60	1		T101	1		T66	1
auto[3489660928:3623878655]	auto[0]	49	1			T58	1		T275	1		T120	1
auto[3489660928:3623878655]	auto[1]	57	1			T60	1		T28	1		T251	1
auto[3623878656:3758096383]	auto[0]	45	1			T3	1		T60	2		T52	1
auto[3623878656:3758096383]	auto[1]	63	1			T6	1		T17	1		T109	1
auto[3758096384:3892314111]	auto[0]	48	1			T3	1		T143	1		T206	1
auto[3758096384:3892314111]	auto[1]	60	1			T143	1		T102	1		T186	1
auto[3892314112:4026531839]	auto[0]	48	1			T48	1		T76	1		T193	1
auto[3892314112:4026531839]	auto[1]	73	1			T6	1		T40	1		T60	1
auto[4026531840:4160749567]	auto[0]	53	1			T15	2		T60	1		T52	1
auto[4026531840:4160749567]	auto[1]	59	1			T60	1		T61	1		T126	1
auto[4160749568:4294967295]	auto[0]	63	1			T3	1		T6	1		T15	1
auto[4160749568:4294967295]	auto[1]	48	1			T6	1		T40	1		T205	2