Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6972

1

T3

32

T6

38

T15

14

auto[1]

303

1

T126

4

T127

2

T131

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	2895	1			T3	13		T6	15		T15	6
auto[134217728:268435455]	168	1			T6	1		T28	1		T76	1
auto[268435456:402653183]	175	1			T3	1		T15	1		T60	2
auto[402653184:536870911]	169	1			T3	1		T6	2		T27	1
auto[536870912:671088639]	137	1			T27	1		T49	1		T52	2
auto[671088640:805306367]	151	1			T6	2		T40	1		T27	1
auto[805306368:939524095]	152	1			T15	1		T363	1		T76	3
auto[939524096:1073741823]	153	1			T60	1		T49	1		T28	2
auto[1073741824:1207959551]	135	1			T6	1		T251	1		T76	1
auto[1207959552:1342177279]	126	1			T3	3		T6	1		T15	1
auto[1342177280:1476395007]	152	1			T6	2		T60	1		T208	1
auto[1476395008:1610612735]	129	1			T6	1		T60	1		T28	1
auto[1610612736:1744830463]	125	1			T3	2		T17	1		T40	1
auto[1744830464:1879048191]	145	1			T6	1		T52	1		T76	2
auto[1879048192:2013265919]	136	1			T17	1		T27	1		T251	1
auto[2013265920:2147483647]	137	1			T6	2		T60	1		T209	1
auto[2147483648:2281701375]	115	1			T3	1		T6	3		T363	1
auto[2281701376:2415919103]	126	1			T3	2		T6	1		T60	1
auto[2415919104:2550136831]	120	1			T17	1		T40	1		T60	1
auto[2550136832:2684354559]	115	1			T3	1		T6	2		T40	1
auto[2684354560:2818572287]	133	1			T3	1		T40	1		T52	1
auto[2818572288:2952790015]	135	1			T53	1		T52	1		T208	1
auto[2952790016:3087007743]	147	1			T3	1		T6	1		T60	1
auto[3087007744:3221225471]	142	1			T3	1		T60	2		T28	2
auto[3221225472:3355443199]	128	1			T3	1		T6	1		T15	1
auto[3355443200:3489660927]	157	1			T3	1		T60	2		T52	1
auto[3489660928:3623878655]	153	1			T6	1		T15	1		T40	1
auto[3623878656:3758096383]	115	1			T6	1		T60	1		T28	1
auto[3758096384:3892314111]	138	1			T3	2		T60	1		T49	1
auto[3892314112:4026531839]	152	1			T109	1		T60	3		T49	1
auto[4026531840:4160749567]	154	1			T3	1		T15	1		T53	1
auto[4160749568:4294967295]	160	1			T15	2		T109	1		T251	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	2883	1			T3	13		T6	15		T15	6
auto[0:134217727]	auto[1]	12	1			T131	1		T184	1		T133	1
auto[134217728:268435455]	auto[0]	162	1			T6	1		T28	1		T76	1
auto[134217728:268435455]	auto[1]	6	1			T132	1		T320	1		T376	1
auto[268435456:402653183]	auto[0]	165	1			T3	1		T15	1		T60	2
auto[268435456:402653183]	auto[1]	10	1			T257	1		T320	1		T376	1
auto[402653184:536870911]	auto[0]	158	1			T3	1		T6	2		T27	1
auto[402653184:536870911]	auto[1]	11	1			T182	2		T136	1		T308	2
auto[536870912:671088639]	auto[0]	131	1			T27	1		T49	1		T52	2
auto[536870912:671088639]	auto[1]	6	1			T244	1		T133	1		T247	1
auto[671088640:805306367]	auto[0]	142	1			T6	2		T40	1		T27	1
auto[671088640:805306367]	auto[1]	9	1			T126	1		T184	1		T133	1
auto[805306368:939524095]	auto[0]	142	1			T15	1		T363	1		T76	3
auto[805306368:939524095]	auto[1]	10	1			T182	1		T244	2		T317	1
auto[939524096:1073741823]	auto[0]	146	1			T60	1		T49	1		T28	2
auto[939524096:1073741823]	auto[1]	7	1			T136	1		T289	1		T424	1
auto[1073741824:1207959551]	auto[0]	127	1			T6	1		T251	1		T76	1
auto[1073741824:1207959551]	auto[1]	8	1			T184	3		T136	1		T257	1
auto[1207959552:1342177279]	auto[0]	122	1			T3	3		T6	1		T15	1
auto[1207959552:1342177279]	auto[1]	4	1			T285	1		T424	1		T359	1
auto[1342177280:1476395007]	auto[0]	140	1			T6	2		T60	1		T208	1
auto[1342177280:1476395007]	auto[1]	12	1			T132	1		T247	1		T136	2
auto[1476395008:1610612735]	auto[0]	115	1			T6	1		T60	1		T28	1
auto[1476395008:1610612735]	auto[1]	14	1			T184	1		T135	1		T257	1
auto[1610612736:1744830463]	auto[0]	118	1			T3	2		T17	1		T40	1
auto[1610612736:1744830463]	auto[1]	7	1			T126	1		T184	1		T257	1
auto[1744830464:1879048191]	auto[0]	135	1			T6	1		T52	1		T76	2
auto[1744830464:1879048191]	auto[1]	10	1			T126	1		T184	3		T285	1
auto[1879048192:2013265919]	auto[0]	123	1			T17	1		T27	1		T251	1
auto[1879048192:2013265919]	auto[1]	13	1			T132	2		T244	1		T247	1
auto[2013265920:2147483647]	auto[0]	131	1			T6	2		T60	1		T209	1
auto[2013265920:2147483647]	auto[1]	6	1			T131	1		T368	1		T376	1
auto[2147483648:2281701375]	auto[0]	102	1			T3	1		T6	3		T363	1
auto[2147483648:2281701375]	auto[1]	13	1			T131	2		T317	1		T352	1
auto[2281701376:2415919103]	auto[0]	122	1			T3	2		T6	1		T60	1
auto[2281701376:2415919103]	auto[1]	4	1			T133	1		T368	1		T416	1
auto[2415919104:2550136831]	auto[0]	115	1			T17	1		T40	1		T60	1
auto[2415919104:2550136831]	auto[1]	5	1			T134	1		T333	1		T368	1
auto[2550136832:2684354559]	auto[0]	105	1			T3	1		T6	2		T40	1
auto[2550136832:2684354559]	auto[1]	10	1			T127	1		T184	1		T257	1
auto[2684354560:2818572287]	auto[0]	124	1			T3	1		T40	1		T52	1
auto[2684354560:2818572287]	auto[1]	9	1			T184	1		T317	1		T135	1
auto[2818572288:2952790015]	auto[0]	123	1			T53	1		T52	1		T208	1
auto[2818572288:2952790015]	auto[1]	12	1			T259	1		T285	1		T403	1
auto[2952790016:3087007743]	auto[0]	140	1			T3	1		T6	1		T60	1
auto[2952790016:3087007743]	auto[1]	7	1			T315	1		T424	1		T425	1
auto[3087007744:3221225471]	auto[0]	130	1			T3	1		T60	2		T28	2
auto[3087007744:3221225471]	auto[1]	12	1			T182	1		T184	1		T244	1
auto[3221225472:3355443199]	auto[0]	118	1			T3	1		T6	1		T15	1
auto[3221225472:3355443199]	auto[1]	10	1			T182	1		T184	1		T244	1
auto[3355443200:3489660927]	auto[0]	142	1			T3	1		T60	2		T52	1
auto[3355443200:3489660927]	auto[1]	15	1			T184	1		T244	1		T136	1
auto[3489660928:3623878655]	auto[0]	144	1			T6	1		T15	1		T40	1
auto[3489660928:3623878655]	auto[1]	9	1			T135	1		T352	1		T320	2
auto[3623878656:3758096383]	auto[0]	104	1			T6	1		T60	1		T28	1
auto[3623878656:3758096383]	auto[1]	11	1			T133	1		T368	1		T315	2
auto[3758096384:3892314111]	auto[0]	130	1			T3	2		T60	1		T49	1
auto[3758096384:3892314111]	auto[1]	8	1			T244	1		T352	1		T289	1
auto[3892314112:4026531839]	auto[0]	138	1			T109	1		T60	3		T49	1
auto[3892314112:4026531839]	auto[1]	14	1			T126	1		T244	1		T247	1
auto[4026531840:4160749567]	auto[0]	145	1			T3	1		T15	1		T53	1
auto[4026531840:4160749567]	auto[1]	9	1			T127	1		T244	1		T133	1
auto[4160749568:4294967295]	auto[0]	150	1			T15	2		T109	1		T251	2
auto[4160749568:4294967295]	auto[1]	10	1			T244	1		T133	1		T289	1