Unified Coverage Report :: Group Instance : max_owner_int_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4560

1

T3

22

T6

32

T15

10

auto[1]

2198

1

T3

20

T6

14

T15

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	220	1			T3	2		T6	4		T48	2
auto[134217728:268435455]	204	1			T3	4		T6	6		T17	4
auto[268435456:402653183]	180	1			T193	2		T119	2		T195	2
auto[402653184:536870911]	228	1			T6	4		T60	2		T28	2
auto[536870912:671088639]	216	1			T15	2		T48	2		T76	2
auto[671088640:805306367]	230	1			T3	2		T6	4		T48	2
auto[805306368:939524095]	224	1			T40	2		T60	4		T145	2
auto[939524096:1073741823]	180	1			T6	2		T109	2		T60	2
auto[1073741824:1207959551]	216	1			T3	4		T17	2		T109	2
auto[1207959552:1342177279]	200	1			T15	2		T28	2		T76	2
auto[1342177280:1476395007]	176	1			T3	4		T6	2		T15	2
auto[1476395008:1610612735]	240	1			T3	2		T6	2		T61	2
auto[1610612736:1744830463]	212	1			T48	4		T49	2		T208	2
auto[1744830464:1879048191]	186	1			T251	2		T205	2		T203	2
auto[1879048192:2013265919]	238	1			T60	2		T143	2		T28	2
auto[2013265920:2147483647]	216	1			T6	4		T15	2		T53	2
auto[2147483648:2281701375]	206	1			T6	2		T60	2		T143	2
auto[2281701376:2415919103]	224	1			T3	2		T6	6		T49	2
auto[2415919104:2550136831]	228	1			T15	2		T60	2		T119	2
auto[2550136832:2684354559]	194	1			T3	2		T60	2		T143	2
auto[2684354560:2818572287]	188	1			T3	2		T109	2		T48	2
auto[2818572288:2952790015]	188	1			T3	2		T6	2		T15	2
auto[2952790016:3087007743]	232	1			T3	2		T6	2		T60	4
auto[3087007744:3221225471]	222	1			T3	2		T60	2		T52	2
auto[3221225472:3355443199]	270	1			T3	2		T15	2		T40	4
auto[3355443200:3489660927]	230	1			T53	2		T60	8		T27	2
auto[3489660928:3623878655]	168	1			T27	4		T49	2		T209	4
auto[3623878656:3758096383]	204	1			T3	6		T17	2		T76	2
auto[3758096384:3892314111]	216	1			T6	2		T48	2		T143	2
auto[3892314112:4026531839]	222	1			T6	2		T40	2		T203	2
auto[4026531840:4160749567]	188	1			T3	2		T6	2		T53	2
auto[4160749568:4294967295]	212	1			T3	2		T27	2		T251	4

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	154	1			T3	2		T6	4		T48	2
auto[0:134217727]	auto[1]	66	1			T77	2		T121	2		T7	2
auto[134217728:268435455]	auto[0]	138	1			T3	4		T6	4		T17	2
auto[134217728:268435455]	auto[1]	66	1			T6	2		T17	2		T121	2
auto[268435456:402653183]	auto[0]	118	1			T193	2		T119	2		T88	2
auto[268435456:402653183]	auto[1]	62	1			T195	2		T101	2		T67	2
auto[402653184:536870911]	auto[0]	148	1			T6	4		T363	2		T76	4
auto[402653184:536870911]	auto[1]	80	1			T60	2		T28	2		T58	2
auto[536870912:671088639]	auto[0]	154	1			T76	2		T197	2		T218	2
auto[536870912:671088639]	auto[1]	62	1			T15	2		T48	2		T120	6
auto[671088640:805306367]	auto[0]	168	1			T6	2		T48	2		T28	2
auto[671088640:805306367]	auto[1]	62	1			T3	2		T6	2		T76	2
auto[805306368:939524095]	auto[0]	142	1			T40	2		T60	4		T208	2
auto[805306368:939524095]	auto[1]	82	1			T145	2		T54	2		T208	2
auto[939524096:1073741823]	auto[0]	116	1			T109	2		T60	2		T49	2
auto[939524096:1073741823]	auto[1]	64	1			T6	2		T49	2		T96	2
auto[1073741824:1207959551]	auto[0]	126	1			T17	2		T28	2		T251	2
auto[1073741824:1207959551]	auto[1]	90	1			T3	4		T109	2		T143	2
auto[1207959552:1342177279]	auto[0]	136	1			T15	2		T76	2		T204	2
auto[1207959552:1342177279]	auto[1]	64	1			T28	2		T131	4		T66	2
auto[1342177280:1476395007]	auto[0]	112	1			T15	2		T60	2		T52	2
auto[1342177280:1476395007]	auto[1]	64	1			T3	4		T6	2		T251	2
auto[1476395008:1610612735]	auto[0]	156	1			T6	2		T76	2		T90	2
auto[1476395008:1610612735]	auto[1]	84	1			T3	2		T61	2		T206	2
auto[1610612736:1744830463]	auto[0]	156	1			T48	4		T49	2		T208	2
auto[1610612736:1744830463]	auto[1]	56	1			T76	2		T399	2		T275	2
auto[1744830464:1879048191]	auto[0]	138	1			T251	2		T205	2		T330	2
auto[1744830464:1879048191]	auto[1]	48	1			T203	2		T427	2		T428	2
auto[1879048192:2013265919]	auto[0]	160	1			T60	2		T143	2		T76	2
auto[1879048192:2013265919]	auto[1]	78	1			T28	2		T275	4		T420	2
auto[2013265920:2147483647]	auto[0]	170	1			T6	4		T15	2		T53	2
auto[2013265920:2147483647]	auto[1]	46	1			T28	2		T212	2		T104	2
auto[2147483648:2281701375]	auto[0]	124	1			T143	2		T49	2		T52	2
auto[2147483648:2281701375]	auto[1]	82	1			T6	2		T60	2		T126	2
auto[2281701376:2415919103]	auto[0]	154	1			T3	2		T6	4		T49	2
auto[2281701376:2415919103]	auto[1]	70	1			T6	2		T145	2		T41	2
auto[2415919104:2550136831]	auto[0]	162	1			T15	2		T60	2		T330	2
auto[2415919104:2550136831]	auto[1]	66	1			T119	2		T197	2		T58	2
auto[2550136832:2684354559]	auto[0]	140	1			T3	2		T143	2		T28	2
auto[2550136832:2684354559]	auto[1]	54	1			T60	2		T251	2		T54	2
auto[2684354560:2818572287]	auto[0]	132	1			T48	2		T70	2		T428	2
auto[2684354560:2818572287]	auto[1]	56	1			T3	2		T109	2		T54	2
auto[2818572288:2952790015]	auto[0]	124	1			T15	2		T27	2		T209	2
auto[2818572288:2952790015]	auto[1]	64	1			T3	2		T6	2		T55	2
auto[2952790016:3087007743]	auto[0]	170	1			T3	2		T6	2		T60	4
auto[2952790016:3087007743]	auto[1]	62	1			T49	4		T28	2		T61	2
auto[3087007744:3221225471]	auto[0]	140	1			T3	2		T60	2		T52	2
auto[3087007744:3221225471]	auto[1]	82	1			T61	2		T119	2		T131	2
auto[3221225472:3355443199]	auto[0]	176	1			T3	2		T40	4		T209	2
auto[3221225472:3355443199]	auto[1]	94	1			T15	2		T28	4		T54	2
auto[3355443200:3489660927]	auto[0]	148	1			T60	2		T27	2		T52	2
auto[3355443200:3489660927]	auto[1]	82	1			T53	2		T60	6		T49	2
auto[3489660928:3623878655]	auto[0]	110	1			T27	2		T49	2		T209	2
auto[3489660928:3623878655]	auto[1]	58	1			T27	2		T209	2		T195	2
auto[3623878656:3758096383]	auto[0]	134	1			T3	4		T204	4		T330	2
auto[3623878656:3758096383]	auto[1]	70	1			T3	2		T17	2		T76	2
auto[3758096384:3892314111]	auto[0]	150	1			T6	2		T48	2		T143	2
auto[3758096384:3892314111]	auto[1]	66	1			T145	2		T205	2		T127	2
auto[3892314112:4026531839]	auto[0]	134	1			T6	2		T203	2		T76	2
auto[3892314112:4026531839]	auto[1]	88	1			T40	2		T204	2		T131	2
auto[4026531840:4160749567]	auto[0]	120	1			T3	2		T6	2		T53	2
auto[4026531840:4160749567]	auto[1]	68	1			T60	2		T52	2		T76	2
auto[4160749568:4294967295]	auto[0]	150	1			T27	2		T208	2		T64	2
auto[4160749568:4294967295]	auto[1]	62	1			T3	2		T251	4		T196	2