Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.73 99.03 98.15 98.37 100.00 99.02 98.41 91.17


Total test records in report: 1090
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T1003 /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.1572149630 May 05 02:17:43 PM PDT 24 May 05 02:17:45 PM PDT 24 78238284 ps
T1004 /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1142574217 May 05 02:17:51 PM PDT 24 May 05 02:17:53 PM PDT 24 476646679 ps
T1005 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.330203089 May 05 02:17:34 PM PDT 24 May 05 02:17:38 PM PDT 24 142969154 ps
T1006 /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.2380079406 May 05 02:17:11 PM PDT 24 May 05 02:17:13 PM PDT 24 52589938 ps
T1007 /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1170044856 May 05 02:17:25 PM PDT 24 May 05 02:17:28 PM PDT 24 554079222 ps
T1008 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.4201781899 May 05 02:17:33 PM PDT 24 May 05 02:17:40 PM PDT 24 291191802 ps
T1009 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.1741786609 May 05 02:17:24 PM PDT 24 May 05 02:17:26 PM PDT 24 54323130 ps
T1010 /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.272509717 May 05 02:17:11 PM PDT 24 May 05 02:17:13 PM PDT 24 37764011 ps
T1011 /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.1767434186 May 05 02:17:34 PM PDT 24 May 05 02:17:35 PM PDT 24 14186089 ps
T1012 /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2750172788 May 05 02:17:20 PM PDT 24 May 05 02:17:25 PM PDT 24 221285751 ps
T1013 /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.1737222445 May 05 02:17:16 PM PDT 24 May 05 02:17:28 PM PDT 24 517975883 ps
T1014 /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.3012416874 May 05 02:17:21 PM PDT 24 May 05 02:17:23 PM PDT 24 20547529 ps
T1015 /workspace/coverage/cover_reg_top/1.keymgr_intr_test.144595554 May 05 02:17:09 PM PDT 24 May 05 02:17:10 PM PDT 24 40326249 ps
T1016 /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.3528688712 May 05 02:17:12 PM PDT 24 May 05 02:17:15 PM PDT 24 287023998 ps
T1017 /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.706955350 May 05 02:17:15 PM PDT 24 May 05 02:17:21 PM PDT 24 2505012168 ps
T1018 /workspace/coverage/cover_reg_top/37.keymgr_intr_test.3411762998 May 05 02:17:52 PM PDT 24 May 05 02:17:53 PM PDT 24 25282358 ps
T1019 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3852031247 May 05 02:17:10 PM PDT 24 May 05 02:17:16 PM PDT 24 180624802 ps
T1020 /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1080738483 May 05 02:17:39 PM PDT 24 May 05 02:17:41 PM PDT 24 50103992 ps
T1021 /workspace/coverage/cover_reg_top/7.keymgr_intr_test.2468337860 May 05 02:17:21 PM PDT 24 May 05 02:17:22 PM PDT 24 27128819 ps
T1022 /workspace/coverage/cover_reg_top/45.keymgr_intr_test.1146160136 May 05 02:17:56 PM PDT 24 May 05 02:17:58 PM PDT 24 9401771 ps
T1023 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2883500514 May 05 02:17:39 PM PDT 24 May 05 02:17:43 PM PDT 24 299956750 ps
T1024 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.1584809212 May 05 02:17:41 PM PDT 24 May 05 02:17:54 PM PDT 24 344689735 ps
T1025 /workspace/coverage/cover_reg_top/24.keymgr_intr_test.3384890648 May 05 02:17:54 PM PDT 24 May 05 02:17:55 PM PDT 24 12376565 ps
T1026 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3451967944 May 05 02:17:05 PM PDT 24 May 05 02:17:08 PM PDT 24 289735286 ps
T1027 /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.949786304 May 05 02:17:26 PM PDT 24 May 05 02:17:28 PM PDT 24 110341322 ps
T1028 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.4089354334 May 05 02:17:42 PM PDT 24 May 05 02:17:52 PM PDT 24 1337497917 ps
T1029 /workspace/coverage/cover_reg_top/21.keymgr_intr_test.3930507472 May 05 02:17:50 PM PDT 24 May 05 02:17:52 PM PDT 24 26165234 ps
T1030 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.464823804 May 05 02:17:23 PM PDT 24 May 05 02:17:25 PM PDT 24 44320318 ps
T1031 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.429070028 May 05 02:17:32 PM PDT 24 May 05 02:17:35 PM PDT 24 328636692 ps
T1032 /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.900144132 May 05 02:17:50 PM PDT 24 May 05 02:17:52 PM PDT 24 93591486 ps
T1033 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.115743494 May 05 02:17:19 PM PDT 24 May 05 02:17:21 PM PDT 24 92814371 ps
T1034 /workspace/coverage/cover_reg_top/2.keymgr_intr_test.594593342 May 05 02:17:16 PM PDT 24 May 05 02:17:17 PM PDT 24 52449437 ps
T1035 /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2880491914 May 05 02:17:22 PM PDT 24 May 05 02:17:39 PM PDT 24 882177166 ps
T1036 /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.905249842 May 05 02:17:39 PM PDT 24 May 05 02:17:41 PM PDT 24 61684278 ps
T1037 /workspace/coverage/cover_reg_top/31.keymgr_intr_test.2692390276 May 05 02:17:52 PM PDT 24 May 05 02:17:53 PM PDT 24 79376938 ps
T1038 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.3111124767 May 05 02:17:24 PM PDT 24 May 05 02:17:27 PM PDT 24 365920236 ps
T1039 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.386362410 May 05 02:17:16 PM PDT 24 May 05 02:17:28 PM PDT 24 1014764525 ps
T171 /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.3702586830 May 05 02:17:29 PM PDT 24 May 05 02:17:34 PM PDT 24 213532340 ps
T1040 /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.1879915340 May 05 02:17:20 PM PDT 24 May 05 02:17:21 PM PDT 24 28013465 ps
T1041 /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.3614733963 May 05 02:17:33 PM PDT 24 May 05 02:17:36 PM PDT 24 80035265 ps
T1042 /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.1453691774 May 05 02:17:40 PM PDT 24 May 05 02:17:43 PM PDT 24 362480370 ps
T1043 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.925431689 May 05 02:17:25 PM PDT 24 May 05 02:17:36 PM PDT 24 682421483 ps
T1044 /workspace/coverage/cover_reg_top/14.keymgr_intr_test.3698885131 May 05 02:17:37 PM PDT 24 May 05 02:17:38 PM PDT 24 12066037 ps
T1045 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.726913331 May 05 02:17:19 PM PDT 24 May 05 02:17:21 PM PDT 24 269932135 ps
T1046 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.1766003433 May 05 02:17:33 PM PDT 24 May 05 02:17:34 PM PDT 24 23780308 ps
T1047 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.4129080299 May 05 02:17:18 PM PDT 24 May 05 02:17:22 PM PDT 24 355982290 ps
T1048 /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.1913666056 May 05 02:17:29 PM PDT 24 May 05 02:17:32 PM PDT 24 67783790 ps
T1049 /workspace/coverage/cover_reg_top/17.keymgr_intr_test.3727737059 May 05 02:17:44 PM PDT 24 May 05 02:17:45 PM PDT 24 40172956 ps
T1050 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.1846200811 May 05 02:17:16 PM PDT 24 May 05 02:17:23 PM PDT 24 547518606 ps
T1051 /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.1103135800 May 05 02:17:09 PM PDT 24 May 05 02:17:18 PM PDT 24 260174778 ps
T1052 /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.1656056499 May 05 02:17:55 PM PDT 24 May 05 02:17:57 PM PDT 24 84884381 ps
T1053 /workspace/coverage/cover_reg_top/8.keymgr_intr_test.2183315262 May 05 02:17:24 PM PDT 24 May 05 02:17:25 PM PDT 24 30891395 ps
T1054 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.1140124055 May 05 02:17:55 PM PDT 24 May 05 02:17:57 PM PDT 24 10328973 ps
T1055 /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.325030907 May 05 02:17:37 PM PDT 24 May 05 02:17:40 PM PDT 24 530689818 ps
T1056 /workspace/coverage/cover_reg_top/47.keymgr_intr_test.878071965 May 05 02:18:07 PM PDT 24 May 05 02:18:09 PM PDT 24 9918009 ps
T1057 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2637588939 May 05 02:17:56 PM PDT 24 May 05 02:17:57 PM PDT 24 57307228 ps
T1058 /workspace/coverage/cover_reg_top/30.keymgr_intr_test.1836241362 May 05 02:17:52 PM PDT 24 May 05 02:17:54 PM PDT 24 8168110 ps
T1059 /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.1852624731 May 05 02:17:15 PM PDT 24 May 05 02:17:17 PM PDT 24 399867551 ps
T1060 /workspace/coverage/cover_reg_top/6.keymgr_intr_test.427168636 May 05 02:17:19 PM PDT 24 May 05 02:17:20 PM PDT 24 8623611 ps
T1061 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1982020982 May 05 02:17:53 PM PDT 24 May 05 02:18:03 PM PDT 24 215750960 ps
T1062 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2104459242 May 05 02:17:43 PM PDT 24 May 05 02:17:52 PM PDT 24 176807344 ps
T1063 /workspace/coverage/cover_reg_top/35.keymgr_intr_test.134706137 May 05 02:17:54 PM PDT 24 May 05 02:17:55 PM PDT 24 9710686 ps
T1064 /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.3594444974 May 05 02:17:50 PM PDT 24 May 05 02:17:52 PM PDT 24 16066396 ps
T1065 /workspace/coverage/cover_reg_top/48.keymgr_intr_test.1824623933 May 05 02:17:56 PM PDT 24 May 05 02:17:58 PM PDT 24 14172680 ps
T1066 /workspace/coverage/cover_reg_top/27.keymgr_intr_test.1604078782 May 05 02:17:53 PM PDT 24 May 05 02:17:55 PM PDT 24 12195305 ps
T1067 /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.1516722189 May 05 02:17:17 PM PDT 24 May 05 02:17:19 PM PDT 24 54308956 ps
T1068 /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.349475255 May 05 02:17:28 PM PDT 24 May 05 02:17:31 PM PDT 24 68145704 ps
T158 /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.2330371984 May 05 02:17:10 PM PDT 24 May 05 02:17:14 PM PDT 24 119503370 ps
T1069 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2904631742 May 05 02:17:32 PM PDT 24 May 05 02:17:37 PM PDT 24 87974732 ps
T1070 /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.495570702 May 05 02:17:10 PM PDT 24 May 05 02:17:19 PM PDT 24 131185959 ps
T1071 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3233063115 May 05 02:17:42 PM PDT 24 May 05 02:17:46 PM PDT 24 931606901 ps
T1072 /workspace/coverage/cover_reg_top/36.keymgr_intr_test.3447436055 May 05 02:17:56 PM PDT 24 May 05 02:17:58 PM PDT 24 87058317 ps
T1073 /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.4069813101 May 05 02:17:42 PM PDT 24 May 05 02:17:43 PM PDT 24 182649844 ps
T1074 /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.2428803599 May 05 02:17:31 PM PDT 24 May 05 02:17:33 PM PDT 24 163583922 ps
T1075 /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3139853683 May 05 02:17:37 PM PDT 24 May 05 02:17:41 PM PDT 24 360579833 ps
T1076 /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3524103612 May 05 02:17:34 PM PDT 24 May 05 02:17:35 PM PDT 24 46130106 ps
T1077 /workspace/coverage/cover_reg_top/29.keymgr_intr_test.4087851156 May 05 02:18:02 PM PDT 24 May 05 02:18:04 PM PDT 24 40254006 ps
T1078 /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.1623488160 May 05 02:17:15 PM PDT 24 May 05 02:17:18 PM PDT 24 34648716 ps
T1079 /workspace/coverage/cover_reg_top/40.keymgr_intr_test.676964476 May 05 02:18:01 PM PDT 24 May 05 02:18:02 PM PDT 24 8344912 ps
T1080 /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.2692985184 May 05 02:17:29 PM PDT 24 May 05 02:17:31 PM PDT 24 29590132 ps
T1081 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.388353342 May 05 02:17:21 PM PDT 24 May 05 02:17:32 PM PDT 24 2575837882 ps
T1082 /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.1557073940 May 05 02:17:11 PM PDT 24 May 05 02:17:12 PM PDT 24 66829192 ps
T1083 /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.1461481141 May 05 02:17:41 PM PDT 24 May 05 02:17:43 PM PDT 24 56163904 ps
T1084 /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.10354440 May 05 02:17:12 PM PDT 24 May 05 02:17:15 PM PDT 24 104828335 ps
T1085 /workspace/coverage/cover_reg_top/11.keymgr_intr_test.22395698 May 05 02:17:27 PM PDT 24 May 05 02:17:28 PM PDT 24 22063351 ps
T1086 /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.206228754 May 05 02:17:24 PM PDT 24 May 05 02:17:29 PM PDT 24 444073158 ps
T1087 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.2933236522 May 05 02:17:52 PM PDT 24 May 05 02:17:53 PM PDT 24 37627825 ps
T1088 /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2657462769 May 05 02:17:47 PM PDT 24 May 05 02:17:50 PM PDT 24 77367949 ps
T1089 /workspace/coverage/cover_reg_top/3.keymgr_intr_test.26940673 May 05 02:17:14 PM PDT 24 May 05 02:17:15 PM PDT 24 15033382 ps
T1090 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.3935556405 May 05 02:17:24 PM PDT 24 May 05 02:17:26 PM PDT 24 155748426 ps

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.3328884344
Short name T3
Test name
Test status
Simulation time 855834641 ps
CPU time 12.91 seconds
Started May 05 02:31:08 PM PDT 24
Finished May 05 02:31:21 PM PDT 24
Peak memory 222508 kb
Host smart-1472f6c7-d83a-433e-b5cf-6f8ce6c8e1dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328884344 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.3328884344
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.1511167307
Short name T6
Test name
Test status
Simulation time 452614420 ps
CPU time 17.15 seconds
Started May 05 02:31:08 PM PDT 24
Finished May 05 02:31:26 PM PDT 24
Peak memory 214312 kb
Host smart-a2221634-7f06-4848-bf2b-6c77511f6f58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511167307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.1511167307
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.1095502616
Short name T66
Test name
Test status
Simulation time 3763821060 ps
CPU time 38.77 seconds
Started May 05 02:34:20 PM PDT 24
Finished May 05 02:35:00 PM PDT 24
Peak memory 222560 kb
Host smart-647ca6af-655c-4ad8-88cb-f811c7d31c81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095502616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.1095502616
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.1277690757
Short name T12
Test name
Test status
Simulation time 654549167 ps
CPU time 12.01 seconds
Started May 05 02:30:05 PM PDT 24
Finished May 05 02:30:17 PM PDT 24
Peak memory 229608 kb
Host smart-f936704a-9984-47a6-85cf-268198563bf3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277690757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.1277690757
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.1552661002
Short name T121
Test name
Test status
Simulation time 676393829 ps
CPU time 21.69 seconds
Started May 05 02:36:11 PM PDT 24
Finished May 05 02:36:34 PM PDT 24
Peak memory 222504 kb
Host smart-d0ea52a9-e63b-43ae-a15a-df889a4bdc52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552661002 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.1552661002
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.2083122215
Short name T50
Test name
Test status
Simulation time 758470107 ps
CPU time 20.35 seconds
Started May 05 02:34:45 PM PDT 24
Finished May 05 02:35:06 PM PDT 24
Peak memory 222392 kb
Host smart-4472c72e-d7fb-4ef5-860c-0f28a8e39a92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083122215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.2083122215
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.3340237653
Short name T76
Test name
Test status
Simulation time 3068792077 ps
CPU time 29.96 seconds
Started May 05 02:35:45 PM PDT 24
Finished May 05 02:36:15 PM PDT 24
Peak memory 220800 kb
Host smart-a77b9e4b-830a-485e-89fa-fc9741bac33a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340237653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.3340237653
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.4281762158
Short name T19
Test name
Test status
Simulation time 752295512 ps
CPU time 3.79 seconds
Started May 05 02:35:12 PM PDT 24
Finished May 05 02:35:16 PM PDT 24
Peak memory 214484 kb
Host smart-8e7c9c08-0493-4cf0-ba3f-40df78641c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281762158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.4281762158
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.1877252923
Short name T52
Test name
Test status
Simulation time 34864042 ps
CPU time 1.99 seconds
Started May 05 02:33:04 PM PDT 24
Finished May 05 02:33:06 PM PDT 24
Peak memory 214248 kb
Host smart-789effb0-2f3b-4193-ab82-8fabfe9bc838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877252923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.1877252923
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.727027278
Short name T244
Test name
Test status
Simulation time 449038395 ps
CPU time 6.3 seconds
Started May 05 02:31:11 PM PDT 24
Finished May 05 02:31:18 PM PDT 24
Peak memory 215280 kb
Host smart-fa3dc25b-b0bd-4798-9a16-cf665d2c812c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=727027278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.727027278
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.4003064445
Short name T112
Test name
Test status
Simulation time 1002364691 ps
CPU time 14.56 seconds
Started May 05 02:17:15 PM PDT 24
Finished May 05 02:17:30 PM PDT 24
Peak memory 214292 kb
Host smart-fbcdeb83-6154-4000-9a9e-3c0e37c4371a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003064445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.4003064445
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.1326234615
Short name T10
Test name
Test status
Simulation time 145203641 ps
CPU time 3.62 seconds
Started May 05 02:34:29 PM PDT 24
Finished May 05 02:34:32 PM PDT 24
Peak memory 221560 kb
Host smart-bac802ea-77d0-47ee-b05e-ce26513d51d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326234615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.1326234615
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.1781750392
Short name T403
Test name
Test status
Simulation time 24527408717 ps
CPU time 62.84 seconds
Started May 05 02:32:56 PM PDT 24
Finished May 05 02:33:59 PM PDT 24
Peak memory 215796 kb
Host smart-bcab5e14-ca19-4595-8ccf-c1e4daf4eea2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1781750392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.1781750392
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.3347802088
Short name T60
Test name
Test status
Simulation time 274526808 ps
CPU time 19.02 seconds
Started May 05 02:30:50 PM PDT 24
Finished May 05 02:31:09 PM PDT 24
Peak memory 222556 kb
Host smart-5173c511-34fb-4304-b536-87e032b0b360
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347802088 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.3347802088
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.267710602
Short name T368
Test name
Test status
Simulation time 9566766382 ps
CPU time 132.37 seconds
Started May 05 02:36:12 PM PDT 24
Finished May 05 02:38:25 PM PDT 24
Peak memory 215536 kb
Host smart-cd990c80-a306-4d56-a243-8d6e7cb217e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=267710602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.267710602
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.358616427
Short name T23
Test name
Test status
Simulation time 77239582 ps
CPU time 2.86 seconds
Started May 05 02:33:43 PM PDT 24
Finished May 05 02:33:46 PM PDT 24
Peak memory 218140 kb
Host smart-e660f1c6-c912-4341-870f-3d188fb0bf9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358616427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.358616427
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.486796470
Short name T15
Test name
Test status
Simulation time 99111942 ps
CPU time 4.55 seconds
Started May 05 02:31:06 PM PDT 24
Finished May 05 02:31:11 PM PDT 24
Peak memory 214280 kb
Host smart-4f11d2dd-c264-4922-9aae-1586f615f183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486796470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.486796470
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.1630222492
Short name T136
Test name
Test status
Simulation time 1099914625 ps
CPU time 14.22 seconds
Started May 05 02:33:13 PM PDT 24
Finished May 05 02:33:28 PM PDT 24
Peak memory 215568 kb
Host smart-afe7b889-ebaa-4cb1-9945-7d44657aab44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1630222492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.1630222492
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.2080938908
Short name T120
Test name
Test status
Simulation time 409279618 ps
CPU time 23.62 seconds
Started May 05 02:34:44 PM PDT 24
Finished May 05 02:35:08 PM PDT 24
Peak memory 220872 kb
Host smart-1dd261e5-db2c-44c7-ad11-6caeda3301f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080938908 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.2080938908
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.3738698969
Short name T374
Test name
Test status
Simulation time 1202022732 ps
CPU time 16.68 seconds
Started May 05 02:30:31 PM PDT 24
Finished May 05 02:30:48 PM PDT 24
Peak memory 214568 kb
Host smart-fdde70f9-5e50-496a-9471-a784e717fe1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3738698969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.3738698969
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.2135796173
Short name T223
Test name
Test status
Simulation time 1323626075 ps
CPU time 53.06 seconds
Started May 05 02:30:58 PM PDT 24
Finished May 05 02:31:52 PM PDT 24
Peak memory 221336 kb
Host smart-4463923d-260e-45ea-bd88-e5c031e633c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135796173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.2135796173
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.3074000655
Short name T41
Test name
Test status
Simulation time 672104874 ps
CPU time 7.37 seconds
Started May 05 02:33:53 PM PDT 24
Finished May 05 02:34:01 PM PDT 24
Peak memory 214144 kb
Host smart-9aab301a-79d4-44ba-8bc5-b15dedd329f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074000655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.3074000655
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3107636385
Short name T113
Test name
Test status
Simulation time 471580985 ps
CPU time 2.72 seconds
Started May 05 02:17:14 PM PDT 24
Finished May 05 02:17:17 PM PDT 24
Peak memory 214288 kb
Host smart-376e78d8-2bc4-4f60-94c2-5a52a62adea3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107636385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.3107636385
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.1352857937
Short name T256
Test name
Test status
Simulation time 1164174726 ps
CPU time 16.03 seconds
Started May 05 02:30:53 PM PDT 24
Finished May 05 02:31:10 PM PDT 24
Peak memory 215616 kb
Host smart-16887d26-8c6d-4f6c-a90e-6ff48f4840d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1352857937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.1352857937
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.1184401127
Short name T88
Test name
Test status
Simulation time 444306168 ps
CPU time 4.55 seconds
Started May 05 02:34:29 PM PDT 24
Finished May 05 02:34:34 PM PDT 24
Peak memory 214320 kb
Host smart-33c803c1-6215-4776-a2d1-cd085e501e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184401127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.1184401127
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.1688425642
Short name T148
Test name
Test status
Simulation time 85244722 ps
CPU time 2.8 seconds
Started May 05 02:30:44 PM PDT 24
Finished May 05 02:30:47 PM PDT 24
Peak memory 217232 kb
Host smart-b66c6212-132c-4d15-af9e-93235c2a2473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688425642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.1688425642
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.2886466580
Short name T79
Test name
Test status
Simulation time 10783399027 ps
CPU time 243.11 seconds
Started May 05 02:32:17 PM PDT 24
Finished May 05 02:36:21 PM PDT 24
Peak memory 222524 kb
Host smart-888796e0-c09c-4420-9ccb-4cd757069302
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886466580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.2886466580
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.1859293462
Short name T67
Test name
Test status
Simulation time 1869124889 ps
CPU time 40.39 seconds
Started May 05 02:31:16 PM PDT 24
Finished May 05 02:31:57 PM PDT 24
Peak memory 216592 kb
Host smart-262da883-b829-4b22-8a81-e9afa9da1c0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859293462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.1859293462
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.1423706919
Short name T359
Test name
Test status
Simulation time 733691169 ps
CPU time 10.82 seconds
Started May 05 02:32:22 PM PDT 24
Finished May 05 02:32:34 PM PDT 24
Peak memory 214400 kb
Host smart-ed07d5b0-870b-496d-8fdc-28426a09ae86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1423706919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.1423706919
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.801883421
Short name T20
Test name
Test status
Simulation time 30212240 ps
CPU time 1.34 seconds
Started May 05 02:30:03 PM PDT 24
Finished May 05 02:30:05 PM PDT 24
Peak memory 214496 kb
Host smart-ee4fe259-0d68-446a-bf67-317e61d0687f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801883421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.801883421
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.1466867991
Short name T32
Test name
Test status
Simulation time 75188025 ps
CPU time 3.28 seconds
Started May 05 02:35:37 PM PDT 24
Finished May 05 02:35:41 PM PDT 24
Peak memory 208724 kb
Host smart-addbb6b9-b6b2-4e36-929a-c22ab8f3ac78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466867991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.1466867991
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.3685712246
Short name T69
Test name
Test status
Simulation time 299323572 ps
CPU time 3.82 seconds
Started May 05 02:32:40 PM PDT 24
Finished May 05 02:32:45 PM PDT 24
Peak memory 208444 kb
Host smart-8315db66-38a0-4595-bf6e-0844520adf76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685712246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.3685712246
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.1007556199
Short name T240
Test name
Test status
Simulation time 559524333 ps
CPU time 11.47 seconds
Started May 05 02:35:42 PM PDT 24
Finished May 05 02:35:54 PM PDT 24
Peak memory 214176 kb
Host smart-580296b2-6c57-4c19-89f1-a0de93fcda80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007556199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.1007556199
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.800370430
Short name T44
Test name
Test status
Simulation time 86563690 ps
CPU time 2.62 seconds
Started May 05 02:35:58 PM PDT 24
Finished May 05 02:36:01 PM PDT 24
Peak memory 210024 kb
Host smart-77d749ba-d211-4ec8-8da4-1ca14933c540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800370430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.800370430
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.209614457
Short name T315
Test name
Test status
Simulation time 2492518381 ps
CPU time 32.96 seconds
Started May 05 02:32:31 PM PDT 24
Finished May 05 02:33:05 PM PDT 24
Peak memory 214712 kb
Host smart-440c0ab1-f750-43d1-8528-c67b23aa47af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=209614457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.209614457
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.1260661594
Short name T486
Test name
Test status
Simulation time 60809321 ps
CPU time 0.82 seconds
Started May 05 02:31:16 PM PDT 24
Finished May 05 02:31:17 PM PDT 24
Peak memory 205868 kb
Host smart-2e06b861-8006-4e88-a68c-4fd1adbb84bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260661594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.1260661594
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.2356045423
Short name T49
Test name
Test status
Simulation time 123559606 ps
CPU time 2.5 seconds
Started May 05 02:33:43 PM PDT 24
Finished May 05 02:33:47 PM PDT 24
Peak memory 214960 kb
Host smart-51d7fc36-d4b1-44c1-87c6-c6b4db3b5581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356045423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.2356045423
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.3650263150
Short name T352
Test name
Test status
Simulation time 662567002 ps
CPU time 4.49 seconds
Started May 05 02:29:45 PM PDT 24
Finished May 05 02:29:50 PM PDT 24
Peak memory 214276 kb
Host smart-3017e9a7-03e0-4908-845f-1b8f135ba64c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3650263150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.3650263150
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.1476461930
Short name T184
Test name
Test status
Simulation time 1258461922 ps
CPU time 13.49 seconds
Started May 05 02:33:23 PM PDT 24
Finished May 05 02:33:37 PM PDT 24
Peak memory 214164 kb
Host smart-0930bb57-8d95-4c3f-97f7-fe7f38bd14fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1476461930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.1476461930
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.1137263277
Short name T272
Test name
Test status
Simulation time 147423926 ps
CPU time 2.73 seconds
Started May 05 02:31:08 PM PDT 24
Finished May 05 02:31:11 PM PDT 24
Peak memory 214576 kb
Host smart-6d48fc91-2901-45f1-87aa-5bb80f69e6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137263277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.1137263277
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.3702586830
Short name T171
Test name
Test status
Simulation time 213532340 ps
CPU time 4.65 seconds
Started May 05 02:17:29 PM PDT 24
Finished May 05 02:17:34 PM PDT 24
Peak memory 205900 kb
Host smart-160f6249-384c-43ff-9b53-0ea2eb723392
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702586830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.3702586830
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.2366758837
Short name T221
Test name
Test status
Simulation time 2453725241 ps
CPU time 53.36 seconds
Started May 05 02:32:55 PM PDT 24
Finished May 05 02:33:49 PM PDT 24
Peak memory 220640 kb
Host smart-6b7e14a2-b287-41ae-9670-c391e8627aa6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366758837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.2366758837
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.250692214
Short name T268
Test name
Test status
Simulation time 33510114025 ps
CPU time 99.05 seconds
Started May 05 02:33:43 PM PDT 24
Finished May 05 02:35:23 PM PDT 24
Peak memory 222560 kb
Host smart-39b8c355-ede7-4751-a4d1-bdd3f910de56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250692214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.250692214
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.2702814928
Short name T164
Test name
Test status
Simulation time 184828795 ps
CPU time 5.64 seconds
Started May 05 02:17:38 PM PDT 24
Finished May 05 02:17:44 PM PDT 24
Peak memory 206052 kb
Host smart-842d840a-cda6-4f82-864b-ceca2a773180
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702814928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.2702814928
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.3661126727
Short name T409
Test name
Test status
Simulation time 729801876 ps
CPU time 3.16 seconds
Started May 05 02:31:59 PM PDT 24
Finished May 05 02:32:03 PM PDT 24
Peak memory 208748 kb
Host smart-e7c7b82c-dbb5-4516-8776-32bfe949f390
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661126727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.3661126727
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.730482115
Short name T539
Test name
Test status
Simulation time 154920330 ps
CPU time 3.51 seconds
Started May 05 02:34:35 PM PDT 24
Finished May 05 02:34:39 PM PDT 24
Peak memory 210676 kb
Host smart-533b88fc-edb2-43f2-bcc8-ba09cab9e3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730482115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.730482115
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.2127392975
Short name T172
Test name
Test status
Simulation time 800364537 ps
CPU time 3.21 seconds
Started May 05 02:35:05 PM PDT 24
Finished May 05 02:35:08 PM PDT 24
Peak memory 209688 kb
Host smart-b32ee0e4-ade5-4de6-86d7-b7555ec11449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127392975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.2127392975
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.4093441768
Short name T155
Test name
Test status
Simulation time 143645395 ps
CPU time 5.04 seconds
Started May 05 02:17:31 PM PDT 24
Finished May 05 02:17:37 PM PDT 24
Peak memory 214096 kb
Host smart-10315532-fa6e-4891-a624-6e2c062e0b73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093441768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.4093441768
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.4098899190
Short name T101
Test name
Test status
Simulation time 85830074 ps
CPU time 3.02 seconds
Started May 05 02:31:41 PM PDT 24
Finished May 05 02:31:44 PM PDT 24
Peak memory 214140 kb
Host smart-acaec572-65bf-43da-8193-a69c6dd6a1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098899190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.4098899190
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.4275481516
Short name T123
Test name
Test status
Simulation time 1004027999 ps
CPU time 20.67 seconds
Started May 05 02:32:36 PM PDT 24
Finished May 05 02:32:57 PM PDT 24
Peak memory 220800 kb
Host smart-f33f95f2-0e2e-4f97-8ded-aa00defcf171
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275481516 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.4275481516
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.2762356485
Short name T334
Test name
Test status
Simulation time 34171578769 ps
CPU time 56.11 seconds
Started May 05 02:33:24 PM PDT 24
Finished May 05 02:34:20 PM PDT 24
Peak memory 216396 kb
Host smart-eef82f4d-40f7-4075-b318-84d3668e5fe8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762356485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.2762356485
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.1797409973
Short name T85
Test name
Test status
Simulation time 2790062542 ps
CPU time 31.55 seconds
Started May 05 02:35:22 PM PDT 24
Finished May 05 02:35:55 PM PDT 24
Peak memory 215092 kb
Host smart-4e59e166-c620-4e3f-89b0-417bb8223d78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797409973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.1797409973
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.1812357887
Short name T430
Test name
Test status
Simulation time 1038278201 ps
CPU time 16.48 seconds
Started May 05 02:35:27 PM PDT 24
Finished May 05 02:35:44 PM PDT 24
Peak memory 215644 kb
Host smart-3e9b2136-6c45-47ec-9074-3d09943f5175
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1812357887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.1812357887
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3451967944
Short name T1026
Test name
Test status
Simulation time 289735286 ps
CPU time 2.73 seconds
Started May 05 02:17:05 PM PDT 24
Finished May 05 02:17:08 PM PDT 24
Peak memory 214192 kb
Host smart-9cf4219d-c0f1-4fd0-bf20-36ba48db33bb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451967944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.3451967944
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.2330371984
Short name T158
Test name
Test status
Simulation time 119503370 ps
CPU time 3.58 seconds
Started May 05 02:17:10 PM PDT 24
Finished May 05 02:17:14 PM PDT 24
Peak memory 214160 kb
Host smart-7c9db4e6-9a01-4301-906c-fdf60ebfff96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330371984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.2330371984
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.1117418701
Short name T168
Test name
Test status
Simulation time 287075680 ps
CPU time 7.76 seconds
Started May 05 02:17:51 PM PDT 24
Finished May 05 02:18:00 PM PDT 24
Peak memory 216592 kb
Host smart-4d160620-cfaf-4d7d-9eeb-d82e879e6d0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117418701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.1117418701
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.2557013479
Short name T162
Test name
Test status
Simulation time 174625494 ps
CPU time 3.64 seconds
Started May 05 02:17:16 PM PDT 24
Finished May 05 02:17:20 PM PDT 24
Peak memory 205792 kb
Host smart-2b299f95-30a4-4fa4-9692-589027633eb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557013479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.2557013479
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.2550436696
Short name T175
Test name
Test status
Simulation time 361735602 ps
CPU time 4.38 seconds
Started May 05 02:17:20 PM PDT 24
Finished May 05 02:17:25 PM PDT 24
Peak memory 205836 kb
Host smart-d8d6e360-2eb6-4158-a46a-d9bc4061d343
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550436696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.2550436696
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.3101117339
Short name T150
Test name
Test status
Simulation time 143578666 ps
CPU time 4.26 seconds
Started May 05 02:31:48 PM PDT 24
Finished May 05 02:31:53 PM PDT 24
Peak memory 217668 kb
Host smart-4abf2d54-39cb-4165-9ae4-f7c6f3648341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101117339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.3101117339
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.1844478063
Short name T286
Test name
Test status
Simulation time 10049398220 ps
CPU time 42.39 seconds
Started May 05 02:29:36 PM PDT 24
Finished May 05 02:30:19 PM PDT 24
Peak memory 222556 kb
Host smart-41088767-48a8-4ee9-904f-e00b88ce54ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844478063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.1844478063
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.1194104906
Short name T800
Test name
Test status
Simulation time 138148727 ps
CPU time 3.15 seconds
Started May 05 02:32:16 PM PDT 24
Finished May 05 02:32:20 PM PDT 24
Peak memory 214268 kb
Host smart-39ef0d59-1747-4d86-beaa-26b34f94d895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194104906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.1194104906
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.3079949799
Short name T81
Test name
Test status
Simulation time 5224714014 ps
CPU time 26.31 seconds
Started May 05 02:32:44 PM PDT 24
Finished May 05 02:33:11 PM PDT 24
Peak memory 223992 kb
Host smart-81b787cf-adf0-4862-9e8d-0ecf944ee11a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079949799 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.3079949799
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.664141812
Short name T559
Test name
Test status
Simulation time 2112781376 ps
CPU time 43.14 seconds
Started May 05 02:34:03 PM PDT 24
Finished May 05 02:34:46 PM PDT 24
Peak memory 215016 kb
Host smart-2690162b-b576-4b29-adb3-4160c2d81746
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664141812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.664141812
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.3628279161
Short name T320
Test name
Test status
Simulation time 236193420 ps
CPU time 12.26 seconds
Started May 05 02:34:58 PM PDT 24
Finished May 05 02:35:10 PM PDT 24
Peak memory 214236 kb
Host smart-ee634614-7e58-4cf1-9b89-f885fd6eebab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3628279161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.3628279161
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.2793182427
Short name T291
Test name
Test status
Simulation time 104146494 ps
CPU time 5.06 seconds
Started May 05 02:34:59 PM PDT 24
Finished May 05 02:35:04 PM PDT 24
Peak memory 221756 kb
Host smart-3c8d46d2-f8c7-4cc1-941a-40c57d625e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793182427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.2793182427
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.2639124262
Short name T51
Test name
Test status
Simulation time 18692380590 ps
CPU time 434.47 seconds
Started May 05 02:35:06 PM PDT 24
Finished May 05 02:42:21 PM PDT 24
Peak memory 222472 kb
Host smart-7d68802c-0cda-459a-ba1b-410be1a8284e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639124262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.2639124262
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.3201968307
Short name T366
Test name
Test status
Simulation time 80196645 ps
CPU time 3.1 seconds
Started May 05 02:35:10 PM PDT 24
Finished May 05 02:35:14 PM PDT 24
Peak memory 214192 kb
Host smart-c5b9b08c-0a21-43e9-8bd5-5255736f7c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201968307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.3201968307
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.3749526731
Short name T96
Test name
Test status
Simulation time 122082860 ps
CPU time 3.29 seconds
Started May 05 02:32:28 PM PDT 24
Finished May 05 02:32:31 PM PDT 24
Peak memory 222376 kb
Host smart-fa73be5a-4a35-4f1f-8c38-5d0273b0aff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749526731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.3749526731
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.844789923
Short name T149
Test name
Test status
Simulation time 130538327 ps
CPU time 1.93 seconds
Started May 05 02:31:36 PM PDT 24
Finished May 05 02:31:38 PM PDT 24
Peak memory 216052 kb
Host smart-d641bbf4-ea93-4143-85e1-f3eee88a9cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844789923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.844789923
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.936988897
Short name T147
Test name
Test status
Simulation time 195880491 ps
CPU time 3.63 seconds
Started May 05 02:33:08 PM PDT 24
Finished May 05 02:33:12 PM PDT 24
Peak memory 216816 kb
Host smart-93790625-b823-438e-bb62-35b7584d562e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936988897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.936988897
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.1250086304
Short name T151
Test name
Test status
Simulation time 148096304 ps
CPU time 3.93 seconds
Started May 05 02:33:34 PM PDT 24
Finished May 05 02:33:38 PM PDT 24
Peak memory 217872 kb
Host smart-8d4b58d8-987b-4e3a-89c5-eac737c2e615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250086304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.1250086304
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.318152247
Short name T153
Test name
Test status
Simulation time 175721777 ps
CPU time 3.38 seconds
Started May 05 02:34:16 PM PDT 24
Finished May 05 02:34:19 PM PDT 24
Peak memory 215708 kb
Host smart-1b91fd41-a6d1-452a-a784-223c889e57f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318152247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.318152247
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.2561258513
Short name T152
Test name
Test status
Simulation time 329498218 ps
CPU time 5.74 seconds
Started May 05 02:30:15 PM PDT 24
Finished May 05 02:30:21 PM PDT 24
Peak memory 217460 kb
Host smart-9eadae76-5a9f-493b-bf05-81e457db400d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561258513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.2561258513
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.1803567715
Short name T329
Test name
Test status
Simulation time 78365697 ps
CPU time 3.11 seconds
Started May 05 02:29:24 PM PDT 24
Finished May 05 02:29:27 PM PDT 24
Peak memory 215208 kb
Host smart-c80bcb6a-f4fb-4930-ac05-5cc3e60482b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1803567715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.1803567715
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.2305941594
Short name T914
Test name
Test status
Simulation time 106093958 ps
CPU time 2.86 seconds
Started May 05 02:29:29 PM PDT 24
Finished May 05 02:29:32 PM PDT 24
Peak memory 214380 kb
Host smart-428c0221-d2b8-4f84-87ea-d47264571e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305941594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.2305941594
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.1599364673
Short name T332
Test name
Test status
Simulation time 91601529 ps
CPU time 3.66 seconds
Started May 05 02:31:40 PM PDT 24
Finished May 05 02:31:44 PM PDT 24
Peak memory 214220 kb
Host smart-00313698-c502-4c80-a862-5e19ec9674c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1599364673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.1599364673
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.534126788
Short name T324
Test name
Test status
Simulation time 744302379 ps
CPU time 3.08 seconds
Started May 05 02:33:00 PM PDT 24
Finished May 05 02:33:03 PM PDT 24
Peak memory 214204 kb
Host smart-6c9083b7-2b05-482a-ba73-dbfb10eb76a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534126788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.534126788
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.3272782746
Short name T133
Test name
Test status
Simulation time 187383152 ps
CPU time 9.89 seconds
Started May 05 02:33:03 PM PDT 24
Finished May 05 02:33:14 PM PDT 24
Peak memory 215468 kb
Host smart-1b50e6f2-bebe-435a-81e3-b524724cef09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3272782746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.3272782746
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.667523025
Short name T37
Test name
Test status
Simulation time 3311197190 ps
CPU time 23.69 seconds
Started May 05 02:33:23 PM PDT 24
Finished May 05 02:33:47 PM PDT 24
Peak memory 207716 kb
Host smart-2ee6e453-b4d6-4d82-b5e3-d00e821daf53
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667523025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.667523025
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.1505777522
Short name T277
Test name
Test status
Simulation time 56261465 ps
CPU time 3.88 seconds
Started May 05 02:33:47 PM PDT 24
Finished May 05 02:33:51 PM PDT 24
Peak memory 215340 kb
Host smart-3f5a6d31-b083-4bc9-988c-7b70a6a2f4f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1505777522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.1505777522
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.175085748
Short name T25
Test name
Test status
Simulation time 784201777 ps
CPU time 24.33 seconds
Started May 05 02:34:37 PM PDT 24
Finished May 05 02:35:02 PM PDT 24
Peak memory 220848 kb
Host smart-217972e8-e463-44ea-89c6-b7c81f575508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175085748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.175085748
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.2376974271
Short name T241
Test name
Test status
Simulation time 105883271 ps
CPU time 3.98 seconds
Started May 05 02:36:05 PM PDT 24
Finished May 05 02:36:10 PM PDT 24
Peak memory 214952 kb
Host smart-245a8c6c-fd9a-4254-8676-1930954db703
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2376974271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.2376974271
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.3998489442
Short name T228
Test name
Test status
Simulation time 1265502272 ps
CPU time 25.64 seconds
Started May 05 02:36:15 PM PDT 24
Finished May 05 02:36:41 PM PDT 24
Peak memory 221600 kb
Host smart-4f5c037f-09e4-44ef-95b7-1091a044bf56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998489442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.3998489442
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.152685759
Short name T167
Test name
Test status
Simulation time 146943907 ps
CPU time 5.98 seconds
Started May 05 02:17:10 PM PDT 24
Finished May 05 02:17:16 PM PDT 24
Peak memory 213816 kb
Host smart-5c87b735-ba56-4374-9bfc-88c57c655569
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152685759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.
152685759
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.531369691
Short name T169
Test name
Test status
Simulation time 942649832 ps
CPU time 7.02 seconds
Started May 05 02:17:38 PM PDT 24
Finished May 05 02:17:45 PM PDT 24
Peak memory 206144 kb
Host smart-64632ce3-da04-4bab-85db-376239ae5343
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531369691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_err
.531369691
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.2281480948
Short name T176
Test name
Test status
Simulation time 102358955 ps
CPU time 5.58 seconds
Started May 05 02:17:41 PM PDT 24
Finished May 05 02:17:47 PM PDT 24
Peak memory 214020 kb
Host smart-65aa0c99-e7ab-462e-993b-6e09476d1d94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281480948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.2281480948
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.1174595758
Short name T46
Test name
Test status
Simulation time 365685105 ps
CPU time 7.75 seconds
Started May 05 02:30:13 PM PDT 24
Finished May 05 02:30:21 PM PDT 24
Peak memory 233328 kb
Host smart-a7610730-de0d-41d7-98b6-91fe0f376b88
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174595758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.1174595758
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.2696800066
Short name T160
Test name
Test status
Simulation time 138400327 ps
CPU time 2.44 seconds
Started May 05 02:35:37 PM PDT 24
Finished May 05 02:35:40 PM PDT 24
Peak memory 210172 kb
Host smart-752c8eaf-031e-4a6b-8fdc-3f7b8246b20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696800066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.2696800066
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.2832631880
Short name T90
Test name
Test status
Simulation time 95966393 ps
CPU time 3.18 seconds
Started May 05 02:30:22 PM PDT 24
Finished May 05 02:30:26 PM PDT 24
Peak memory 214212 kb
Host smart-20696620-5353-41ac-a204-2ff88c376d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832631880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.2832631880
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.3824505815
Short name T347
Test name
Test status
Simulation time 85153543 ps
CPU time 3.85 seconds
Started May 05 02:29:28 PM PDT 24
Finished May 05 02:29:33 PM PDT 24
Peak memory 214128 kb
Host smart-8f213bf5-e9a1-4717-bb14-1a9c20fed23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824505815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.3824505815
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.1986422938
Short name T231
Test name
Test status
Simulation time 77378737 ps
CPU time 2.56 seconds
Started May 05 02:29:32 PM PDT 24
Finished May 05 02:29:35 PM PDT 24
Peak memory 209664 kb
Host smart-eb5303b0-e2ca-4e8f-b1e0-dcf117c08995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986422938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.1986422938
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.1613839000
Short name T554
Test name
Test status
Simulation time 1134378205 ps
CPU time 11.47 seconds
Started May 05 02:29:24 PM PDT 24
Finished May 05 02:29:36 PM PDT 24
Peak memory 208236 kb
Host smart-3c463a65-92b4-4027-8d6d-bac5047563b5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613839000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.1613839000
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.4159601777
Short name T97
Test name
Test status
Simulation time 91516549 ps
CPU time 3.89 seconds
Started May 05 02:29:38 PM PDT 24
Finished May 05 02:29:43 PM PDT 24
Peak memory 222360 kb
Host smart-2f5c2cef-e7fc-4cf6-9a70-089cde4a8132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159601777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.4159601777
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_random.878133215
Short name T213
Test name
Test status
Simulation time 62859320 ps
CPU time 3.9 seconds
Started May 05 02:29:28 PM PDT 24
Finished May 05 02:29:32 PM PDT 24
Peak memory 207204 kb
Host smart-542a9253-5a20-4a56-8404-b6cd4c8afaae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878133215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.878133215
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.800234058
Short name T451
Test name
Test status
Simulation time 103548753 ps
CPU time 2.97 seconds
Started May 05 02:31:12 PM PDT 24
Finished May 05 02:31:16 PM PDT 24
Peak memory 206808 kb
Host smart-336aa2b6-1aa7-4ef4-b3c9-fcd3ee26c71f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800234058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.800234058
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.2460253503
Short name T227
Test name
Test status
Simulation time 677718088 ps
CPU time 4.06 seconds
Started May 05 02:31:21 PM PDT 24
Finished May 05 02:31:26 PM PDT 24
Peak memory 214312 kb
Host smart-ac863c9c-f73b-4ef3-9994-e4fde70a7c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460253503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.2460253503
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.1686308084
Short name T503
Test name
Test status
Simulation time 616773361 ps
CPU time 1.89 seconds
Started May 05 02:31:23 PM PDT 24
Finished May 05 02:31:25 PM PDT 24
Peak memory 209668 kb
Host smart-536707b1-62d9-46f1-b257-65fa4ca347c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686308084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.1686308084
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.1260307461
Short name T230
Test name
Test status
Simulation time 1374202079 ps
CPU time 42.62 seconds
Started May 05 02:32:03 PM PDT 24
Finished May 05 02:32:46 PM PDT 24
Peak memory 222452 kb
Host smart-ca6fb2d1-c77f-4fbd-bfbc-ed47c511cf7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260307461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.1260307461
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.3393306730
Short name T357
Test name
Test status
Simulation time 34279462 ps
CPU time 2.78 seconds
Started May 05 02:32:14 PM PDT 24
Finished May 05 02:32:17 PM PDT 24
Peak memory 214300 kb
Host smart-7a9ecc4d-2735-4895-ae79-52f606a35328
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3393306730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.3393306730
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.4209335868
Short name T234
Test name
Test status
Simulation time 510822762 ps
CPU time 5.06 seconds
Started May 05 02:32:33 PM PDT 24
Finished May 05 02:32:38 PM PDT 24
Peak memory 209752 kb
Host smart-ebffa22b-b9dd-434c-b7d6-25e56d16e8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209335868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.4209335868
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.1597347296
Short name T183
Test name
Test status
Simulation time 375211559 ps
CPU time 6.2 seconds
Started May 05 02:33:17 PM PDT 24
Finished May 05 02:33:24 PM PDT 24
Peak memory 209548 kb
Host smart-f6ea6258-77c3-4f32-af57-65be51eb131a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597347296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.1597347296
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.1807361769
Short name T62
Test name
Test status
Simulation time 174286543 ps
CPU time 3.24 seconds
Started May 05 02:33:37 PM PDT 24
Finished May 05 02:33:41 PM PDT 24
Peak memory 208796 kb
Host smart-9480f2fd-0891-4ae9-80fa-888c6406c31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807361769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.1807361769
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.1740830242
Short name T261
Test name
Test status
Simulation time 1171207297 ps
CPU time 16.48 seconds
Started May 05 02:34:07 PM PDT 24
Finished May 05 02:34:24 PM PDT 24
Peak memory 222428 kb
Host smart-029b0df9-d7f4-41b5-a095-fa0a43a10cfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740830242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.1740830242
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.2112966609
Short name T348
Test name
Test status
Simulation time 76225386 ps
CPU time 3.39 seconds
Started May 05 02:36:19 PM PDT 24
Finished May 05 02:36:23 PM PDT 24
Peak memory 214224 kb
Host smart-97bf1be6-25b5-40c9-a617-50ca4dfc9e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112966609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.2112966609
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.4291256416
Short name T29
Test name
Test status
Simulation time 187233706 ps
CPU time 5.16 seconds
Started May 05 02:31:09 PM PDT 24
Finished May 05 02:31:15 PM PDT 24
Peak memory 214596 kb
Host smart-04f67ed0-449f-432e-95ab-23a0463754c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291256416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.4291256416
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.495570702
Short name T1070
Test name
Test status
Simulation time 131185959 ps
CPU time 7.63 seconds
Started May 05 02:17:10 PM PDT 24
Finished May 05 02:17:19 PM PDT 24
Peak memory 205884 kb
Host smart-2a517d77-1c3f-44d7-bcfc-5ae6bf1a13c9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495570702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.495570702
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.4082422147
Short name T925
Test name
Test status
Simulation time 523878413 ps
CPU time 6.99 seconds
Started May 05 02:17:10 PM PDT 24
Finished May 05 02:17:17 PM PDT 24
Peak memory 205760 kb
Host smart-ad3b3dc5-b1e7-4f7e-8864-ae74979f51cf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082422147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.4
082422147
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.2159817623
Short name T979
Test name
Test status
Simulation time 395878934 ps
CPU time 1.2 seconds
Started May 05 02:17:10 PM PDT 24
Finished May 05 02:17:12 PM PDT 24
Peak memory 205772 kb
Host smart-d3d0e0db-bb19-4ce4-8072-408f1ee6ab5e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159817623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.2
159817623
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.1646456889
Short name T934
Test name
Test status
Simulation time 211884271 ps
CPU time 2.23 seconds
Started May 05 02:17:08 PM PDT 24
Finished May 05 02:17:11 PM PDT 24
Peak memory 214148 kb
Host smart-1d5a0aed-d3a7-41f7-9376-dfb9e83515a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646456889 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.1646456889
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.906969011
Short name T950
Test name
Test status
Simulation time 15940602 ps
CPU time 0.94 seconds
Started May 05 02:17:08 PM PDT 24
Finished May 05 02:17:10 PM PDT 24
Peak memory 205604 kb
Host smart-385f7c8e-4d4b-4a93-a21f-da34ccc24ac8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906969011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.906969011
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2254206675
Short name T977
Test name
Test status
Simulation time 36122465 ps
CPU time 0.87 seconds
Started May 05 02:17:12 PM PDT 24
Finished May 05 02:17:13 PM PDT 24
Peak memory 205536 kb
Host smart-66afdb87-67d5-4ff7-943f-de4e87dea381
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254206675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.2254206675
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.2380079406
Short name T1006
Test name
Test status
Simulation time 52589938 ps
CPU time 1.5 seconds
Started May 05 02:17:11 PM PDT 24
Finished May 05 02:17:13 PM PDT 24
Peak memory 205816 kb
Host smart-29d93eaa-d89f-4ad3-af20-78e3afcc2050
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380079406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.2380079406
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.2304984799
Short name T139
Test name
Test status
Simulation time 362865484 ps
CPU time 8.48 seconds
Started May 05 02:17:10 PM PDT 24
Finished May 05 02:17:19 PM PDT 24
Peak memory 220676 kb
Host smart-4985f285-af33-43b1-b219-8861a55a49db
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304984799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.2304984799
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.2980400150
Short name T926
Test name
Test status
Simulation time 247242607 ps
CPU time 1.94 seconds
Started May 05 02:17:07 PM PDT 24
Finished May 05 02:17:09 PM PDT 24
Peak memory 214076 kb
Host smart-09e856e2-31cc-4092-8e7f-ca439664f16f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980400150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.2980400150
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.1103135800
Short name T1051
Test name
Test status
Simulation time 260174778 ps
CPU time 8.87 seconds
Started May 05 02:17:09 PM PDT 24
Finished May 05 02:17:18 PM PDT 24
Peak memory 205700 kb
Host smart-d938f437-91c5-4dc6-a9a4-c854a1ccd351
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103135800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.1
103135800
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.3504752264
Short name T975
Test name
Test status
Simulation time 1046029189 ps
CPU time 15.1 seconds
Started May 05 02:17:09 PM PDT 24
Finished May 05 02:17:24 PM PDT 24
Peak memory 205716 kb
Host smart-9b44bdc4-81fc-4db4-b257-8ece2e09cfaf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504752264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.3
504752264
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.1993181035
Short name T937
Test name
Test status
Simulation time 46413045 ps
CPU time 1 seconds
Started May 05 02:17:12 PM PDT 24
Finished May 05 02:17:14 PM PDT 24
Peak memory 205680 kb
Host smart-e997d8e0-adfc-4a88-b36e-9cfc9fe6d482
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993181035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.1
993181035
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.3528688712
Short name T1016
Test name
Test status
Simulation time 287023998 ps
CPU time 2.62 seconds
Started May 05 02:17:12 PM PDT 24
Finished May 05 02:17:15 PM PDT 24
Peak memory 214064 kb
Host smart-53dc4b62-e402-4365-ad5a-cd98902d28c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528688712 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.3528688712
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.1557073940
Short name T1082
Test name
Test status
Simulation time 66829192 ps
CPU time 1.17 seconds
Started May 05 02:17:11 PM PDT 24
Finished May 05 02:17:12 PM PDT 24
Peak memory 205724 kb
Host smart-30ed7dfc-01bd-4f55-9b69-19f0c41deed7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557073940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.1557073940
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.144595554
Short name T1015
Test name
Test status
Simulation time 40326249 ps
CPU time 0.7 seconds
Started May 05 02:17:09 PM PDT 24
Finished May 05 02:17:10 PM PDT 24
Peak memory 205460 kb
Host smart-47621b03-952b-46e1-a3f3-78de1c2b3335
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144595554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.144595554
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.272509717
Short name T1010
Test name
Test status
Simulation time 37764011 ps
CPU time 2.02 seconds
Started May 05 02:17:11 PM PDT 24
Finished May 05 02:17:13 PM PDT 24
Peak memory 205740 kb
Host smart-9427d197-70d7-4ae5-8729-67a2cf562ec4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272509717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sam
e_csr_outstanding.272509717
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3852031247
Short name T1019
Test name
Test status
Simulation time 180624802 ps
CPU time 4.92 seconds
Started May 05 02:17:10 PM PDT 24
Finished May 05 02:17:16 PM PDT 24
Peak memory 214276 kb
Host smart-66aafc72-f17b-456d-9df7-6d03041d8cbb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852031247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.3852031247
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.10354440
Short name T1084
Test name
Test status
Simulation time 104828335 ps
CPU time 2.87 seconds
Started May 05 02:17:12 PM PDT 24
Finished May 05 02:17:15 PM PDT 24
Peak memory 214040 kb
Host smart-15d7726e-3d66-4bed-b0e0-40d84242cbe0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10354440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.10354440
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.2692985184
Short name T1080
Test name
Test status
Simulation time 29590132 ps
CPU time 1.54 seconds
Started May 05 02:17:29 PM PDT 24
Finished May 05 02:17:31 PM PDT 24
Peak memory 214148 kb
Host smart-4b1b6089-f5ae-4ac2-a272-156f2a8bd679
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692985184 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.2692985184
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.822286139
Short name T989
Test name
Test status
Simulation time 59702834 ps
CPU time 1.28 seconds
Started May 05 02:17:29 PM PDT 24
Finished May 05 02:17:31 PM PDT 24
Peak memory 205704 kb
Host smart-507c9861-e4a7-4c47-8806-bf1fc3fa8e14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822286139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.822286139
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.751662213
Short name T921
Test name
Test status
Simulation time 84313209 ps
CPU time 0.72 seconds
Started May 05 02:17:30 PM PDT 24
Finished May 05 02:17:31 PM PDT 24
Peak memory 205504 kb
Host smart-8cb0bb80-6c82-4642-85ec-deaba778d865
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751662213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.751662213
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.1913666056
Short name T1048
Test name
Test status
Simulation time 67783790 ps
CPU time 2.49 seconds
Started May 05 02:17:29 PM PDT 24
Finished May 05 02:17:32 PM PDT 24
Peak memory 205864 kb
Host smart-9c31ded3-b76e-463b-92cd-87764f4de967
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913666056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.1913666056
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.464823804
Short name T1030
Test name
Test status
Simulation time 44320318 ps
CPU time 1.47 seconds
Started May 05 02:17:23 PM PDT 24
Finished May 05 02:17:25 PM PDT 24
Peak memory 214228 kb
Host smart-35135e59-3021-4833-908a-d9d289e93256
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464823804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shado
w_reg_errors.464823804
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3337910429
Short name T117
Test name
Test status
Simulation time 80212444 ps
CPU time 3.72 seconds
Started May 05 02:17:28 PM PDT 24
Finished May 05 02:17:33 PM PDT 24
Peak memory 214308 kb
Host smart-1b9b0155-e23f-4d65-aeff-1858679a06a3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337910429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.3337910429
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.3522384582
Short name T960
Test name
Test status
Simulation time 1202677358 ps
CPU time 4.4 seconds
Started May 05 02:17:28 PM PDT 24
Finished May 05 02:17:33 PM PDT 24
Peak memory 216200 kb
Host smart-98c3b75c-1841-4738-88fc-6060fbdea48b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522384582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.3522384582
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.2428803599
Short name T1074
Test name
Test status
Simulation time 163583922 ps
CPU time 1.89 seconds
Started May 05 02:17:31 PM PDT 24
Finished May 05 02:17:33 PM PDT 24
Peak memory 214132 kb
Host smart-28678378-e4f5-4061-934d-0c1ba5bea1a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428803599 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.2428803599
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.3340933296
Short name T137
Test name
Test status
Simulation time 28182736 ps
CPU time 1.43 seconds
Started May 05 02:17:28 PM PDT 24
Finished May 05 02:17:29 PM PDT 24
Peak memory 205728 kb
Host smart-43c29a2b-a052-4323-af88-d2df367272b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340933296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.3340933296
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.22395698
Short name T1085
Test name
Test status
Simulation time 22063351 ps
CPU time 0.7 seconds
Started May 05 02:17:27 PM PDT 24
Finished May 05 02:17:28 PM PDT 24
Peak memory 205468 kb
Host smart-17c4a063-038d-40d4-a868-05d5ffb09a4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22395698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.22395698
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.1231156540
Short name T952
Test name
Test status
Simulation time 526949342 ps
CPU time 2.12 seconds
Started May 05 02:17:30 PM PDT 24
Finished May 05 02:17:32 PM PDT 24
Peak memory 205912 kb
Host smart-312909ea-7bbf-4566-a7c1-9417c37cb044
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231156540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.1231156540
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.4211590052
Short name T118
Test name
Test status
Simulation time 145448742 ps
CPU time 1.93 seconds
Started May 05 02:17:27 PM PDT 24
Finished May 05 02:17:29 PM PDT 24
Peak memory 214280 kb
Host smart-de65ec87-5f16-46ec-8b4b-f519276f885f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211590052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.4211590052
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2199748357
Short name T114
Test name
Test status
Simulation time 257187703 ps
CPU time 6.11 seconds
Started May 05 02:17:27 PM PDT 24
Finished May 05 02:17:34 PM PDT 24
Peak memory 214360 kb
Host smart-56c9b1e6-fa5a-45cc-8431-2890fa10b617
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199748357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.2199748357
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.349475255
Short name T1068
Test name
Test status
Simulation time 68145704 ps
CPU time 1.79 seconds
Started May 05 02:17:28 PM PDT 24
Finished May 05 02:17:31 PM PDT 24
Peak memory 214060 kb
Host smart-8d901686-0c90-491e-ac43-8005e94e8fe5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349475255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.349475255
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2957437976
Short name T954
Test name
Test status
Simulation time 139535670 ps
CPU time 4.27 seconds
Started May 05 02:17:28 PM PDT 24
Finished May 05 02:17:33 PM PDT 24
Peak memory 215036 kb
Host smart-6079b347-a02b-4263-bf16-c20b508ffc68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957437976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.2957437976
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.1355575047
Short name T976
Test name
Test status
Simulation time 51837415 ps
CPU time 2.13 seconds
Started May 05 02:17:32 PM PDT 24
Finished May 05 02:17:34 PM PDT 24
Peak memory 214080 kb
Host smart-2e186a39-3131-4e28-b99e-2d5d57ba21ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355575047 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.1355575047
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.1767434186
Short name T1011
Test name
Test status
Simulation time 14186089 ps
CPU time 1.06 seconds
Started May 05 02:17:34 PM PDT 24
Finished May 05 02:17:35 PM PDT 24
Peak memory 205680 kb
Host smart-81b3fc35-2971-40b1-90ec-21a5d086f599
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767434186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.1767434186
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.3357551552
Short name T933
Test name
Test status
Simulation time 16016621 ps
CPU time 0.75 seconds
Started May 05 02:17:33 PM PDT 24
Finished May 05 02:17:34 PM PDT 24
Peak memory 205544 kb
Host smart-dfa691c9-444c-425b-9c68-ec280e8d109d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357551552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.3357551552
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.2300197255
Short name T1000
Test name
Test status
Simulation time 543422135 ps
CPU time 1.92 seconds
Started May 05 02:17:34 PM PDT 24
Finished May 05 02:17:37 PM PDT 24
Peak memory 205924 kb
Host smart-5115a368-22ac-4e16-8527-ecd2d4276211
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300197255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.2300197255
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2514342735
Short name T985
Test name
Test status
Simulation time 57259187 ps
CPU time 1.9 seconds
Started May 05 02:17:35 PM PDT 24
Finished May 05 02:17:37 PM PDT 24
Peak memory 214212 kb
Host smart-52862962-dcc6-4cab-ad65-1dd150c61616
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514342735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.2514342735
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.4201781899
Short name T1008
Test name
Test status
Simulation time 291191802 ps
CPU time 6.59 seconds
Started May 05 02:17:33 PM PDT 24
Finished May 05 02:17:40 PM PDT 24
Peak memory 214224 kb
Host smart-f1ed4693-60c6-4219-8e9a-dbad41b25fa8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201781899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.4201781899
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.1963768516
Short name T970
Test name
Test status
Simulation time 3023407681 ps
CPU time 4.71 seconds
Started May 05 02:17:31 PM PDT 24
Finished May 05 02:17:36 PM PDT 24
Peak memory 217148 kb
Host smart-e8899a25-bd5d-41b4-8057-f0606d96c7d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963768516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.1963768516
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.3274321516
Short name T988
Test name
Test status
Simulation time 22110194 ps
CPU time 1.78 seconds
Started May 05 02:17:32 PM PDT 24
Finished May 05 02:17:34 PM PDT 24
Peak memory 214160 kb
Host smart-4e2e155c-42d6-4cb9-8fbd-bd53e39805f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274321516 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.3274321516
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.1766003433
Short name T1046
Test name
Test status
Simulation time 23780308 ps
CPU time 1.05 seconds
Started May 05 02:17:33 PM PDT 24
Finished May 05 02:17:34 PM PDT 24
Peak memory 205476 kb
Host smart-1907f5dc-21f1-4a1c-8627-4c52d8da64fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766003433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.1766003433
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3524103612
Short name T1076
Test name
Test status
Simulation time 46130106 ps
CPU time 0.7 seconds
Started May 05 02:17:34 PM PDT 24
Finished May 05 02:17:35 PM PDT 24
Peak memory 205452 kb
Host smart-c30a8256-c751-4a67-b1d1-2f0cb3ca8ca9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524103612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.3524103612
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.1874993286
Short name T138
Test name
Test status
Simulation time 263057897 ps
CPU time 1.76 seconds
Started May 05 02:17:34 PM PDT 24
Finished May 05 02:17:36 PM PDT 24
Peak memory 205780 kb
Host smart-bde0b9de-1a13-4282-b89e-0cf4bc6ca047
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874993286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.1874993286
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.330203089
Short name T1005
Test name
Test status
Simulation time 142969154 ps
CPU time 2.79 seconds
Started May 05 02:17:34 PM PDT 24
Finished May 05 02:17:38 PM PDT 24
Peak memory 214232 kb
Host smart-3b9d9383-a32f-4f9c-861b-e1a6a6584586
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330203089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shado
w_reg_errors.330203089
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2904631742
Short name T1069
Test name
Test status
Simulation time 87974732 ps
CPU time 4.89 seconds
Started May 05 02:17:32 PM PDT 24
Finished May 05 02:17:37 PM PDT 24
Peak memory 214312 kb
Host smart-2c20f10e-e3f8-4a00-986d-87f4c9c1b0e3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904631742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.2904631742
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.3614733963
Short name T1041
Test name
Test status
Simulation time 80035265 ps
CPU time 2.7 seconds
Started May 05 02:17:33 PM PDT 24
Finished May 05 02:17:36 PM PDT 24
Peak memory 213992 kb
Host smart-537bb3b7-bae0-4ad6-8395-6cc2067e8718
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614733963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.3614733963
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.267400959
Short name T157
Test name
Test status
Simulation time 154971731 ps
CPU time 6.77 seconds
Started May 05 02:17:38 PM PDT 24
Finished May 05 02:17:45 PM PDT 24
Peak memory 213996 kb
Host smart-ce76650b-92df-47b8-9da2-a2fc039968ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267400959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err
.267400959
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.1461481141
Short name T1083
Test name
Test status
Simulation time 56163904 ps
CPU time 1.37 seconds
Started May 05 02:17:41 PM PDT 24
Finished May 05 02:17:43 PM PDT 24
Peak memory 205920 kb
Host smart-704ff446-1465-4d54-8da3-1e1fd328d81a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461481141 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.1461481141
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.238013970
Short name T949
Test name
Test status
Simulation time 26387138 ps
CPU time 0.95 seconds
Started May 05 02:17:37 PM PDT 24
Finished May 05 02:17:39 PM PDT 24
Peak memory 205496 kb
Host smart-31e74f7f-cd16-4397-a744-90ddfcaff75c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238013970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.238013970
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.3698885131
Short name T1044
Test name
Test status
Simulation time 12066037 ps
CPU time 0.69 seconds
Started May 05 02:17:37 PM PDT 24
Finished May 05 02:17:38 PM PDT 24
Peak memory 205476 kb
Host smart-c7ea3cb9-f060-4fc3-8141-e1eae80eb258
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698885131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.3698885131
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.325030907
Short name T1055
Test name
Test status
Simulation time 530689818 ps
CPU time 2.98 seconds
Started May 05 02:17:37 PM PDT 24
Finished May 05 02:17:40 PM PDT 24
Peak memory 205928 kb
Host smart-b2143c95-9936-4ac8-9291-d4c8d07291ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325030907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_sa
me_csr_outstanding.325030907
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.429070028
Short name T1031
Test name
Test status
Simulation time 328636692 ps
CPU time 1.98 seconds
Started May 05 02:17:32 PM PDT 24
Finished May 05 02:17:35 PM PDT 24
Peak memory 214360 kb
Host smart-6103ad25-16ac-4131-bf11-cf7790ea2d55
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429070028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shado
w_reg_errors.429070028
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2883500514
Short name T1023
Test name
Test status
Simulation time 299956750 ps
CPU time 4.14 seconds
Started May 05 02:17:39 PM PDT 24
Finished May 05 02:17:43 PM PDT 24
Peak memory 220276 kb
Host smart-42e2f3e5-9425-4319-a154-b6f142b5415c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883500514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.2883500514
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.1225420084
Short name T953
Test name
Test status
Simulation time 234107822 ps
CPU time 3.14 seconds
Started May 05 02:17:40 PM PDT 24
Finished May 05 02:17:44 PM PDT 24
Peak memory 213936 kb
Host smart-1f5c7b0d-0168-40f3-bb78-f1fdc3e55103
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225420084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.1225420084
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1080738483
Short name T1020
Test name
Test status
Simulation time 50103992 ps
CPU time 1.53 seconds
Started May 05 02:17:39 PM PDT 24
Finished May 05 02:17:41 PM PDT 24
Peak memory 214156 kb
Host smart-6df15793-9cda-44ec-b446-49f785cd303e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080738483 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.1080738483
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.905249842
Short name T1036
Test name
Test status
Simulation time 61684278 ps
CPU time 1.25 seconds
Started May 05 02:17:39 PM PDT 24
Finished May 05 02:17:41 PM PDT 24
Peak memory 205760 kb
Host smart-9c8fe1bf-2183-4730-929f-8ad6ae7f8e68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905249842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.905249842
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.2476834817
Short name T930
Test name
Test status
Simulation time 7420008 ps
CPU time 0.79 seconds
Started May 05 02:17:37 PM PDT 24
Finished May 05 02:17:38 PM PDT 24
Peak memory 205564 kb
Host smart-85f7782f-0b50-4772-bd9d-39fd42c60fa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476834817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.2476834817
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3139853683
Short name T1075
Test name
Test status
Simulation time 360579833 ps
CPU time 2.8 seconds
Started May 05 02:17:37 PM PDT 24
Finished May 05 02:17:41 PM PDT 24
Peak memory 205888 kb
Host smart-c31b1646-bc2d-443b-bee8-ae44fbdacc0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139853683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.3139853683
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.2652872243
Short name T996
Test name
Test status
Simulation time 98408601 ps
CPU time 2.11 seconds
Started May 05 02:17:37 PM PDT 24
Finished May 05 02:17:39 PM PDT 24
Peak memory 214536 kb
Host smart-52b4623d-6e56-4278-b133-61c49eb25751
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652872243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.2652872243
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.2177060229
Short name T1002
Test name
Test status
Simulation time 317703559 ps
CPU time 6.58 seconds
Started May 05 02:17:41 PM PDT 24
Finished May 05 02:17:48 PM PDT 24
Peak memory 214240 kb
Host smart-84d39c17-36e6-449a-bedb-c5f779fe03c2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177060229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.2177060229
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.1453691774
Short name T1042
Test name
Test status
Simulation time 362480370 ps
CPU time 2.31 seconds
Started May 05 02:17:40 PM PDT 24
Finished May 05 02:17:43 PM PDT 24
Peak memory 214004 kb
Host smart-e0c6a506-3b57-4029-a2b4-0ddbb49d2952
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453691774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.1453691774
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.1572149630
Short name T1003
Test name
Test status
Simulation time 78238284 ps
CPU time 1.46 seconds
Started May 05 02:17:43 PM PDT 24
Finished May 05 02:17:45 PM PDT 24
Peak memory 214036 kb
Host smart-58150d91-a249-4c01-ac33-91afe53ec347
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572149630 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.1572149630
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.85496222
Short name T957
Test name
Test status
Simulation time 69090176 ps
CPU time 1.08 seconds
Started May 05 02:17:43 PM PDT 24
Finished May 05 02:17:45 PM PDT 24
Peak memory 205760 kb
Host smart-37cd0b94-289d-4a16-8960-a311d9590b1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85496222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.85496222
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3483977562
Short name T986
Test name
Test status
Simulation time 13457585 ps
CPU time 0.72 seconds
Started May 05 02:17:43 PM PDT 24
Finished May 05 02:17:44 PM PDT 24
Peak memory 205480 kb
Host smart-fb6c3458-a579-4d89-bbd5-ba72e0eb32ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483977562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.3483977562
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.1643005728
Short name T955
Test name
Test status
Simulation time 84831197 ps
CPU time 2.18 seconds
Started May 05 02:17:41 PM PDT 24
Finished May 05 02:17:43 PM PDT 24
Peak memory 205840 kb
Host smart-1e7f249d-4c64-4684-95ed-0fbd54e27c2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643005728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.1643005728
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.2397566355
Short name T944
Test name
Test status
Simulation time 87081771 ps
CPU time 1.93 seconds
Started May 05 02:17:41 PM PDT 24
Finished May 05 02:17:43 PM PDT 24
Peak memory 214304 kb
Host smart-f6266cba-6129-4f05-b6d1-5db42f205bea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397566355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.2397566355
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.1584809212
Short name T1024
Test name
Test status
Simulation time 344689735 ps
CPU time 12.03 seconds
Started May 05 02:17:41 PM PDT 24
Finished May 05 02:17:54 PM PDT 24
Peak memory 220392 kb
Host smart-54f132f9-62f1-46a0-949b-db10fac8a27e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584809212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.1584809212
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.1165707638
Short name T942
Test name
Test status
Simulation time 259541907 ps
CPU time 2.27 seconds
Started May 05 02:17:41 PM PDT 24
Finished May 05 02:17:44 PM PDT 24
Peak memory 214064 kb
Host smart-5ec680f8-f828-4e05-823c-00e0d1c6dccb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165707638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.1165707638
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.1324262329
Short name T174
Test name
Test status
Simulation time 791039255 ps
CPU time 8.24 seconds
Started May 05 02:17:41 PM PDT 24
Finished May 05 02:17:50 PM PDT 24
Peak memory 214012 kb
Host smart-e30fc822-fa4c-4da7-a27a-3e06a1e1a45c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324262329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.1324262329
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1129231970
Short name T159
Test name
Test status
Simulation time 57853064 ps
CPU time 1.59 seconds
Started May 05 02:17:44 PM PDT 24
Finished May 05 02:17:46 PM PDT 24
Peak memory 214116 kb
Host smart-2edb7b9b-003e-4c0c-996c-99cd063c795e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129231970 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.1129231970
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.4069813101
Short name T1073
Test name
Test status
Simulation time 182649844 ps
CPU time 1.19 seconds
Started May 05 02:17:42 PM PDT 24
Finished May 05 02:17:43 PM PDT 24
Peak memory 205616 kb
Host smart-9011233f-9613-4bec-9a17-698984adaa30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069813101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.4069813101
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.3727737059
Short name T1049
Test name
Test status
Simulation time 40172956 ps
CPU time 0.7 seconds
Started May 05 02:17:44 PM PDT 24
Finished May 05 02:17:45 PM PDT 24
Peak memory 205468 kb
Host smart-3bdb5b06-692c-41d7-9d6c-78a8c177b6a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727737059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.3727737059
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.1643579377
Short name T987
Test name
Test status
Simulation time 55914777 ps
CPU time 2.47 seconds
Started May 05 02:17:42 PM PDT 24
Finished May 05 02:17:45 PM PDT 24
Peak memory 205792 kb
Host smart-2e20d1fc-f89a-416e-a438-9c0d847a890d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643579377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.1643579377
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.1082981938
Short name T110
Test name
Test status
Simulation time 165033902 ps
CPU time 1.59 seconds
Started May 05 02:17:43 PM PDT 24
Finished May 05 02:17:45 PM PDT 24
Peak memory 214284 kb
Host smart-f7344d42-fa88-4d6e-b9f1-461998f62f79
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082981938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.1082981938
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.4089354334
Short name T1028
Test name
Test status
Simulation time 1337497917 ps
CPU time 9.17 seconds
Started May 05 02:17:42 PM PDT 24
Finished May 05 02:17:52 PM PDT 24
Peak memory 220360 kb
Host smart-b7a4207c-bb1c-4ec8-9a7d-c91219035d62
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089354334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.4089354334
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.2596183239
Short name T947
Test name
Test status
Simulation time 134384449 ps
CPU time 1.77 seconds
Started May 05 02:17:43 PM PDT 24
Finished May 05 02:17:46 PM PDT 24
Peak memory 205848 kb
Host smart-7ddf95b3-5b69-4840-bc41-f54eb319c551
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596183239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.2596183239
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.1695161059
Short name T962
Test name
Test status
Simulation time 187739674 ps
CPU time 1.44 seconds
Started May 05 02:17:50 PM PDT 24
Finished May 05 02:17:52 PM PDT 24
Peak memory 214124 kb
Host smart-d77fb9dc-4985-431f-8d46-b4cd4363e73a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695161059 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.1695161059
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.3594444974
Short name T1064
Test name
Test status
Simulation time 16066396 ps
CPU time 0.98 seconds
Started May 05 02:17:50 PM PDT 24
Finished May 05 02:17:52 PM PDT 24
Peak memory 205528 kb
Host smart-21792aa3-7be4-4771-995c-993f6a495017
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594444974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.3594444974
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.2975926179
Short name T948
Test name
Test status
Simulation time 44761849 ps
CPU time 0.74 seconds
Started May 05 02:17:51 PM PDT 24
Finished May 05 02:17:52 PM PDT 24
Peak memory 205480 kb
Host smart-69ed474f-7f2d-4591-a94a-23382b22a8c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975926179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.2975926179
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2657462769
Short name T1088
Test name
Test status
Simulation time 77367949 ps
CPU time 2.5 seconds
Started May 05 02:17:47 PM PDT 24
Finished May 05 02:17:50 PM PDT 24
Peak memory 205776 kb
Host smart-e88fda38-5ef7-4566-856e-e2b0fd8072db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657462769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.2657462769
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3233063115
Short name T1071
Test name
Test status
Simulation time 931606901 ps
CPU time 3.08 seconds
Started May 05 02:17:42 PM PDT 24
Finished May 05 02:17:46 PM PDT 24
Peak memory 214308 kb
Host smart-56dd2882-2c21-4cfb-8240-9948770ca400
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233063115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.3233063115
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2104459242
Short name T1062
Test name
Test status
Simulation time 176807344 ps
CPU time 8.66 seconds
Started May 05 02:17:43 PM PDT 24
Finished May 05 02:17:52 PM PDT 24
Peak memory 214300 kb
Host smart-8921e0c9-3ca3-4b2f-b436-62259a245ec1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104459242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.2104459242
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.2123468415
Short name T940
Test name
Test status
Simulation time 88100348 ps
CPU time 1.47 seconds
Started May 05 02:17:45 PM PDT 24
Finished May 05 02:17:47 PM PDT 24
Peak memory 214044 kb
Host smart-4e3f0f4b-1a35-4f7b-8d28-8a00c5372dbb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123468415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.2123468415
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.877210924
Short name T156
Test name
Test status
Simulation time 622092492 ps
CPU time 5.82 seconds
Started May 05 02:17:51 PM PDT 24
Finished May 05 02:17:58 PM PDT 24
Peak memory 213980 kb
Host smart-5a5301fd-d3eb-495e-b067-484eeef218f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877210924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_err
.877210924
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1576373938
Short name T967
Test name
Test status
Simulation time 12968769 ps
CPU time 0.99 seconds
Started May 05 02:17:51 PM PDT 24
Finished May 05 02:17:53 PM PDT 24
Peak memory 205608 kb
Host smart-ed90ed4a-91d7-41ae-978a-4320fb8c62ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576373938 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.1576373938
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.1656056499
Short name T1052
Test name
Test status
Simulation time 84884381 ps
CPU time 1.41 seconds
Started May 05 02:17:55 PM PDT 24
Finished May 05 02:17:57 PM PDT 24
Peak memory 205648 kb
Host smart-d99612f0-4fe8-44e4-999a-4793aadba360
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656056499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.1656056499
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.3109538832
Short name T943
Test name
Test status
Simulation time 10530386 ps
CPU time 0.72 seconds
Started May 05 02:17:50 PM PDT 24
Finished May 05 02:17:52 PM PDT 24
Peak memory 205472 kb
Host smart-edf91460-d46b-4752-a19f-25ca6daa59b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109538832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.3109538832
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1142574217
Short name T1004
Test name
Test status
Simulation time 476646679 ps
CPU time 1.73 seconds
Started May 05 02:17:51 PM PDT 24
Finished May 05 02:17:53 PM PDT 24
Peak memory 205884 kb
Host smart-21df3b41-1826-44f0-bdf8-838d6c859c35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142574217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.1142574217
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.2012322061
Short name T115
Test name
Test status
Simulation time 598732199 ps
CPU time 4.16 seconds
Started May 05 02:17:50 PM PDT 24
Finished May 05 02:17:55 PM PDT 24
Peak memory 214212 kb
Host smart-84ff6837-b92f-4fd9-bcee-f5ec575cf819
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012322061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.2012322061
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1982020982
Short name T1061
Test name
Test status
Simulation time 215750960 ps
CPU time 10.09 seconds
Started May 05 02:17:53 PM PDT 24
Finished May 05 02:18:03 PM PDT 24
Peak memory 220400 kb
Host smart-9249531e-3437-40ff-b135-ff8615e19e05
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982020982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.1982020982
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.900144132
Short name T1032
Test name
Test status
Simulation time 93591486 ps
CPU time 1.76 seconds
Started May 05 02:17:50 PM PDT 24
Finished May 05 02:17:52 PM PDT 24
Peak memory 205764 kb
Host smart-2e278074-ae37-45b5-8b12-857c5f056996
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900144132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.900144132
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.386362410
Short name T1039
Test name
Test status
Simulation time 1014764525 ps
CPU time 10.47 seconds
Started May 05 02:17:16 PM PDT 24
Finished May 05 02:17:28 PM PDT 24
Peak memory 205816 kb
Host smart-141b5981-a4a9-45ad-9cea-995bb9fa1570
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386362410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.386362410
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.1737222445
Short name T1013
Test name
Test status
Simulation time 517975883 ps
CPU time 11.7 seconds
Started May 05 02:17:16 PM PDT 24
Finished May 05 02:17:28 PM PDT 24
Peak memory 205856 kb
Host smart-87ac6846-9f4d-4f3c-96e1-007b79668c58
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737222445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.1
737222445
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.3953822520
Short name T1001
Test name
Test status
Simulation time 11615535 ps
CPU time 0.88 seconds
Started May 05 02:17:15 PM PDT 24
Finished May 05 02:17:17 PM PDT 24
Peak memory 205584 kb
Host smart-5dfa24e3-1894-49ee-ae00-209ff986b860
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953822520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.3
953822520
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1558754584
Short name T929
Test name
Test status
Simulation time 113098749 ps
CPU time 1.5 seconds
Started May 05 02:17:17 PM PDT 24
Finished May 05 02:17:19 PM PDT 24
Peak memory 217600 kb
Host smart-73248e11-2d76-45f8-80f7-01ef87880e1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558754584 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.1558754584
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3870174442
Short name T999
Test name
Test status
Simulation time 60903270 ps
CPU time 1.14 seconds
Started May 05 02:17:15 PM PDT 24
Finished May 05 02:17:17 PM PDT 24
Peak memory 205792 kb
Host smart-2d94a2ab-26da-47a4-b3ec-7f951eb5ca1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870174442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.3870174442
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.594593342
Short name T1034
Test name
Test status
Simulation time 52449437 ps
CPU time 0.86 seconds
Started May 05 02:17:16 PM PDT 24
Finished May 05 02:17:17 PM PDT 24
Peak memory 205476 kb
Host smart-371a3516-0354-405b-9a1f-05bcd5baf754
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594593342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.594593342
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.297905455
Short name T141
Test name
Test status
Simulation time 217270503 ps
CPU time 3.87 seconds
Started May 05 02:17:15 PM PDT 24
Finished May 05 02:17:20 PM PDT 24
Peak memory 205832 kb
Host smart-f95dc619-531a-4375-8609-4bb2097d74fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297905455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sam
e_csr_outstanding.297905455
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.3412923407
Short name T983
Test name
Test status
Simulation time 88380912 ps
CPU time 3.32 seconds
Started May 05 02:17:11 PM PDT 24
Finished May 05 02:17:15 PM PDT 24
Peak memory 214260 kb
Host smart-5b31892e-af24-4386-a30b-f0f8ec1f41e8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412923407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.3412923407
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.1780586443
Short name T111
Test name
Test status
Simulation time 1342895031 ps
CPU time 12.72 seconds
Started May 05 02:17:14 PM PDT 24
Finished May 05 02:17:28 PM PDT 24
Peak memory 214248 kb
Host smart-bee3d63f-aaac-41dc-922e-217231383612
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780586443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.1780586443
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.1852624731
Short name T1059
Test name
Test status
Simulation time 399867551 ps
CPU time 1.4 seconds
Started May 05 02:17:15 PM PDT 24
Finished May 05 02:17:17 PM PDT 24
Peak memory 214024 kb
Host smart-2c376879-d50c-4341-900a-fcfa0559ae45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852624731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.1852624731
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.2717521443
Short name T165
Test name
Test status
Simulation time 103792433 ps
CPU time 4.62 seconds
Started May 05 02:17:14 PM PDT 24
Finished May 05 02:17:19 PM PDT 24
Peak memory 214052 kb
Host smart-28684896-36c1-4440-8c8a-10dd6853aa40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717521443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.2717521443
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.3251215369
Short name T928
Test name
Test status
Simulation time 15541941 ps
CPU time 0.76 seconds
Started May 05 02:17:53 PM PDT 24
Finished May 05 02:17:54 PM PDT 24
Peak memory 205532 kb
Host smart-361251a8-7a1b-45c3-9cdc-61392d3bd479
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251215369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.3251215369
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.3930507472
Short name T1029
Test name
Test status
Simulation time 26165234 ps
CPU time 0.71 seconds
Started May 05 02:17:50 PM PDT 24
Finished May 05 02:17:52 PM PDT 24
Peak memory 205524 kb
Host smart-4ca65a2a-8433-4b59-b326-a1628e0697e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930507472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.3930507472
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.524092842
Short name T946
Test name
Test status
Simulation time 12007414 ps
CPU time 0.7 seconds
Started May 05 02:17:50 PM PDT 24
Finished May 05 02:17:52 PM PDT 24
Peak memory 205536 kb
Host smart-9da4399c-0b50-4a53-be71-77288272c50a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524092842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.524092842
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.1756656353
Short name T922
Test name
Test status
Simulation time 47141572 ps
CPU time 0.84 seconds
Started May 05 02:17:54 PM PDT 24
Finished May 05 02:17:55 PM PDT 24
Peak memory 205452 kb
Host smart-82341dc3-d6b4-4f64-b075-681d4d72bd2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756656353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.1756656353
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.3384890648
Short name T1025
Test name
Test status
Simulation time 12376565 ps
CPU time 0.69 seconds
Started May 05 02:17:54 PM PDT 24
Finished May 05 02:17:55 PM PDT 24
Peak memory 205444 kb
Host smart-c730d0c3-e74d-4fad-8c51-de749d1b19ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384890648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.3384890648
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.2895618080
Short name T935
Test name
Test status
Simulation time 9016352 ps
CPU time 0.7 seconds
Started May 05 02:17:53 PM PDT 24
Finished May 05 02:17:54 PM PDT 24
Peak memory 205540 kb
Host smart-61a31ecf-3cf0-48cd-b742-c3a52257c7ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895618080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.2895618080
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.3350815230
Short name T927
Test name
Test status
Simulation time 14024411 ps
CPU time 0.73 seconds
Started May 05 02:17:54 PM PDT 24
Finished May 05 02:17:55 PM PDT 24
Peak memory 205520 kb
Host smart-0e8e680f-b0a1-42dc-b6e4-a922f571f27e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350815230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.3350815230
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.1604078782
Short name T1066
Test name
Test status
Simulation time 12195305 ps
CPU time 0.72 seconds
Started May 05 02:17:53 PM PDT 24
Finished May 05 02:17:55 PM PDT 24
Peak memory 205520 kb
Host smart-b6a503be-7e81-4448-bfd2-54b62699d42d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604078782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.1604078782
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.3456480597
Short name T941
Test name
Test status
Simulation time 20293197 ps
CPU time 0.73 seconds
Started May 05 02:17:51 PM PDT 24
Finished May 05 02:17:53 PM PDT 24
Peak memory 205740 kb
Host smart-f04806a4-2746-433b-b388-f3a5f368db73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456480597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.3456480597
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.4087851156
Short name T1077
Test name
Test status
Simulation time 40254006 ps
CPU time 0.73 seconds
Started May 05 02:18:02 PM PDT 24
Finished May 05 02:18:04 PM PDT 24
Peak memory 205512 kb
Host smart-7efc89d5-15e8-417b-ae33-d90871302952
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087851156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.4087851156
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.2758532439
Short name T998
Test name
Test status
Simulation time 2039855106 ps
CPU time 11.2 seconds
Started May 05 02:17:17 PM PDT 24
Finished May 05 02:17:29 PM PDT 24
Peak memory 205760 kb
Host smart-fa4f4afb-6a7d-4de9-b7a4-b95c19ffb8a8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758532439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.2
758532439
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.4001937776
Short name T995
Test name
Test status
Simulation time 438034002 ps
CPU time 7.67 seconds
Started May 05 02:17:15 PM PDT 24
Finished May 05 02:17:23 PM PDT 24
Peak memory 205816 kb
Host smart-3d4bca68-f09c-4251-956b-1a8d0f1baa48
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001937776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.4
001937776
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.3576424360
Short name T993
Test name
Test status
Simulation time 106694474 ps
CPU time 0.98 seconds
Started May 05 02:17:17 PM PDT 24
Finished May 05 02:17:18 PM PDT 24
Peak memory 205472 kb
Host smart-4205595d-e397-404c-b15d-360c01b90f86
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576424360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.3
576424360
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.1623488160
Short name T1078
Test name
Test status
Simulation time 34648716 ps
CPU time 2.44 seconds
Started May 05 02:17:15 PM PDT 24
Finished May 05 02:17:18 PM PDT 24
Peak memory 213984 kb
Host smart-b8a0b14b-6c08-424b-9cac-96a2eca72040
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623488160 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.1623488160
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.1516722189
Short name T1067
Test name
Test status
Simulation time 54308956 ps
CPU time 1.07 seconds
Started May 05 02:17:17 PM PDT 24
Finished May 05 02:17:19 PM PDT 24
Peak memory 205760 kb
Host smart-64a123a8-26f5-44a7-bfe3-7aeda8d72fd8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516722189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.1516722189
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.26940673
Short name T1089
Test name
Test status
Simulation time 15033382 ps
CPU time 0.75 seconds
Started May 05 02:17:14 PM PDT 24
Finished May 05 02:17:15 PM PDT 24
Peak memory 205484 kb
Host smart-1b277092-94b6-4675-a262-b3ed1742e794
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26940673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.26940673
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.4176003846
Short name T974
Test name
Test status
Simulation time 351344331 ps
CPU time 3.26 seconds
Started May 05 02:17:17 PM PDT 24
Finished May 05 02:17:21 PM PDT 24
Peak memory 205872 kb
Host smart-3b324585-c250-4704-870f-50c3d1ad9906
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176003846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.4176003846
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.2151452031
Short name T116
Test name
Test status
Simulation time 572579724 ps
CPU time 3.12 seconds
Started May 05 02:17:13 PM PDT 24
Finished May 05 02:17:17 PM PDT 24
Peak memory 214376 kb
Host smart-792f1d64-172d-4d4c-a758-1e0bac052dae
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151452031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.2151452031
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.2599751693
Short name T920
Test name
Test status
Simulation time 33204773 ps
CPU time 2.03 seconds
Started May 05 02:17:14 PM PDT 24
Finished May 05 02:17:17 PM PDT 24
Peak memory 216148 kb
Host smart-d088251e-0cdc-4c51-bb91-ad13db5feec2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599751693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.2599751693
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.706955350
Short name T1017
Test name
Test status
Simulation time 2505012168 ps
CPU time 5.32 seconds
Started May 05 02:17:15 PM PDT 24
Finished May 05 02:17:21 PM PDT 24
Peak memory 214036 kb
Host smart-534be21e-1eee-46c3-a507-51ccca2c29d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706955350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.
706955350
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.1836241362
Short name T1058
Test name
Test status
Simulation time 8168110 ps
CPU time 0.75 seconds
Started May 05 02:17:52 PM PDT 24
Finished May 05 02:17:54 PM PDT 24
Peak memory 205444 kb
Host smart-8d796557-cf87-41c5-8e5d-45cdcd7e560b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836241362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.1836241362
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.2692390276
Short name T1037
Test name
Test status
Simulation time 79376938 ps
CPU time 0.76 seconds
Started May 05 02:17:52 PM PDT 24
Finished May 05 02:17:53 PM PDT 24
Peak memory 205588 kb
Host smart-b6d9a0f3-a9bf-494c-93d5-9f456e35b163
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692390276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.2692390276
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.2866429856
Short name T981
Test name
Test status
Simulation time 9439573 ps
CPU time 0.73 seconds
Started May 05 02:17:52 PM PDT 24
Finished May 05 02:17:53 PM PDT 24
Peak memory 205484 kb
Host smart-b07fc779-484c-44a9-ada4-5c4e3789acec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866429856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.2866429856
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.2453059458
Short name T969
Test name
Test status
Simulation time 43169022 ps
CPU time 0.69 seconds
Started May 05 02:17:51 PM PDT 24
Finished May 05 02:17:52 PM PDT 24
Peak memory 205448 kb
Host smart-eb39f4ac-1375-4eb1-adc8-60e0628efec6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453059458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.2453059458
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.2933236522
Short name T1087
Test name
Test status
Simulation time 37627825 ps
CPU time 0.7 seconds
Started May 05 02:17:52 PM PDT 24
Finished May 05 02:17:53 PM PDT 24
Peak memory 205528 kb
Host smart-e2e523a6-0b71-4c1a-acfa-2fcee944b8bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933236522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.2933236522
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.134706137
Short name T1063
Test name
Test status
Simulation time 9710686 ps
CPU time 0.8 seconds
Started May 05 02:17:54 PM PDT 24
Finished May 05 02:17:55 PM PDT 24
Peak memory 205496 kb
Host smart-6be310a6-b5c2-46a5-97bd-041a23fc12f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134706137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.134706137
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.3447436055
Short name T1072
Test name
Test status
Simulation time 87058317 ps
CPU time 0.8 seconds
Started May 05 02:17:56 PM PDT 24
Finished May 05 02:17:58 PM PDT 24
Peak memory 205420 kb
Host smart-68a3cc5b-d27c-4589-8a16-d5f02d6f2d8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447436055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.3447436055
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.3411762998
Short name T1018
Test name
Test status
Simulation time 25282358 ps
CPU time 0.71 seconds
Started May 05 02:17:52 PM PDT 24
Finished May 05 02:17:53 PM PDT 24
Peak memory 205408 kb
Host smart-5d36c2ff-46c8-4fcd-9ce9-ab0c18d79df5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411762998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.3411762998
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.1388817200
Short name T932
Test name
Test status
Simulation time 21505783 ps
CPU time 0.87 seconds
Started May 05 02:18:02 PM PDT 24
Finished May 05 02:18:03 PM PDT 24
Peak memory 205668 kb
Host smart-a3951872-6640-4c1c-bd34-9a1caedd6942
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388817200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.1388817200
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.2742436121
Short name T958
Test name
Test status
Simulation time 13361601 ps
CPU time 0.69 seconds
Started May 05 02:17:54 PM PDT 24
Finished May 05 02:17:55 PM PDT 24
Peak memory 205420 kb
Host smart-f66a7c75-7215-4be9-b3f8-01ec02383271
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742436121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.2742436121
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.455266083
Short name T177
Test name
Test status
Simulation time 260967251 ps
CPU time 5.5 seconds
Started May 05 02:17:21 PM PDT 24
Finished May 05 02:17:27 PM PDT 24
Peak memory 205752 kb
Host smart-ebe82b31-4252-4bfd-94ff-e0077d991007
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455266083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.455266083
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2880491914
Short name T1035
Test name
Test status
Simulation time 882177166 ps
CPU time 16.4 seconds
Started May 05 02:17:22 PM PDT 24
Finished May 05 02:17:39 PM PDT 24
Peak memory 205740 kb
Host smart-d7e12f91-1f26-4370-a49c-b67ec0189122
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880491914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.2
880491914
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.403241516
Short name T931
Test name
Test status
Simulation time 37810570 ps
CPU time 1.49 seconds
Started May 05 02:17:22 PM PDT 24
Finished May 05 02:17:23 PM PDT 24
Peak memory 205852 kb
Host smart-e15f8898-807f-41a5-b6b8-349634de2230
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403241516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.403241516
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.667792221
Short name T956
Test name
Test status
Simulation time 82823105 ps
CPU time 1.75 seconds
Started May 05 02:17:22 PM PDT 24
Finished May 05 02:17:24 PM PDT 24
Peak memory 217180 kb
Host smart-2f70f6fb-cba9-43ad-a3f7-a5cc29eb49a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667792221 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.667792221
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.1879915340
Short name T1040
Test name
Test status
Simulation time 28013465 ps
CPU time 0.84 seconds
Started May 05 02:17:20 PM PDT 24
Finished May 05 02:17:21 PM PDT 24
Peak memory 205540 kb
Host smart-cc2127eb-0f53-4805-8050-23ed8f9fd9bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879915340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.1879915340
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.3241912083
Short name T936
Test name
Test status
Simulation time 9333986 ps
CPU time 0.73 seconds
Started May 05 02:17:13 PM PDT 24
Finished May 05 02:17:14 PM PDT 24
Peak memory 205540 kb
Host smart-e5bfe187-9a78-496f-8b70-0a2d565d099d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241912083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.3241912083
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2633499907
Short name T140
Test name
Test status
Simulation time 44034771 ps
CPU time 2.4 seconds
Started May 05 02:17:19 PM PDT 24
Finished May 05 02:17:22 PM PDT 24
Peak memory 205828 kb
Host smart-6de13205-369d-43b0-8cf1-4be2e6e92b8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633499907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.2633499907
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.2488407334
Short name T966
Test name
Test status
Simulation time 58217755 ps
CPU time 2.08 seconds
Started May 05 02:17:15 PM PDT 24
Finished May 05 02:17:18 PM PDT 24
Peak memory 214472 kb
Host smart-5c4329e2-c5a5-4ae6-9440-bf98bb3859ad
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488407334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.2488407334
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.1846200811
Short name T1050
Test name
Test status
Simulation time 547518606 ps
CPU time 6.79 seconds
Started May 05 02:17:16 PM PDT 24
Finished May 05 02:17:23 PM PDT 24
Peak memory 214204 kb
Host smart-57afdd71-ef11-454b-a55c-30437ea8a7a6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846200811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.1846200811
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.339412821
Short name T939
Test name
Test status
Simulation time 79413260 ps
CPU time 2.94 seconds
Started May 05 02:17:17 PM PDT 24
Finished May 05 02:17:21 PM PDT 24
Peak memory 214060 kb
Host smart-b1b5c8ed-b012-4ed8-b8bd-a545f2783105
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339412821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.339412821
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.676964476
Short name T1079
Test name
Test status
Simulation time 8344912 ps
CPU time 0.73 seconds
Started May 05 02:18:01 PM PDT 24
Finished May 05 02:18:02 PM PDT 24
Peak memory 205436 kb
Host smart-65efa0ce-7522-4a0a-a9d5-04bef0ec950f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676964476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.676964476
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.3486692309
Short name T990
Test name
Test status
Simulation time 131393380 ps
CPU time 0.82 seconds
Started May 05 02:17:52 PM PDT 24
Finished May 05 02:17:54 PM PDT 24
Peak memory 205484 kb
Host smart-36437075-6dec-40e4-af2e-88d9f8c8cc27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486692309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.3486692309
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.2570031098
Short name T964
Test name
Test status
Simulation time 52447590 ps
CPU time 0.65 seconds
Started May 05 02:17:51 PM PDT 24
Finished May 05 02:17:52 PM PDT 24
Peak memory 205408 kb
Host smart-65e8f33d-75f7-4dd4-9741-65ff581e52c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570031098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.2570031098
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.1814424952
Short name T924
Test name
Test status
Simulation time 42981241 ps
CPU time 0.84 seconds
Started May 05 02:17:53 PM PDT 24
Finished May 05 02:17:55 PM PDT 24
Peak memory 205588 kb
Host smart-eac6a8e8-5297-413e-9f99-3c86a800d18f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814424952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.1814424952
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2637588939
Short name T1057
Test name
Test status
Simulation time 57307228 ps
CPU time 0.96 seconds
Started May 05 02:17:56 PM PDT 24
Finished May 05 02:17:57 PM PDT 24
Peak memory 205544 kb
Host smart-f0b9551e-5900-422b-94b1-cb8fec9ba502
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637588939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.2637588939
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.1146160136
Short name T1022
Test name
Test status
Simulation time 9401771 ps
CPU time 0.86 seconds
Started May 05 02:17:56 PM PDT 24
Finished May 05 02:17:58 PM PDT 24
Peak memory 205544 kb
Host smart-80edd169-b721-4fcd-8f7b-d8728ba217e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146160136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.1146160136
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.1140124055
Short name T1054
Test name
Test status
Simulation time 10328973 ps
CPU time 0.71 seconds
Started May 05 02:17:55 PM PDT 24
Finished May 05 02:17:57 PM PDT 24
Peak memory 205452 kb
Host smart-99076fd0-24d9-407b-8666-221f881927a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140124055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.1140124055
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.878071965
Short name T1056
Test name
Test status
Simulation time 9918009 ps
CPU time 0.82 seconds
Started May 05 02:18:07 PM PDT 24
Finished May 05 02:18:09 PM PDT 24
Peak memory 205428 kb
Host smart-539e683e-1331-46c7-a91d-3bd0a65ee2d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878071965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.878071965
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.1824623933
Short name T1065
Test name
Test status
Simulation time 14172680 ps
CPU time 0.75 seconds
Started May 05 02:17:56 PM PDT 24
Finished May 05 02:17:58 PM PDT 24
Peak memory 205456 kb
Host smart-120b29ba-dc89-43fb-8f27-3d8a749c243b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824623933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.1824623933
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.692705430
Short name T980
Test name
Test status
Simulation time 37228367 ps
CPU time 0.84 seconds
Started May 05 02:17:56 PM PDT 24
Finished May 05 02:17:58 PM PDT 24
Peak memory 205476 kb
Host smart-070cd42b-8f69-4ece-af8d-10882926dea4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692705430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.692705430
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.1812236837
Short name T992
Test name
Test status
Simulation time 86963461 ps
CPU time 1.21 seconds
Started May 05 02:17:23 PM PDT 24
Finished May 05 02:17:24 PM PDT 24
Peak memory 205916 kb
Host smart-b9898b30-4de4-4efb-b418-287e015f97d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812236837 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.1812236837
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.3991821571
Short name T938
Test name
Test status
Simulation time 115003321 ps
CPU time 1.49 seconds
Started May 05 02:17:21 PM PDT 24
Finished May 05 02:17:23 PM PDT 24
Peak memory 205696 kb
Host smart-59743f5a-b46f-4eb0-abaa-aecaa61f734e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991821571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.3991821571
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.1482732829
Short name T959
Test name
Test status
Simulation time 17029915 ps
CPU time 0.81 seconds
Started May 05 02:17:19 PM PDT 24
Finished May 05 02:17:20 PM PDT 24
Peak memory 205456 kb
Host smart-46cc6511-a129-478a-a77a-7eaa95d3bc26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482732829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.1482732829
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.3012416874
Short name T1014
Test name
Test status
Simulation time 20547529 ps
CPU time 1.37 seconds
Started May 05 02:17:21 PM PDT 24
Finished May 05 02:17:23 PM PDT 24
Peak memory 205756 kb
Host smart-5482d80a-6c96-44c8-8510-f47a370889f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012416874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.3012416874
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.726913331
Short name T1045
Test name
Test status
Simulation time 269932135 ps
CPU time 1.97 seconds
Started May 05 02:17:19 PM PDT 24
Finished May 05 02:17:21 PM PDT 24
Peak memory 214260 kb
Host smart-8c100ea2-8496-4e23-a977-f1da08dbdb08
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726913331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow
_reg_errors.726913331
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.388353342
Short name T1081
Test name
Test status
Simulation time 2575837882 ps
CPU time 10.9 seconds
Started May 05 02:17:21 PM PDT 24
Finished May 05 02:17:32 PM PDT 24
Peak memory 221256 kb
Host smart-1df80406-4dca-4670-8578-14dd6856ea13
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388353342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.k
eymgr_shadow_reg_errors_with_csr_rw.388353342
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.1729450348
Short name T965
Test name
Test status
Simulation time 109892358 ps
CPU time 2.95 seconds
Started May 05 02:17:21 PM PDT 24
Finished May 05 02:17:25 PM PDT 24
Peak memory 214020 kb
Host smart-d9b44eed-baee-4197-85c0-709fb5b726e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729450348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.1729450348
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.690638037
Short name T163
Test name
Test status
Simulation time 125320399 ps
CPU time 4.65 seconds
Started May 05 02:17:21 PM PDT 24
Finished May 05 02:17:26 PM PDT 24
Peak memory 215264 kb
Host smart-5cf071c1-8c05-4b85-be82-d9afc1f70175
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690638037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err.
690638037
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.3093010818
Short name T919
Test name
Test status
Simulation time 134915839 ps
CPU time 2.22 seconds
Started May 05 02:17:20 PM PDT 24
Finished May 05 02:17:23 PM PDT 24
Peak memory 214072 kb
Host smart-e2169fd2-0bcc-4632-8f3e-bc33f33db7ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093010818 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.3093010818
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.712867631
Short name T951
Test name
Test status
Simulation time 16462437 ps
CPU time 0.88 seconds
Started May 05 02:17:21 PM PDT 24
Finished May 05 02:17:23 PM PDT 24
Peak memory 205608 kb
Host smart-39789b28-fa54-4b7b-88e3-13c059be63fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712867631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.712867631
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.427168636
Short name T1060
Test name
Test status
Simulation time 8623611 ps
CPU time 0.8 seconds
Started May 05 02:17:19 PM PDT 24
Finished May 05 02:17:20 PM PDT 24
Peak memory 205540 kb
Host smart-f92153f5-104a-4a98-b929-5f88ebb94106
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427168636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.427168636
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1438758485
Short name T984
Test name
Test status
Simulation time 38046055 ps
CPU time 2.21 seconds
Started May 05 02:17:20 PM PDT 24
Finished May 05 02:17:23 PM PDT 24
Peak memory 205820 kb
Host smart-e498f4da-7840-4aef-bd29-9af8c6ead722
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438758485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.1438758485
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.115743494
Short name T1033
Test name
Test status
Simulation time 92814371 ps
CPU time 1.54 seconds
Started May 05 02:17:19 PM PDT 24
Finished May 05 02:17:21 PM PDT 24
Peak memory 214280 kb
Host smart-ba6d4491-ce12-4d0d-a798-e9d9de0c34f6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115743494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow
_reg_errors.115743494
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3666017935
Short name T978
Test name
Test status
Simulation time 183889264 ps
CPU time 6.06 seconds
Started May 05 02:17:19 PM PDT 24
Finished May 05 02:17:25 PM PDT 24
Peak memory 220124 kb
Host smart-a0d7db11-6f6a-4c13-93ac-96d2cb94d61d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666017935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.3666017935
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2841961254
Short name T968
Test name
Test status
Simulation time 130969574 ps
CPU time 4.56 seconds
Started May 05 02:17:22 PM PDT 24
Finished May 05 02:17:27 PM PDT 24
Peak memory 216304 kb
Host smart-2aa49f09-babd-482a-9d85-dfc11c91d3a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841961254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.2841961254
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2750172788
Short name T1012
Test name
Test status
Simulation time 221285751 ps
CPU time 4.4 seconds
Started May 05 02:17:20 PM PDT 24
Finished May 05 02:17:25 PM PDT 24
Peak memory 205940 kb
Host smart-72a78494-b518-4304-b6ea-c1082e072736
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750172788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.2750172788
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2358585785
Short name T997
Test name
Test status
Simulation time 119835803 ps
CPU time 1.91 seconds
Started May 05 02:17:25 PM PDT 24
Finished May 05 02:17:27 PM PDT 24
Peak memory 220040 kb
Host smart-3e980394-e05c-42ae-990a-f7b957bf91b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358585785 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.2358585785
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.3935556405
Short name T1090
Test name
Test status
Simulation time 155748426 ps
CPU time 1.29 seconds
Started May 05 02:17:24 PM PDT 24
Finished May 05 02:17:26 PM PDT 24
Peak memory 205820 kb
Host smart-fc3691f3-2c83-4ac9-a2f3-357dbe848ee8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935556405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.3935556405
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.2468337860
Short name T1021
Test name
Test status
Simulation time 27128819 ps
CPU time 0.76 seconds
Started May 05 02:17:21 PM PDT 24
Finished May 05 02:17:22 PM PDT 24
Peak memory 205476 kb
Host smart-9d4ff8b7-acc3-4fbc-b692-d7ec076eb487
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468337860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.2468337860
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2738701503
Short name T973
Test name
Test status
Simulation time 41113702 ps
CPU time 1.3 seconds
Started May 05 02:17:23 PM PDT 24
Finished May 05 02:17:25 PM PDT 24
Peak memory 205788 kb
Host smart-a69c769c-626a-4f0e-b9f3-7004183b15fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738701503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.2738701503
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.4129080299
Short name T1047
Test name
Test status
Simulation time 355982290 ps
CPU time 3.18 seconds
Started May 05 02:17:18 PM PDT 24
Finished May 05 02:17:22 PM PDT 24
Peak memory 214324 kb
Host smart-0ed74670-62a7-4c7a-9356-a903c7d4ae5e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129080299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.4129080299
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.1980003726
Short name T945
Test name
Test status
Simulation time 803481437 ps
CPU time 4.93 seconds
Started May 05 02:17:20 PM PDT 24
Finished May 05 02:17:25 PM PDT 24
Peak memory 214200 kb
Host smart-30cc16b4-5da5-4600-b269-f6ae5753f219
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980003726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.1980003726
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.353930907
Short name T923
Test name
Test status
Simulation time 292780783 ps
CPU time 1.63 seconds
Started May 05 02:17:20 PM PDT 24
Finished May 05 02:17:22 PM PDT 24
Peak memory 213920 kb
Host smart-234d8310-b600-4b95-9e19-008eb0b94316
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353930907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.353930907
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.2879673464
Short name T991
Test name
Test status
Simulation time 445599941 ps
CPU time 1.81 seconds
Started May 05 02:17:23 PM PDT 24
Finished May 05 02:17:25 PM PDT 24
Peak memory 214344 kb
Host smart-2aaaab80-4cb4-4e48-9e98-1be681c1a172
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879673464 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.2879673464
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.890052940
Short name T961
Test name
Test status
Simulation time 27157534 ps
CPU time 1.45 seconds
Started May 05 02:17:23 PM PDT 24
Finished May 05 02:17:25 PM PDT 24
Peak memory 205716 kb
Host smart-4e1dabad-1274-4436-afa8-3ae6dbdf8996
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890052940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.890052940
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.2183315262
Short name T1053
Test name
Test status
Simulation time 30891395 ps
CPU time 0.76 seconds
Started May 05 02:17:24 PM PDT 24
Finished May 05 02:17:25 PM PDT 24
Peak memory 205528 kb
Host smart-9a13be37-7e0e-45df-af48-6d0290a480e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183315262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.2183315262
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.363589278
Short name T142
Test name
Test status
Simulation time 292765828 ps
CPU time 1.44 seconds
Started May 05 02:17:24 PM PDT 24
Finished May 05 02:17:26 PM PDT 24
Peak memory 205872 kb
Host smart-27dd4c18-f909-4c77-a8c7-3f4df45266ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363589278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sam
e_csr_outstanding.363589278
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.3111124767
Short name T1038
Test name
Test status
Simulation time 365920236 ps
CPU time 2.91 seconds
Started May 05 02:17:24 PM PDT 24
Finished May 05 02:17:27 PM PDT 24
Peak memory 214308 kb
Host smart-67031dbd-39fb-4e96-97ca-d163ac19ec71
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111124767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.3111124767
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.925431689
Short name T1043
Test name
Test status
Simulation time 682421483 ps
CPU time 10.92 seconds
Started May 05 02:17:25 PM PDT 24
Finished May 05 02:17:36 PM PDT 24
Peak memory 214264 kb
Host smart-337275c6-1630-46a3-bb87-470d7304343e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925431689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.k
eymgr_shadow_reg_errors_with_csr_rw.925431689
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.949786304
Short name T1027
Test name
Test status
Simulation time 110341322 ps
CPU time 1.86 seconds
Started May 05 02:17:26 PM PDT 24
Finished May 05 02:17:28 PM PDT 24
Peak memory 213840 kb
Host smart-dd7b9531-0a80-4a82-b352-40e781de494d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949786304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.949786304
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.206228754
Short name T1086
Test name
Test status
Simulation time 444073158 ps
CPU time 5.19 seconds
Started May 05 02:17:24 PM PDT 24
Finished May 05 02:17:29 PM PDT 24
Peak memory 214028 kb
Host smart-d3a79d78-af41-4db1-b2a2-7e3d7ecf70d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206228754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err.
206228754
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1170044856
Short name T1007
Test name
Test status
Simulation time 554079222 ps
CPU time 2.32 seconds
Started May 05 02:17:25 PM PDT 24
Finished May 05 02:17:28 PM PDT 24
Peak memory 214028 kb
Host smart-c1767b37-7a93-4587-b2ad-654c8615d003
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170044856 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.1170044856
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.1741786609
Short name T1009
Test name
Test status
Simulation time 54323130 ps
CPU time 1.58 seconds
Started May 05 02:17:24 PM PDT 24
Finished May 05 02:17:26 PM PDT 24
Peak memory 205736 kb
Host smart-3db00a47-5fe4-4346-9f38-6aa7aacc5312
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741786609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.1741786609
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.4221199097
Short name T982
Test name
Test status
Simulation time 13469082 ps
CPU time 0.75 seconds
Started May 05 02:17:23 PM PDT 24
Finished May 05 02:17:24 PM PDT 24
Peak memory 205504 kb
Host smart-9b669365-9635-4cd8-8c61-8c499ef06f6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221199097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.4221199097
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.183903602
Short name T971
Test name
Test status
Simulation time 37635071 ps
CPU time 2.39 seconds
Started May 05 02:17:23 PM PDT 24
Finished May 05 02:17:26 PM PDT 24
Peak memory 205876 kb
Host smart-bce9f74a-6335-478e-a9f8-0ddd9d9137df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183903602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sam
e_csr_outstanding.183903602
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.1988549307
Short name T972
Test name
Test status
Simulation time 39900352 ps
CPU time 1.77 seconds
Started May 05 02:17:23 PM PDT 24
Finished May 05 02:17:25 PM PDT 24
Peak memory 214208 kb
Host smart-981befee-3f3e-47fa-8bde-f71dd2728bbe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988549307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.1988549307
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.634747663
Short name T963
Test name
Test status
Simulation time 1634842145 ps
CPU time 9.38 seconds
Started May 05 02:17:24 PM PDT 24
Finished May 05 02:17:34 PM PDT 24
Peak memory 214300 kb
Host smart-ee6afa69-ca9d-41d7-8fe3-3bf113277ff2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634747663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.k
eymgr_shadow_reg_errors_with_csr_rw.634747663
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.795444388
Short name T994
Test name
Test status
Simulation time 39013463 ps
CPU time 3.04 seconds
Started May 05 02:17:25 PM PDT 24
Finished May 05 02:17:28 PM PDT 24
Peak memory 214016 kb
Host smart-f3103b54-cafa-4e1b-b721-b5481105ec8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795444388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.795444388
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.1248412873
Short name T173
Test name
Test status
Simulation time 316531434 ps
CPU time 7.33 seconds
Started May 05 02:17:24 PM PDT 24
Finished May 05 02:17:32 PM PDT 24
Peak memory 214108 kb
Host smart-fd5a5cf7-423d-40f6-9b24-c574ccb7c567
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248412873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.1248412873
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.2445782291
Short name T550
Test name
Test status
Simulation time 40725001 ps
CPU time 0.73 seconds
Started May 05 02:29:27 PM PDT 24
Finished May 05 02:29:28 PM PDT 24
Peak memory 205904 kb
Host smart-8183bf12-b978-4932-89a2-4bc25c5a1139
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445782291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.2445782291
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.3304093895
Short name T730
Test name
Test status
Simulation time 352757139 ps
CPU time 4.28 seconds
Started May 05 02:29:27 PM PDT 24
Finished May 05 02:29:32 PM PDT 24
Peak memory 218088 kb
Host smart-ea16b0f0-fc4a-42e1-aafa-75077cbd92dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304093895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.3304093895
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.2496078126
Short name T593
Test name
Test status
Simulation time 283487019 ps
CPU time 2.83 seconds
Started May 05 02:29:22 PM PDT 24
Finished May 05 02:29:26 PM PDT 24
Peak memory 209248 kb
Host smart-def05b08-ab5f-41b2-a7c3-50b6062ebbc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496078126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.2496078126
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_random.2495746398
Short name T450
Test name
Test status
Simulation time 131889064 ps
CPU time 5.83 seconds
Started May 05 02:29:25 PM PDT 24
Finished May 05 02:29:32 PM PDT 24
Peak memory 218208 kb
Host smart-e219d911-f8b1-41d6-b864-f0edf5e731ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495746398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.2495746398
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.2754728048
Short name T47
Test name
Test status
Simulation time 1575563370 ps
CPU time 7.23 seconds
Started May 05 02:29:31 PM PDT 24
Finished May 05 02:29:39 PM PDT 24
Peak memory 230684 kb
Host smart-d1ded81a-0d07-4b62-9595-ac57120081ba
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754728048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.2754728048
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.2384679103
Short name T502
Test name
Test status
Simulation time 117600129 ps
CPU time 3.13 seconds
Started May 05 02:29:23 PM PDT 24
Finished May 05 02:29:27 PM PDT 24
Peak memory 207360 kb
Host smart-bddef61b-80e4-4690-a33c-f26b4b4d12ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384679103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.2384679103
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.1705207081
Short name T210
Test name
Test status
Simulation time 163866620 ps
CPU time 2.51 seconds
Started May 05 02:29:32 PM PDT 24
Finished May 05 02:29:35 PM PDT 24
Peak memory 206728 kb
Host smart-8a3388dc-b443-438e-8b26-42e9dfa7271e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705207081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.1705207081
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.1336123387
Short name T307
Test name
Test status
Simulation time 170972689 ps
CPU time 2.04 seconds
Started May 05 02:29:22 PM PDT 24
Finished May 05 02:29:25 PM PDT 24
Peak memory 208336 kb
Host smart-0a53d239-3227-4391-8167-43e3a6b238d0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336123387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.1336123387
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.126318070
Short name T745
Test name
Test status
Simulation time 129897103 ps
CPU time 2.34 seconds
Started May 05 02:29:27 PM PDT 24
Finished May 05 02:29:29 PM PDT 24
Peak memory 207908 kb
Host smart-f4ebc210-9b4b-418e-a22f-86a01799ba39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126318070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.126318070
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.3967577771
Short name T130
Test name
Test status
Simulation time 206615467 ps
CPU time 2.29 seconds
Started May 05 02:29:32 PM PDT 24
Finished May 05 02:29:35 PM PDT 24
Peak memory 206636 kb
Host smart-681d6922-e979-4095-b119-ab1118d57b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967577771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.3967577771
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.1112178262
Short name T806
Test name
Test status
Simulation time 5054249052 ps
CPU time 8.3 seconds
Started May 05 02:29:30 PM PDT 24
Finished May 05 02:29:39 PM PDT 24
Peak memory 209540 kb
Host smart-b420f436-c7ce-4e53-acc2-910f047b7aeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112178262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.1112178262
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.2216400610
Short name T17
Test name
Test status
Simulation time 443606050 ps
CPU time 9.6 seconds
Started May 05 02:29:31 PM PDT 24
Finished May 05 02:29:41 PM PDT 24
Peak memory 222556 kb
Host smart-780dbc31-3698-4fa5-81fb-844dab7883f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216400610 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.2216400610
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.2947965245
Short name T421
Test name
Test status
Simulation time 230304053 ps
CPU time 3.75 seconds
Started May 05 02:29:24 PM PDT 24
Finished May 05 02:29:28 PM PDT 24
Peak memory 207724 kb
Host smart-db6c5420-33cf-4384-895a-cb4df566d01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947965245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.2947965245
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.3941591868
Short name T547
Test name
Test status
Simulation time 85361696 ps
CPU time 3.01 seconds
Started May 05 02:29:31 PM PDT 24
Finished May 05 02:29:35 PM PDT 24
Peak memory 209528 kb
Host smart-d07658a2-90e2-41a2-adc1-24e80b1fcc60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941591868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.3941591868
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.3791803853
Short name T658
Test name
Test status
Simulation time 10183621 ps
CPU time 0.81 seconds
Started May 05 02:29:41 PM PDT 24
Finished May 05 02:29:42 PM PDT 24
Peak memory 205848 kb
Host smart-0de7af24-7677-4c4b-ae91-fc3351f21047
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791803853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.3791803853
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.2470346537
Short name T431
Test name
Test status
Simulation time 56511803 ps
CPU time 2.41 seconds
Started May 05 02:29:28 PM PDT 24
Finished May 05 02:29:31 PM PDT 24
Peak memory 214220 kb
Host smart-12c18fda-d783-4260-9794-b2fe4594e7f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2470346537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.2470346537
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.3208148985
Short name T758
Test name
Test status
Simulation time 2147981894 ps
CPU time 14.07 seconds
Started May 05 02:29:35 PM PDT 24
Finished May 05 02:29:50 PM PDT 24
Peak memory 214408 kb
Host smart-e9e492b2-aa77-4a81-9e56-759ef1a82fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208148985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.3208148985
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.1298585855
Short name T518
Test name
Test status
Simulation time 82864409 ps
CPU time 2.36 seconds
Started May 05 02:29:31 PM PDT 24
Finished May 05 02:29:34 PM PDT 24
Peak memory 206996 kb
Host smart-8b731dbb-72ae-4d6e-9027-b4a3583a1eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298585855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.1298585855
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.697323548
Short name T253
Test name
Test status
Simulation time 51154053 ps
CPU time 3.31 seconds
Started May 05 02:29:37 PM PDT 24
Finished May 05 02:29:40 PM PDT 24
Peak memory 222304 kb
Host smart-f84de498-419e-49a5-8931-481db49237e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697323548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.697323548
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.1501560625
Short name T225
Test name
Test status
Simulation time 102954836 ps
CPU time 3.71 seconds
Started May 05 02:29:33 PM PDT 24
Finished May 05 02:29:37 PM PDT 24
Peak memory 219236 kb
Host smart-6e6f4fc7-ae12-4331-b422-eb6ec86a6299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501560625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.1501560625
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.1455783877
Short name T14
Test name
Test status
Simulation time 320978600 ps
CPU time 10.02 seconds
Started May 05 02:29:43 PM PDT 24
Finished May 05 02:29:53 PM PDT 24
Peak memory 231444 kb
Host smart-d6912a11-527a-4e0c-b705-8e413bf1f878
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455783877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.1455783877
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.2026253756
Short name T583
Test name
Test status
Simulation time 2241586536 ps
CPU time 22.31 seconds
Started May 05 02:29:30 PM PDT 24
Finished May 05 02:29:53 PM PDT 24
Peak memory 208656 kb
Host smart-a486d44b-b839-42af-ad0f-a275d847312f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026253756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.2026253756
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.2229109719
Short name T1
Test name
Test status
Simulation time 435168610 ps
CPU time 5.49 seconds
Started May 05 02:29:30 PM PDT 24
Finished May 05 02:29:36 PM PDT 24
Peak memory 206588 kb
Host smart-ed282fb9-36a3-4621-8c24-5bd33f9cfed1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229109719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.2229109719
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.2079746772
Short name T805
Test name
Test status
Simulation time 91584442 ps
CPU time 3.54 seconds
Started May 05 02:29:27 PM PDT 24
Finished May 05 02:29:31 PM PDT 24
Peak memory 206804 kb
Host smart-5cf5cde4-1808-496d-8a68-6ec96e7570d7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079746772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.2079746772
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.1417284572
Short name T675
Test name
Test status
Simulation time 747955631 ps
CPU time 7.84 seconds
Started May 05 02:29:32 PM PDT 24
Finished May 05 02:29:40 PM PDT 24
Peak memory 207928 kb
Host smart-ac4cae7f-e9fd-4cdc-b37d-a7a798284b63
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417284572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.1417284572
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.1190366577
Short name T545
Test name
Test status
Simulation time 87165408 ps
CPU time 3.46 seconds
Started May 05 02:29:37 PM PDT 24
Finished May 05 02:29:41 PM PDT 24
Peak memory 209580 kb
Host smart-f7bb44ec-6379-41f2-9d6e-96b99349ae18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190366577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.1190366577
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.1697792715
Short name T916
Test name
Test status
Simulation time 5919554137 ps
CPU time 50.27 seconds
Started May 05 02:29:28 PM PDT 24
Finished May 05 02:30:18 PM PDT 24
Peak memory 208936 kb
Host smart-41410351-6e12-4464-adb2-4a17f4681c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697792715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.1697792715
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.3989358422
Short name T84
Test name
Test status
Simulation time 204700592 ps
CPU time 14.16 seconds
Started May 05 02:29:37 PM PDT 24
Finished May 05 02:29:52 PM PDT 24
Peak memory 222668 kb
Host smart-8d580103-21e5-4822-8067-0dc77ca69689
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989358422 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.3989358422
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.1661390309
Short name T243
Test name
Test status
Simulation time 184392501 ps
CPU time 6.74 seconds
Started May 05 02:29:31 PM PDT 24
Finished May 05 02:29:39 PM PDT 24
Peak memory 207440 kb
Host smart-a40495df-bf91-4e5f-ba6c-6cdd743049aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661390309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.1661390309
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.447224686
Short name T129
Test name
Test status
Simulation time 526198489 ps
CPU time 3.27 seconds
Started May 05 02:29:36 PM PDT 24
Finished May 05 02:29:39 PM PDT 24
Peak memory 209768 kb
Host smart-c7805952-738c-4b24-be39-51443f22a850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447224686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.447224686
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.1953006809
Short name T72
Test name
Test status
Simulation time 112546843 ps
CPU time 5.15 seconds
Started May 05 02:31:20 PM PDT 24
Finished May 05 02:31:26 PM PDT 24
Peak memory 210868 kb
Host smart-2d99154d-71b2-49e2-b6a1-31fe2e0e471c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953006809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.1953006809
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.3619241187
Short name T83
Test name
Test status
Simulation time 56619155 ps
CPU time 2.28 seconds
Started May 05 02:31:13 PM PDT 24
Finished May 05 02:31:16 PM PDT 24
Peak memory 209276 kb
Host smart-476c96d0-1ea3-499f-abd9-da53994281da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619241187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.3619241187
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.1447958935
Short name T94
Test name
Test status
Simulation time 944191374 ps
CPU time 9.07 seconds
Started May 05 02:31:16 PM PDT 24
Finished May 05 02:31:25 PM PDT 24
Peak memory 214232 kb
Host smart-283326e0-8f0a-4c68-af4e-60f04c2339a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447958935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.1447958935
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.2769369292
Short name T716
Test name
Test status
Simulation time 80545678 ps
CPU time 3.92 seconds
Started May 05 02:31:19 PM PDT 24
Finished May 05 02:31:23 PM PDT 24
Peak memory 219864 kb
Host smart-85455d00-4b5c-4fae-aeb8-8a673d7b27f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769369292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.2769369292
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.2932143568
Short name T48
Test name
Test status
Simulation time 463383887 ps
CPU time 2.88 seconds
Started May 05 02:31:11 PM PDT 24
Finished May 05 02:31:15 PM PDT 24
Peak memory 206624 kb
Host smart-92b02d5e-5956-4e59-bad2-b33ee24b7372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932143568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.2932143568
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.3373061880
Short name T405
Test name
Test status
Simulation time 2050325024 ps
CPU time 20.02 seconds
Started May 05 02:31:16 PM PDT 24
Finished May 05 02:31:36 PM PDT 24
Peak memory 207984 kb
Host smart-06cc0d65-29be-4999-b935-a5902f09e0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373061880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.3373061880
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.2589795323
Short name T799
Test name
Test status
Simulation time 118797763 ps
CPU time 2.54 seconds
Started May 05 02:31:13 PM PDT 24
Finished May 05 02:31:16 PM PDT 24
Peak memory 206060 kb
Host smart-b74dee59-2cb5-4627-9b2a-ad47bea2917e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589795323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.2589795323
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.4063799996
Short name T650
Test name
Test status
Simulation time 115503722 ps
CPU time 2.98 seconds
Started May 05 02:31:11 PM PDT 24
Finished May 05 02:31:15 PM PDT 24
Peak memory 208496 kb
Host smart-89855740-9437-4de0-b8e9-3b80209ee8fb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063799996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.4063799996
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.2865204815
Short name T735
Test name
Test status
Simulation time 96187508 ps
CPU time 3.44 seconds
Started May 05 02:31:14 PM PDT 24
Finished May 05 02:31:19 PM PDT 24
Peak memory 206540 kb
Host smart-6e2ed373-03d1-4df3-8ade-cd3f0267016e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865204815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.2865204815
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.401419442
Short name T480
Test name
Test status
Simulation time 165488621 ps
CPU time 2.16 seconds
Started May 05 02:31:18 PM PDT 24
Finished May 05 02:31:21 PM PDT 24
Peak memory 208968 kb
Host smart-b6e46374-8db7-4a57-94e2-99045af7322d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401419442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.401419442
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.2350316366
Short name T776
Test name
Test status
Simulation time 68586870 ps
CPU time 3.04 seconds
Started May 05 02:31:07 PM PDT 24
Finished May 05 02:31:10 PM PDT 24
Peak memory 207808 kb
Host smart-bd20990a-743b-4b41-af3a-f81d2eda1c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350316366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.2350316366
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.2314486427
Short name T215
Test name
Test status
Simulation time 540826398 ps
CPU time 11.29 seconds
Started May 05 02:31:19 PM PDT 24
Finished May 05 02:31:31 PM PDT 24
Peak memory 219196 kb
Host smart-26163484-578d-463c-ab47-d53ebf1c0a4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314486427 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.2314486427
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.895478251
Short name T820
Test name
Test status
Simulation time 166658136 ps
CPU time 3.15 seconds
Started May 05 02:31:11 PM PDT 24
Finished May 05 02:31:15 PM PDT 24
Peak memory 207092 kb
Host smart-849f1ebe-87dc-4d78-95d7-99a22fdcdab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895478251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.895478251
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.4097279684
Short name T841
Test name
Test status
Simulation time 523215017 ps
CPU time 11.24 seconds
Started May 05 02:31:20 PM PDT 24
Finished May 05 02:31:31 PM PDT 24
Peak memory 210980 kb
Host smart-c4c46077-5eb3-4844-8570-91117e8d1cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097279684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.4097279684
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.2535868518
Short name T493
Test name
Test status
Simulation time 42481398 ps
CPU time 0.77 seconds
Started May 05 02:31:20 PM PDT 24
Finished May 05 02:31:22 PM PDT 24
Peak memory 205864 kb
Host smart-88fc7007-5a07-4f7c-abe9-cb8cba634cc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535868518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.2535868518
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.253586182
Short name T412
Test name
Test status
Simulation time 189596959 ps
CPU time 9.52 seconds
Started May 05 02:31:19 PM PDT 24
Finished May 05 02:31:29 PM PDT 24
Peak memory 214232 kb
Host smart-151841c8-8922-4b5d-9fb4-bf66554b4152
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=253586182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.253586182
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.537108932
Short name T595
Test name
Test status
Simulation time 85296886 ps
CPU time 1.33 seconds
Started May 05 02:31:22 PM PDT 24
Finished May 05 02:31:24 PM PDT 24
Peak memory 207524 kb
Host smart-63566291-b6b2-4a65-954d-9268a65b52d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537108932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.537108932
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.3446593854
Short name T270
Test name
Test status
Simulation time 299842382 ps
CPU time 2.11 seconds
Started May 05 02:31:23 PM PDT 24
Finished May 05 02:31:25 PM PDT 24
Peak memory 207636 kb
Host smart-01464e62-63f5-40a0-b091-b9b65461e0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446593854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.3446593854
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.3428836645
Short name T906
Test name
Test status
Simulation time 3156492932 ps
CPU time 20.32 seconds
Started May 05 02:31:22 PM PDT 24
Finished May 05 02:31:43 PM PDT 24
Peak memory 214428 kb
Host smart-e05222f6-f241-4114-a9fa-e8a9c849b0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428836645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.3428836645
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.3018120289
Short name T679
Test name
Test status
Simulation time 79169765 ps
CPU time 4.06 seconds
Started May 05 02:31:22 PM PDT 24
Finished May 05 02:31:26 PM PDT 24
Peak memory 214224 kb
Host smart-77de85df-56de-40ef-bbe5-a7a26e895f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018120289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.3018120289
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_random.3293096130
Short name T381
Test name
Test status
Simulation time 1335319550 ps
CPU time 5.6 seconds
Started May 05 02:31:17 PM PDT 24
Finished May 05 02:31:23 PM PDT 24
Peak memory 210280 kb
Host smart-8e3acb6a-b114-459f-ae28-5f7e1ad50e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293096130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.3293096130
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.2982692799
Short name T734
Test name
Test status
Simulation time 146603022 ps
CPU time 2.94 seconds
Started May 05 02:31:17 PM PDT 24
Finished May 05 02:31:20 PM PDT 24
Peak memory 206704 kb
Host smart-a89e2e5a-6f83-413f-ab1a-75ca9edef75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982692799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.2982692799
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.249860265
Short name T724
Test name
Test status
Simulation time 69009982 ps
CPU time 3.64 seconds
Started May 05 02:31:17 PM PDT 24
Finished May 05 02:31:21 PM PDT 24
Peak memory 208384 kb
Host smart-e8b98053-2a3d-4777-b615-02dcd5c3b5a2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249860265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.249860265
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.755528460
Short name T870
Test name
Test status
Simulation time 70099222 ps
CPU time 3.56 seconds
Started May 05 02:31:17 PM PDT 24
Finished May 05 02:31:21 PM PDT 24
Peak memory 208808 kb
Host smart-0b274511-4b51-4122-b9ad-eefabbc122c6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755528460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.755528460
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.357162091
Short name T772
Test name
Test status
Simulation time 386533160 ps
CPU time 4.36 seconds
Started May 05 02:31:17 PM PDT 24
Finished May 05 02:31:22 PM PDT 24
Peak memory 208580 kb
Host smart-eda1e4a4-310b-4e8d-abab-f09ea2605e0c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357162091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.357162091
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.2327765172
Short name T721
Test name
Test status
Simulation time 396373982 ps
CPU time 8.1 seconds
Started May 05 02:31:20 PM PDT 24
Finished May 05 02:31:29 PM PDT 24
Peak memory 209700 kb
Host smart-47571691-c5e8-4683-b99b-81fa7b8db782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327765172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.2327765172
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.4022348654
Short name T725
Test name
Test status
Simulation time 3338184873 ps
CPU time 20.11 seconds
Started May 05 02:31:17 PM PDT 24
Finished May 05 02:31:38 PM PDT 24
Peak memory 208528 kb
Host smart-4ea30686-5619-42d7-91e2-8ce64d7a1f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022348654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.4022348654
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.2870242367
Short name T59
Test name
Test status
Simulation time 391649480 ps
CPU time 10.47 seconds
Started May 05 02:31:21 PM PDT 24
Finished May 05 02:31:32 PM PDT 24
Peak memory 215712 kb
Host smart-6a7d81e4-be1b-41d3-9fc8-5ece0bcff9b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870242367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.2870242367
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.2217245262
Short name T538
Test name
Test status
Simulation time 110523538 ps
CPU time 4.76 seconds
Started May 05 02:31:20 PM PDT 24
Finished May 05 02:31:25 PM PDT 24
Peak memory 218284 kb
Host smart-b1cd7053-ab8f-4b94-8329-ce3870f3ce0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217245262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.2217245262
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.3565018829
Short name T669
Test name
Test status
Simulation time 16835733 ps
CPU time 0.76 seconds
Started May 05 02:31:36 PM PDT 24
Finished May 05 02:31:37 PM PDT 24
Peak memory 205880 kb
Host smart-0f2c62de-4a59-410c-a55c-9d233f712207
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565018829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.3565018829
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.1839473207
Short name T182
Test name
Test status
Simulation time 337096171 ps
CPU time 9.49 seconds
Started May 05 02:31:33 PM PDT 24
Finished May 05 02:31:43 PM PDT 24
Peak memory 215372 kb
Host smart-bf94833f-d069-48a4-9819-a3d148220342
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1839473207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.1839473207
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.1151546650
Short name T749
Test name
Test status
Simulation time 1285303544 ps
CPU time 22.26 seconds
Started May 05 02:31:30 PM PDT 24
Finished May 05 02:31:52 PM PDT 24
Peak memory 209864 kb
Host smart-a30bf66a-fb7f-419e-b539-ae841eb65e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151546650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.1151546650
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.1273978611
Short name T306
Test name
Test status
Simulation time 81353661 ps
CPU time 1.68 seconds
Started May 05 02:31:31 PM PDT 24
Finished May 05 02:31:33 PM PDT 24
Peak memory 214256 kb
Host smart-faff00fe-d3cc-4d54-a480-a31ab2bdaf8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273978611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.1273978611
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.1787034307
Short name T294
Test name
Test status
Simulation time 69077991 ps
CPU time 2.81 seconds
Started May 05 02:31:37 PM PDT 24
Finished May 05 02:31:40 PM PDT 24
Peak memory 220720 kb
Host smart-2b06e3a7-2d87-4795-8082-bb7742b9e450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787034307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.1787034307
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.1025954588
Short name T851
Test name
Test status
Simulation time 54132724 ps
CPU time 3.14 seconds
Started May 05 02:31:32 PM PDT 24
Finished May 05 02:31:35 PM PDT 24
Peak memory 220476 kb
Host smart-38b33b23-4dea-47e2-b42c-1b6acba89f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025954588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.1025954588
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.2329343631
Short name T512
Test name
Test status
Simulation time 137785419 ps
CPU time 4.98 seconds
Started May 05 02:31:33 PM PDT 24
Finished May 05 02:31:38 PM PDT 24
Peak memory 207824 kb
Host smart-8b4b9bf1-9c78-4310-8f6e-d39b533199a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329343631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.2329343631
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.3063471606
Short name T766
Test name
Test status
Simulation time 136443553 ps
CPU time 3.69 seconds
Started May 05 02:31:27 PM PDT 24
Finished May 05 02:31:31 PM PDT 24
Peak memory 208476 kb
Host smart-2aae9e1d-bdb0-4160-8843-a80da7df62dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063471606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.3063471606
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.2515926395
Short name T435
Test name
Test status
Simulation time 265767402 ps
CPU time 2.66 seconds
Started May 05 02:31:31 PM PDT 24
Finished May 05 02:31:34 PM PDT 24
Peak memory 208600 kb
Host smart-235b026c-0e02-4f9e-a1f5-965375183990
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515926395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.2515926395
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.2373885126
Short name T750
Test name
Test status
Simulation time 274534670 ps
CPU time 2.93 seconds
Started May 05 02:31:29 PM PDT 24
Finished May 05 02:31:33 PM PDT 24
Peak memory 206740 kb
Host smart-a41fb028-f2ce-4bfa-9f50-29a72a798fb1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373885126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.2373885126
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.80631027
Short name T524
Test name
Test status
Simulation time 131453328 ps
CPU time 2.71 seconds
Started May 05 02:31:31 PM PDT 24
Finished May 05 02:31:34 PM PDT 24
Peak memory 206708 kb
Host smart-dc1b8974-39f3-4075-8ee0-bbe7cb3c9091
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80631027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.80631027
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.1294932781
Short name T825
Test name
Test status
Simulation time 17891551 ps
CPU time 1.54 seconds
Started May 05 02:31:36 PM PDT 24
Finished May 05 02:31:38 PM PDT 24
Peak memory 209680 kb
Host smart-76b6b50a-9ccf-4efe-9e6f-461857b2d2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294932781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.1294932781
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.2938568669
Short name T624
Test name
Test status
Simulation time 171762179 ps
CPU time 5.79 seconds
Started May 05 02:31:26 PM PDT 24
Finished May 05 02:31:32 PM PDT 24
Peak memory 207900 kb
Host smart-2279899a-0570-4225-bea0-0f70d75308a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938568669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.2938568669
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.3742370502
Short name T82
Test name
Test status
Simulation time 2815357905 ps
CPU time 90.6 seconds
Started May 05 02:31:38 PM PDT 24
Finished May 05 02:33:09 PM PDT 24
Peak memory 216048 kb
Host smart-f56d096a-536c-4d4f-81d8-a2dba90f11b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742370502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.3742370502
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.457548782
Short name T589
Test name
Test status
Simulation time 545143209 ps
CPU time 11.17 seconds
Started May 05 02:31:31 PM PDT 24
Finished May 05 02:31:43 PM PDT 24
Peak memory 214260 kb
Host smart-ddb6a92d-c76d-49a9-8331-013e697924f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457548782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.457548782
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.386453871
Short name T689
Test name
Test status
Simulation time 123043111 ps
CPU time 2.33 seconds
Started May 05 02:31:37 PM PDT 24
Finished May 05 02:31:40 PM PDT 24
Peak memory 210056 kb
Host smart-212a1ab4-4cd7-4381-a742-c01ac8e6c4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386453871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.386453871
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.1265386431
Short name T499
Test name
Test status
Simulation time 38626066 ps
CPU time 0.9 seconds
Started May 05 02:31:49 PM PDT 24
Finished May 05 02:31:52 PM PDT 24
Peak memory 205840 kb
Host smart-8488f2cc-c7c1-4259-a82c-adee8abf7078
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265386431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.1265386431
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.2478823772
Short name T783
Test name
Test status
Simulation time 105761308 ps
CPU time 4.07 seconds
Started May 05 02:31:49 PM PDT 24
Finished May 05 02:31:54 PM PDT 24
Peak memory 214496 kb
Host smart-b47fa366-ecdf-4756-b43b-d624c015d1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478823772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.2478823772
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.2411956227
Short name T839
Test name
Test status
Simulation time 68574717 ps
CPU time 2.24 seconds
Started May 05 02:31:39 PM PDT 24
Finished May 05 02:31:41 PM PDT 24
Peak memory 208524 kb
Host smart-515ea15e-58db-4948-9fbe-8839b5c73255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411956227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.2411956227
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.756577507
Short name T288
Test name
Test status
Simulation time 111293447 ps
CPU time 2.33 seconds
Started May 05 02:31:41 PM PDT 24
Finished May 05 02:31:44 PM PDT 24
Peak memory 208452 kb
Host smart-7dc1a212-f19d-429f-ae3d-a68f62936b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756577507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.756577507
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.346414259
Short name T433
Test name
Test status
Simulation time 127844654 ps
CPU time 3.13 seconds
Started May 05 02:31:38 PM PDT 24
Finished May 05 02:31:42 PM PDT 24
Peak memory 219812 kb
Host smart-7d170a0a-0715-425d-be22-c89142cd78ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346414259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.346414259
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.218636670
Short name T880
Test name
Test status
Simulation time 1195971187 ps
CPU time 29.61 seconds
Started May 05 02:31:45 PM PDT 24
Finished May 05 02:32:15 PM PDT 24
Peak memory 207976 kb
Host smart-a0675c68-1c4f-4bf2-bda8-f7e930930dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218636670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.218636670
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.1287086799
Short name T848
Test name
Test status
Simulation time 42846141 ps
CPU time 2.44 seconds
Started May 05 02:31:37 PM PDT 24
Finished May 05 02:31:41 PM PDT 24
Peak memory 206548 kb
Host smart-f8d5a3f1-fb67-4be2-912e-0d740a616385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287086799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.1287086799
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.410522801
Short name T912
Test name
Test status
Simulation time 67386846 ps
CPU time 3.39 seconds
Started May 05 02:31:36 PM PDT 24
Finished May 05 02:31:40 PM PDT 24
Peak memory 208944 kb
Host smart-f004dfa0-a1c6-495c-a7bc-d0d5f4e0127c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410522801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.410522801
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.4081834146
Short name T249
Test name
Test status
Simulation time 88793465 ps
CPU time 3.48 seconds
Started May 05 02:31:38 PM PDT 24
Finished May 05 02:31:42 PM PDT 24
Peak memory 208488 kb
Host smart-b26ad637-055c-4473-8064-c69654e969cb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081834146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.4081834146
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.1909337754
Short name T541
Test name
Test status
Simulation time 171859907 ps
CPU time 6.61 seconds
Started May 05 02:31:41 PM PDT 24
Finished May 05 02:31:48 PM PDT 24
Peak memory 207800 kb
Host smart-56184fdd-c057-4108-905b-843168f76a08
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909337754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.1909337754
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.2110105775
Short name T427
Test name
Test status
Simulation time 122820455 ps
CPU time 1.97 seconds
Started May 05 02:31:43 PM PDT 24
Finished May 05 02:31:46 PM PDT 24
Peak memory 207360 kb
Host smart-c9c31d1f-4bb1-4994-8f65-07af57de4fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110105775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.2110105775
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.4216089873
Short name T194
Test name
Test status
Simulation time 102740017 ps
CPU time 3.79 seconds
Started May 05 02:31:37 PM PDT 24
Finished May 05 02:31:42 PM PDT 24
Peak memory 206676 kb
Host smart-8bc5fc58-05cd-46b1-9c5c-04b8ac83613a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216089873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.4216089873
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.756694611
Short name T807
Test name
Test status
Simulation time 1090962834 ps
CPU time 34.77 seconds
Started May 05 02:31:48 PM PDT 24
Finished May 05 02:32:24 PM PDT 24
Peak memory 222448 kb
Host smart-cd3ed578-6986-449e-bbe7-d26bb11ac283
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756694611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.756694611
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.2529022908
Short name T220
Test name
Test status
Simulation time 246398408 ps
CPU time 7.65 seconds
Started May 05 02:31:48 PM PDT 24
Finished May 05 02:31:56 PM PDT 24
Peak memory 222448 kb
Host smart-b600e6f7-13bc-4b56-b6b2-8004cf6a8fb5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529022908 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.2529022908
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.1409470272
Short name T874
Test name
Test status
Simulation time 415874402 ps
CPU time 6.19 seconds
Started May 05 02:31:41 PM PDT 24
Finished May 05 02:31:48 PM PDT 24
Peak memory 209004 kb
Host smart-40d6e385-ba5f-4652-9145-29c752d55b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409470272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.1409470272
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.2817000861
Short name T170
Test name
Test status
Simulation time 466825775 ps
CPU time 5.01 seconds
Started May 05 02:31:48 PM PDT 24
Finished May 05 02:31:54 PM PDT 24
Peak memory 210308 kb
Host smart-20a6880a-7b1e-46d5-b0a3-b505ae929993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817000861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.2817000861
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.983659335
Short name T445
Test name
Test status
Simulation time 113713459 ps
CPU time 0.69 seconds
Started May 05 02:31:53 PM PDT 24
Finished May 05 02:31:55 PM PDT 24
Peak memory 205912 kb
Host smart-ccd1a4d3-bbc8-41a8-8f0c-080bcd2a5002
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983659335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.983659335
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.896303023
Short name T878
Test name
Test status
Simulation time 157118052 ps
CPU time 8.78 seconds
Started May 05 02:31:50 PM PDT 24
Finished May 05 02:32:00 PM PDT 24
Peak memory 214412 kb
Host smart-f581c37c-a560-4f15-ab78-3fbd060778c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=896303023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.896303023
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.87856639
Short name T756
Test name
Test status
Simulation time 119807234 ps
CPU time 1.91 seconds
Started May 05 02:31:48 PM PDT 24
Finished May 05 02:31:51 PM PDT 24
Peak memory 206964 kb
Host smart-4d11be6d-c2c7-436f-9dd7-2a3db2b3ad92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87856639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.87856639
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.2260357161
Short name T915
Test name
Test status
Simulation time 458893823 ps
CPU time 4.91 seconds
Started May 05 02:31:51 PM PDT 24
Finished May 05 02:31:56 PM PDT 24
Peak memory 214244 kb
Host smart-0edf09f8-051a-4176-b62e-e5bcc9ae27be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260357161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.2260357161
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.748402623
Short name T495
Test name
Test status
Simulation time 384927303 ps
CPU time 4.44 seconds
Started May 05 02:31:54 PM PDT 24
Finished May 05 02:31:59 PM PDT 24
Peak memory 214104 kb
Host smart-d5fdd46a-e178-4dcf-9d6b-7cfde78b7349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748402623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.748402623
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.3013100030
Short name T53
Test name
Test status
Simulation time 99557124 ps
CPU time 2.03 seconds
Started May 05 02:31:51 PM PDT 24
Finished May 05 02:31:54 PM PDT 24
Peak memory 219516 kb
Host smart-863ebeb6-0dcc-4ae5-81a8-e6cd847bcef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013100030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.3013100030
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.1333395421
Short name T849
Test name
Test status
Simulation time 377528353 ps
CPU time 4.63 seconds
Started May 05 02:31:49 PM PDT 24
Finished May 05 02:31:55 PM PDT 24
Peak memory 214212 kb
Host smart-cea43e22-db02-4fb6-8f98-6cce1b4f4dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333395421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.1333395421
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.3347873067
Short name T736
Test name
Test status
Simulation time 238443796 ps
CPU time 1.87 seconds
Started May 05 02:31:49 PM PDT 24
Finished May 05 02:31:52 PM PDT 24
Peak memory 206664 kb
Host smart-3b448e7f-481d-45c3-be38-e5600f5373a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347873067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.3347873067
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.2472796338
Short name T705
Test name
Test status
Simulation time 33033425 ps
CPU time 2.23 seconds
Started May 05 02:31:48 PM PDT 24
Finished May 05 02:31:50 PM PDT 24
Peak memory 206556 kb
Host smart-94f6203d-3c14-4689-9c7e-739606f8bf7f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472796338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.2472796338
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.503111289
Short name T309
Test name
Test status
Simulation time 601257890 ps
CPU time 7.39 seconds
Started May 05 02:31:50 PM PDT 24
Finished May 05 02:31:58 PM PDT 24
Peak memory 208256 kb
Host smart-6f2c6317-6d65-4d23-b79e-74a623dfdd97
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503111289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.503111289
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.2579305378
Short name T691
Test name
Test status
Simulation time 1761260063 ps
CPU time 9.16 seconds
Started May 05 02:31:51 PM PDT 24
Finished May 05 02:32:02 PM PDT 24
Peak memory 208764 kb
Host smart-2be0bc0c-038d-44bd-8ed0-62253fa49135
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579305378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.2579305378
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.1801746163
Short name T349
Test name
Test status
Simulation time 1808450889 ps
CPU time 10.46 seconds
Started May 05 02:31:53 PM PDT 24
Finished May 05 02:32:05 PM PDT 24
Peak memory 222512 kb
Host smart-9dcc38b7-7b6f-4ecc-8b46-fd1cfc865b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801746163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.1801746163
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.3064846236
Short name T695
Test name
Test status
Simulation time 893794089 ps
CPU time 8.32 seconds
Started May 05 02:31:44 PM PDT 24
Finished May 05 02:31:53 PM PDT 24
Peak memory 208232 kb
Host smart-38200f20-2bfe-4d0d-b03b-3ccd8b20558c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064846236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.3064846236
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.1266274957
Short name T719
Test name
Test status
Simulation time 1461914658 ps
CPU time 30.74 seconds
Started May 05 02:31:53 PM PDT 24
Finished May 05 02:32:25 PM PDT 24
Peak memory 216232 kb
Host smart-9af32ce6-04da-44be-b2e0-0e6be9713006
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266274957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.1266274957
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.1936843549
Short name T181
Test name
Test status
Simulation time 428273752 ps
CPU time 17.03 seconds
Started May 05 02:31:53 PM PDT 24
Finished May 05 02:32:11 PM PDT 24
Peak memory 220872 kb
Host smart-d4f3cdc2-3b72-4a71-a1a6-a661a731617c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936843549 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.1936843549
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.1422325892
Short name T401
Test name
Test status
Simulation time 55281839 ps
CPU time 2.63 seconds
Started May 05 02:31:51 PM PDT 24
Finished May 05 02:31:55 PM PDT 24
Peak memory 218044 kb
Host smart-a4fe6352-d881-4aa9-afb0-03ae4805cdf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422325892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.1422325892
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.3733473001
Short name T468
Test name
Test status
Simulation time 84547756 ps
CPU time 2.04 seconds
Started May 05 02:31:52 PM PDT 24
Finished May 05 02:31:55 PM PDT 24
Peak memory 209752 kb
Host smart-6a2a6bd1-9e17-4bd3-8372-8439f225bf91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733473001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.3733473001
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.2888039383
Short name T584
Test name
Test status
Simulation time 62343616 ps
CPU time 0.78 seconds
Started May 05 02:32:04 PM PDT 24
Finished May 05 02:32:05 PM PDT 24
Peak memory 205784 kb
Host smart-217ab183-b17a-4617-90e4-ab1622bf215c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888039383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.2888039383
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.3113736772
Short name T247
Test name
Test status
Simulation time 53156141 ps
CPU time 4.09 seconds
Started May 05 02:32:04 PM PDT 24
Finished May 05 02:32:09 PM PDT 24
Peak memory 214880 kb
Host smart-c8ee445d-e901-4ec1-8d9a-1738d7ec6940
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3113736772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.3113736772
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.3281580688
Short name T602
Test name
Test status
Simulation time 337216158 ps
CPU time 3.17 seconds
Started May 05 02:32:00 PM PDT 24
Finished May 05 02:32:04 PM PDT 24
Peak memory 210184 kb
Host smart-25d36a8a-c139-4ae3-90eb-2d0ffbd9008f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281580688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.3281580688
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.396343518
Short name T865
Test name
Test status
Simulation time 93202874 ps
CPU time 1.88 seconds
Started May 05 02:32:01 PM PDT 24
Finished May 05 02:32:04 PM PDT 24
Peak memory 218140 kb
Host smart-4a7a115c-9143-4812-8f1b-f175d4d64c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396343518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.396343518
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.1278151339
Short name T344
Test name
Test status
Simulation time 302968927 ps
CPU time 3.16 seconds
Started May 05 02:32:02 PM PDT 24
Finished May 05 02:32:05 PM PDT 24
Peak memory 214176 kb
Host smart-42908020-6441-4fe9-95e9-2de7ff33ebb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278151339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.1278151339
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.1719300190
Short name T711
Test name
Test status
Simulation time 169572346 ps
CPU time 2.36 seconds
Started May 05 02:32:01 PM PDT 24
Finished May 05 02:32:03 PM PDT 24
Peak memory 214152 kb
Host smart-a7f1dee8-41b2-43d6-bfed-11dbe1d762aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719300190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.1719300190
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.2708542589
Short name T881
Test name
Test status
Simulation time 77677342 ps
CPU time 2.38 seconds
Started May 05 02:32:02 PM PDT 24
Finished May 05 02:32:05 PM PDT 24
Peak memory 215240 kb
Host smart-276ea34f-9d24-4ced-a324-b14b757a127f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708542589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.2708542589
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.811832602
Short name T269
Test name
Test status
Simulation time 76913131 ps
CPU time 3.79 seconds
Started May 05 02:32:01 PM PDT 24
Finished May 05 02:32:05 PM PDT 24
Peak memory 207256 kb
Host smart-ad9646da-8e55-428c-905d-eb2f89c24354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811832602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.811832602
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.2920963926
Short name T654
Test name
Test status
Simulation time 63350327 ps
CPU time 2.9 seconds
Started May 05 02:31:56 PM PDT 24
Finished May 05 02:32:00 PM PDT 24
Peak memory 208120 kb
Host smart-fcae27c8-3d95-48d9-af8b-de5d1daf54df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920963926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.2920963926
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.3957789618
Short name T313
Test name
Test status
Simulation time 3409032451 ps
CPU time 23.79 seconds
Started May 05 02:31:56 PM PDT 24
Finished May 05 02:32:20 PM PDT 24
Peak memory 208716 kb
Host smart-db6d3ff9-34b5-4b59-9049-5d3685be69a4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957789618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.3957789618
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.3962075688
Short name T793
Test name
Test status
Simulation time 226925964 ps
CPU time 3.04 seconds
Started May 05 02:32:03 PM PDT 24
Finished May 05 02:32:07 PM PDT 24
Peak memory 206744 kb
Host smart-008fc009-a5ea-4168-beb3-4db8f92ee743
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962075688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.3962075688
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.3925643051
Short name T193
Test name
Test status
Simulation time 136923195 ps
CPU time 2.64 seconds
Started May 05 02:31:59 PM PDT 24
Finished May 05 02:32:02 PM PDT 24
Peak memory 208056 kb
Host smart-1d26cc42-b984-4124-9d77-3ffc74de3613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925643051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.3925643051
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.377287513
Short name T827
Test name
Test status
Simulation time 89342610 ps
CPU time 2.06 seconds
Started May 05 02:31:54 PM PDT 24
Finished May 05 02:31:57 PM PDT 24
Peak memory 208472 kb
Host smart-1ced5bc6-c7aa-4f32-8c59-438c0f008a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377287513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.377287513
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.1113350383
Short name T907
Test name
Test status
Simulation time 240244517 ps
CPU time 9.82 seconds
Started May 05 02:32:03 PM PDT 24
Finished May 05 02:32:13 PM PDT 24
Peak memory 222644 kb
Host smart-f42dad52-8926-4420-ac35-da345f102618
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113350383 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.1113350383
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.1941428149
Short name T530
Test name
Test status
Simulation time 3490263652 ps
CPU time 14.98 seconds
Started May 05 02:32:05 PM PDT 24
Finished May 05 02:32:20 PM PDT 24
Peak memory 214384 kb
Host smart-1ddfd664-9b39-46c2-a97f-86b432a03fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941428149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.1941428149
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.1484921996
Short name T387
Test name
Test status
Simulation time 104421591 ps
CPU time 3.2 seconds
Started May 05 02:32:05 PM PDT 24
Finished May 05 02:32:08 PM PDT 24
Peak memory 210096 kb
Host smart-c86d6c35-5444-41f3-bedc-6804bf7849fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484921996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.1484921996
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.1833403361
Short name T484
Test name
Test status
Simulation time 50160614 ps
CPU time 0.89 seconds
Started May 05 02:32:11 PM PDT 24
Finished May 05 02:32:12 PM PDT 24
Peak memory 205820 kb
Host smart-f4cf60a1-cfb3-4a3e-bb44-7ff0822f7263
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833403361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.1833403361
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.1328257765
Short name T289
Test name
Test status
Simulation time 340884364 ps
CPU time 4.89 seconds
Started May 05 02:32:08 PM PDT 24
Finished May 05 02:32:13 PM PDT 24
Peak memory 214248 kb
Host smart-e6fc83da-ba8b-469c-92c5-5d91427c1f80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1328257765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.1328257765
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.982604171
Short name T862
Test name
Test status
Simulation time 99617841 ps
CPU time 3.22 seconds
Started May 05 02:32:09 PM PDT 24
Finished May 05 02:32:12 PM PDT 24
Peak memory 218248 kb
Host smart-3f81278b-5e69-4b61-b72d-d2db60bc23f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982604171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.982604171
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.233289388
Short name T594
Test name
Test status
Simulation time 111765433 ps
CPU time 2.26 seconds
Started May 05 02:32:10 PM PDT 24
Finished May 05 02:32:12 PM PDT 24
Peak memory 214128 kb
Host smart-f5560923-a820-4587-902a-895923d72a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233289388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.233289388
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.1069235085
Short name T788
Test name
Test status
Simulation time 1077426151 ps
CPU time 32.63 seconds
Started May 05 02:32:08 PM PDT 24
Finished May 05 02:32:41 PM PDT 24
Peak memory 214256 kb
Host smart-813b57c0-2d7b-4b52-994d-4cdd31f05aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069235085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.1069235085
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.3984599930
Short name T343
Test name
Test status
Simulation time 224690918 ps
CPU time 4.91 seconds
Started May 05 02:32:08 PM PDT 24
Finished May 05 02:32:13 PM PDT 24
Peak memory 214088 kb
Host smart-d29a15a6-20df-4253-bfab-e2e79ec4d4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984599930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.3984599930
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.3144979240
Short name T578
Test name
Test status
Simulation time 124943644 ps
CPU time 2.31 seconds
Started May 05 02:32:09 PM PDT 24
Finished May 05 02:32:12 PM PDT 24
Peak memory 219732 kb
Host smart-d7d54a0b-c166-47ce-8c66-f5ac456e4f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144979240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.3144979240
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.3449223417
Short name T109
Test name
Test status
Simulation time 44969007 ps
CPU time 2.98 seconds
Started May 05 02:32:08 PM PDT 24
Finished May 05 02:32:12 PM PDT 24
Peak memory 208524 kb
Host smart-6550e42d-fe9e-434a-9c07-860ecbeae34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449223417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.3449223417
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.3623177342
Short name T548
Test name
Test status
Simulation time 60450024 ps
CPU time 2.31 seconds
Started May 05 02:32:02 PM PDT 24
Finished May 05 02:32:05 PM PDT 24
Peak memory 206684 kb
Host smart-78fd2ca3-fd35-4ca3-a883-dbd32c4445ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623177342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.3623177342
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.706099532
Short name T789
Test name
Test status
Simulation time 348095500 ps
CPU time 2.38 seconds
Started May 05 02:32:02 PM PDT 24
Finished May 05 02:32:05 PM PDT 24
Peak memory 206580 kb
Host smart-61751848-6e92-404f-86c1-da1de2b9afeb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706099532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.706099532
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.2078394317
Short name T718
Test name
Test status
Simulation time 57574898 ps
CPU time 2.82 seconds
Started May 05 02:32:05 PM PDT 24
Finished May 05 02:32:09 PM PDT 24
Peak memory 207792 kb
Host smart-691d2238-566c-448d-9e35-f4bc8c2a6a73
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078394317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.2078394317
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.1069088246
Short name T214
Test name
Test status
Simulation time 144250746 ps
CPU time 5.09 seconds
Started May 05 02:32:03 PM PDT 24
Finished May 05 02:32:09 PM PDT 24
Peak memory 208400 kb
Host smart-eec0d389-3745-4cc2-a048-190472fd4c8f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069088246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.1069088246
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.3187259625
Short name T298
Test name
Test status
Simulation time 39106460 ps
CPU time 1.92 seconds
Started May 05 02:32:08 PM PDT 24
Finished May 05 02:32:11 PM PDT 24
Peak memory 208576 kb
Host smart-5669904f-c725-4603-b0cc-0ed60d3f3209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187259625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.3187259625
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.3136592435
Short name T105
Test name
Test status
Simulation time 61332557 ps
CPU time 2.27 seconds
Started May 05 02:32:01 PM PDT 24
Finished May 05 02:32:04 PM PDT 24
Peak memory 208516 kb
Host smart-ada7ad90-e7c4-407a-a427-91b26a594785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136592435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.3136592435
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.3792471470
Short name T607
Test name
Test status
Simulation time 733753828 ps
CPU time 7.5 seconds
Started May 05 02:32:14 PM PDT 24
Finished May 05 02:32:21 PM PDT 24
Peak memory 209176 kb
Host smart-cf375766-4362-4540-b615-9a3a4efd168a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792471470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.3792471470
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.336146068
Short name T312
Test name
Test status
Simulation time 216073872 ps
CPU time 10.42 seconds
Started May 05 02:32:12 PM PDT 24
Finished May 05 02:32:23 PM PDT 24
Peak memory 222500 kb
Host smart-44226733-3158-44c1-b140-48f186098f95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336146068 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.336146068
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.3812919730
Short name T560
Test name
Test status
Simulation time 314962107 ps
CPU time 4.18 seconds
Started May 05 02:32:08 PM PDT 24
Finished May 05 02:32:13 PM PDT 24
Peak memory 216448 kb
Host smart-51137f06-5c2d-4ab0-af76-4e82d4eb022c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812919730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.3812919730
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.3870321134
Short name T393
Test name
Test status
Simulation time 261374249 ps
CPU time 2.01 seconds
Started May 05 02:32:14 PM PDT 24
Finished May 05 02:32:16 PM PDT 24
Peak memory 209848 kb
Host smart-3e6cae4b-7817-4b18-bc3e-dc9cba3d1ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870321134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.3870321134
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.973766156
Short name T100
Test name
Test status
Simulation time 13269019 ps
CPU time 0.9 seconds
Started May 05 02:32:17 PM PDT 24
Finished May 05 02:32:19 PM PDT 24
Peak memory 206068 kb
Host smart-502dcf1c-c03d-4e5b-a084-d161df69e41d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973766156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.973766156
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.405277882
Short name T22
Test name
Test status
Simulation time 233754783 ps
CPU time 2.8 seconds
Started May 05 02:32:18 PM PDT 24
Finished May 05 02:32:21 PM PDT 24
Peak memory 209828 kb
Host smart-06887a41-07ea-404c-aea6-88c97d1b31ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405277882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.405277882
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.1367041460
Short name T731
Test name
Test status
Simulation time 5980111665 ps
CPU time 38.13 seconds
Started May 05 02:32:13 PM PDT 24
Finished May 05 02:32:52 PM PDT 24
Peak memory 218976 kb
Host smart-72db09f5-54aa-4808-8fe6-f7a8859d26b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367041460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.1367041460
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.3282249528
Short name T383
Test name
Test status
Simulation time 85923945 ps
CPU time 3.94 seconds
Started May 05 02:32:18 PM PDT 24
Finished May 05 02:32:22 PM PDT 24
Peak memory 214188 kb
Host smart-201808c2-582e-4ceb-9417-76fc9d7a786d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282249528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.3282249528
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.244327873
Short name T185
Test name
Test status
Simulation time 914824584 ps
CPU time 3.78 seconds
Started May 05 02:32:14 PM PDT 24
Finished May 05 02:32:18 PM PDT 24
Peak memory 222404 kb
Host smart-3850f972-3362-48ad-8498-838031083ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244327873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.244327873
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.4076929968
Short name T549
Test name
Test status
Simulation time 326341187 ps
CPU time 4.55 seconds
Started May 05 02:32:12 PM PDT 24
Finished May 05 02:32:17 PM PDT 24
Peak memory 214340 kb
Host smart-fe1cc5fa-2e37-4542-b57f-23c67fbcb077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076929968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.4076929968
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.3950824488
Short name T671
Test name
Test status
Simulation time 476075068 ps
CPU time 2.96 seconds
Started May 05 02:32:12 PM PDT 24
Finished May 05 02:32:16 PM PDT 24
Peak memory 208588 kb
Host smart-a22fe8c0-6416-4ec2-9e22-985552574446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950824488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.3950824488
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.1740168047
Short name T556
Test name
Test status
Simulation time 374578731 ps
CPU time 4.21 seconds
Started May 05 02:32:16 PM PDT 24
Finished May 05 02:32:21 PM PDT 24
Peak memory 208748 kb
Host smart-66ee8e05-0d42-46e1-baba-f930e2b1c454
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740168047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.1740168047
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.2367851825
Short name T668
Test name
Test status
Simulation time 24916310 ps
CPU time 1.86 seconds
Started May 05 02:32:14 PM PDT 24
Finished May 05 02:32:16 PM PDT 24
Peak memory 206716 kb
Host smart-a81d2f9e-9a04-4dcb-b8e2-25e06a4de97c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367851825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.2367851825
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.4180171146
Short name T653
Test name
Test status
Simulation time 214704278 ps
CPU time 3.29 seconds
Started May 05 02:32:14 PM PDT 24
Finished May 05 02:32:18 PM PDT 24
Peak memory 206828 kb
Host smart-90eef364-f001-402d-b5e5-ae05a2f8dad7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180171146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.4180171146
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.1509516957
Short name T632
Test name
Test status
Simulation time 97827456 ps
CPU time 2.01 seconds
Started May 05 02:32:18 PM PDT 24
Finished May 05 02:32:21 PM PDT 24
Peak memory 207888 kb
Host smart-2cd7ded7-7aa6-4d84-9607-4b2646481574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509516957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.1509516957
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.3345352346
Short name T757
Test name
Test status
Simulation time 485423084 ps
CPU time 3.1 seconds
Started May 05 02:32:15 PM PDT 24
Finished May 05 02:32:19 PM PDT 24
Peak memory 206840 kb
Host smart-9d7af8a7-ec35-4a9c-9d60-dcfdd7a3509d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345352346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.3345352346
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.4134400119
Short name T448
Test name
Test status
Simulation time 2375864345 ps
CPU time 14.32 seconds
Started May 05 02:32:17 PM PDT 24
Finished May 05 02:32:31 PM PDT 24
Peak memory 210144 kb
Host smart-997342c6-0186-4c28-9843-50a3d776719f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134400119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.4134400119
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.1381711445
Short name T389
Test name
Test status
Simulation time 96008617 ps
CPU time 1.5 seconds
Started May 05 02:32:18 PM PDT 24
Finished May 05 02:32:20 PM PDT 24
Peak memory 210008 kb
Host smart-06f12280-4bbb-446a-ac8a-6a59749df5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381711445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.1381711445
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.2601618365
Short name T792
Test name
Test status
Simulation time 176400238 ps
CPU time 0.87 seconds
Started May 05 02:32:30 PM PDT 24
Finished May 05 02:32:31 PM PDT 24
Peak memory 206096 kb
Host smart-7e4e385d-b265-4998-aa52-b915b3fb71d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601618365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.2601618365
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.3281788248
Short name T394
Test name
Test status
Simulation time 302313474 ps
CPU time 2.57 seconds
Started May 05 02:32:27 PM PDT 24
Finished May 05 02:32:30 PM PDT 24
Peak memory 210076 kb
Host smart-17983fb2-47cf-426f-9d7b-14c41614fa29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281788248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.3281788248
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.2585744896
Short name T571
Test name
Test status
Simulation time 120585961 ps
CPU time 1.84 seconds
Started May 05 02:32:26 PM PDT 24
Finished May 05 02:32:29 PM PDT 24
Peak memory 209312 kb
Host smart-04536fae-8796-4823-888d-c23665a4071b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585744896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.2585744896
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.57978956
Short name T365
Test name
Test status
Simulation time 220013126 ps
CPU time 3.01 seconds
Started May 05 02:32:27 PM PDT 24
Finished May 05 02:32:30 PM PDT 24
Peak memory 214192 kb
Host smart-c8b68ceb-4a07-418f-b3c1-151655d68a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57978956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.57978956
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.4127987214
Short name T813
Test name
Test status
Simulation time 121965883 ps
CPU time 2.18 seconds
Started May 05 02:32:28 PM PDT 24
Finished May 05 02:32:31 PM PDT 24
Peak memory 219852 kb
Host smart-966ffcf5-26e3-4923-984c-b4efc9250753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127987214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.4127987214
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.694413589
Short name T733
Test name
Test status
Simulation time 4612202640 ps
CPU time 47.23 seconds
Started May 05 02:32:22 PM PDT 24
Finished May 05 02:33:10 PM PDT 24
Peak memory 220332 kb
Host smart-4d113c9a-7b75-4213-bd56-b5c515ed37c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694413589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.694413589
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.3127268598
Short name T321
Test name
Test status
Simulation time 79638056 ps
CPU time 2.68 seconds
Started May 05 02:32:19 PM PDT 24
Finished May 05 02:32:22 PM PDT 24
Peak memory 206732 kb
Host smart-8a50f597-32f0-4289-a5b8-f3ca5eec8317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127268598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.3127268598
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.853534112
Short name T476
Test name
Test status
Simulation time 22821703 ps
CPU time 2.02 seconds
Started May 05 02:32:22 PM PDT 24
Finished May 05 02:32:24 PM PDT 24
Peak memory 208376 kb
Host smart-031cd7b9-cbe2-4f97-8f19-9151f39a38b6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853534112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.853534112
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.3380700973
Short name T563
Test name
Test status
Simulation time 214296576 ps
CPU time 2.92 seconds
Started May 05 02:32:17 PM PDT 24
Finished May 05 02:32:20 PM PDT 24
Peak memory 208788 kb
Host smart-64673c1d-8551-4fb7-a0af-6352c8a2135a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380700973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.3380700973
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.86924262
Short name T899
Test name
Test status
Simulation time 875123149 ps
CPU time 6.86 seconds
Started May 05 02:32:23 PM PDT 24
Finished May 05 02:32:30 PM PDT 24
Peak memory 208352 kb
Host smart-74732ead-2c45-4b24-8778-513b1d83fe24
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86924262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.86924262
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.289808186
Short name T579
Test name
Test status
Simulation time 285016515 ps
CPU time 3.28 seconds
Started May 05 02:32:27 PM PDT 24
Finished May 05 02:32:31 PM PDT 24
Peak memory 209304 kb
Host smart-2f5e9eeb-0782-4dad-ad18-19358ea43d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289808186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.289808186
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.2966597488
Short name T201
Test name
Test status
Simulation time 4440942481 ps
CPU time 42.62 seconds
Started May 05 02:32:18 PM PDT 24
Finished May 05 02:33:01 PM PDT 24
Peak memory 208540 kb
Host smart-3b002fdf-15db-4c26-858f-ba8f75390201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966597488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.2966597488
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.1104180886
Short name T189
Test name
Test status
Simulation time 695561072 ps
CPU time 23.05 seconds
Started May 05 02:32:27 PM PDT 24
Finished May 05 02:32:50 PM PDT 24
Peak memory 222424 kb
Host smart-30275f70-bc73-4cdb-8162-6cbe11bc03f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104180886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.1104180886
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.1284826427
Short name T382
Test name
Test status
Simulation time 2614272082 ps
CPU time 18.08 seconds
Started May 05 02:32:27 PM PDT 24
Finished May 05 02:32:46 PM PDT 24
Peak memory 220824 kb
Host smart-58a46364-38a2-4dce-b430-b6871bc5b78a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284826427 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.1284826427
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.204023042
Short name T659
Test name
Test status
Simulation time 494929309 ps
CPU time 4.09 seconds
Started May 05 02:32:26 PM PDT 24
Finished May 05 02:32:30 PM PDT 24
Peak memory 209640 kb
Host smart-2d8e188e-290d-4155-819a-cfed05cdac54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204023042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.204023042
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.1032094750
Short name T812
Test name
Test status
Simulation time 99621482 ps
CPU time 1.74 seconds
Started May 05 02:32:28 PM PDT 24
Finished May 05 02:32:30 PM PDT 24
Peak memory 209708 kb
Host smart-f59db93e-04fd-4052-a626-3b1e383d677c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032094750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.1032094750
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.1254697000
Short name T900
Test name
Test status
Simulation time 15796990 ps
CPU time 0.91 seconds
Started May 05 02:32:36 PM PDT 24
Finished May 05 02:32:37 PM PDT 24
Peak memory 205992 kb
Host smart-b235bb44-7fa7-4487-8eff-4516553b916d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254697000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.1254697000
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.1128660213
Short name T33
Test name
Test status
Simulation time 201407406 ps
CPU time 2.3 seconds
Started May 05 02:32:37 PM PDT 24
Finished May 05 02:32:39 PM PDT 24
Peak memory 208760 kb
Host smart-2836c1a9-b0da-49ce-aca8-aa9536f2f074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128660213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.1128660213
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.737395820
Short name T569
Test name
Test status
Simulation time 93658918 ps
CPU time 2.79 seconds
Started May 05 02:32:31 PM PDT 24
Finished May 05 02:32:34 PM PDT 24
Peak memory 208584 kb
Host smart-c287c3ae-c0f9-4066-8747-00193283efc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737395820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.737395820
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.3202275721
Short name T305
Test name
Test status
Simulation time 26807917 ps
CPU time 1.69 seconds
Started May 05 02:32:30 PM PDT 24
Finished May 05 02:32:32 PM PDT 24
Peak memory 214196 kb
Host smart-4b04f08e-3cde-4fee-8fe5-b868509a9350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202275721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.3202275721
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.4284728921
Short name T362
Test name
Test status
Simulation time 49364339 ps
CPU time 2.21 seconds
Started May 05 02:32:35 PM PDT 24
Finished May 05 02:32:37 PM PDT 24
Peak memory 214164 kb
Host smart-5aa6d7a8-0e2e-4e27-a239-ed4b373d6580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284728921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.4284728921
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_random.2505509486
Short name T337
Test name
Test status
Simulation time 96264606 ps
CPU time 3.53 seconds
Started May 05 02:32:32 PM PDT 24
Finished May 05 02:32:36 PM PDT 24
Peak memory 214196 kb
Host smart-63899430-05ff-425d-a8f6-a5ff1c37ba6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505509486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.2505509486
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.751596376
Short name T798
Test name
Test status
Simulation time 38676227 ps
CPU time 2.19 seconds
Started May 05 02:32:26 PM PDT 24
Finished May 05 02:32:29 PM PDT 24
Peak memory 206736 kb
Host smart-8126652e-1cfa-45b1-b422-9b169820a740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751596376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.751596376
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.1229830344
Short name T630
Test name
Test status
Simulation time 23807835 ps
CPU time 2.03 seconds
Started May 05 02:32:34 PM PDT 24
Finished May 05 02:32:36 PM PDT 24
Peak memory 206968 kb
Host smart-16cb0fb5-ce4e-410f-84a5-bd74cee39fb6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229830344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.1229830344
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.4183873550
Short name T902
Test name
Test status
Simulation time 75976711 ps
CPU time 3.55 seconds
Started May 05 02:32:27 PM PDT 24
Finished May 05 02:32:31 PM PDT 24
Peak memory 208544 kb
Host smart-5f5e68bb-8533-4cb8-abdd-b0fc8ad72337
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183873550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.4183873550
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.1219771702
Short name T803
Test name
Test status
Simulation time 210862105 ps
CPU time 2.89 seconds
Started May 05 02:32:32 PM PDT 24
Finished May 05 02:32:35 PM PDT 24
Peak memory 206616 kb
Host smart-f7f16ca9-ffb8-45dd-8ac7-1d5f04142646
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219771702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.1219771702
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.2909242522
Short name T108
Test name
Test status
Simulation time 208548782 ps
CPU time 3.37 seconds
Started May 05 02:32:38 PM PDT 24
Finished May 05 02:32:42 PM PDT 24
Peak memory 215608 kb
Host smart-57dd0862-53a1-438d-95be-b96438f44043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909242522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.2909242522
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.571300695
Short name T645
Test name
Test status
Simulation time 2235980008 ps
CPU time 4.37 seconds
Started May 05 02:32:29 PM PDT 24
Finished May 05 02:32:33 PM PDT 24
Peak memory 206748 kb
Host smart-3a16535c-42e7-4550-8877-851db5833364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571300695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.571300695
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.2738137450
Short name T646
Test name
Test status
Simulation time 401120179 ps
CPU time 10.9 seconds
Started May 05 02:32:36 PM PDT 24
Finished May 05 02:32:47 PM PDT 24
Peak memory 215448 kb
Host smart-974c2368-dca2-4134-ba3d-e7d6d27ca478
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738137450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.2738137450
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.1829591581
Short name T336
Test name
Test status
Simulation time 210844983 ps
CPU time 5.77 seconds
Started May 05 02:32:31 PM PDT 24
Finished May 05 02:32:37 PM PDT 24
Peak memory 208040 kb
Host smart-593c64c6-93a4-4f8f-8579-26cd2c6dfd70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829591581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.1829591581
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.1087548030
Short name T531
Test name
Test status
Simulation time 248058436 ps
CPU time 2.8 seconds
Started May 05 02:32:37 PM PDT 24
Finished May 05 02:32:40 PM PDT 24
Peak memory 209952 kb
Host smart-89da711c-5bf3-4d13-a5ee-7317e3bdf044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087548030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.1087548030
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.136417464
Short name T529
Test name
Test status
Simulation time 12648984 ps
CPU time 0.72 seconds
Started May 05 02:29:55 PM PDT 24
Finished May 05 02:29:56 PM PDT 24
Peak memory 205808 kb
Host smart-fef0e8d5-d37b-4c9b-9fe9-664c7a5aea23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136417464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.136417464
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.2999052678
Short name T43
Test name
Test status
Simulation time 164234830 ps
CPU time 5.95 seconds
Started May 05 02:29:49 PM PDT 24
Finished May 05 02:29:56 PM PDT 24
Peak memory 208784 kb
Host smart-00e3eb2e-bd8f-40a4-8bce-6b79c798c981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999052678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.2999052678
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.1368743821
Short name T75
Test name
Test status
Simulation time 112862695 ps
CPU time 1.65 seconds
Started May 05 02:29:44 PM PDT 24
Finished May 05 02:29:46 PM PDT 24
Peak memory 207388 kb
Host smart-b059728a-97fa-4b99-afcd-271a597d473c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368743821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.1368743821
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.1236739954
Short name T761
Test name
Test status
Simulation time 71416236 ps
CPU time 3.03 seconds
Started May 05 02:29:52 PM PDT 24
Finished May 05 02:29:56 PM PDT 24
Peak memory 214484 kb
Host smart-1e49ac08-3f58-447f-9243-546e9526fae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236739954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.1236739954
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.3933778097
Short name T325
Test name
Test status
Simulation time 192347245 ps
CPU time 3 seconds
Started May 05 02:29:49 PM PDT 24
Finished May 05 02:29:52 PM PDT 24
Peak memory 214168 kb
Host smart-5e2172c0-91c3-469b-a66b-ce0419cf04e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933778097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.3933778097
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.225890742
Short name T649
Test name
Test status
Simulation time 446286983 ps
CPU time 3.92 seconds
Started May 05 02:29:44 PM PDT 24
Finished May 05 02:29:48 PM PDT 24
Peak memory 219728 kb
Host smart-9be1866e-d29f-4b15-8d39-80d1d9785064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225890742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.225890742
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.2314553938
Short name T278
Test name
Test status
Simulation time 1197846011 ps
CPU time 9.42 seconds
Started May 05 02:29:44 PM PDT 24
Finished May 05 02:29:54 PM PDT 24
Peak memory 210268 kb
Host smart-9685ba5a-11f1-4af3-8b6f-a5d2aa344297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314553938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.2314553938
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.816689818
Short name T13
Test name
Test status
Simulation time 799260390 ps
CPU time 9.72 seconds
Started May 05 02:29:54 PM PDT 24
Finished May 05 02:30:04 PM PDT 24
Peak memory 230828 kb
Host smart-98628005-d17a-41f8-ba71-9c71db750689
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816689818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.816689818
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.4222723643
Short name T510
Test name
Test status
Simulation time 1153247279 ps
CPU time 6.81 seconds
Started May 05 02:29:41 PM PDT 24
Finished May 05 02:29:49 PM PDT 24
Peak memory 207664 kb
Host smart-6ff01314-11d8-406a-8a3d-9b98af3b91eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222723643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.4222723643
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.2077964904
Short name T647
Test name
Test status
Simulation time 672815281 ps
CPU time 20.21 seconds
Started May 05 02:29:46 PM PDT 24
Finished May 05 02:30:06 PM PDT 24
Peak memory 208048 kb
Host smart-c8c780df-e9b4-4fca-8e09-96571048903d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077964904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.2077964904
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.1865706359
Short name T796
Test name
Test status
Simulation time 171393953 ps
CPU time 3.93 seconds
Started May 05 02:29:45 PM PDT 24
Finished May 05 02:29:50 PM PDT 24
Peak memory 208572 kb
Host smart-dba9cf91-b663-4cf7-8aa1-1f8973eed435
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865706359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.1865706359
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.557726855
Short name T740
Test name
Test status
Simulation time 4583064821 ps
CPU time 54.55 seconds
Started May 05 02:29:44 PM PDT 24
Finished May 05 02:30:39 PM PDT 24
Peak memory 208876 kb
Host smart-f078b864-9778-4805-bda2-2eace668bd0e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557726855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.557726855
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.3804969151
Short name T351
Test name
Test status
Simulation time 395925437 ps
CPU time 4.65 seconds
Started May 05 02:29:52 PM PDT 24
Finished May 05 02:29:58 PM PDT 24
Peak memory 218096 kb
Host smart-8d98f8e9-7c45-409d-883b-bf6b6d6be5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804969151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.3804969151
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.101006652
Short name T608
Test name
Test status
Simulation time 34031047 ps
CPU time 2.34 seconds
Started May 05 02:29:41 PM PDT 24
Finished May 05 02:29:43 PM PDT 24
Peak memory 208104 kb
Host smart-466f3cc5-14bd-4f4e-9e63-713489962e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101006652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.101006652
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.4144544938
Short name T245
Test name
Test status
Simulation time 3363483584 ps
CPU time 47.75 seconds
Started May 05 02:29:53 PM PDT 24
Finished May 05 02:30:42 PM PDT 24
Peak memory 216968 kb
Host smart-1bdf5079-a9d3-40a0-8993-7bdd48fbec06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144544938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.4144544938
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.2110029996
Short name T764
Test name
Test status
Simulation time 230665742 ps
CPU time 11.01 seconds
Started May 05 02:29:53 PM PDT 24
Finished May 05 02:30:05 PM PDT 24
Peak memory 219660 kb
Host smart-828a59c2-b919-4b69-adb7-97d0049464ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110029996 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.2110029996
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.3363771828
Short name T319
Test name
Test status
Simulation time 256534492 ps
CPU time 3.1 seconds
Started May 05 02:29:49 PM PDT 24
Finished May 05 02:29:52 PM PDT 24
Peak memory 209460 kb
Host smart-3bd19486-f60e-435f-a5ea-25d68230d8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363771828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.3363771828
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.3648353931
Short name T65
Test name
Test status
Simulation time 223185950 ps
CPU time 2.74 seconds
Started May 05 02:29:50 PM PDT 24
Finished May 05 02:29:53 PM PDT 24
Peak memory 210424 kb
Host smart-1affa37d-af49-4a73-b669-4b10d9affc77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648353931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.3648353931
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.2627944280
Short name T505
Test name
Test status
Simulation time 14961006 ps
CPU time 0.94 seconds
Started May 05 02:32:47 PM PDT 24
Finished May 05 02:32:48 PM PDT 24
Peak memory 206008 kb
Host smart-5a96ea87-1912-409b-9319-0827c7a4717c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627944280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.2627944280
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.3449168461
Short name T416
Test name
Test status
Simulation time 52898083 ps
CPU time 3.81 seconds
Started May 05 02:32:42 PM PDT 24
Finished May 05 02:32:46 PM PDT 24
Peak memory 214844 kb
Host smart-c1064c66-efce-4587-a507-5e99383ec0b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3449168461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.3449168461
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.3354793685
Short name T35
Test name
Test status
Simulation time 457960555 ps
CPU time 3.82 seconds
Started May 05 02:32:49 PM PDT 24
Finished May 05 02:32:54 PM PDT 24
Peak memory 222664 kb
Host smart-4bf03464-ab02-4a8e-ae5b-b0dca3296c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354793685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.3354793685
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.326570547
Short name T80
Test name
Test status
Simulation time 202007685 ps
CPU time 2.48 seconds
Started May 05 02:32:39 PM PDT 24
Finished May 05 02:32:42 PM PDT 24
Peak memory 208108 kb
Host smart-23be9715-79d7-45d1-b41b-74bc846b5a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326570547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.326570547
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.94891332
Short name T760
Test name
Test status
Simulation time 250248197 ps
CPU time 2.25 seconds
Started May 05 02:32:39 PM PDT 24
Finished May 05 02:32:42 PM PDT 24
Peak memory 214276 kb
Host smart-968063be-0094-4dbc-a4d2-3dacdb06130e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94891332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.94891332
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.164382248
Short name T297
Test name
Test status
Simulation time 34614140 ps
CPU time 2.19 seconds
Started May 05 02:32:39 PM PDT 24
Finished May 05 02:32:42 PM PDT 24
Peak memory 214188 kb
Host smart-7888c7c0-459d-4096-924b-ce234b4774c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164382248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.164382248
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_random.2800186441
Short name T399
Test name
Test status
Simulation time 2083994081 ps
CPU time 8.62 seconds
Started May 05 02:32:40 PM PDT 24
Finished May 05 02:32:49 PM PDT 24
Peak memory 209104 kb
Host smart-4ae9cc76-903a-4b18-87bb-c76ca27a11b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800186441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.2800186441
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.939403348
Short name T18
Test name
Test status
Simulation time 327192242 ps
CPU time 3.87 seconds
Started May 05 02:32:36 PM PDT 24
Finished May 05 02:32:40 PM PDT 24
Peak memory 208468 kb
Host smart-73c11409-c46c-46fb-ae52-af9c2620ca1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939403348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.939403348
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.1877172345
Short name T551
Test name
Test status
Simulation time 1687640692 ps
CPU time 43.51 seconds
Started May 05 02:32:36 PM PDT 24
Finished May 05 02:33:20 PM PDT 24
Peak memory 208844 kb
Host smart-29bcfea6-8051-4bf7-8db5-fbad3c1153d7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877172345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.1877172345
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.2735421836
Short name T855
Test name
Test status
Simulation time 108296467 ps
CPU time 2.8 seconds
Started May 05 02:32:36 PM PDT 24
Finished May 05 02:32:39 PM PDT 24
Peak memory 208716 kb
Host smart-a46f0af8-46c8-4538-a0ca-09123350d9fa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735421836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.2735421836
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.1044006050
Short name T354
Test name
Test status
Simulation time 1036159612 ps
CPU time 6.99 seconds
Started May 05 02:32:40 PM PDT 24
Finished May 05 02:32:48 PM PDT 24
Peak memory 207812 kb
Host smart-7a48b98e-e855-41f1-b5a3-facb2bce7d75
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044006050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.1044006050
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.1891078201
Short name T611
Test name
Test status
Simulation time 47814369 ps
CPU time 2.76 seconds
Started May 05 02:32:46 PM PDT 24
Finished May 05 02:32:50 PM PDT 24
Peak memory 209112 kb
Host smart-3d89588c-2ad0-4126-9f11-87685a16d6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891078201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.1891078201
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.3696063405
Short name T577
Test name
Test status
Simulation time 973342834 ps
CPU time 19.72 seconds
Started May 05 02:32:37 PM PDT 24
Finished May 05 02:32:57 PM PDT 24
Peak memory 208420 kb
Host smart-2b419523-ad7d-4623-8bf3-49a3c23311ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696063405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.3696063405
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.3425160833
Short name T708
Test name
Test status
Simulation time 61039351133 ps
CPU time 283.66 seconds
Started May 05 02:32:49 PM PDT 24
Finished May 05 02:37:33 PM PDT 24
Peak memory 219088 kb
Host smart-0d37311e-7715-4425-8db0-5c0f894fc430
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425160833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.3425160833
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.176499582
Short name T574
Test name
Test status
Simulation time 353968649 ps
CPU time 5.71 seconds
Started May 05 02:32:40 PM PDT 24
Finished May 05 02:32:46 PM PDT 24
Peak memory 218232 kb
Host smart-c3ce18df-d043-481a-a8f1-71df69641f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176499582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.176499582
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.3970876951
Short name T38
Test name
Test status
Simulation time 903143499 ps
CPU time 2.6 seconds
Started May 05 02:32:48 PM PDT 24
Finished May 05 02:32:51 PM PDT 24
Peak memory 209956 kb
Host smart-a93ab7cc-2fa2-4ae0-bb29-5d5ac9070c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970876951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.3970876951
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.121038222
Short name T903
Test name
Test status
Simulation time 13378968 ps
CPU time 0.8 seconds
Started May 05 02:32:56 PM PDT 24
Finished May 05 02:32:57 PM PDT 24
Peak memory 205868 kb
Host smart-b081e0b1-3b8c-4b1d-a8fd-59e6210f91a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121038222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.121038222
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.1345645388
Short name T317
Test name
Test status
Simulation time 280643953 ps
CPU time 4.72 seconds
Started May 05 02:32:50 PM PDT 24
Finished May 05 02:32:55 PM PDT 24
Peak memory 222472 kb
Host smart-3d7e3181-3d27-4f02-8e65-dfab62e680f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1345645388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.1345645388
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.2786160145
Short name T73
Test name
Test status
Simulation time 360034799 ps
CPU time 2.66 seconds
Started May 05 02:32:49 PM PDT 24
Finished May 05 02:32:53 PM PDT 24
Peak memory 221036 kb
Host smart-de5132ec-2bbd-4e0d-82c1-f5be34eb17df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786160145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.2786160145
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.2418740015
Short name T487
Test name
Test status
Simulation time 32217498 ps
CPU time 2.17 seconds
Started May 05 02:32:49 PM PDT 24
Finished May 05 02:32:51 PM PDT 24
Peak memory 207104 kb
Host smart-16c75a55-110d-4224-91d0-12a67e421d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418740015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.2418740015
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.404629157
Short name T21
Test name
Test status
Simulation time 6647700441 ps
CPU time 39.29 seconds
Started May 05 02:32:50 PM PDT 24
Finished May 05 02:33:29 PM PDT 24
Peak memory 209488 kb
Host smart-87225ef3-0477-48e3-998b-943d40b29a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404629157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.404629157
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.3048868382
Short name T292
Test name
Test status
Simulation time 694416511 ps
CPU time 1.88 seconds
Started May 05 02:32:49 PM PDT 24
Finished May 05 02:32:52 PM PDT 24
Peak memory 214160 kb
Host smart-465b9126-06a8-43c1-b7a9-180d21db2757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048868382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.3048868382
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_random.1247312772
Short name T633
Test name
Test status
Simulation time 1618445078 ps
CPU time 43.31 seconds
Started May 05 02:32:43 PM PDT 24
Finished May 05 02:33:26 PM PDT 24
Peak memory 214264 kb
Host smart-3f196973-f81e-4352-a4ef-d8404b69a94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247312772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.1247312772
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.56223513
Short name T501
Test name
Test status
Simulation time 94267852 ps
CPU time 2.1 seconds
Started May 05 02:32:46 PM PDT 24
Finished May 05 02:32:49 PM PDT 24
Peak memory 207444 kb
Host smart-57b5590e-1552-4250-8355-456daa5e8c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56223513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.56223513
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.188019488
Short name T466
Test name
Test status
Simulation time 250579091 ps
CPU time 2.75 seconds
Started May 05 02:32:47 PM PDT 24
Finished May 05 02:32:51 PM PDT 24
Peak memory 206668 kb
Host smart-f1b57a99-68f4-4d83-834b-7d605bb2fed7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188019488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.188019488
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.2880924294
Short name T619
Test name
Test status
Simulation time 294766603 ps
CPU time 3.26 seconds
Started May 05 02:32:46 PM PDT 24
Finished May 05 02:32:50 PM PDT 24
Peak memory 208856 kb
Host smart-3a808bcb-9c40-4ee9-a548-fb81f7245005
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880924294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.2880924294
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.3190300713
Short name T687
Test name
Test status
Simulation time 418726237 ps
CPU time 2 seconds
Started May 05 02:32:44 PM PDT 24
Finished May 05 02:32:47 PM PDT 24
Peak memory 207204 kb
Host smart-9fbc0676-2995-494e-b4dc-06c12f67ff76
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190300713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.3190300713
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.1565051083
Short name T145
Test name
Test status
Simulation time 159085995 ps
CPU time 3.12 seconds
Started May 05 02:32:51 PM PDT 24
Finished May 05 02:32:54 PM PDT 24
Peak memory 208448 kb
Host smart-1a0f8ccf-5e65-4275-94ae-1843f282614f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565051083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.1565051083
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.2719229341
Short name T612
Test name
Test status
Simulation time 1008091083 ps
CPU time 3.06 seconds
Started May 05 02:32:44 PM PDT 24
Finished May 05 02:32:48 PM PDT 24
Peak memory 208556 kb
Host smart-2b8020e0-73d0-413c-b89b-c88147a30752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719229341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.2719229341
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.3341662704
Short name T586
Test name
Test status
Simulation time 259245220 ps
CPU time 9.32 seconds
Started May 05 02:32:53 PM PDT 24
Finished May 05 02:33:03 PM PDT 24
Peak memory 217708 kb
Host smart-f3b554cf-181a-4d2c-9ac0-fda0f2e8c5ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341662704 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.3341662704
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.3977041791
Short name T888
Test name
Test status
Simulation time 1137252509 ps
CPU time 41.35 seconds
Started May 05 02:32:50 PM PDT 24
Finished May 05 02:33:32 PM PDT 24
Peak memory 214288 kb
Host smart-454a6717-373b-4c1e-8b38-6cda4d0a78a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977041791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.3977041791
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.185593182
Short name T537
Test name
Test status
Simulation time 94402664 ps
CPU time 3.16 seconds
Started May 05 02:32:49 PM PDT 24
Finished May 05 02:32:53 PM PDT 24
Peak memory 209748 kb
Host smart-f5f4d73a-68a5-4286-a970-e7b044d6d8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185593182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.185593182
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.3274183098
Short name T693
Test name
Test status
Simulation time 59006562 ps
CPU time 0.72 seconds
Started May 05 02:33:02 PM PDT 24
Finished May 05 02:33:03 PM PDT 24
Peak memory 205884 kb
Host smart-94e54ed6-8312-44df-bc7e-19c8835c769d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274183098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.3274183098
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.2011704581
Short name T854
Test name
Test status
Simulation time 62752611 ps
CPU time 2.63 seconds
Started May 05 02:33:00 PM PDT 24
Finished May 05 02:33:03 PM PDT 24
Peak memory 209720 kb
Host smart-f227eb94-eeaf-429d-b29c-fc3fcc1a02d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011704581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.2011704581
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.2043791792
Short name T290
Test name
Test status
Simulation time 1006651254 ps
CPU time 17.59 seconds
Started May 05 02:32:53 PM PDT 24
Finished May 05 02:33:11 PM PDT 24
Peak memory 207964 kb
Host smart-5fc18c87-47a1-46ca-8b63-87aa47e38fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043791792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.2043791792
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.977316718
Short name T274
Test name
Test status
Simulation time 101722684 ps
CPU time 2.12 seconds
Started May 05 02:32:58 PM PDT 24
Finished May 05 02:33:01 PM PDT 24
Peak memory 214320 kb
Host smart-23eca154-aa5e-4f6d-8bed-ca75bbd00a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977316718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.977316718
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.187313062
Short name T302
Test name
Test status
Simulation time 188211305 ps
CPU time 4.31 seconds
Started May 05 02:32:55 PM PDT 24
Finished May 05 02:32:59 PM PDT 24
Peak memory 214180 kb
Host smart-ade1f5e1-f2df-40ff-996c-d2bd499a0b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187313062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.187313062
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.3223459710
Short name T838
Test name
Test status
Simulation time 47493499 ps
CPU time 2.7 seconds
Started May 05 02:32:54 PM PDT 24
Finished May 05 02:32:57 PM PDT 24
Peak memory 208504 kb
Host smart-a54507ca-0c7f-4922-a2b5-9712d2660c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223459710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.3223459710
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.579407722
Short name T697
Test name
Test status
Simulation time 382411495 ps
CPU time 2.36 seconds
Started May 05 02:32:55 PM PDT 24
Finished May 05 02:32:58 PM PDT 24
Peak memory 208488 kb
Host smart-07139165-60d7-40a8-853d-c31d74722b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579407722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.579407722
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.1956205162
Short name T777
Test name
Test status
Simulation time 145474406 ps
CPU time 3.71 seconds
Started May 05 02:32:55 PM PDT 24
Finished May 05 02:33:00 PM PDT 24
Peak memory 208192 kb
Host smart-0716ac45-f5b2-48a6-9648-3a17ee3cc6ed
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956205162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.1956205162
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.8485149
Short name T617
Test name
Test status
Simulation time 734829667 ps
CPU time 4.29 seconds
Started May 05 02:32:57 PM PDT 24
Finished May 05 02:33:02 PM PDT 24
Peak memory 208764 kb
Host smart-b32d2a5c-3e56-48f1-84aa-fcb64ed7bafb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8485149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.8485149
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.2990235139
Short name T125
Test name
Test status
Simulation time 1875457132 ps
CPU time 59.53 seconds
Started May 05 02:32:55 PM PDT 24
Finished May 05 02:33:55 PM PDT 24
Peak memory 208956 kb
Host smart-2e624fc0-1c03-45f4-a181-de501bd1be8f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990235139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.2990235139
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.2959160565
Short name T676
Test name
Test status
Simulation time 104828301 ps
CPU time 1.93 seconds
Started May 05 02:32:58 PM PDT 24
Finished May 05 02:33:00 PM PDT 24
Peak memory 207416 kb
Host smart-f4f94f16-6a2a-4e0b-bffa-47ef89de7057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959160565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.2959160565
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.3736751189
Short name T442
Test name
Test status
Simulation time 120883574 ps
CPU time 4.33 seconds
Started May 05 02:32:54 PM PDT 24
Finished May 05 02:32:58 PM PDT 24
Peak memory 207992 kb
Host smart-239edebc-5f68-46ba-92c1-bb2c7d93454a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736751189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.3736751189
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.2674424709
Short name T342
Test name
Test status
Simulation time 254098018 ps
CPU time 3.07 seconds
Started May 05 02:33:01 PM PDT 24
Finished May 05 02:33:05 PM PDT 24
Peak memory 209216 kb
Host smart-589bbdd7-0151-4a47-b316-5ed950f36273
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674424709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.2674424709
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.50265886
Short name T179
Test name
Test status
Simulation time 1119529648 ps
CPU time 11.74 seconds
Started May 05 02:33:11 PM PDT 24
Finished May 05 02:33:23 PM PDT 24
Peak memory 222532 kb
Host smart-a03f3b4d-62de-4086-a6f3-dbe23e3ce99c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50265886 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.50265886
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.535324262
Short name T378
Test name
Test status
Simulation time 4156856342 ps
CPU time 29.36 seconds
Started May 05 02:32:55 PM PDT 24
Finished May 05 02:33:25 PM PDT 24
Peak memory 210472 kb
Host smart-1f3404dc-b1d8-4c17-bbc4-c4a5e8946551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535324262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.535324262
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.159350353
Short name T561
Test name
Test status
Simulation time 2059359348 ps
CPU time 16.08 seconds
Started May 05 02:33:07 PM PDT 24
Finished May 05 02:33:23 PM PDT 24
Peak memory 210212 kb
Host smart-8c27e758-5cc0-48d1-be8f-026580c395f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159350353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.159350353
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.3507276618
Short name T456
Test name
Test status
Simulation time 38377033 ps
CPU time 0.79 seconds
Started May 05 02:33:08 PM PDT 24
Finished May 05 02:33:09 PM PDT 24
Peak memory 205888 kb
Host smart-00b4653f-b1be-4f13-b5dd-f8dda5d8abc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507276618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.3507276618
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.2242894263
Short name T271
Test name
Test status
Simulation time 197068962 ps
CPU time 2.43 seconds
Started May 05 02:33:06 PM PDT 24
Finished May 05 02:33:09 PM PDT 24
Peak memory 210232 kb
Host smart-091de5c1-05ab-43e5-9593-29e620301d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242894263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.2242894263
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.296036840
Short name T254
Test name
Test status
Simulation time 801565278 ps
CPU time 5.75 seconds
Started May 05 02:33:02 PM PDT 24
Finished May 05 02:33:08 PM PDT 24
Peak memory 214440 kb
Host smart-2f969599-c421-4e65-9dcb-b088afe3c33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296036840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.296036840
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.2122982538
Short name T68
Test name
Test status
Simulation time 223680562 ps
CPU time 7.04 seconds
Started May 05 02:33:04 PM PDT 24
Finished May 05 02:33:11 PM PDT 24
Peak memory 209496 kb
Host smart-253c21c1-9d3f-4048-aad3-82f4e4b0d2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122982538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.2122982538
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.4263217543
Short name T497
Test name
Test status
Simulation time 104584636 ps
CPU time 5.04 seconds
Started May 05 02:33:11 PM PDT 24
Finished May 05 02:33:16 PM PDT 24
Peak memory 208508 kb
Host smart-9c0de29c-b6a5-4ecc-ac96-639ad2abc4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263217543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.4263217543
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.386619754
Short name T883
Test name
Test status
Simulation time 1097845671 ps
CPU time 6.35 seconds
Started May 05 02:33:04 PM PDT 24
Finished May 05 02:33:10 PM PDT 24
Peak memory 206656 kb
Host smart-0bf1334d-1afc-4815-81aa-4c02a1ad72e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386619754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.386619754
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.1008377084
Short name T778
Test name
Test status
Simulation time 270315838 ps
CPU time 8.26 seconds
Started May 05 02:33:03 PM PDT 24
Finished May 05 02:33:11 PM PDT 24
Peak memory 208648 kb
Host smart-d89a7cf9-1d60-4e61-ac0e-466b6b6b12de
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008377084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1008377084
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.3746026997
Short name T832
Test name
Test status
Simulation time 105145850 ps
CPU time 2.53 seconds
Started May 05 02:33:11 PM PDT 24
Finished May 05 02:33:14 PM PDT 24
Peak memory 206820 kb
Host smart-d15e8222-bad3-493a-9e6b-2b9dcbd7056f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746026997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.3746026997
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.372568200
Short name T672
Test name
Test status
Simulation time 1452152783 ps
CPU time 10.11 seconds
Started May 05 02:33:04 PM PDT 24
Finished May 05 02:33:14 PM PDT 24
Peak memory 207776 kb
Host smart-c1a9ea35-cedc-4cda-84ba-a246829c5029
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372568200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.372568200
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.3103132044
Short name T208
Test name
Test status
Simulation time 732514546 ps
CPU time 3.21 seconds
Started May 05 02:33:06 PM PDT 24
Finished May 05 02:33:10 PM PDT 24
Peak memory 214240 kb
Host smart-ac2a9399-e4b7-40ab-9f1c-6b3cfc955228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103132044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.3103132044
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.1548877353
Short name T398
Test name
Test status
Simulation time 1794608151 ps
CPU time 47.86 seconds
Started May 05 02:33:02 PM PDT 24
Finished May 05 02:33:50 PM PDT 24
Peak memory 208812 kb
Host smart-6d0fc6e6-24a8-415f-9075-66d7c0c2d83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548877353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.1548877353
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.2491407010
Short name T835
Test name
Test status
Simulation time 5076580687 ps
CPU time 152.4 seconds
Started May 05 02:33:08 PM PDT 24
Finished May 05 02:35:41 PM PDT 24
Peak memory 217924 kb
Host smart-f4d29bac-ad53-4f4c-b029-a53c3aa3ab6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491407010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.2491407010
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.86087491
Short name T426
Test name
Test status
Simulation time 91810363 ps
CPU time 3.38 seconds
Started May 05 02:33:11 PM PDT 24
Finished May 05 02:33:15 PM PDT 24
Peak memory 214236 kb
Host smart-8a61fd34-419c-4876-b635-df06590a0e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86087491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.86087491
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.502757576
Short name T592
Test name
Test status
Simulation time 190101630 ps
CPU time 5 seconds
Started May 05 02:33:08 PM PDT 24
Finished May 05 02:33:14 PM PDT 24
Peak memory 210476 kb
Host smart-e5f47ee5-6825-49f3-b3eb-ca6d22502849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502757576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.502757576
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.3684946558
Short name T678
Test name
Test status
Simulation time 18189521 ps
CPU time 0.79 seconds
Started May 05 02:33:18 PM PDT 24
Finished May 05 02:33:19 PM PDT 24
Peak memory 205820 kb
Host smart-e0338c84-8e53-4a0e-ae10-fcede4011427
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684946558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.3684946558
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.1766157059
Short name T229
Test name
Test status
Simulation time 154630127 ps
CPU time 2.13 seconds
Started May 05 02:33:15 PM PDT 24
Finished May 05 02:33:18 PM PDT 24
Peak memory 208752 kb
Host smart-ed000317-d2da-4c2f-8bab-b1e1227d7bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766157059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.1766157059
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.2361490321
Short name T680
Test name
Test status
Simulation time 3017934312 ps
CPU time 29.55 seconds
Started May 05 02:33:14 PM PDT 24
Finished May 05 02:33:44 PM PDT 24
Peak memory 209820 kb
Host smart-2bddfce6-b54f-403c-be19-b4351ecb73e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361490321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.2361490321
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.3262237342
Short name T239
Test name
Test status
Simulation time 219241019 ps
CPU time 4.53 seconds
Started May 05 02:33:11 PM PDT 24
Finished May 05 02:33:16 PM PDT 24
Peak memory 220044 kb
Host smart-246c5eb6-6ca4-4838-af48-cff20d96c0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262237342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.3262237342
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.3162822934
Short name T729
Test name
Test status
Simulation time 753924263 ps
CPU time 2.71 seconds
Started May 05 02:33:18 PM PDT 24
Finished May 05 02:33:21 PM PDT 24
Peak memory 214112 kb
Host smart-f0ffd247-5fc2-4694-8cc2-9aab0d39a07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162822934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.3162822934
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.556638478
Short name T216
Test name
Test status
Simulation time 2872987940 ps
CPU time 38.47 seconds
Started May 05 02:33:12 PM PDT 24
Finished May 05 02:33:50 PM PDT 24
Peak memory 217632 kb
Host smart-69646670-cca9-4140-bf79-e7e5b62f8d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556638478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.556638478
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.3771375780
Short name T701
Test name
Test status
Simulation time 2639701903 ps
CPU time 15.3 seconds
Started May 05 02:33:11 PM PDT 24
Finished May 05 02:33:27 PM PDT 24
Peak memory 208752 kb
Host smart-cc45eac7-eec6-4ef1-81cb-d74651dc20a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771375780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.3771375780
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.2812623149
Short name T353
Test name
Test status
Simulation time 304732138 ps
CPU time 8.06 seconds
Started May 05 02:33:14 PM PDT 24
Finished May 05 02:33:22 PM PDT 24
Peak memory 208404 kb
Host smart-217197a3-ffb2-47c5-bf23-d73c21289aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812623149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.2812623149
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.3327719700
Short name T452
Test name
Test status
Simulation time 242401562 ps
CPU time 3.21 seconds
Started May 05 02:33:12 PM PDT 24
Finished May 05 02:33:15 PM PDT 24
Peak memory 206564 kb
Host smart-8eedd1c7-f699-45cd-aa27-9d3cd73623fc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327719700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.3327719700
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.2335637067
Short name T748
Test name
Test status
Simulation time 65331497 ps
CPU time 2.6 seconds
Started May 05 02:33:11 PM PDT 24
Finished May 05 02:33:14 PM PDT 24
Peak memory 207392 kb
Host smart-da108d34-71c2-4995-b49a-14bb7a60575f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335637067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.2335637067
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.1988198385
Short name T690
Test name
Test status
Simulation time 3824512988 ps
CPU time 9.22 seconds
Started May 05 02:33:10 PM PDT 24
Finished May 05 02:33:20 PM PDT 24
Peak memory 208752 kb
Host smart-0d02d9ac-1c66-461f-9cef-f4e32d1e864a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988198385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.1988198385
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.3997208481
Short name T327
Test name
Test status
Simulation time 84178666 ps
CPU time 3.02 seconds
Started May 05 02:33:16 PM PDT 24
Finished May 05 02:33:20 PM PDT 24
Peak memory 209836 kb
Host smart-a98a3d6e-8941-444e-8496-fd6d84c96e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997208481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.3997208481
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.1899853686
Short name T871
Test name
Test status
Simulation time 13591170945 ps
CPU time 28.43 seconds
Started May 05 02:33:08 PM PDT 24
Finished May 05 02:33:37 PM PDT 24
Peak memory 208252 kb
Host smart-cc15a1cb-0feb-4cbc-8b97-e75dc1d13bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899853686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.1899853686
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.1626480381
Short name T122
Test name
Test status
Simulation time 2238762021 ps
CPU time 11.68 seconds
Started May 05 02:33:16 PM PDT 24
Finished May 05 02:33:28 PM PDT 24
Peak memory 222592 kb
Host smart-36b47d20-f65c-40df-8cd5-924af93e7eee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626480381 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.1626480381
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.3764293619
Short name T656
Test name
Test status
Simulation time 524508504 ps
CPU time 6.14 seconds
Started May 05 02:33:12 PM PDT 24
Finished May 05 02:33:18 PM PDT 24
Peak memory 214240 kb
Host smart-561a6c1a-7100-458d-94ef-b26563828032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764293619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.3764293619
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.2677734143
Short name T396
Test name
Test status
Simulation time 174013260 ps
CPU time 3.29 seconds
Started May 05 02:33:17 PM PDT 24
Finished May 05 02:33:20 PM PDT 24
Peak memory 209980 kb
Host smart-f957ece1-9a09-4528-948e-32419b0f14fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677734143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.2677734143
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.51869922
Short name T2
Test name
Test status
Simulation time 14678865 ps
CPU time 0.93 seconds
Started May 05 02:33:25 PM PDT 24
Finished May 05 02:33:27 PM PDT 24
Peak memory 206052 kb
Host smart-250a6aa2-f2b5-45f4-83b4-4072c37dbcaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51869922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.51869922
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.1670816501
Short name T42
Test name
Test status
Simulation time 58345073 ps
CPU time 1.94 seconds
Started May 05 02:33:22 PM PDT 24
Finished May 05 02:33:24 PM PDT 24
Peak memory 215468 kb
Host smart-ff6fd906-4e5d-4651-8b4b-9a0887e84d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670816501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.1670816501
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.1236741796
Short name T77
Test name
Test status
Simulation time 87128841 ps
CPU time 1.38 seconds
Started May 05 02:33:21 PM PDT 24
Finished May 05 02:33:23 PM PDT 24
Peak memory 207624 kb
Host smart-e2902c58-47a8-43d2-8878-6eb062fbeb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236741796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.1236741796
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.4036411925
Short name T694
Test name
Test status
Simulation time 175911418 ps
CPU time 2.05 seconds
Started May 05 02:33:21 PM PDT 24
Finished May 05 02:33:23 PM PDT 24
Peak memory 214280 kb
Host smart-2a0d16ca-4a31-4796-bfa1-5b465540d36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036411925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.4036411925
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.1491644558
Short name T251
Test name
Test status
Simulation time 71600134 ps
CPU time 2.37 seconds
Started May 05 02:33:21 PM PDT 24
Finished May 05 02:33:24 PM PDT 24
Peak memory 214248 kb
Host smart-019d37cc-a236-471e-a859-bce9a3d5a7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491644558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.1491644558
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.3538253868
Short name T63
Test name
Test status
Simulation time 830304213 ps
CPU time 4.91 seconds
Started May 05 02:33:25 PM PDT 24
Finished May 05 02:33:30 PM PDT 24
Peak memory 209956 kb
Host smart-50f6e319-7a0e-4d29-a162-7f815ea9ca42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538253868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.3538253868
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.1987970491
Short name T635
Test name
Test status
Simulation time 165372465 ps
CPU time 3.28 seconds
Started May 05 02:33:22 PM PDT 24
Finished May 05 02:33:26 PM PDT 24
Peak memory 209640 kb
Host smart-860f7d81-6343-42bf-a93e-fdd3d11902af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987970491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.1987970491
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.4258176477
Short name T715
Test name
Test status
Simulation time 2019398566 ps
CPU time 10.63 seconds
Started May 05 02:33:20 PM PDT 24
Finished May 05 02:33:31 PM PDT 24
Peak memory 208632 kb
Host smart-ad6fc2a5-5633-486f-9baa-bac71b17af14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258176477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.4258176477
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.2458189105
Short name T809
Test name
Test status
Simulation time 288275749 ps
CPU time 3.68 seconds
Started May 05 02:33:20 PM PDT 24
Finished May 05 02:33:24 PM PDT 24
Peak memory 208760 kb
Host smart-6dbff178-e7b9-4aaa-93c6-b866b403876d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458189105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.2458189105
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.3154195531
Short name T872
Test name
Test status
Simulation time 38606559 ps
CPU time 2.33 seconds
Started May 05 02:33:24 PM PDT 24
Finished May 05 02:33:27 PM PDT 24
Peak memory 206876 kb
Host smart-a12c5559-8aa0-4266-b562-62bb590dc17c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154195531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.3154195531
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.4112490786
Short name T787
Test name
Test status
Simulation time 175896377 ps
CPU time 2.56 seconds
Started May 05 02:33:25 PM PDT 24
Finished May 05 02:33:28 PM PDT 24
Peak memory 208716 kb
Host smart-5643840b-321b-48a9-bba6-7467517720ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112490786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.4112490786
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.517385072
Short name T567
Test name
Test status
Simulation time 100614000 ps
CPU time 3.47 seconds
Started May 05 02:33:21 PM PDT 24
Finished May 05 02:33:25 PM PDT 24
Peak memory 206656 kb
Host smart-774be19d-4fe5-4527-9131-34b0267b1db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517385072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.517385072
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.2190950077
Short name T282
Test name
Test status
Simulation time 180512110 ps
CPU time 10.75 seconds
Started May 05 02:33:27 PM PDT 24
Finished May 05 02:33:38 PM PDT 24
Peak memory 222500 kb
Host smart-f05d5ecd-cfcd-48e7-a668-b0ab49e1f8c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190950077 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.2190950077
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.233278892
Short name T527
Test name
Test status
Simulation time 100132303 ps
CPU time 4.98 seconds
Started May 05 02:33:22 PM PDT 24
Finished May 05 02:33:27 PM PDT 24
Peak memory 207280 kb
Host smart-78efb50e-175a-4843-907d-8e1f374b9666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233278892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.233278892
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.959436753
Short name T200
Test name
Test status
Simulation time 978343407 ps
CPU time 12.87 seconds
Started May 05 02:33:25 PM PDT 24
Finished May 05 02:33:39 PM PDT 24
Peak memory 210992 kb
Host smart-92eddabb-b93e-4569-9a6c-95b17559f0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959436753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.959436753
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.2276550396
Short name T657
Test name
Test status
Simulation time 17117835 ps
CPU time 0.81 seconds
Started May 05 02:33:34 PM PDT 24
Finished May 05 02:33:36 PM PDT 24
Peak memory 205888 kb
Host smart-1a5d50ca-e2cc-46fa-9c98-441d2149213e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276550396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.2276550396
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.669650361
Short name T376
Test name
Test status
Simulation time 147405155 ps
CPU time 3.01 seconds
Started May 05 02:33:31 PM PDT 24
Finished May 05 02:33:35 PM PDT 24
Peak memory 215188 kb
Host smart-f4df2539-a2fd-4b53-af5b-c1d50c3123ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=669650361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.669650361
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.592421167
Short name T621
Test name
Test status
Simulation time 147640134 ps
CPU time 2.13 seconds
Started May 05 02:33:30 PM PDT 24
Finished May 05 02:33:32 PM PDT 24
Peak memory 207840 kb
Host smart-22c71bed-b956-4a2d-930e-33ef54797489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592421167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.592421167
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.551594306
Short name T744
Test name
Test status
Simulation time 42869391 ps
CPU time 2.41 seconds
Started May 05 02:33:32 PM PDT 24
Finished May 05 02:33:35 PM PDT 24
Peak memory 214272 kb
Host smart-28cb9bf7-5d7d-4c7c-9013-fd3f5e805901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551594306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.551594306
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.2546586776
Short name T363
Test name
Test status
Simulation time 70152696 ps
CPU time 3.69 seconds
Started May 05 02:33:44 PM PDT 24
Finished May 05 02:33:49 PM PDT 24
Peak memory 213980 kb
Host smart-99908b44-b747-45b4-909c-3254d5cb80a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546586776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.2546586776
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.271177648
Short name T901
Test name
Test status
Simulation time 151907751 ps
CPU time 4.32 seconds
Started May 05 02:33:43 PM PDT 24
Finished May 05 02:33:48 PM PDT 24
Peak memory 210164 kb
Host smart-2dbf9cea-74d7-4063-9a4d-c12cf2e52f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271177648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.271177648
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.4176551085
Short name T262
Test name
Test status
Simulation time 94469018 ps
CPU time 4.58 seconds
Started May 05 02:33:44 PM PDT 24
Finished May 05 02:33:50 PM PDT 24
Peak memory 208404 kb
Host smart-309bba4b-2fe3-436c-a76e-f13e2760717a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176551085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.4176551085
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.2565487146
Short name T564
Test name
Test status
Simulation time 255952343 ps
CPU time 2.7 seconds
Started May 05 02:33:25 PM PDT 24
Finished May 05 02:33:28 PM PDT 24
Peak memory 206732 kb
Host smart-0f643eea-83c2-4ac1-88bc-f7bd4c17eb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565487146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.2565487146
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.1923159614
Short name T404
Test name
Test status
Simulation time 47687565 ps
CPU time 2.74 seconds
Started May 05 02:33:31 PM PDT 24
Finished May 05 02:33:34 PM PDT 24
Peak memory 208720 kb
Host smart-c843d633-59cb-4750-959d-2d13d0e7447d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923159614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.1923159614
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.2221872323
Short name T572
Test name
Test status
Simulation time 56128942 ps
CPU time 2.86 seconds
Started May 05 02:33:27 PM PDT 24
Finished May 05 02:33:30 PM PDT 24
Peak memory 206712 kb
Host smart-09d304d3-e1fe-4a85-89ba-c17f1c397295
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221872323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.2221872323
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.3060615313
Short name T397
Test name
Test status
Simulation time 49215369 ps
CPU time 2.12 seconds
Started May 05 02:33:28 PM PDT 24
Finished May 05 02:33:30 PM PDT 24
Peak memory 206528 kb
Host smart-f275996f-8857-4ef0-a3c0-4368cb330233
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060615313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.3060615313
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.1026072246
Short name T373
Test name
Test status
Simulation time 186684376 ps
CPU time 2.55 seconds
Started May 05 02:33:35 PM PDT 24
Finished May 05 02:33:38 PM PDT 24
Peak memory 218228 kb
Host smart-72046c1a-c7f9-46ce-a76d-ffa2ca77b68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026072246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.1026072246
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.2529926310
Short name T763
Test name
Test status
Simulation time 167985287 ps
CPU time 5.33 seconds
Started May 05 02:33:27 PM PDT 24
Finished May 05 02:33:33 PM PDT 24
Peak memory 206440 kb
Host smart-c68640fb-478b-4982-b29f-498d0d95ecfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529926310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.2529926310
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.3155366101
Short name T521
Test name
Test status
Simulation time 237215974 ps
CPU time 5.41 seconds
Started May 05 02:33:44 PM PDT 24
Finished May 05 02:33:51 PM PDT 24
Peak memory 208700 kb
Host smart-dbe6d1bb-549a-4baa-a2db-84167fe668f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155366101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.3155366101
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.1799090097
Short name T178
Test name
Test status
Simulation time 1360163070 ps
CPU time 13.81 seconds
Started May 05 02:33:44 PM PDT 24
Finished May 05 02:33:59 PM PDT 24
Peak memory 219620 kb
Host smart-8a85db95-3f1c-4d23-b66e-2333f64acd28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799090097 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.1799090097
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.733060807
Short name T830
Test name
Test status
Simulation time 652905672 ps
CPU time 7.36 seconds
Started May 05 02:33:44 PM PDT 24
Finished May 05 02:33:52 PM PDT 24
Peak memory 209744 kb
Host smart-a43fb7eb-8444-4d70-b670-97421ebb44e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733060807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.733060807
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.3675267239
Short name T39
Test name
Test status
Simulation time 426403336 ps
CPU time 3.01 seconds
Started May 05 02:33:44 PM PDT 24
Finished May 05 02:33:48 PM PDT 24
Peak memory 210244 kb
Host smart-3576fee2-61fc-4f4d-bd7b-68751683e9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675267239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.3675267239
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.775048839
Short name T573
Test name
Test status
Simulation time 123769947 ps
CPU time 0.82 seconds
Started May 05 02:33:44 PM PDT 24
Finished May 05 02:33:45 PM PDT 24
Peak memory 205840 kb
Host smart-76ab192e-ace1-4f29-9d12-3fa5970e4dd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775048839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.775048839
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.1827587651
Short name T429
Test name
Test status
Simulation time 1962527178 ps
CPU time 53.26 seconds
Started May 05 02:33:38 PM PDT 24
Finished May 05 02:34:31 PM PDT 24
Peak memory 216152 kb
Host smart-d8abf0e9-294f-4101-94bf-a377e2138cef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1827587651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.1827587651
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.3772417669
Short name T455
Test name
Test status
Simulation time 195658530 ps
CPU time 2.16 seconds
Started May 05 02:33:43 PM PDT 24
Finished May 05 02:33:46 PM PDT 24
Peak memory 210228 kb
Host smart-310829d8-69c7-4d86-bc6b-b0a3653854ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772417669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.3772417669
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.3409635363
Short name T683
Test name
Test status
Simulation time 55469378 ps
CPU time 2.92 seconds
Started May 05 02:33:38 PM PDT 24
Finished May 05 02:33:41 PM PDT 24
Peak memory 209632 kb
Host smart-de8f65fe-1e0a-49c5-9249-518579a0d611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409635363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.3409635363
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_random.2535644511
Short name T328
Test name
Test status
Simulation time 1745469366 ps
CPU time 41.36 seconds
Started May 05 02:33:40 PM PDT 24
Finished May 05 02:34:22 PM PDT 24
Peak memory 209628 kb
Host smart-cc79d4c3-b386-4f43-8af7-3aa8a70219ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535644511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.2535644511
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.3629022865
Short name T540
Test name
Test status
Simulation time 273919636 ps
CPU time 4.01 seconds
Started May 05 02:33:34 PM PDT 24
Finished May 05 02:33:38 PM PDT 24
Peak memory 206612 kb
Host smart-d308a983-1d70-4f76-adac-daf5010724ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629022865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.3629022865
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.3259277387
Short name T144
Test name
Test status
Simulation time 64146660 ps
CPU time 3.01 seconds
Started May 05 02:33:34 PM PDT 24
Finished May 05 02:33:38 PM PDT 24
Peak memory 207168 kb
Host smart-e84d1b60-225a-4713-b8f5-31255708ac89
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259277387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.3259277387
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.2874444675
Short name T406
Test name
Test status
Simulation time 467947064 ps
CPU time 6.65 seconds
Started May 05 02:33:35 PM PDT 24
Finished May 05 02:33:43 PM PDT 24
Peak memory 208376 kb
Host smart-e571dcf1-c79a-48b0-8d26-4e081b15f9ba
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874444675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.2874444675
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.349781
Short name T16
Test name
Test status
Simulation time 674661315 ps
CPU time 9.36 seconds
Started May 05 02:33:39 PM PDT 24
Finished May 05 02:33:48 PM PDT 24
Peak memory 207908 kb
Host smart-79e0a4ef-4733-485b-98b6-3b9bf7cdc69e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.349781
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.2971391933
Short name T775
Test name
Test status
Simulation time 113871344 ps
CPU time 2.31 seconds
Started May 05 02:33:44 PM PDT 24
Finished May 05 02:33:47 PM PDT 24
Peak memory 215344 kb
Host smart-4422abec-e87b-4c46-91c5-11c9910337f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971391933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.2971391933
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.52689491
Short name T202
Test name
Test status
Simulation time 320437254 ps
CPU time 4.61 seconds
Started May 05 02:33:44 PM PDT 24
Finished May 05 02:33:50 PM PDT 24
Peak memory 208204 kb
Host smart-3566b515-2fb4-4b5b-b4af-86c15eec66ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52689491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.52689491
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.1718149711
Short name T335
Test name
Test status
Simulation time 1236564084 ps
CPU time 30.34 seconds
Started May 05 02:33:42 PM PDT 24
Finished May 05 02:34:13 PM PDT 24
Peak memory 208924 kb
Host smart-5bea258d-8e13-4456-b548-50e03bee7616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718149711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.1718149711
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.1690696261
Short name T391
Test name
Test status
Simulation time 121645595 ps
CPU time 2.19 seconds
Started May 05 02:33:46 PM PDT 24
Finished May 05 02:33:49 PM PDT 24
Peak memory 209852 kb
Host smart-2caed6bf-c533-4e98-a826-44bb5d3d2320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690696261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.1690696261
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.2887280183
Short name T631
Test name
Test status
Simulation time 50127233 ps
CPU time 0.93 seconds
Started May 05 02:34:02 PM PDT 24
Finished May 05 02:34:04 PM PDT 24
Peak memory 205820 kb
Host smart-88f16744-84fa-43b3-aca6-2e8938fa1786
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887280183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.2887280183
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.885851504
Short name T651
Test name
Test status
Simulation time 143258031 ps
CPU time 2.32 seconds
Started May 05 02:33:48 PM PDT 24
Finished May 05 02:33:51 PM PDT 24
Peak memory 209688 kb
Host smart-b0d06ea1-4220-43e0-9c39-79e9a13a1860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885851504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.885851504
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.3544771958
Short name T276
Test name
Test status
Simulation time 224095259 ps
CPU time 3.66 seconds
Started May 05 02:33:46 PM PDT 24
Finished May 05 02:33:50 PM PDT 24
Peak memory 214544 kb
Host smart-ab918615-508a-4dd1-8ad1-d54f91ec20de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544771958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.3544771958
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.4058563450
Short name T542
Test name
Test status
Simulation time 88483030 ps
CPU time 3.73 seconds
Started May 05 02:33:47 PM PDT 24
Finished May 05 02:33:51 PM PDT 24
Peak memory 222408 kb
Host smart-cb4ee253-61bc-4c01-b1b0-6a70c4862688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058563450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.4058563450
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.3815025009
Short name T58
Test name
Test status
Simulation time 148351598 ps
CPU time 2.74 seconds
Started May 05 02:33:49 PM PDT 24
Finished May 05 02:33:52 PM PDT 24
Peak memory 209804 kb
Host smart-7254f329-c181-457f-9f83-93f6b4139e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815025009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.3815025009
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.2393844057
Short name T810
Test name
Test status
Simulation time 185068649 ps
CPU time 3.55 seconds
Started May 05 02:33:47 PM PDT 24
Finished May 05 02:33:51 PM PDT 24
Peak memory 218356 kb
Host smart-883ad723-1607-4aca-84e4-de7d3694d1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393844057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.2393844057
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.2440571030
Short name T514
Test name
Test status
Simulation time 475261315 ps
CPU time 5.05 seconds
Started May 05 02:33:43 PM PDT 24
Finished May 05 02:33:49 PM PDT 24
Peak memory 206672 kb
Host smart-a87719f0-d3a3-4f4a-b0bc-fa2c0effcfcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440571030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.2440571030
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.3218582261
Short name T644
Test name
Test status
Simulation time 65452190 ps
CPU time 3.27 seconds
Started May 05 02:33:50 PM PDT 24
Finished May 05 02:33:53 PM PDT 24
Peak memory 206772 kb
Host smart-f084f846-8bb4-4826-bba0-fff5115c42da
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218582261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.3218582261
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.3636324200
Short name T314
Test name
Test status
Simulation time 848831613 ps
CPU time 7.8 seconds
Started May 05 02:33:47 PM PDT 24
Finished May 05 02:33:56 PM PDT 24
Peak memory 208476 kb
Host smart-c8e4495f-2436-4e12-a3a5-e85d07a54c3c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636324200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.3636324200
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.2208157707
Short name T509
Test name
Test status
Simulation time 28765820 ps
CPU time 2.07 seconds
Started May 05 02:33:49 PM PDT 24
Finished May 05 02:33:51 PM PDT 24
Peak memory 206896 kb
Host smart-efd777a0-80f9-4844-82b0-379f42bbe625
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208157707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.2208157707
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.3835392387
Short name T616
Test name
Test status
Simulation time 345530516 ps
CPU time 2.78 seconds
Started May 05 02:34:02 PM PDT 24
Finished May 05 02:34:05 PM PDT 24
Peak memory 208468 kb
Host smart-061f3415-d5e9-4871-a58c-96569c104ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835392387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.3835392387
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.4273091970
Short name T439
Test name
Test status
Simulation time 113180409 ps
CPU time 2.86 seconds
Started May 05 02:33:42 PM PDT 24
Finished May 05 02:33:46 PM PDT 24
Peak memory 206556 kb
Host smart-2126ca6f-3956-4a92-a03d-f8542e37fe51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273091970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.4273091970
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.2013847004
Short name T847
Test name
Test status
Simulation time 3093022060 ps
CPU time 24.9 seconds
Started May 05 02:33:52 PM PDT 24
Finished May 05 02:34:18 PM PDT 24
Peak memory 215716 kb
Host smart-e4499085-9f5f-40c0-b0d1-a1c6e8b40a47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013847004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.2013847004
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.582125651
Short name T643
Test name
Test status
Simulation time 116032153 ps
CPU time 4.82 seconds
Started May 05 02:33:47 PM PDT 24
Finished May 05 02:33:53 PM PDT 24
Peak memory 209076 kb
Host smart-5250fcec-5c15-4d03-b389-38b71485dbfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582125651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.582125651
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.2911590071
Short name T894
Test name
Test status
Simulation time 47463665 ps
CPU time 2.11 seconds
Started May 05 02:33:54 PM PDT 24
Finished May 05 02:33:56 PM PDT 24
Peak memory 210176 kb
Host smart-023fa59d-94b3-40b0-a1c7-b6e4842aab15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911590071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.2911590071
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.1071999103
Short name T600
Test name
Test status
Simulation time 67582469 ps
CPU time 0.76 seconds
Started May 05 02:34:00 PM PDT 24
Finished May 05 02:34:02 PM PDT 24
Peak memory 205900 kb
Host smart-ca0d1a29-e0a8-44a5-b88a-3710442f10ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071999103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.1071999103
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.724580858
Short name T132
Test name
Test status
Simulation time 206268529 ps
CPU time 4.02 seconds
Started May 05 02:34:05 PM PDT 24
Finished May 05 02:34:09 PM PDT 24
Peak memory 214164 kb
Host smart-bfbace67-67de-4b26-b11c-98dac9fc0eca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=724580858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.724580858
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.2260280365
Short name T226
Test name
Test status
Simulation time 92879459 ps
CPU time 2.45 seconds
Started May 05 02:34:02 PM PDT 24
Finished May 05 02:34:05 PM PDT 24
Peak memory 208880 kb
Host smart-c9afd801-7d58-47d6-9afe-e232a2682fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260280365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.2260280365
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.1772362663
Short name T576
Test name
Test status
Simulation time 161025533 ps
CPU time 2.1 seconds
Started May 05 02:33:57 PM PDT 24
Finished May 05 02:33:59 PM PDT 24
Peak memory 207260 kb
Host smart-5d62b5eb-3f97-4707-8db4-87dd9cc92d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772362663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.1772362663
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.1591396198
Short name T738
Test name
Test status
Simulation time 54942500 ps
CPU time 3.33 seconds
Started May 05 02:34:01 PM PDT 24
Finished May 05 02:34:05 PM PDT 24
Peak memory 208600 kb
Host smart-a9a22eb4-f866-406d-8b03-41a499edb7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591396198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.1591396198
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.3411019246
Short name T364
Test name
Test status
Simulation time 44059838 ps
CPU time 2.82 seconds
Started May 05 02:34:04 PM PDT 24
Finished May 05 02:34:07 PM PDT 24
Peak memory 214224 kb
Host smart-10d90924-d9c5-4919-82c3-8ddc251c5cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411019246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.3411019246
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.1109094869
Short name T61
Test name
Test status
Simulation time 209504190 ps
CPU time 3.41 seconds
Started May 05 02:33:57 PM PDT 24
Finished May 05 02:34:00 PM PDT 24
Peak memory 214152 kb
Host smart-bc9999c9-5272-4555-babc-81d11df55898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109094869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.1109094869
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.3858913863
Short name T637
Test name
Test status
Simulation time 7743950006 ps
CPU time 39.54 seconds
Started May 05 02:34:02 PM PDT 24
Finished May 05 02:34:42 PM PDT 24
Peak memory 209700 kb
Host smart-0ce11d87-9a72-4b34-a269-47fa70c11936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858913863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.3858913863
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.3617815062
Short name T207
Test name
Test status
Simulation time 51281834 ps
CPU time 2.83 seconds
Started May 05 02:34:03 PM PDT 24
Finished May 05 02:34:07 PM PDT 24
Peak memory 206004 kb
Host smart-507cffa1-2d3d-460c-806f-72a27bfda1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617815062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.3617815062
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.2237240815
Short name T786
Test name
Test status
Simulation time 382056924 ps
CPU time 4.84 seconds
Started May 05 02:33:56 PM PDT 24
Finished May 05 02:34:02 PM PDT 24
Peak memory 208644 kb
Host smart-7729c3bf-7e2b-426a-a7ff-af8f41b520c4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237240815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.2237240815
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.2315602845
Short name T722
Test name
Test status
Simulation time 193091659 ps
CPU time 2.84 seconds
Started May 05 02:33:57 PM PDT 24
Finished May 05 02:34:00 PM PDT 24
Peak memory 206776 kb
Host smart-e636e0a9-2cf4-42c9-a2ea-0f3a4cdf7f6a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315602845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.2315602845
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.4028970698
Short name T562
Test name
Test status
Simulation time 676113019 ps
CPU time 5.85 seconds
Started May 05 02:34:01 PM PDT 24
Finished May 05 02:34:07 PM PDT 24
Peak memory 208804 kb
Host smart-8fe975b8-3b62-4ee0-9ce5-d9b3d2a25c85
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028970698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.4028970698
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.3563578393
Short name T859
Test name
Test status
Simulation time 76106107 ps
CPU time 3.14 seconds
Started May 05 02:34:01 PM PDT 24
Finished May 05 02:34:04 PM PDT 24
Peak memory 214208 kb
Host smart-37c76d30-0df1-4b11-ad51-e74fa3dded1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563578393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.3563578393
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.3567775277
Short name T86
Test name
Test status
Simulation time 146251980 ps
CPU time 2.92 seconds
Started May 05 02:34:02 PM PDT 24
Finished May 05 02:34:05 PM PDT 24
Peak memory 208484 kb
Host smart-8e4cc749-7adb-42f3-a712-9ee3a9b0b083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567775277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.3567775277
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.3672868915
Short name T180
Test name
Test status
Simulation time 190180239 ps
CPU time 6.65 seconds
Started May 05 02:34:03 PM PDT 24
Finished May 05 02:34:10 PM PDT 24
Peak memory 222584 kb
Host smart-7026a73f-637c-4b88-8f58-714c5c91023f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672868915 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.3672868915
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.3438339353
Short name T629
Test name
Test status
Simulation time 705318104 ps
CPU time 5.85 seconds
Started May 05 02:34:01 PM PDT 24
Finished May 05 02:34:08 PM PDT 24
Peak memory 207300 kb
Host smart-4a74af62-540e-448b-9ffa-c4108f08e74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438339353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.3438339353
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.2924998000
Short name T390
Test name
Test status
Simulation time 176098780 ps
CPU time 1.61 seconds
Started May 05 02:33:58 PM PDT 24
Finished May 05 02:34:00 PM PDT 24
Peak memory 209700 kb
Host smart-2adc0e13-f308-4ea9-81ea-555c8b4f9c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924998000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.2924998000
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.2591042566
Short name T743
Test name
Test status
Simulation time 10408486 ps
CPU time 0.84 seconds
Started May 05 02:30:02 PM PDT 24
Finished May 05 02:30:03 PM PDT 24
Peak memory 205880 kb
Host smart-bd154e2d-90fa-44c5-8c90-333040d07d11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591042566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.2591042566
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.420707698
Short name T425
Test name
Test status
Simulation time 41874788 ps
CPU time 3.23 seconds
Started May 05 02:29:58 PM PDT 24
Finished May 05 02:30:01 PM PDT 24
Peak memory 214208 kb
Host smart-8ea398cc-6e52-4b5b-8b9c-335d3ea3d927
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=420707698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.420707698
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.1677797566
Short name T490
Test name
Test status
Simulation time 229015537 ps
CPU time 3.16 seconds
Started May 05 02:30:03 PM PDT 24
Finished May 05 02:30:07 PM PDT 24
Peak memory 214240 kb
Host smart-e449bc9f-f2a7-4973-a933-83db455524f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677797566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.1677797566
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.2560856254
Short name T864
Test name
Test status
Simulation time 5118811685 ps
CPU time 26.82 seconds
Started May 05 02:30:03 PM PDT 24
Finished May 05 02:30:30 PM PDT 24
Peak memory 214280 kb
Host smart-af2e2af3-afa2-4f7a-903a-9fccea01e5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560856254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.2560856254
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.2929990739
Short name T275
Test name
Test status
Simulation time 338126701 ps
CPU time 6.39 seconds
Started May 05 02:30:02 PM PDT 24
Finished May 05 02:30:09 PM PDT 24
Peak memory 214352 kb
Host smart-14532bfc-574b-424b-b64d-b48f6b6b14bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929990739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.2929990739
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.1599161615
Short name T70
Test name
Test status
Simulation time 343514872 ps
CPU time 3.9 seconds
Started May 05 02:30:00 PM PDT 24
Finished May 05 02:30:04 PM PDT 24
Peak memory 209096 kb
Host smart-2299a692-6b88-4d64-9fac-709abad6d96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599161615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.1599161615
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.3195886727
Short name T459
Test name
Test status
Simulation time 199590649 ps
CPU time 5.53 seconds
Started May 05 02:29:58 PM PDT 24
Finished May 05 02:30:04 PM PDT 24
Peak memory 209472 kb
Host smart-cfeee8dc-e91d-4318-b2ba-ad7077a2f503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195886727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.3195886727
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sideload.1973126636
Short name T804
Test name
Test status
Simulation time 914808773 ps
CPU time 3.35 seconds
Started May 05 02:29:54 PM PDT 24
Finished May 05 02:29:58 PM PDT 24
Peak memory 208456 kb
Host smart-84e4bb3a-a5a3-417f-9091-fe62b1838bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973126636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.1973126636
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.1121491326
Short name T355
Test name
Test status
Simulation time 214548481 ps
CPU time 6.39 seconds
Started May 05 02:29:58 PM PDT 24
Finished May 05 02:30:04 PM PDT 24
Peak memory 207760 kb
Host smart-99929649-37ab-4768-bc16-41aa6229d7f1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121491326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.1121491326
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.938022563
Short name T601
Test name
Test status
Simulation time 47114784 ps
CPU time 1.9 seconds
Started May 05 02:29:52 PM PDT 24
Finished May 05 02:29:55 PM PDT 24
Peak memory 206684 kb
Host smart-2fc340a9-4986-4f46-b0d0-3f6f87f67c0b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938022563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.938022563
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.1700252778
Short name T627
Test name
Test status
Simulation time 249689400 ps
CPU time 3.4 seconds
Started May 05 02:29:58 PM PDT 24
Finished May 05 02:30:01 PM PDT 24
Peak memory 207372 kb
Host smart-cd940172-ca09-49e7-a1f8-45f40060f1e1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700252778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.1700252778
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.3562604698
Short name T102
Test name
Test status
Simulation time 689308053 ps
CPU time 4.63 seconds
Started May 05 02:30:03 PM PDT 24
Finished May 05 02:30:08 PM PDT 24
Peak memory 207976 kb
Host smart-2012ee58-e1b1-493d-aa11-efe10995672a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562604698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.3562604698
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.1990809920
Short name T520
Test name
Test status
Simulation time 67904415 ps
CPU time 2.31 seconds
Started May 05 02:29:55 PM PDT 24
Finished May 05 02:29:57 PM PDT 24
Peak memory 206620 kb
Host smart-dae2d754-b222-4651-86cb-ecb5293184d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990809920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.1990809920
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.1634819220
Short name T605
Test name
Test status
Simulation time 3682913894 ps
CPU time 89.64 seconds
Started May 05 02:30:02 PM PDT 24
Finished May 05 02:31:33 PM PDT 24
Peak memory 216364 kb
Host smart-d01e62c3-a51f-4d64-af34-705332429b30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634819220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.1634819220
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.4144064248
Short name T780
Test name
Test status
Simulation time 680651561 ps
CPU time 25.04 seconds
Started May 05 02:30:02 PM PDT 24
Finished May 05 02:30:27 PM PDT 24
Peak memory 222464 kb
Host smart-ebd579a4-95df-40c0-bb67-13d8752d3d01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144064248 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.4144064248
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.2115612980
Short name T623
Test name
Test status
Simulation time 109898452 ps
CPU time 4.94 seconds
Started May 05 02:29:57 PM PDT 24
Finished May 05 02:30:02 PM PDT 24
Peak memory 208368 kb
Host smart-348a5421-faf4-4738-b550-23e5049043b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115612980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.2115612980
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.1696024660
Short name T666
Test name
Test status
Simulation time 60158836 ps
CPU time 0.82 seconds
Started May 05 02:34:06 PM PDT 24
Finished May 05 02:34:08 PM PDT 24
Peak memory 205820 kb
Host smart-0851ddb8-e0c9-4b36-ace8-d25546ae6fb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696024660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.1696024660
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.968566082
Short name T432
Test name
Test status
Simulation time 4338329968 ps
CPU time 61.27 seconds
Started May 05 02:34:03 PM PDT 24
Finished May 05 02:35:05 PM PDT 24
Peak memory 217660 kb
Host smart-b9408af7-60fc-4dfc-87f0-300e867d59a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=968566082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.968566082
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.4163473026
Short name T154
Test name
Test status
Simulation time 69163204 ps
CPU time 3.36 seconds
Started May 05 02:34:08 PM PDT 24
Finished May 05 02:34:12 PM PDT 24
Peak memory 222528 kb
Host smart-14ccb2d6-7403-45b0-b110-7b80ba34469e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163473026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.4163473026
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.2726961686
Short name T826
Test name
Test status
Simulation time 22976059 ps
CPU time 1.76 seconds
Started May 05 02:34:04 PM PDT 24
Finished May 05 02:34:06 PM PDT 24
Peak memory 207540 kb
Host smart-309dbeec-d890-4653-8c6f-56b30b42c40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726961686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.2726961686
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.2903190317
Short name T238
Test name
Test status
Simulation time 544315844 ps
CPU time 6.43 seconds
Started May 05 02:34:01 PM PDT 24
Finished May 05 02:34:08 PM PDT 24
Peak memory 214292 kb
Host smart-688ad0a0-1dcd-4a0b-8878-94b40173ed9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903190317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.2903190317
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.4096374553
Short name T386
Test name
Test status
Simulation time 201929115 ps
CPU time 4.23 seconds
Started May 05 02:34:06 PM PDT 24
Finished May 05 02:34:10 PM PDT 24
Peak memory 206820 kb
Host smart-8c4416c5-a101-4897-a9a1-c492029976b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096374553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.4096374553
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.3094532633
Short name T591
Test name
Test status
Simulation time 142222494 ps
CPU time 3.93 seconds
Started May 05 02:34:05 PM PDT 24
Finished May 05 02:34:09 PM PDT 24
Peak memory 219940 kb
Host smart-0c3e9dd6-400f-4a39-8df4-fd946f71c7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094532633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.3094532633
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.1988332282
Short name T528
Test name
Test status
Simulation time 2110414513 ps
CPU time 30.51 seconds
Started May 05 02:34:03 PM PDT 24
Finished May 05 02:34:34 PM PDT 24
Peak memory 209544 kb
Host smart-013148b9-52b6-4580-9404-2798efaa973e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988332282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.1988332282
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.3279168598
Short name T358
Test name
Test status
Simulation time 247495510 ps
CPU time 6.63 seconds
Started May 05 02:34:02 PM PDT 24
Finished May 05 02:34:09 PM PDT 24
Peak memory 207760 kb
Host smart-bacc4a83-3331-4c33-8054-d20bd1c963b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279168598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.3279168598
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.4267483461
Short name T604
Test name
Test status
Simulation time 173769646 ps
CPU time 5.22 seconds
Started May 05 02:34:02 PM PDT 24
Finished May 05 02:34:08 PM PDT 24
Peak memory 208056 kb
Host smart-313e8d7c-5feb-476b-b3b6-1309bad93137
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267483461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.4267483461
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.360925227
Short name T438
Test name
Test status
Simulation time 879760425 ps
CPU time 4.17 seconds
Started May 05 02:34:02 PM PDT 24
Finished May 05 02:34:07 PM PDT 24
Peak memory 206752 kb
Host smart-003f2ecf-2521-4410-9279-7c92046238f1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360925227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.360925227
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.2058291635
Short name T536
Test name
Test status
Simulation time 77086961 ps
CPU time 3.71 seconds
Started May 05 02:34:03 PM PDT 24
Finished May 05 02:34:07 PM PDT 24
Peak memory 208428 kb
Host smart-0689c23f-2bec-47db-ad26-b64bd9e59a1d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058291635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.2058291635
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.2063776718
Short name T868
Test name
Test status
Simulation time 63295318 ps
CPU time 3.11 seconds
Started May 05 02:34:07 PM PDT 24
Finished May 05 02:34:10 PM PDT 24
Peak memory 215820 kb
Host smart-a8d74d32-59fc-4f42-9419-82724ff260b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063776718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.2063776718
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.1302651742
Short name T747
Test name
Test status
Simulation time 602625351 ps
CPU time 7.71 seconds
Started May 05 02:34:03 PM PDT 24
Finished May 05 02:34:11 PM PDT 24
Peak memory 208176 kb
Host smart-c82ef192-a4b1-4c1d-a92a-d6fb4369f2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302651742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.1302651742
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.4210876068
Short name T860
Test name
Test status
Simulation time 376889290 ps
CPU time 13.97 seconds
Started May 05 02:34:07 PM PDT 24
Finished May 05 02:34:22 PM PDT 24
Peak memory 222556 kb
Host smart-c728ba97-446a-45da-83c8-3519ff9fd644
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210876068 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.4210876068
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.1171416471
Short name T186
Test name
Test status
Simulation time 62480387 ps
CPU time 3.75 seconds
Started May 05 02:34:00 PM PDT 24
Finished May 05 02:34:05 PM PDT 24
Peak memory 214252 kb
Host smart-c77b1f94-bed5-4ba4-bbb3-66f9035e1b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171416471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.1171416471
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.592217286
Short name T392
Test name
Test status
Simulation time 202242620 ps
CPU time 1.72 seconds
Started May 05 02:34:08 PM PDT 24
Finished May 05 02:34:10 PM PDT 24
Peak memory 209444 kb
Host smart-76b15da5-c46c-4f1c-9331-0a5b79a52524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592217286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.592217286
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.3034869839
Short name T840
Test name
Test status
Simulation time 28243203 ps
CPU time 0.74 seconds
Started May 05 02:34:19 PM PDT 24
Finished May 05 02:34:20 PM PDT 24
Peak memory 205916 kb
Host smart-617b53f4-745c-451a-bd87-5da151352f81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034869839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.3034869839
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.2293193350
Short name T824
Test name
Test status
Simulation time 130758769 ps
CPU time 2.73 seconds
Started May 05 02:34:12 PM PDT 24
Finished May 05 02:34:15 PM PDT 24
Peak memory 214948 kb
Host smart-51ec68cd-f2b1-424b-9777-cb8b2b6c4aa3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2293193350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.2293193350
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.3373129443
Short name T892
Test name
Test status
Simulation time 749276263 ps
CPU time 10 seconds
Started May 05 02:34:13 PM PDT 24
Finished May 05 02:34:23 PM PDT 24
Peak memory 214276 kb
Host smart-835d9329-b942-4b09-9bdd-d04fabb706ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373129443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.3373129443
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.8400208
Short name T638
Test name
Test status
Simulation time 694835408 ps
CPU time 5.02 seconds
Started May 05 02:34:11 PM PDT 24
Finished May 05 02:34:17 PM PDT 24
Peak memory 221028 kb
Host smart-d6e6a685-fb95-4242-9fa1-9628c969c362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8400208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.8400208
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.2025030029
Short name T814
Test name
Test status
Simulation time 1015415304 ps
CPU time 3.23 seconds
Started May 05 02:34:11 PM PDT 24
Finished May 05 02:34:15 PM PDT 24
Peak memory 214116 kb
Host smart-14698e1c-af2d-4302-9b0b-daddb14ce8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025030029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.2025030029
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.2178752842
Short name T648
Test name
Test status
Simulation time 394513830 ps
CPU time 3.68 seconds
Started May 05 02:34:11 PM PDT 24
Finished May 05 02:34:15 PM PDT 24
Peak memory 208916 kb
Host smart-35b82ee9-8a18-43f4-aac0-72db8086741e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178752842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.2178752842
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.4010994479
Short name T765
Test name
Test status
Simulation time 973232829 ps
CPU time 5.48 seconds
Started May 05 02:34:12 PM PDT 24
Finished May 05 02:34:18 PM PDT 24
Peak memory 207684 kb
Host smart-73e09293-76a7-4b52-a251-74cdf4bbedbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010994479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.4010994479
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.945234432
Short name T379
Test name
Test status
Simulation time 755387356 ps
CPU time 18.53 seconds
Started May 05 02:34:13 PM PDT 24
Finished May 05 02:34:32 PM PDT 24
Peak memory 208852 kb
Host smart-c7d4535e-22aa-436c-bfa2-0b01073eb97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945234432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.945234432
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.3076869383
Short name T720
Test name
Test status
Simulation time 637117571 ps
CPU time 18.86 seconds
Started May 05 02:34:12 PM PDT 24
Finished May 05 02:34:31 PM PDT 24
Peak memory 208056 kb
Host smart-b3178d19-856a-4943-ae24-f66108677064
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076869383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.3076869383
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.628404127
Short name T842
Test name
Test status
Simulation time 244323768 ps
CPU time 1.88 seconds
Started May 05 02:34:13 PM PDT 24
Finished May 05 02:34:15 PM PDT 24
Peak memory 207564 kb
Host smart-7adb1629-2c77-430b-b6a0-75dce00816c2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628404127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.628404127
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.2643837917
Short name T717
Test name
Test status
Simulation time 29629107 ps
CPU time 2.11 seconds
Started May 05 02:34:11 PM PDT 24
Finished May 05 02:34:13 PM PDT 24
Peak memory 206780 kb
Host smart-bf7e5ca2-7220-426c-b95e-2350c4acaf9c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643837917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.2643837917
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.4075166352
Short name T852
Test name
Test status
Simulation time 47397124 ps
CPU time 2.05 seconds
Started May 05 02:34:16 PM PDT 24
Finished May 05 02:34:18 PM PDT 24
Peak memory 207664 kb
Host smart-ba836844-0061-4aee-9947-10dc72878b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075166352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.4075166352
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.2583580277
Short name T4
Test name
Test status
Simulation time 1683894903 ps
CPU time 33.75 seconds
Started May 05 02:34:07 PM PDT 24
Finished May 05 02:34:41 PM PDT 24
Peak memory 207752 kb
Host smart-f8fa72d8-60a8-42c6-a4bf-fffdd31bd522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583580277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.2583580277
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.1751610998
Short name T263
Test name
Test status
Simulation time 1534250798 ps
CPU time 18.08 seconds
Started May 05 02:34:15 PM PDT 24
Finished May 05 02:34:34 PM PDT 24
Peak memory 222340 kb
Host smart-0c8e582f-1f75-4a83-aab4-a63be0c56c1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751610998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.1751610998
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.954522552
Short name T463
Test name
Test status
Simulation time 72870521 ps
CPU time 3.52 seconds
Started May 05 02:34:13 PM PDT 24
Finished May 05 02:34:17 PM PDT 24
Peak memory 207680 kb
Host smart-f6bf4e58-5745-4599-9f25-52b59b2d8eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954522552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.954522552
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.894834371
Short name T526
Test name
Test status
Simulation time 274069909 ps
CPU time 2.62 seconds
Started May 05 02:34:17 PM PDT 24
Finished May 05 02:34:20 PM PDT 24
Peak memory 210236 kb
Host smart-ab8ddf9f-dcac-476e-b832-0d858240ec19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894834371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.894834371
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.3629397915
Short name T544
Test name
Test status
Simulation time 57164975 ps
CPU time 0.81 seconds
Started May 05 02:34:21 PM PDT 24
Finished May 05 02:34:22 PM PDT 24
Peak memory 205884 kb
Host smart-27fab59e-08e3-4d65-b1be-7f2d65ab4afd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629397915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.3629397915
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.3591403495
Short name T259
Test name
Test status
Simulation time 140096255 ps
CPU time 3.03 seconds
Started May 05 02:34:27 PM PDT 24
Finished May 05 02:34:31 PM PDT 24
Peak memory 215068 kb
Host smart-08019c1a-9005-4e61-ac90-b9cf60bf5b52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3591403495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.3591403495
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.1663729169
Short name T34
Test name
Test status
Simulation time 51147145 ps
CPU time 1.18 seconds
Started May 05 02:34:21 PM PDT 24
Finished May 05 02:34:22 PM PDT 24
Peak memory 205968 kb
Host smart-e02749e0-b3e2-4a1b-abbf-6e6f0e4af07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663729169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.1663729169
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.3494371004
Short name T755
Test name
Test status
Simulation time 22331902 ps
CPU time 1.47 seconds
Started May 05 02:34:22 PM PDT 24
Finished May 05 02:34:24 PM PDT 24
Peak memory 209120 kb
Host smart-4ba35e66-31f7-43b5-9729-bd7a3cb38c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494371004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.3494371004
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.915292186
Short name T863
Test name
Test status
Simulation time 201692892 ps
CPU time 3.44 seconds
Started May 05 02:34:21 PM PDT 24
Finished May 05 02:34:25 PM PDT 24
Peak memory 214348 kb
Host smart-c9f7b9f1-9455-468e-9b0a-6b29464babcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915292186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.915292186
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.3882393839
Short name T367
Test name
Test status
Simulation time 447327780 ps
CPU time 4.01 seconds
Started May 05 02:34:28 PM PDT 24
Finished May 05 02:34:32 PM PDT 24
Peak memory 214200 kb
Host smart-57166700-a58c-488f-88eb-2e8173c0ed39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882393839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.3882393839
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.3883382504
Short name T614
Test name
Test status
Simulation time 187582132 ps
CPU time 2.97 seconds
Started May 05 02:34:22 PM PDT 24
Finished May 05 02:34:25 PM PDT 24
Peak memory 220308 kb
Host smart-0a0fa60c-d9e5-4b46-9a50-fc6ce02a8c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883382504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.3883382504
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.3859750016
Short name T258
Test name
Test status
Simulation time 1954557141 ps
CPU time 22.1 seconds
Started May 05 02:34:23 PM PDT 24
Finished May 05 02:34:45 PM PDT 24
Peak memory 209524 kb
Host smart-daba4642-6767-42f1-b15d-2165af868683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859750016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.3859750016
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.177556787
Short name T876
Test name
Test status
Simulation time 1868947377 ps
CPU time 44.79 seconds
Started May 05 02:34:28 PM PDT 24
Finished May 05 02:35:13 PM PDT 24
Peak memory 208496 kb
Host smart-c456e372-10d9-4016-9d21-14eaa8029be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177556787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.177556787
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.3942964509
Short name T523
Test name
Test status
Simulation time 1498699474 ps
CPU time 15.54 seconds
Started May 05 02:34:20 PM PDT 24
Finished May 05 02:34:35 PM PDT 24
Peak memory 208016 kb
Host smart-c2ad1773-5240-47b1-9c42-d38e70048e5e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942964509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.3942964509
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.2748020681
Short name T884
Test name
Test status
Simulation time 51677061 ps
CPU time 2.74 seconds
Started May 05 02:34:20 PM PDT 24
Finished May 05 02:34:23 PM PDT 24
Peak memory 208532 kb
Host smart-73de5efe-c3e8-4de1-8d1c-04cbb64f55c5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748020681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.2748020681
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.870511945
Short name T727
Test name
Test status
Simulation time 399947483 ps
CPU time 6 seconds
Started May 05 02:34:20 PM PDT 24
Finished May 05 02:34:26 PM PDT 24
Peak memory 208428 kb
Host smart-ccd13e8a-1848-426f-b797-8801a4281fa6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870511945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.870511945
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.872010582
Short name T628
Test name
Test status
Simulation time 641719410 ps
CPU time 7.03 seconds
Started May 05 02:34:27 PM PDT 24
Finished May 05 02:34:35 PM PDT 24
Peak memory 214240 kb
Host smart-ada8051b-4675-44e9-bc32-eb7a1e432161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872010582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.872010582
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.2102065497
Short name T794
Test name
Test status
Simulation time 226644950 ps
CPU time 3.12 seconds
Started May 05 02:34:20 PM PDT 24
Finished May 05 02:34:24 PM PDT 24
Peak memory 206532 kb
Host smart-2c7a8051-c1e0-4ec8-971e-2a5226b7322a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102065497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.2102065497
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.2941016720
Short name T625
Test name
Test status
Simulation time 1462235741 ps
CPU time 16.46 seconds
Started May 05 02:34:28 PM PDT 24
Finished May 05 02:34:45 PM PDT 24
Peak memory 209364 kb
Host smart-409fdfc6-7672-4882-8950-f0047fd01689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941016720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.2941016720
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.1864761504
Short name T634
Test name
Test status
Simulation time 40919804 ps
CPU time 2.4 seconds
Started May 05 02:34:23 PM PDT 24
Finished May 05 02:34:26 PM PDT 24
Peak memory 209744 kb
Host smart-d8d8753e-f92a-4605-8095-15a5b4b53f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864761504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.1864761504
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.3656210831
Short name T641
Test name
Test status
Simulation time 30501013 ps
CPU time 0.95 seconds
Started May 05 02:34:31 PM PDT 24
Finished May 05 02:34:32 PM PDT 24
Peak memory 206048 kb
Host smart-c2f6be70-fd27-4169-8f5b-945bb85511f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656210831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.3656210831
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.2591419394
Short name T131
Test name
Test status
Simulation time 64604680 ps
CPU time 4.62 seconds
Started May 05 02:34:26 PM PDT 24
Finished May 05 02:34:31 PM PDT 24
Peak memory 215280 kb
Host smart-682ccf7c-9d42-413d-9d3b-ae36f12ff8e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2591419394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.2591419394
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.3798950631
Short name T908
Test name
Test status
Simulation time 465507582 ps
CPU time 5.74 seconds
Started May 05 02:34:32 PM PDT 24
Finished May 05 02:34:38 PM PDT 24
Peak memory 218124 kb
Host smart-1419da33-b908-4266-b16f-3b7d4ac64895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798950631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.3798950631
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.865888302
Short name T27
Test name
Test status
Simulation time 118974694 ps
CPU time 3.98 seconds
Started May 05 02:34:28 PM PDT 24
Finished May 05 02:34:32 PM PDT 24
Peak memory 221456 kb
Host smart-0e25a86d-5f0a-4434-972a-dfd4f8cc68a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865888302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.865888302
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.1571788115
Short name T420
Test name
Test status
Simulation time 227799625 ps
CPU time 3.24 seconds
Started May 05 02:34:26 PM PDT 24
Finished May 05 02:34:29 PM PDT 24
Peak memory 208728 kb
Host smart-3e210778-528f-43b5-bc0a-4d6e7917cda8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571788115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.1571788115
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.3098047638
Short name T316
Test name
Test status
Simulation time 40314213 ps
CPU time 2.67 seconds
Started May 05 02:34:26 PM PDT 24
Finished May 05 02:34:29 PM PDT 24
Peak memory 214236 kb
Host smart-468c810d-8e97-42a0-8b72-c3734b4e2a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098047638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.3098047638
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.1447545582
Short name T78
Test name
Test status
Simulation time 143024529 ps
CPU time 4.66 seconds
Started May 05 02:34:27 PM PDT 24
Finished May 05 02:34:32 PM PDT 24
Peak memory 208732 kb
Host smart-60f3f6fd-d747-48a1-b20a-5231333ea045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447545582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.1447545582
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.1267731999
Short name T759
Test name
Test status
Simulation time 1491894006 ps
CPU time 48.64 seconds
Started May 05 02:34:26 PM PDT 24
Finished May 05 02:35:15 PM PDT 24
Peak memory 207860 kb
Host smart-c1a280cc-786c-48ee-9db9-9b65797fd209
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267731999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.1267731999
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.2638564444
Short name T877
Test name
Test status
Simulation time 239335368 ps
CPU time 5.53 seconds
Started May 05 02:34:32 PM PDT 24
Finished May 05 02:34:38 PM PDT 24
Peak memory 208440 kb
Host smart-d8935fa5-a412-406a-a53a-df15c5e190bf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638564444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.2638564444
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.4240445121
Short name T482
Test name
Test status
Simulation time 93927646 ps
CPU time 3.4 seconds
Started May 05 02:34:26 PM PDT 24
Finished May 05 02:34:30 PM PDT 24
Peak memory 208040 kb
Host smart-ad9d0aec-f6bf-4e54-95d8-22c22802b870
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240445121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.4240445121
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.2679201650
Short name T890
Test name
Test status
Simulation time 55563549 ps
CPU time 2.69 seconds
Started May 05 02:34:28 PM PDT 24
Finished May 05 02:34:31 PM PDT 24
Peak memory 209044 kb
Host smart-7fd285ef-9bad-452d-ae1e-56d42c71b7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679201650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.2679201650
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.816827585
Short name T565
Test name
Test status
Simulation time 1653112902 ps
CPU time 21.35 seconds
Started May 05 02:34:26 PM PDT 24
Finished May 05 02:34:47 PM PDT 24
Peak memory 208076 kb
Host smart-49371c1b-38d9-40eb-982c-e2915494b681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816827585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.816827585
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.3303201690
Short name T28
Test name
Test status
Simulation time 118379833 ps
CPU time 6.96 seconds
Started May 05 02:34:33 PM PDT 24
Finished May 05 02:34:40 PM PDT 24
Peak memory 215568 kb
Host smart-3ac2726d-2f0d-489b-9627-492178ce5fa8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303201690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.3303201690
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.976244156
Short name T310
Test name
Test status
Simulation time 164061662 ps
CPU time 3.23 seconds
Started May 05 02:34:32 PM PDT 24
Finished May 05 02:34:36 PM PDT 24
Peak memory 214344 kb
Host smart-39c6be77-491d-429f-98fb-e4fbf1ae58d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976244156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.976244156
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.596284930
Short name T875
Test name
Test status
Simulation time 54534707 ps
CPU time 1.82 seconds
Started May 05 02:34:28 PM PDT 24
Finished May 05 02:34:30 PM PDT 24
Peak memory 209868 kb
Host smart-669a3737-fa70-4320-a165-3b7e105f4de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596284930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.596284930
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.4174154768
Short name T773
Test name
Test status
Simulation time 14608286 ps
CPU time 0.9 seconds
Started May 05 02:34:40 PM PDT 24
Finished May 05 02:34:42 PM PDT 24
Peak memory 205776 kb
Host smart-9fc2e33f-35e6-402e-bbe7-a2ce35a2fbad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174154768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.4174154768
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.318423147
Short name T135
Test name
Test status
Simulation time 443936496 ps
CPU time 3.7 seconds
Started May 05 02:34:37 PM PDT 24
Finished May 05 02:34:41 PM PDT 24
Peak memory 214264 kb
Host smart-b808a575-156e-4fa1-a3d3-28a883b916af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=318423147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.318423147
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.2044905794
Short name T831
Test name
Test status
Simulation time 227239054 ps
CPU time 4.47 seconds
Started May 05 02:34:36 PM PDT 24
Finished May 05 02:34:41 PM PDT 24
Peak memory 222684 kb
Host smart-9f950eac-836c-4fe6-9b89-fbf3de1dc4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044905794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.2044905794
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.1365484208
Short name T197
Test name
Test status
Simulation time 975211333 ps
CPU time 25.34 seconds
Started May 05 02:34:37 PM PDT 24
Finished May 05 02:35:03 PM PDT 24
Peak memory 208872 kb
Host smart-2a59f3a8-760b-492c-a916-9843b3a1eb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365484208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.1365484208
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.799915818
Short name T54
Test name
Test status
Simulation time 380487600 ps
CPU time 3.5 seconds
Started May 05 02:34:37 PM PDT 24
Finished May 05 02:34:40 PM PDT 24
Peak memory 214200 kb
Host smart-288a9f95-b649-4df4-8bca-513ca07abcb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799915818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.799915818
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.1256047264
Short name T8
Test name
Test status
Simulation time 114980274 ps
CPU time 2.36 seconds
Started May 05 02:34:37 PM PDT 24
Finished May 05 02:34:40 PM PDT 24
Peak memory 216160 kb
Host smart-954e4610-f239-4a77-9d57-ef1c48f483b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256047264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.1256047264
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.2857849333
Short name T311
Test name
Test status
Simulation time 353757149 ps
CPU time 12.68 seconds
Started May 05 02:34:32 PM PDT 24
Finished May 05 02:34:45 PM PDT 24
Peak memory 218172 kb
Host smart-36741a34-5d56-45cb-9912-55c6a7be6ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857849333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.2857849333
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.2639393162
Short name T369
Test name
Test status
Simulation time 55622028 ps
CPU time 2.93 seconds
Started May 05 02:34:31 PM PDT 24
Finished May 05 02:34:34 PM PDT 24
Peak memory 208588 kb
Host smart-e60582fc-cee0-45f8-bb30-67b31a6648d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639393162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.2639393162
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.552484907
Short name T264
Test name
Test status
Simulation time 117491612 ps
CPU time 3.71 seconds
Started May 05 02:34:32 PM PDT 24
Finished May 05 02:34:36 PM PDT 24
Peak memory 206724 kb
Host smart-df24efcd-6340-477b-a9ca-249b288ea5b0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552484907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.552484907
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.842835810
Short name T322
Test name
Test status
Simulation time 590768075 ps
CPU time 19.31 seconds
Started May 05 02:34:32 PM PDT 24
Finished May 05 02:34:52 PM PDT 24
Peak memory 207952 kb
Host smart-a5b2ec64-d806-41f5-ba16-10ce748f025c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842835810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.842835810
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.3143200173
Short name T211
Test name
Test status
Simulation time 177012130 ps
CPU time 2.74 seconds
Started May 05 02:34:30 PM PDT 24
Finished May 05 02:34:33 PM PDT 24
Peak memory 208528 kb
Host smart-2eabaaf6-638e-43f6-ab04-c45da4e3295d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143200173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.3143200173
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.4232914827
Short name T260
Test name
Test status
Simulation time 216849239 ps
CPU time 2.73 seconds
Started May 05 02:34:37 PM PDT 24
Finished May 05 02:34:40 PM PDT 24
Peak memory 215828 kb
Host smart-9c970463-6397-4894-96e0-5bbfc3de8f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232914827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.4232914827
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.549350520
Short name T471
Test name
Test status
Simulation time 73665914 ps
CPU time 3.05 seconds
Started May 05 02:34:33 PM PDT 24
Finished May 05 02:34:36 PM PDT 24
Peak memory 206628 kb
Host smart-e80cc4bc-9fc1-4132-a1d8-4ee91d5693e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549350520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.549350520
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.3569148082
Short name T280
Test name
Test status
Simulation time 38265889010 ps
CPU time 220.19 seconds
Started May 05 02:34:39 PM PDT 24
Finished May 05 02:38:20 PM PDT 24
Peak memory 219328 kb
Host smart-25992b1a-c2ba-45d1-8746-b35743bdf7d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569148082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.3569148082
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.1827493107
Short name T119
Test name
Test status
Simulation time 1361747606 ps
CPU time 11.23 seconds
Started May 05 02:34:41 PM PDT 24
Finished May 05 02:34:53 PM PDT 24
Peak memory 222556 kb
Host smart-ece3dc9d-edc3-4105-9129-b42182aee407
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827493107 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.1827493107
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.3315311000
Short name T710
Test name
Test status
Simulation time 3722266882 ps
CPU time 51.11 seconds
Started May 05 02:34:37 PM PDT 24
Finished May 05 02:35:29 PM PDT 24
Peak memory 214384 kb
Host smart-0a256994-d759-41b8-8277-e39ac8761796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315311000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.3315311000
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.2378114981
Short name T498
Test name
Test status
Simulation time 10576265 ps
CPU time 0.73 seconds
Started May 05 02:34:43 PM PDT 24
Finished May 05 02:34:44 PM PDT 24
Peak memory 205808 kb
Host smart-620f5d7c-d8fc-4fa3-986c-6860b8fcc828
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378114981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.2378114981
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.2961837795
Short name T308
Test name
Test status
Simulation time 180084725 ps
CPU time 3.66 seconds
Started May 05 02:34:40 PM PDT 24
Finished May 05 02:34:44 PM PDT 24
Peak memory 215340 kb
Host smart-6e375bf8-2387-44d4-ab7e-30a02d6fc603
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2961837795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.2961837795
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.3837335845
Short name T553
Test name
Test status
Simulation time 61809826 ps
CPU time 2.23 seconds
Started May 05 02:34:42 PM PDT 24
Finished May 05 02:34:44 PM PDT 24
Peak memory 209596 kb
Host smart-8f9e1836-d374-4dd0-966e-04d7ff152b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837335845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.3837335845
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.2016720962
Short name T762
Test name
Test status
Simulation time 177896386 ps
CPU time 4.92 seconds
Started May 05 02:34:40 PM PDT 24
Finished May 05 02:34:46 PM PDT 24
Peak memory 209508 kb
Host smart-08d86368-1877-41b7-96e3-0c6f094d0238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016720962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.2016720962
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.1996887897
Short name T418
Test name
Test status
Simulation time 505457388 ps
CPU time 10.14 seconds
Started May 05 02:34:42 PM PDT 24
Finished May 05 02:34:53 PM PDT 24
Peak memory 220424 kb
Host smart-afdae0b3-407e-41d4-b029-56133f62d43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996887897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.1996887897
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.1348339463
Short name T684
Test name
Test status
Simulation time 2342498361 ps
CPU time 12.38 seconds
Started May 05 02:34:41 PM PDT 24
Finished May 05 02:34:53 PM PDT 24
Peak memory 214324 kb
Host smart-f86fcb69-30bc-45ff-9ac7-b19164e76cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348339463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.1348339463
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.3911505502
Short name T219
Test name
Test status
Simulation time 247611809 ps
CPU time 3.13 seconds
Started May 05 02:34:40 PM PDT 24
Finished May 05 02:34:44 PM PDT 24
Peak memory 209220 kb
Host smart-bdc4df17-9a2f-4afc-af0b-0d838fabfdde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911505502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.3911505502
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.1310039936
Short name T204
Test name
Test status
Simulation time 337809885 ps
CPU time 4.62 seconds
Started May 05 02:34:40 PM PDT 24
Finished May 05 02:34:45 PM PDT 24
Peak memory 207464 kb
Host smart-7e64212c-5c5f-4d9f-a3d0-ca13672d5a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310039936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.1310039936
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.1443686703
Short name T709
Test name
Test status
Simulation time 520243176 ps
CPU time 12.79 seconds
Started May 05 02:34:40 PM PDT 24
Finished May 05 02:34:53 PM PDT 24
Peak memory 207856 kb
Host smart-3f4ed30b-35d7-4be4-8f1e-0045086328d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443686703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.1443686703
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.979007412
Short name T692
Test name
Test status
Simulation time 162428947 ps
CPU time 4.87 seconds
Started May 05 02:34:40 PM PDT 24
Finished May 05 02:34:46 PM PDT 24
Peak memory 208628 kb
Host smart-9ac1807c-bfdc-41c2-9d5f-37f72c213cdf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979007412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.979007412
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.1587592161
Short name T546
Test name
Test status
Simulation time 26347971 ps
CPU time 2.1 seconds
Started May 05 02:34:42 PM PDT 24
Finished May 05 02:34:45 PM PDT 24
Peak memory 208460 kb
Host smart-b9826ab8-66c3-457d-a410-ddc8bbf25007
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587592161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.1587592161
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.86274815
Short name T790
Test name
Test status
Simulation time 149686471 ps
CPU time 2.45 seconds
Started May 05 02:34:42 PM PDT 24
Finished May 05 02:34:45 PM PDT 24
Peak memory 207116 kb
Host smart-320c63a7-4881-43f1-9ba4-a8cd4790991d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86274815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.86274815
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.3071248528
Short name T447
Test name
Test status
Simulation time 169037270 ps
CPU time 1.64 seconds
Started May 05 02:34:40 PM PDT 24
Finished May 05 02:34:42 PM PDT 24
Peak memory 206884 kb
Host smart-436b3676-684d-4bec-a3af-e3cdaafbce4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071248528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.3071248528
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.1598137130
Short name T613
Test name
Test status
Simulation time 704382208 ps
CPU time 7.78 seconds
Started May 05 02:34:40 PM PDT 24
Finished May 05 02:34:48 PM PDT 24
Peak memory 208360 kb
Host smart-fed1cef5-2e0c-417b-8e5f-a2f1476133a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598137130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.1598137130
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.2286632077
Short name T246
Test name
Test status
Simulation time 75603846 ps
CPU time 3.77 seconds
Started May 05 02:34:40 PM PDT 24
Finished May 05 02:34:44 PM PDT 24
Peak memory 209536 kb
Host smart-a7ff2ef7-cff3-42d3-a112-fa7713f2abef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286632077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.2286632077
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.3562746187
Short name T817
Test name
Test status
Simulation time 114558578 ps
CPU time 1.56 seconds
Started May 05 02:34:47 PM PDT 24
Finished May 05 02:34:49 PM PDT 24
Peak memory 209784 kb
Host smart-0cb2917b-00b5-450a-a40e-af9baed12d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562746187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.3562746187
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.4181521740
Short name T99
Test name
Test status
Simulation time 16966817 ps
CPU time 0.9 seconds
Started May 05 02:34:53 PM PDT 24
Finished May 05 02:34:55 PM PDT 24
Peak memory 205732 kb
Host smart-081f2043-515c-41de-8679-fad6f0ca27c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181521740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.4181521740
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.186370826
Short name T333
Test name
Test status
Simulation time 265275315 ps
CPU time 4.92 seconds
Started May 05 02:34:50 PM PDT 24
Finished May 05 02:34:55 PM PDT 24
Peak memory 215604 kb
Host smart-6ecb73be-5471-4635-acc3-8af30cdd16b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=186370826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.186370826
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.905716743
Short name T816
Test name
Test status
Simulation time 103282668 ps
CPU time 3.53 seconds
Started May 05 02:34:50 PM PDT 24
Finished May 05 02:34:54 PM PDT 24
Peak memory 222648 kb
Host smart-3dbf7e25-520f-4f66-a17a-085893869025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905716743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.905716743
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.1319024146
Short name T284
Test name
Test status
Simulation time 228564342 ps
CPU time 2.67 seconds
Started May 05 02:34:49 PM PDT 24
Finished May 05 02:34:53 PM PDT 24
Peak memory 208188 kb
Host smart-60d36175-de4b-4c4e-8d40-24ea1539d479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319024146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.1319024146
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.4051486031
Short name T98
Test name
Test status
Simulation time 359426505 ps
CPU time 4.43 seconds
Started May 05 02:34:50 PM PDT 24
Finished May 05 02:34:55 PM PDT 24
Peak memory 209444 kb
Host smart-46a5f38e-d4d4-4360-bb28-d69a0c079d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051486031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.4051486031
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.752442590
Short name T423
Test name
Test status
Simulation time 104805974 ps
CPU time 2.03 seconds
Started May 05 02:34:49 PM PDT 24
Finished May 05 02:34:52 PM PDT 24
Peak memory 214152 kb
Host smart-c505dd41-c42d-4e52-8be1-a19b343f9383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752442590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.752442590
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.1167265387
Short name T222
Test name
Test status
Simulation time 208567666 ps
CPU time 3.01 seconds
Started May 05 02:34:50 PM PDT 24
Finished May 05 02:34:53 PM PDT 24
Peak memory 222416 kb
Host smart-840d2401-8ae7-4729-8c7d-d348d8fea248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167265387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.1167265387
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.2663794517
Short name T330
Test name
Test status
Simulation time 173160308 ps
CPU time 4.33 seconds
Started May 05 02:34:51 PM PDT 24
Finished May 05 02:34:56 PM PDT 24
Peak memory 208156 kb
Host smart-cfd7e61a-667d-4338-92f2-c9a6251110cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663794517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.2663794517
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.3472946507
Short name T248
Test name
Test status
Simulation time 78043206 ps
CPU time 2.9 seconds
Started May 05 02:34:46 PM PDT 24
Finished May 05 02:34:50 PM PDT 24
Peak memory 208152 kb
Host smart-d5a1acfc-9f0d-47f2-a13c-c20eda81f67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472946507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.3472946507
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.2190612769
Short name T566
Test name
Test status
Simulation time 60819581 ps
CPU time 2.95 seconds
Started May 05 02:34:45 PM PDT 24
Finished May 05 02:34:48 PM PDT 24
Peak memory 207716 kb
Host smart-36d6ed05-98ec-4a78-b4aa-44971880adad
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190612769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.2190612769
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.2083220531
Short name T372
Test name
Test status
Simulation time 7657301636 ps
CPU time 75.44 seconds
Started May 05 02:34:44 PM PDT 24
Finished May 05 02:36:00 PM PDT 24
Peak memory 208448 kb
Host smart-f9a9fc78-b991-47de-b5e8-2d63069ca474
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083220531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.2083220531
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.2761425021
Short name T723
Test name
Test status
Simulation time 429241235 ps
CPU time 3.61 seconds
Started May 05 02:34:49 PM PDT 24
Finished May 05 02:34:53 PM PDT 24
Peak memory 208392 kb
Host smart-5a84c8bc-8d6d-4eab-b072-5f557f0eb16d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761425021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.2761425021
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.3607565175
Short name T685
Test name
Test status
Simulation time 898801265 ps
CPU time 27.99 seconds
Started May 05 02:34:52 PM PDT 24
Finished May 05 02:35:20 PM PDT 24
Peak memory 210000 kb
Host smart-6609aa07-cda2-4803-ad8a-3f4f63a44dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607565175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.3607565175
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.2379334553
Short name T802
Test name
Test status
Simulation time 102329211 ps
CPU time 3.55 seconds
Started May 05 02:34:46 PM PDT 24
Finished May 05 02:34:50 PM PDT 24
Peak memory 208256 kb
Host smart-288ddbf0-8cc3-46fa-80b6-59f255e06b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379334553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.2379334553
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.3761056097
Short name T886
Test name
Test status
Simulation time 7451304512 ps
CPU time 34.28 seconds
Started May 05 02:34:55 PM PDT 24
Finished May 05 02:35:29 PM PDT 24
Peak memory 216936 kb
Host smart-3333a879-d961-49f2-b6b5-38c0082db7a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761056097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.3761056097
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.3864742965
Short name T474
Test name
Test status
Simulation time 416652488 ps
CPU time 4.47 seconds
Started May 05 02:34:51 PM PDT 24
Finished May 05 02:34:56 PM PDT 24
Peak memory 208808 kb
Host smart-8aa47ab2-190d-417d-9ffd-f5f0abdadfaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864742965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.3864742965
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.1153940525
Short name T128
Test name
Test status
Simulation time 179785586 ps
CPU time 1.42 seconds
Started May 05 02:34:54 PM PDT 24
Finished May 05 02:34:56 PM PDT 24
Peak memory 209428 kb
Host smart-ce20699b-2425-455c-8be6-bf367b845980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153940525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.1153940525
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.2752757386
Short name T640
Test name
Test status
Simulation time 37132814 ps
CPU time 0.69 seconds
Started May 05 02:35:09 PM PDT 24
Finished May 05 02:35:10 PM PDT 24
Peak memory 205656 kb
Host smart-2654c135-8495-47c2-ab64-eecb561acf36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752757386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.2752757386
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.3881600770
Short name T36
Test name
Test status
Simulation time 188087208 ps
CPU time 3.2 seconds
Started May 05 02:34:58 PM PDT 24
Finished May 05 02:35:02 PM PDT 24
Peak memory 210360 kb
Host smart-e070b98c-ba3b-4e84-8592-4fb2d246e140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881600770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.3881600770
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.3681235859
Short name T873
Test name
Test status
Simulation time 30464672 ps
CPU time 1.63 seconds
Started May 05 02:34:58 PM PDT 24
Finished May 05 02:35:00 PM PDT 24
Peak memory 214316 kb
Host smart-ba68b86a-c98d-48c5-a309-383b5fe281a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681235859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.3681235859
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.268943276
Short name T626
Test name
Test status
Simulation time 230705109 ps
CPU time 6.2 seconds
Started May 05 02:34:57 PM PDT 24
Finished May 05 02:35:04 PM PDT 24
Peak memory 209528 kb
Host smart-3e20382d-a183-48ff-8124-17e9e2025a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268943276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.268943276
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.3995254070
Short name T7
Test name
Test status
Simulation time 686283437 ps
CPU time 2.99 seconds
Started May 05 02:34:58 PM PDT 24
Finished May 05 02:35:02 PM PDT 24
Peak memory 208888 kb
Host smart-a14828fc-9e3b-4707-a0ea-59079ae99de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995254070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.3995254070
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.3573028163
Short name T287
Test name
Test status
Simulation time 121706908 ps
CPU time 5.6 seconds
Started May 05 02:34:56 PM PDT 24
Finished May 05 02:35:02 PM PDT 24
Peak memory 218444 kb
Host smart-67ca4d12-3b5f-42e3-9edf-5218107d8cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573028163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.3573028163
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.4105251742
Short name T303
Test name
Test status
Simulation time 136934217 ps
CPU time 3.24 seconds
Started May 05 02:34:56 PM PDT 24
Finished May 05 02:35:00 PM PDT 24
Peak memory 208276 kb
Host smart-22dfc5c2-7fa2-4795-a8b6-5e8f01a4bb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105251742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.4105251742
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.1434026609
Short name T457
Test name
Test status
Simulation time 118340661 ps
CPU time 2.35 seconds
Started May 05 02:34:54 PM PDT 24
Finished May 05 02:34:57 PM PDT 24
Peak memory 208508 kb
Host smart-840c74f4-a13b-4c28-b339-9c1c3ca4810b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434026609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.1434026609
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.2200391113
Short name T377
Test name
Test status
Simulation time 40770451 ps
CPU time 2.6 seconds
Started May 05 02:34:55 PM PDT 24
Finished May 05 02:34:58 PM PDT 24
Peak memory 206736 kb
Host smart-412ce7fb-3f95-4143-92a0-d9c01a823683
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200391113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.2200391113
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.55678381
Short name T791
Test name
Test status
Simulation time 194942671 ps
CPU time 2.75 seconds
Started May 05 02:34:58 PM PDT 24
Finished May 05 02:35:01 PM PDT 24
Peak memory 206752 kb
Host smart-f876de3e-80d5-46fd-9f9d-89ef69323b11
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55678381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.55678381
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.780582925
Short name T478
Test name
Test status
Simulation time 34525081 ps
CPU time 2.5 seconds
Started May 05 02:34:59 PM PDT 24
Finished May 05 02:35:02 PM PDT 24
Peak memory 207252 kb
Host smart-a11a0d7a-2975-4231-95a2-583d03a8d0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780582925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.780582925
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.687587537
Short name T444
Test name
Test status
Simulation time 280762235 ps
CPU time 3.01 seconds
Started May 05 02:34:54 PM PDT 24
Finished May 05 02:34:58 PM PDT 24
Peak memory 206556 kb
Host smart-8d757a81-7fa7-463e-be07-c699963b31c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687587537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.687587537
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.2603970493
Short name T9
Test name
Test status
Simulation time 208072424 ps
CPU time 13.4 seconds
Started May 05 02:35:03 PM PDT 24
Finished May 05 02:35:17 PM PDT 24
Peak memory 220484 kb
Host smart-b4e963d7-22f1-46b5-8f5d-1b648802eb4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603970493 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.2603970493
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.3612701318
Short name T580
Test name
Test status
Simulation time 108771922 ps
CPU time 2.36 seconds
Started May 05 02:34:59 PM PDT 24
Finished May 05 02:35:02 PM PDT 24
Peak memory 207944 kb
Host smart-2398657d-a8ca-499d-a23a-dbd6e957ad7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612701318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.3612701318
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.1254781195
Short name T887
Test name
Test status
Simulation time 13869046 ps
CPU time 0.91 seconds
Started May 05 02:35:07 PM PDT 24
Finished May 05 02:35:08 PM PDT 24
Peak memory 206056 kb
Host smart-665c69fc-01f3-4ff2-b6f7-8793e5f46b13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254781195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.1254781195
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.3049735013
Short name T414
Test name
Test status
Simulation time 83913647 ps
CPU time 3.32 seconds
Started May 05 02:35:05 PM PDT 24
Finished May 05 02:35:09 PM PDT 24
Peak memory 215104 kb
Host smart-6024f72a-ca6d-482c-8e70-577bf13a1f90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3049735013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.3049735013
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.4240181060
Short name T754
Test name
Test status
Simulation time 80089558 ps
CPU time 3.6 seconds
Started May 05 02:35:07 PM PDT 24
Finished May 05 02:35:11 PM PDT 24
Peak memory 209996 kb
Host smart-982d0069-3f69-4007-8409-811a01a3afab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240181060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.4240181060
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.980076129
Short name T400
Test name
Test status
Simulation time 2760462623 ps
CPU time 9.83 seconds
Started May 05 02:35:02 PM PDT 24
Finished May 05 02:35:12 PM PDT 24
Peak memory 208800 kb
Host smart-f3aa6acd-0eb2-471c-871a-147a4e4c925f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980076129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.980076129
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.1069882291
Short name T237
Test name
Test status
Simulation time 66592989 ps
CPU time 3.7 seconds
Started May 05 02:35:09 PM PDT 24
Finished May 05 02:35:13 PM PDT 24
Peak memory 209108 kb
Host smart-a7887863-2553-4ec7-9c03-47dcf5b4c015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069882291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.1069882291
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.3975280808
Short name T346
Test name
Test status
Simulation time 133254338 ps
CPU time 2.78 seconds
Started May 05 02:35:03 PM PDT 24
Finished May 05 02:35:06 PM PDT 24
Peak memory 214128 kb
Host smart-4eb9a98b-20ef-47b7-b7af-ad3d6c0d64af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975280808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.3975280808
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.1571608994
Short name T104
Test name
Test status
Simulation time 114710998 ps
CPU time 3.27 seconds
Started May 05 02:35:03 PM PDT 24
Finished May 05 02:35:07 PM PDT 24
Peak memory 208788 kb
Host smart-e6e3484f-aa38-4deb-8775-35026353138b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571608994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.1571608994
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.399953096
Short name T371
Test name
Test status
Simulation time 177180931 ps
CPU time 5.62 seconds
Started May 05 02:35:03 PM PDT 24
Finished May 05 02:35:09 PM PDT 24
Peak memory 218140 kb
Host smart-349a9792-bb7a-4551-8767-92dcde1aaa68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399953096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.399953096
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.2418180082
Short name T642
Test name
Test status
Simulation time 194820564 ps
CPU time 7.27 seconds
Started May 05 02:35:05 PM PDT 24
Finished May 05 02:35:12 PM PDT 24
Peak memory 208460 kb
Host smart-c3e05abb-8abd-49ef-831e-0af0764bbabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418180082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.2418180082
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.2333416740
Short name T861
Test name
Test status
Simulation time 6580474315 ps
CPU time 74.65 seconds
Started May 05 02:35:03 PM PDT 24
Finished May 05 02:36:18 PM PDT 24
Peak memory 208648 kb
Host smart-aac55e56-0725-4a16-b9c5-39bf36232abd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333416740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.2333416740
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.568656680
Short name T5
Test name
Test status
Simulation time 174700775 ps
CPU time 1.91 seconds
Started May 05 02:35:01 PM PDT 24
Finished May 05 02:35:03 PM PDT 24
Peak memory 207416 kb
Host smart-19e2f747-d678-4c89-9412-754c14a0fe8e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568656680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.568656680
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.2978479639
Short name T516
Test name
Test status
Simulation time 33878481 ps
CPU time 2.64 seconds
Started May 05 02:35:06 PM PDT 24
Finished May 05 02:35:09 PM PDT 24
Peak memory 206976 kb
Host smart-d7f5f31c-7e05-4789-bfd2-946ba068093c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978479639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.2978479639
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.2703137384
Short name T882
Test name
Test status
Simulation time 71230077 ps
CPU time 3.19 seconds
Started May 05 02:35:06 PM PDT 24
Finished May 05 02:35:10 PM PDT 24
Peak memory 208568 kb
Host smart-78414393-8850-4e34-84e1-c3b769627eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703137384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.2703137384
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.2666764662
Short name T700
Test name
Test status
Simulation time 873524365 ps
CPU time 5.87 seconds
Started May 05 02:35:02 PM PDT 24
Finished May 05 02:35:08 PM PDT 24
Peak memory 208476 kb
Host smart-82600173-3897-4f93-ad58-680757ad7952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666764662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.2666764662
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.1139434336
Short name T191
Test name
Test status
Simulation time 2651105630 ps
CPU time 31.12 seconds
Started May 05 02:35:08 PM PDT 24
Finished May 05 02:35:39 PM PDT 24
Peak memory 216740 kb
Host smart-1786ae89-e162-451d-a264-e9c80a4ae1e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139434336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.1139434336
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.1892121930
Short name T522
Test name
Test status
Simulation time 981260687 ps
CPU time 11.03 seconds
Started May 05 02:35:06 PM PDT 24
Finished May 05 02:35:17 PM PDT 24
Peak memory 220680 kb
Host smart-b3ea4bf1-1504-4434-ade7-84490baf94f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892121930 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.1892121930
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.918741074
Short name T188
Test name
Test status
Simulation time 321780620 ps
CPU time 4.76 seconds
Started May 05 02:35:02 PM PDT 24
Finished May 05 02:35:07 PM PDT 24
Peak memory 207604 kb
Host smart-1e3a4047-97c2-4a51-a12f-13963a3ed340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918741074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.918741074
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.2317646947
Short name T636
Test name
Test status
Simulation time 2278131504 ps
CPU time 22.48 seconds
Started May 05 02:35:07 PM PDT 24
Finished May 05 02:35:30 PM PDT 24
Peak memory 210508 kb
Host smart-03e336ec-9f1f-4473-a2a0-1331ff2c10c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317646947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.2317646947
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.62731530
Short name T598
Test name
Test status
Simulation time 103667045 ps
CPU time 0.81 seconds
Started May 05 02:35:19 PM PDT 24
Finished May 05 02:35:21 PM PDT 24
Peak memory 205840 kb
Host smart-fd9bc022-a7b2-4e6a-b8c8-55d78a7542c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62731530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.62731530
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.868409136
Short name T126
Test name
Test status
Simulation time 38374439 ps
CPU time 2.92 seconds
Started May 05 02:35:05 PM PDT 24
Finished May 05 02:35:09 PM PDT 24
Peak memory 215160 kb
Host smart-4f68c388-d5f5-4308-8159-9f0aa51265bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=868409136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.868409136
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.4050348164
Short name T64
Test name
Test status
Simulation time 32021266 ps
CPU time 2.27 seconds
Started May 05 02:35:11 PM PDT 24
Finished May 05 02:35:14 PM PDT 24
Peak memory 214324 kb
Host smart-63e08d33-4f60-4dfd-9556-d36d8b05e1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050348164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.4050348164
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.754938930
Short name T92
Test name
Test status
Simulation time 88891712 ps
CPU time 3.31 seconds
Started May 05 02:35:13 PM PDT 24
Finished May 05 02:35:17 PM PDT 24
Peak memory 220956 kb
Host smart-b75daaec-adbf-43b5-9881-5d87bad47ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754938930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.754938930
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.636736281
Short name T143
Test name
Test status
Simulation time 106446384 ps
CPU time 4.94 seconds
Started May 05 02:35:15 PM PDT 24
Finished May 05 02:35:20 PM PDT 24
Peak memory 209420 kb
Host smart-860a88b5-f294-4295-b569-efe81211c058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636736281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.636736281
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.1385270817
Short name T867
Test name
Test status
Simulation time 372963958 ps
CPU time 4.44 seconds
Started May 05 02:35:08 PM PDT 24
Finished May 05 02:35:13 PM PDT 24
Peak memory 209880 kb
Host smart-6e302119-085f-4c8e-939c-5aa24d0154ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385270817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.1385270817
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.598352170
Short name T380
Test name
Test status
Simulation time 485123149 ps
CPU time 7.13 seconds
Started May 05 02:35:08 PM PDT 24
Finished May 05 02:35:15 PM PDT 24
Peak memory 208668 kb
Host smart-eb2e404e-e2d1-41b0-af0c-76fa5a021f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598352170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.598352170
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.2374354160
Short name T199
Test name
Test status
Simulation time 23234652 ps
CPU time 1.92 seconds
Started May 05 02:35:08 PM PDT 24
Finished May 05 02:35:10 PM PDT 24
Peak memory 208620 kb
Host smart-8abf8831-6fee-4b09-97d1-74ad36d11cf6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374354160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.2374354160
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.2788523942
Short name T370
Test name
Test status
Simulation time 62025054 ps
CPU time 3.28 seconds
Started May 05 02:35:06 PM PDT 24
Finished May 05 02:35:10 PM PDT 24
Peak memory 208736 kb
Host smart-f21a1d6b-51f6-49a2-9524-e3f70e0c9703
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788523942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.2788523942
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.2853498673
Short name T470
Test name
Test status
Simulation time 136621776 ps
CPU time 3.45 seconds
Started May 05 02:35:07 PM PDT 24
Finished May 05 02:35:11 PM PDT 24
Peak memory 208144 kb
Host smart-b20bfc7c-1aea-4c5f-affb-5252e1d09389
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853498673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.2853498673
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.2920318459
Short name T489
Test name
Test status
Simulation time 680681148 ps
CPU time 10.9 seconds
Started May 05 02:35:12 PM PDT 24
Finished May 05 02:35:23 PM PDT 24
Peak memory 208848 kb
Host smart-e522295e-da31-4eed-af26-6a7a5849ec45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920318459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.2920318459
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.3257809007
Short name T402
Test name
Test status
Simulation time 306931304 ps
CPU time 3.94 seconds
Started May 05 02:35:07 PM PDT 24
Finished May 05 02:35:12 PM PDT 24
Peak memory 206720 kb
Host smart-14e93f9f-71d0-41d8-a95d-2ba828b0beec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257809007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.3257809007
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.918985187
Short name T639
Test name
Test status
Simulation time 334452187 ps
CPU time 9.33 seconds
Started May 05 02:35:22 PM PDT 24
Finished May 05 02:35:31 PM PDT 24
Peak memory 215412 kb
Host smart-e53a47fa-cf68-4c49-bb8d-65057e2a337c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918985187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.918985187
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.300198964
Short name T742
Test name
Test status
Simulation time 464076525 ps
CPU time 7.77 seconds
Started May 05 02:35:16 PM PDT 24
Finished May 05 02:35:24 PM PDT 24
Peak memory 222524 kb
Host smart-6647d23a-4923-4f68-bd11-a0065c6c4d2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300198964 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.300198964
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.2205827734
Short name T911
Test name
Test status
Simulation time 84409413 ps
CPU time 3.93 seconds
Started May 05 02:35:12 PM PDT 24
Finished May 05 02:35:16 PM PDT 24
Peak memory 208120 kb
Host smart-e0f3cb6c-698d-4100-a723-cb041a6f0a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205827734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.2205827734
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.2848843169
Short name T45
Test name
Test status
Simulation time 104944294 ps
CPU time 3.92 seconds
Started May 05 02:35:12 PM PDT 24
Finished May 05 02:35:16 PM PDT 24
Peak memory 210292 kb
Host smart-8837a4b9-2cea-4ad5-ba9d-f8aa2172d38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848843169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.2848843169
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.3052866878
Short name T664
Test name
Test status
Simulation time 10520180 ps
CPU time 0.82 seconds
Started May 05 02:30:12 PM PDT 24
Finished May 05 02:30:13 PM PDT 24
Peak memory 205824 kb
Host smart-bc4c97a2-dab6-4030-b1d8-566817cd0bd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052866878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.3052866878
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.3468777295
Short name T242
Test name
Test status
Simulation time 32196082 ps
CPU time 2.67 seconds
Started May 05 02:30:09 PM PDT 24
Finished May 05 02:30:12 PM PDT 24
Peak memory 214276 kb
Host smart-29b1a94e-b584-4ff4-bf9d-4df76e106600
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3468777295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.3468777295
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.2861168042
Short name T106
Test name
Test status
Simulation time 208372326 ps
CPU time 1.67 seconds
Started May 05 02:30:06 PM PDT 24
Finished May 05 02:30:08 PM PDT 24
Peak memory 208208 kb
Host smart-d40ecb99-2664-4540-9283-480776dcc7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861168042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.2861168042
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.319538172
Short name T808
Test name
Test status
Simulation time 1215937301 ps
CPU time 8.95 seconds
Started May 05 02:30:13 PM PDT 24
Finished May 05 02:30:22 PM PDT 24
Peak memory 219204 kb
Host smart-24cfe2bd-0471-476c-a6be-c6eb33d3b166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319538172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.319538172
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.3161411461
Short name T543
Test name
Test status
Simulation time 174400055 ps
CPU time 4.44 seconds
Started May 05 02:30:13 PM PDT 24
Finished May 05 02:30:18 PM PDT 24
Peak memory 222372 kb
Host smart-b3fa7fa3-8fd0-4de5-ad85-00ef0201f0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161411461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.3161411461
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.161650429
Short name T496
Test name
Test status
Simulation time 74941896 ps
CPU time 2.61 seconds
Started May 05 02:30:08 PM PDT 24
Finished May 05 02:30:12 PM PDT 24
Peak memory 214264 kb
Host smart-d4af51a9-d606-465c-807e-612e0647de31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161650429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.161650429
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.1033047897
Short name T209
Test name
Test status
Simulation time 444461594 ps
CPU time 5.56 seconds
Started May 05 02:30:08 PM PDT 24
Finished May 05 02:30:14 PM PDT 24
Peak memory 214292 kb
Host smart-3c82d565-1c9f-4fad-a957-6673b7341731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033047897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.1033047897
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sideload.4125584277
Short name T801
Test name
Test status
Simulation time 3646203045 ps
CPU time 64.56 seconds
Started May 05 02:30:08 PM PDT 24
Finished May 05 02:31:13 PM PDT 24
Peak memory 208432 kb
Host smart-3413d480-9e2a-481b-8212-6d0f647fc1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125584277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.4125584277
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.4144076510
Short name T568
Test name
Test status
Simulation time 193692454 ps
CPU time 1.89 seconds
Started May 05 02:30:08 PM PDT 24
Finished May 05 02:30:10 PM PDT 24
Peak memory 208556 kb
Host smart-01dbf754-531f-481a-bab2-e8f220e19e8c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144076510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.4144076510
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.2985231063
Short name T726
Test name
Test status
Simulation time 103318663 ps
CPU time 4.16 seconds
Started May 05 02:30:08 PM PDT 24
Finished May 05 02:30:13 PM PDT 24
Peak memory 206544 kb
Host smart-b5af5c0b-3518-48b3-826e-a413babf1ec7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985231063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.2985231063
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.1214055130
Short name T519
Test name
Test status
Simulation time 103340774 ps
CPU time 3.56 seconds
Started May 05 02:30:08 PM PDT 24
Finished May 05 02:30:12 PM PDT 24
Peak memory 208480 kb
Host smart-820d67ef-63cf-43d2-abeb-4a72531b397c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214055130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.1214055130
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.3163848412
Short name T662
Test name
Test status
Simulation time 173936450 ps
CPU time 3.54 seconds
Started May 05 02:30:19 PM PDT 24
Finished May 05 02:30:23 PM PDT 24
Peak memory 209500 kb
Host smart-b0acc2c6-0148-4b1a-8102-f1fbc524e86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163848412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.3163848412
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.294980933
Short name T703
Test name
Test status
Simulation time 39155525 ps
CPU time 2.4 seconds
Started May 05 02:30:01 PM PDT 24
Finished May 05 02:30:04 PM PDT 24
Peak memory 206648 kb
Host smart-f9ceff85-1537-4e67-88f6-574ebebad472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294980933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.294980933
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.3257408703
Short name T850
Test name
Test status
Simulation time 18964821925 ps
CPU time 421.38 seconds
Started May 05 02:30:19 PM PDT 24
Finished May 05 02:37:20 PM PDT 24
Peak memory 222528 kb
Host smart-9ce35c8e-e360-4efd-91b8-47f93ba8b582
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257408703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.3257408703
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.4031168668
Short name T677
Test name
Test status
Simulation time 438143377 ps
CPU time 9.8 seconds
Started May 05 02:30:19 PM PDT 24
Finished May 05 02:30:29 PM PDT 24
Peak memory 222656 kb
Host smart-bfdf4ff3-2de1-43d1-9266-8ffd4e9dafaf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031168668 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.4031168668
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.544125271
Short name T585
Test name
Test status
Simulation time 1405490512 ps
CPU time 13.86 seconds
Started May 05 02:30:08 PM PDT 24
Finished May 05 02:30:22 PM PDT 24
Peak memory 208580 kb
Host smart-a4c80931-a357-432c-88c9-9cb6046c24a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544125271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.544125271
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.2398691347
Short name T896
Test name
Test status
Simulation time 447447095 ps
CPU time 1.95 seconds
Started May 05 02:30:12 PM PDT 24
Finished May 05 02:30:15 PM PDT 24
Peak memory 209864 kb
Host smart-067757cf-8a16-4713-ab2d-9c2cfc94f8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398691347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.2398691347
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.1380768077
Short name T465
Test name
Test status
Simulation time 12435751 ps
CPU time 0.72 seconds
Started May 05 02:35:21 PM PDT 24
Finished May 05 02:35:22 PM PDT 24
Peak memory 205832 kb
Host smart-108e2edd-770f-4634-a6cd-c171e6288f1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380768077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.1380768077
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.129030591
Short name T889
Test name
Test status
Simulation time 332907322 ps
CPU time 11.93 seconds
Started May 05 02:35:16 PM PDT 24
Finished May 05 02:35:28 PM PDT 24
Peak memory 214876 kb
Host smart-a4d43d79-0bca-4283-8c47-f6dd30e32abd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=129030591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.129030591
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.2554918732
Short name T770
Test name
Test status
Simulation time 509563478 ps
CPU time 5.3 seconds
Started May 05 02:35:17 PM PDT 24
Finished May 05 02:35:23 PM PDT 24
Peak memory 219332 kb
Host smart-776815b9-9537-4138-889b-ef29d222c6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554918732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.2554918732
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.2858434415
Short name T532
Test name
Test status
Simulation time 279140106 ps
CPU time 5.74 seconds
Started May 05 02:35:22 PM PDT 24
Finished May 05 02:35:28 PM PDT 24
Peak memory 214268 kb
Host smart-90c32a7b-4424-4b73-8f38-90cdd70fafc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858434415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.2858434415
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.3054256372
Short name T93
Test name
Test status
Simulation time 154788362 ps
CPU time 6.57 seconds
Started May 05 02:35:17 PM PDT 24
Finished May 05 02:35:24 PM PDT 24
Peak memory 214304 kb
Host smart-c2bdb1d2-e5ce-4ce1-bd17-c8c557d7060f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054256372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.3054256372
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.184649031
Short name T252
Test name
Test status
Simulation time 290324449 ps
CPU time 3.13 seconds
Started May 05 02:35:20 PM PDT 24
Finished May 05 02:35:24 PM PDT 24
Peak memory 211204 kb
Host smart-6bba5d3d-a664-49e4-b69f-8afaae0a512d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184649031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.184649031
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.849391334
Short name T819
Test name
Test status
Simulation time 642400956 ps
CPU time 3.81 seconds
Started May 05 02:35:18 PM PDT 24
Finished May 05 02:35:22 PM PDT 24
Peak memory 214248 kb
Host smart-8d3cc962-926b-413a-a93e-b0e2a51d584d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849391334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.849391334
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.2804880871
Short name T603
Test name
Test status
Simulation time 271574170 ps
CPU time 6.66 seconds
Started May 05 02:35:16 PM PDT 24
Finished May 05 02:35:23 PM PDT 24
Peak memory 209592 kb
Host smart-ba2925a6-d19a-4ab4-8c94-4610c36fd6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804880871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.2804880871
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.2691708451
Short name T652
Test name
Test status
Simulation time 79549895 ps
CPU time 2.98 seconds
Started May 05 02:35:18 PM PDT 24
Finished May 05 02:35:22 PM PDT 24
Peak memory 208688 kb
Host smart-3ec26c05-0d2b-4412-ba01-af091bfc0b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691708451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.2691708451
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.762157858
Short name T599
Test name
Test status
Simulation time 174055098 ps
CPU time 4.39 seconds
Started May 05 02:35:18 PM PDT 24
Finished May 05 02:35:22 PM PDT 24
Peak memory 208108 kb
Host smart-cb70d053-f9d1-4d70-bf78-bdcab9202d21
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762157858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.762157858
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.3500535335
Short name T265
Test name
Test status
Simulation time 208347741 ps
CPU time 8.54 seconds
Started May 05 02:35:19 PM PDT 24
Finished May 05 02:35:28 PM PDT 24
Peak memory 207884 kb
Host smart-bb6c1ef0-2755-4905-99ab-5918cee649f7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500535335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.3500535335
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.4163132896
Short name T681
Test name
Test status
Simulation time 265425385 ps
CPU time 3.56 seconds
Started May 05 02:35:17 PM PDT 24
Finished May 05 02:35:21 PM PDT 24
Peak memory 206792 kb
Host smart-ffbf1253-5c62-4f9a-b71f-e0089b22c20e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163132896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.4163132896
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.2377837823
Short name T195
Test name
Test status
Simulation time 381454145 ps
CPU time 4.82 seconds
Started May 05 02:35:16 PM PDT 24
Finished May 05 02:35:21 PM PDT 24
Peak memory 208108 kb
Host smart-861c5140-2873-4dcf-82ac-611a1994fc71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377837823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.2377837823
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.990082581
Short name T441
Test name
Test status
Simulation time 450992105 ps
CPU time 2.98 seconds
Started May 05 02:35:18 PM PDT 24
Finished May 05 02:35:22 PM PDT 24
Peak memory 208400 kb
Host smart-a9456cdf-25c9-463e-9f2d-f855cc7e6738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990082581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.990082581
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.3837400628
Short name T267
Test name
Test status
Simulation time 2456829480 ps
CPU time 22.99 seconds
Started May 05 02:35:22 PM PDT 24
Finished May 05 02:35:46 PM PDT 24
Peak memory 221140 kb
Host smart-0e03ab27-cbe3-46d9-8cb0-d2717634a609
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837400628 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.3837400628
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.3424791985
Short name T879
Test name
Test status
Simulation time 1015636721 ps
CPU time 8.51 seconds
Started May 05 02:35:18 PM PDT 24
Finished May 05 02:35:27 PM PDT 24
Peak memory 214252 kb
Host smart-ca8f4766-9e59-4275-9c69-d1efcc385e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424791985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.3424791985
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.1189170624
Short name T828
Test name
Test status
Simulation time 165079406 ps
CPU time 1.61 seconds
Started May 05 02:35:20 PM PDT 24
Finished May 05 02:35:22 PM PDT 24
Peak memory 209336 kb
Host smart-0f36a378-fb35-4225-835d-1fdbd6f6a03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189170624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.1189170624
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.3905125113
Short name T771
Test name
Test status
Simulation time 15181969 ps
CPU time 0.94 seconds
Started May 05 02:35:29 PM PDT 24
Finished May 05 02:35:30 PM PDT 24
Peak memory 206156 kb
Host smart-40d55831-4d8b-4cfe-a082-090bcd709a66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905125113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.3905125113
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.4293147252
Short name T823
Test name
Test status
Simulation time 117821585 ps
CPU time 4.09 seconds
Started May 05 02:35:33 PM PDT 24
Finished May 05 02:35:38 PM PDT 24
Peak memory 221028 kb
Host smart-64818cc6-7dd5-4c5f-86f7-0425e3a8398e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293147252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.4293147252
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.228132391
Short name T615
Test name
Test status
Simulation time 153816759 ps
CPU time 2.3 seconds
Started May 05 02:35:33 PM PDT 24
Finished May 05 02:35:36 PM PDT 24
Peak memory 209660 kb
Host smart-b0f61f84-431d-4108-bf6b-b01c9ae6bfd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228132391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.228132391
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.1454655175
Short name T24
Test name
Test status
Simulation time 6175275601 ps
CPU time 35.51 seconds
Started May 05 02:35:35 PM PDT 24
Finished May 05 02:36:11 PM PDT 24
Peak memory 214372 kb
Host smart-da7ca0de-8ffe-43af-b2e0-f706dbb005ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454655175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.1454655175
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.2606736849
Short name T293
Test name
Test status
Simulation time 112178720 ps
CPU time 3.59 seconds
Started May 05 02:35:27 PM PDT 24
Finished May 05 02:35:31 PM PDT 24
Peak memory 214176 kb
Host smart-ac617484-1d14-4e86-89ee-d726d38d1a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606736849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.2606736849
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.1408343324
Short name T417
Test name
Test status
Simulation time 166673981 ps
CPU time 3.73 seconds
Started May 05 02:35:27 PM PDT 24
Finished May 05 02:35:31 PM PDT 24
Peak memory 219988 kb
Host smart-b3eace37-3d2d-4f34-a18e-fb365881a516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408343324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.1408343324
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.3634599449
Short name T301
Test name
Test status
Simulation time 110983696 ps
CPU time 5.23 seconds
Started May 05 02:35:22 PM PDT 24
Finished May 05 02:35:28 PM PDT 24
Peak memory 207248 kb
Host smart-e18e4178-b7ed-4fad-af5b-4904fca2b62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634599449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.3634599449
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.941578613
Short name T488
Test name
Test status
Simulation time 919032907 ps
CPU time 7.35 seconds
Started May 05 02:35:23 PM PDT 24
Finished May 05 02:35:31 PM PDT 24
Peak memory 207644 kb
Host smart-8f0abf63-0a1a-43d6-8d89-5b70d2a67162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941578613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.941578613
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.2835463368
Short name T479
Test name
Test status
Simulation time 270252337 ps
CPU time 1.9 seconds
Started May 05 02:35:21 PM PDT 24
Finished May 05 02:35:23 PM PDT 24
Peak memory 207208 kb
Host smart-114b78ea-d0ed-477f-8ddd-dc53d4516867
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835463368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.2835463368
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.3794173313
Short name T712
Test name
Test status
Simulation time 76563177 ps
CPU time 2.63 seconds
Started May 05 02:35:21 PM PDT 24
Finished May 05 02:35:24 PM PDT 24
Peak memory 208780 kb
Host smart-d7a15459-33d1-4f9c-ae99-0bc7f2853b1a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794173313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.3794173313
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.2711169922
Short name T891
Test name
Test status
Simulation time 198463303 ps
CPU time 2.49 seconds
Started May 05 02:35:22 PM PDT 24
Finished May 05 02:35:25 PM PDT 24
Peak memory 208564 kb
Host smart-f712aa75-e81a-4d43-8dca-b48539ccfd26
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711169922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.2711169922
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.2040808722
Short name T511
Test name
Test status
Simulation time 78297456 ps
CPU time 1.86 seconds
Started May 05 02:35:28 PM PDT 24
Finished May 05 02:35:30 PM PDT 24
Peak memory 215024 kb
Host smart-61d767fc-62df-4e8a-a42a-162e52ba10c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040808722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.2040808722
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.2956035208
Short name T492
Test name
Test status
Simulation time 338397490 ps
CPU time 9.9 seconds
Started May 05 02:35:22 PM PDT 24
Finished May 05 02:35:32 PM PDT 24
Peak memory 208292 kb
Host smart-19a13e26-eb8e-4a1f-9eaf-f07a54196613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956035208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.2956035208
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.1255326407
Short name T235
Test name
Test status
Simulation time 1378541985 ps
CPU time 46.53 seconds
Started May 05 02:35:27 PM PDT 24
Finished May 05 02:36:14 PM PDT 24
Peak memory 216456 kb
Host smart-5b0e352c-ef5c-4af4-bb41-0af4b0262ce7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255326407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.1255326407
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.3320159347
Short name T570
Test name
Test status
Simulation time 465652946 ps
CPU time 5.75 seconds
Started May 05 02:35:28 PM PDT 24
Finished May 05 02:35:34 PM PDT 24
Peak memory 207992 kb
Host smart-05e7d9c2-095b-4dc1-baf2-396dd0502fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320159347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.3320159347
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.4010953686
Short name T475
Test name
Test status
Simulation time 124581745 ps
CPU time 2.12 seconds
Started May 05 02:35:27 PM PDT 24
Finished May 05 02:35:30 PM PDT 24
Peak memory 209864 kb
Host smart-64cdd980-48a8-4f55-8f6d-e4a181fc4ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010953686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.4010953686
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.1702216939
Short name T606
Test name
Test status
Simulation time 9261459 ps
CPU time 0.72 seconds
Started May 05 02:35:36 PM PDT 24
Finished May 05 02:35:37 PM PDT 24
Peak memory 205892 kb
Host smart-a7ebceaa-5ff2-4905-bdf7-a439fce4ad32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702216939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.1702216939
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.2441338395
Short name T413
Test name
Test status
Simulation time 1672768279 ps
CPU time 42.01 seconds
Started May 05 02:35:34 PM PDT 24
Finished May 05 02:36:16 PM PDT 24
Peak memory 222384 kb
Host smart-42cd08d5-d1b3-4364-a1e3-2fa7003c906a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2441338395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.2441338395
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.3747396280
Short name T419
Test name
Test status
Simulation time 212820733 ps
CPU time 2.19 seconds
Started May 05 02:35:34 PM PDT 24
Finished May 05 02:35:37 PM PDT 24
Peak memory 206708 kb
Host smart-8e67e113-6203-4083-b970-bf719bcea95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747396280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.3747396280
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.810383195
Short name T345
Test name
Test status
Simulation time 34356017 ps
CPU time 2.2 seconds
Started May 05 02:35:32 PM PDT 24
Finished May 05 02:35:35 PM PDT 24
Peak memory 214308 kb
Host smart-b7dcaf04-2c04-4656-9fa9-f172ef3dc391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810383195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.810383195
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.91720797
Short name T361
Test name
Test status
Simulation time 111287738 ps
CPU time 5.26 seconds
Started May 05 02:35:37 PM PDT 24
Finished May 05 02:35:43 PM PDT 24
Peak memory 214140 kb
Host smart-81ec29a8-aa11-4402-a741-3f28980b6fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91720797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.91720797
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.2199345245
Short name T232
Test name
Test status
Simulation time 42389743 ps
CPU time 2.99 seconds
Started May 05 02:35:34 PM PDT 24
Finished May 05 02:35:37 PM PDT 24
Peak memory 209440 kb
Host smart-8cd48e3c-f4aa-4719-b3ba-714bb89ad0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199345245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.2199345245
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.1257590639
Short name T356
Test name
Test status
Simulation time 717026960 ps
CPU time 4.25 seconds
Started May 05 02:35:33 PM PDT 24
Finished May 05 02:35:38 PM PDT 24
Peak memory 206972 kb
Host smart-4bf5d57e-9f18-469d-8042-a3e494379dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257590639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.1257590639
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.3198065627
Short name T300
Test name
Test status
Simulation time 139397848 ps
CPU time 4.61 seconds
Started May 05 02:35:32 PM PDT 24
Finished May 05 02:35:37 PM PDT 24
Peak memory 207716 kb
Host smart-fbc4753a-354a-457a-96d1-3ffce9ac1e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198065627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.3198065627
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.4156592159
Short name T507
Test name
Test status
Simulation time 166446520 ps
CPU time 3.21 seconds
Started May 05 02:35:32 PM PDT 24
Finished May 05 02:35:35 PM PDT 24
Peak memory 208828 kb
Host smart-e228034c-6435-4b87-a870-97ca50714c2f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156592159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.4156592159
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.6520485
Short name T893
Test name
Test status
Simulation time 306856479 ps
CPU time 6.13 seconds
Started May 05 02:35:31 PM PDT 24
Finished May 05 02:35:38 PM PDT 24
Peak memory 207812 kb
Host smart-59989200-acea-4f4b-b134-595d736cdcba
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6520485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.6520485
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.394488780
Short name T500
Test name
Test status
Simulation time 133387587 ps
CPU time 2.43 seconds
Started May 05 02:35:34 PM PDT 24
Finished May 05 02:35:37 PM PDT 24
Peak memory 206716 kb
Host smart-9e6f1241-653b-4ecc-9a57-bd04f8586fb2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394488780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.394488780
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.1485854999
Short name T513
Test name
Test status
Simulation time 33292645 ps
CPU time 1.56 seconds
Started May 05 02:35:36 PM PDT 24
Finished May 05 02:35:38 PM PDT 24
Peak memory 207552 kb
Host smart-255621f5-4b67-40fe-846b-54a8eeae7f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485854999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.1485854999
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.2657801199
Short name T494
Test name
Test status
Simulation time 4472740303 ps
CPU time 27.37 seconds
Started May 05 02:35:35 PM PDT 24
Finished May 05 02:36:02 PM PDT 24
Peak memory 207628 kb
Host smart-2b09181b-e73a-4eaf-819c-38a8d6e3e331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657801199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.2657801199
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.1392360623
Short name T192
Test name
Test status
Simulation time 662759114 ps
CPU time 26.43 seconds
Started May 05 02:35:37 PM PDT 24
Finished May 05 02:36:04 PM PDT 24
Peak memory 216188 kb
Host smart-493e5fa9-1eb8-45fa-bed1-7da9b0684412
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392360623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.1392360623
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.3875861162
Short name T829
Test name
Test status
Simulation time 717727424 ps
CPU time 8.64 seconds
Started May 05 02:35:33 PM PDT 24
Finished May 05 02:35:43 PM PDT 24
Peak memory 207864 kb
Host smart-557b8103-a60e-4928-a4b2-799a6217adb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875861162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.3875861162
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.4115173874
Short name T462
Test name
Test status
Simulation time 9733852 ps
CPU time 0.89 seconds
Started May 05 02:35:46 PM PDT 24
Finished May 05 02:35:47 PM PDT 24
Peak memory 205836 kb
Host smart-e0a89afa-ab23-4be7-8d4c-77dc86c31f6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115173874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.4115173874
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.2023140285
Short name T821
Test name
Test status
Simulation time 44693818 ps
CPU time 3.36 seconds
Started May 05 02:35:44 PM PDT 24
Finished May 05 02:35:48 PM PDT 24
Peak memory 214172 kb
Host smart-00072778-8aac-4530-8b04-2ae1c1bac33c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2023140285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.2023140285
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.4246806329
Short name T696
Test name
Test status
Simulation time 523890213 ps
CPU time 3.38 seconds
Started May 05 02:35:45 PM PDT 24
Finished May 05 02:35:49 PM PDT 24
Peak memory 209948 kb
Host smart-44f00e54-d2d6-403c-a262-ab9083a362ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246806329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.4246806329
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.1411971030
Short name T836
Test name
Test status
Simulation time 498458815 ps
CPU time 15.24 seconds
Started May 05 02:35:41 PM PDT 24
Finished May 05 02:35:57 PM PDT 24
Peak memory 208896 kb
Host smart-0ded91e4-be4f-4d34-8189-a551bc74b250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411971030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.1411971030
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.1215150287
Short name T699
Test name
Test status
Simulation time 156275235 ps
CPU time 3 seconds
Started May 05 02:35:41 PM PDT 24
Finished May 05 02:35:44 PM PDT 24
Peak memory 220584 kb
Host smart-4ef3dfa7-676f-45fa-8ef6-d14ec0d64d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215150287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.1215150287
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.1229216683
Short name T217
Test name
Test status
Simulation time 175564962 ps
CPU time 5.06 seconds
Started May 05 02:35:41 PM PDT 24
Finished May 05 02:35:46 PM PDT 24
Peak memory 208944 kb
Host smart-cb7a83bc-8241-461c-9f92-3edc3aeaa72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229216683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.1229216683
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.3838179726
Short name T853
Test name
Test status
Simulation time 202557968 ps
CPU time 5.56 seconds
Started May 05 02:35:35 PM PDT 24
Finished May 05 02:35:41 PM PDT 24
Peak memory 207876 kb
Host smart-67214b9e-d340-47d1-a144-91659aa32d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838179726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.3838179726
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.2336837354
Short name T446
Test name
Test status
Simulation time 302721772 ps
CPU time 2.84 seconds
Started May 05 02:35:37 PM PDT 24
Finished May 05 02:35:40 PM PDT 24
Peak memory 206692 kb
Host smart-20519fda-5e36-4b12-8199-2a1d35db7f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336837354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.2336837354
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.2833562556
Short name T250
Test name
Test status
Simulation time 635350659 ps
CPU time 4.83 seconds
Started May 05 02:35:35 PM PDT 24
Finished May 05 02:35:40 PM PDT 24
Peak memory 208532 kb
Host smart-eb23e88c-63c6-44b4-afbf-a54988ed9999
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833562556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.2833562556
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.4168302497
Short name T844
Test name
Test status
Simulation time 679673680 ps
CPU time 5.94 seconds
Started May 05 02:35:36 PM PDT 24
Finished May 05 02:35:42 PM PDT 24
Peak memory 208604 kb
Host smart-07ddbdab-7eec-424f-8bc6-f34362baf5a6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168302497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.4168302497
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.1938921261
Short name T784
Test name
Test status
Simulation time 1385713546 ps
CPU time 9.83 seconds
Started May 05 02:35:38 PM PDT 24
Finished May 05 02:35:48 PM PDT 24
Peak memory 208568 kb
Host smart-91f54834-20c9-4ef0-bfbc-0c6632ed8966
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938921261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.1938921261
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.3037829902
Short name T898
Test name
Test status
Simulation time 91638782 ps
CPU time 3.03 seconds
Started May 05 02:35:42 PM PDT 24
Finished May 05 02:35:46 PM PDT 24
Peak memory 214280 kb
Host smart-71b74628-6fd4-4190-9ac2-146f9a620c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037829902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.3037829902
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.3028891741
Short name T866
Test name
Test status
Simulation time 60041373 ps
CPU time 2.74 seconds
Started May 05 02:35:36 PM PDT 24
Finished May 05 02:35:39 PM PDT 24
Peak memory 206712 kb
Host smart-799d460e-9cf2-4d82-82a6-bef8c12c1f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028891741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.3028891741
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.855134950
Short name T707
Test name
Test status
Simulation time 112735024 ps
CPU time 3.25 seconds
Started May 05 02:35:45 PM PDT 24
Finished May 05 02:35:49 PM PDT 24
Peak memory 208600 kb
Host smart-5e091d69-70fb-432b-b2f3-1ddcd20a4510
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855134950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.855134950
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.2624839468
Short name T728
Test name
Test status
Simulation time 829154841 ps
CPU time 4.59 seconds
Started May 05 02:35:41 PM PDT 24
Finished May 05 02:35:46 PM PDT 24
Peak memory 209436 kb
Host smart-a92e9d6c-d109-4f0b-b3d7-024e74dbad79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624839468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.2624839468
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.2251730644
Short name T610
Test name
Test status
Simulation time 108491236 ps
CPU time 2.59 seconds
Started May 05 02:35:44 PM PDT 24
Finished May 05 02:35:47 PM PDT 24
Peak memory 209884 kb
Host smart-677692d5-8752-48b4-84de-5e90202fd70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251730644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.2251730644
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.1754565461
Short name T449
Test name
Test status
Simulation time 12933414 ps
CPU time 0.91 seconds
Started May 05 02:35:55 PM PDT 24
Finished May 05 02:35:56 PM PDT 24
Peak memory 205888 kb
Host smart-29bb1601-10fc-4b19-869e-45f467aa190a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754565461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.1754565461
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.4155379899
Short name T257
Test name
Test status
Simulation time 6793754120 ps
CPU time 78.46 seconds
Started May 05 02:35:46 PM PDT 24
Finished May 05 02:37:05 PM PDT 24
Peak memory 217660 kb
Host smart-42d74b67-c9d8-4e44-b351-22d5bfef75a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4155379899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.4155379899
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.1770776893
Short name T30
Test name
Test status
Simulation time 35192186 ps
CPU time 2.52 seconds
Started May 05 02:35:46 PM PDT 24
Finished May 05 02:35:49 PM PDT 24
Peak memory 221648 kb
Host smart-cd6980c3-c69d-4c1b-84ff-5e6c45f44b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770776893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.1770776893
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.1303184395
Short name T741
Test name
Test status
Simulation time 58347454 ps
CPU time 2.97 seconds
Started May 05 02:35:49 PM PDT 24
Finished May 05 02:35:53 PM PDT 24
Peak memory 209236 kb
Host smart-f3d8fa34-6f45-4f54-9d5b-b562adf5016d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303184395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.1303184395
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.1541149130
Short name T40
Test name
Test status
Simulation time 97036293 ps
CPU time 1.85 seconds
Started May 05 02:35:44 PM PDT 24
Finished May 05 02:35:47 PM PDT 24
Peak memory 214188 kb
Host smart-affefcf8-7871-4106-9462-42f76978a631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541149130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.1541149130
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.3412970149
Short name T785
Test name
Test status
Simulation time 155586128 ps
CPU time 4.13 seconds
Started May 05 02:35:47 PM PDT 24
Finished May 05 02:35:52 PM PDT 24
Peak memory 214124 kb
Host smart-6b619ab6-4f35-454e-a77d-5196ea97e999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412970149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.3412970149
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.2942723778
Short name T458
Test name
Test status
Simulation time 854796102 ps
CPU time 2.37 seconds
Started May 05 02:35:47 PM PDT 24
Finished May 05 02:35:50 PM PDT 24
Peak memory 206968 kb
Host smart-076ac7bf-6b7b-42f0-994d-f285d3857b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942723778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.2942723778
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.3355743181
Short name T913
Test name
Test status
Simulation time 306778055 ps
CPU time 3.86 seconds
Started May 05 02:35:47 PM PDT 24
Finished May 05 02:35:51 PM PDT 24
Peak memory 209084 kb
Host smart-217f9998-66c2-4127-b9ed-6ac0dba28363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355743181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.3355743181
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.3229201171
Short name T299
Test name
Test status
Simulation time 71306906 ps
CPU time 3.74 seconds
Started May 05 02:35:47 PM PDT 24
Finished May 05 02:35:51 PM PDT 24
Peak memory 208308 kb
Host smart-1477c620-d6db-4133-8981-3b0f3c22a05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229201171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.3229201171
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.1289371269
Short name T515
Test name
Test status
Simulation time 193483926 ps
CPU time 2.86 seconds
Started May 05 02:35:48 PM PDT 24
Finished May 05 02:35:52 PM PDT 24
Peak memory 206704 kb
Host smart-bb9fc34e-251a-48db-8bab-bc5d6432481a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289371269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.1289371269
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.88666463
Short name T779
Test name
Test status
Simulation time 1401845047 ps
CPU time 38.44 seconds
Started May 05 02:35:45 PM PDT 24
Finished May 05 02:36:24 PM PDT 24
Peak memory 208236 kb
Host smart-331253fc-0ca0-4f66-84bf-bd7e35156be1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88666463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.88666463
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.1250844947
Short name T436
Test name
Test status
Simulation time 60247763 ps
CPU time 2.35 seconds
Started May 05 02:35:47 PM PDT 24
Finished May 05 02:35:50 PM PDT 24
Peak memory 206796 kb
Host smart-e41b0246-7e9a-42e6-bf76-38c74aa6e109
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250844947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.1250844947
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.1732583651
Short name T673
Test name
Test status
Simulation time 137165130 ps
CPU time 3.36 seconds
Started May 05 02:35:45 PM PDT 24
Finished May 05 02:35:49 PM PDT 24
Peak memory 214236 kb
Host smart-46f0e4c3-2264-48ae-9afc-f51c29033794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732583651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.1732583651
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.2432126363
Short name T555
Test name
Test status
Simulation time 127969518 ps
CPU time 2.78 seconds
Started May 05 02:35:43 PM PDT 24
Finished May 05 02:35:46 PM PDT 24
Peak memory 208216 kb
Host smart-3f7a8340-e49a-4ea7-97e7-535abf41f9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432126363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.2432126363
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.2006066672
Short name T196
Test name
Test status
Simulation time 172205952 ps
CPU time 3.13 seconds
Started May 05 02:35:49 PM PDT 24
Finished May 05 02:35:53 PM PDT 24
Peak memory 219828 kb
Host smart-f3099983-25df-44bd-998b-40004cb83bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006066672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.2006066672
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.3849982820
Short name T161
Test name
Test status
Simulation time 5748225717 ps
CPU time 9.41 seconds
Started May 05 02:35:46 PM PDT 24
Finished May 05 02:35:56 PM PDT 24
Peak memory 211320 kb
Host smart-6fb2aac1-2c2f-49bb-9b9d-6a172ed29cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849982820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.3849982820
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.340411883
Short name T620
Test name
Test status
Simulation time 19150206 ps
CPU time 0.79 seconds
Started May 05 02:35:53 PM PDT 24
Finished May 05 02:35:55 PM PDT 24
Peak memory 205888 kb
Host smart-62e310e7-a869-44c6-9317-09fe1a32eacf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340411883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.340411883
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.1069636970
Short name T350
Test name
Test status
Simulation time 304812140 ps
CPU time 17.52 seconds
Started May 05 02:35:55 PM PDT 24
Finished May 05 02:36:12 PM PDT 24
Peak memory 214260 kb
Host smart-d567e22a-551c-4e4d-b002-225e4c89fda5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1069636970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.1069636970
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.2736393207
Short name T224
Test name
Test status
Simulation time 60632421 ps
CPU time 2.13 seconds
Started May 05 02:35:58 PM PDT 24
Finished May 05 02:36:01 PM PDT 24
Peak memory 208632 kb
Host smart-80af449e-d135-49fb-8588-f00baccc8887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736393207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.2736393207
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.2875369096
Short name T843
Test name
Test status
Simulation time 298138162 ps
CPU time 3.67 seconds
Started May 05 02:35:51 PM PDT 24
Finished May 05 02:35:55 PM PDT 24
Peak memory 207672 kb
Host smart-2a41756f-bd4a-4d8a-b689-4616effbecc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875369096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.2875369096
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.2836829208
Short name T846
Test name
Test status
Simulation time 36316233 ps
CPU time 2.18 seconds
Started May 05 02:35:55 PM PDT 24
Finished May 05 02:35:58 PM PDT 24
Peak memory 214236 kb
Host smart-8c50fd20-51fc-40b4-b96b-29dc8f279501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836829208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.2836829208
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.1118607535
Short name T296
Test name
Test status
Simulation time 155811900 ps
CPU time 2.95 seconds
Started May 05 02:35:57 PM PDT 24
Finished May 05 02:36:00 PM PDT 24
Peak memory 222240 kb
Host smart-29c3d972-e9fa-4bfe-9e10-64cde2268d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118607535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.1118607535
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.966905656
Short name T218
Test name
Test status
Simulation time 62483446 ps
CPU time 4.07 seconds
Started May 05 02:35:54 PM PDT 24
Finished May 05 02:35:59 PM PDT 24
Peak memory 222432 kb
Host smart-23297aeb-703a-431f-9493-71c890a6b6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966905656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.966905656
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.3586952334
Short name T469
Test name
Test status
Simulation time 331050207 ps
CPU time 4.37 seconds
Started May 05 02:35:55 PM PDT 24
Finished May 05 02:35:59 PM PDT 24
Peak memory 207420 kb
Host smart-c6efb109-522b-44f3-8647-e656340a29a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586952334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.3586952334
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.24139266
Short name T752
Test name
Test status
Simulation time 352647191 ps
CPU time 5.46 seconds
Started May 05 02:35:48 PM PDT 24
Finished May 05 02:35:54 PM PDT 24
Peak memory 208304 kb
Host smart-41696c42-2c10-451f-b053-c2b7e05c1305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24139266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.24139266
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.2997283233
Short name T410
Test name
Test status
Simulation time 42066789 ps
CPU time 2.62 seconds
Started May 05 02:35:56 PM PDT 24
Finished May 05 02:35:59 PM PDT 24
Peak memory 206780 kb
Host smart-d4d46e34-0fa0-409f-953b-5fef9655839c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997283233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.2997283233
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.3367542126
Short name T460
Test name
Test status
Simulation time 126088601 ps
CPU time 2.54 seconds
Started May 05 02:35:51 PM PDT 24
Finished May 05 02:35:54 PM PDT 24
Peak memory 207212 kb
Host smart-3ed5ac6a-290a-4f56-99a4-39e9bdbc4571
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367542126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.3367542126
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.1452989993
Short name T833
Test name
Test status
Simulation time 156417752 ps
CPU time 2.73 seconds
Started May 05 02:35:55 PM PDT 24
Finished May 05 02:35:58 PM PDT 24
Peak memory 208664 kb
Host smart-dfad5aac-b80b-434f-841c-8d7615bcb601
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452989993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.1452989993
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.3235911413
Short name T622
Test name
Test status
Simulation time 77654813 ps
CPU time 2.16 seconds
Started May 05 02:35:55 PM PDT 24
Finished May 05 02:35:58 PM PDT 24
Peak memory 215536 kb
Host smart-fe84cc0b-373f-435b-a692-d3748a5bd1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235911413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.3235911413
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.3161210277
Short name T686
Test name
Test status
Simulation time 31948725 ps
CPU time 2.15 seconds
Started May 05 02:35:52 PM PDT 24
Finished May 05 02:35:55 PM PDT 24
Peak memory 206548 kb
Host smart-7f794cb2-95ed-4fdd-8ece-29741e53fa4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161210277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.3161210277
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.321029356
Short name T667
Test name
Test status
Simulation time 22754605108 ps
CPU time 211.5 seconds
Started May 05 02:35:56 PM PDT 24
Finished May 05 02:39:28 PM PDT 24
Peak memory 222104 kb
Host smart-25899cff-7eb4-4ff3-842c-c95b530de7f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321029356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.321029356
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.2951059971
Short name T660
Test name
Test status
Simulation time 400980990 ps
CPU time 5.12 seconds
Started May 05 02:35:59 PM PDT 24
Finished May 05 02:36:04 PM PDT 24
Peak memory 207524 kb
Host smart-3fb04cb3-1842-4e46-bd38-056a75d26d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951059971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.2951059971
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.2040708575
Short name T107
Test name
Test status
Simulation time 97870295 ps
CPU time 1.96 seconds
Started May 05 02:36:03 PM PDT 24
Finished May 05 02:36:06 PM PDT 24
Peak memory 210180 kb
Host smart-689f2821-c9ce-4636-8f5a-21e0ca4ccec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040708575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.2040708575
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.3647556850
Short name T504
Test name
Test status
Simulation time 14779615 ps
CPU time 0.75 seconds
Started May 05 02:36:05 PM PDT 24
Finished May 05 02:36:07 PM PDT 24
Peak memory 205860 kb
Host smart-2b91ee77-59c8-428e-8f5b-073361c07773
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647556850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.3647556850
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.4098915225
Short name T134
Test name
Test status
Simulation time 82601977 ps
CPU time 2.8 seconds
Started May 05 02:36:00 PM PDT 24
Finished May 05 02:36:03 PM PDT 24
Peak memory 214164 kb
Host smart-7d8b6011-e0e7-41cb-89cf-7e0d261b921d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4098915225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.4098915225
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.2768571271
Short name T74
Test name
Test status
Simulation time 203029290 ps
CPU time 3.27 seconds
Started May 05 02:35:59 PM PDT 24
Finished May 05 02:36:03 PM PDT 24
Peak memory 216464 kb
Host smart-3eff218f-2137-4b8e-a1b1-d3a9e13bc6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768571271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.2768571271
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.604352767
Short name T55
Test name
Test status
Simulation time 1732828266 ps
CPU time 2.36 seconds
Started May 05 02:35:58 PM PDT 24
Finished May 05 02:36:01 PM PDT 24
Peak memory 207984 kb
Host smart-ff3eafa7-7635-4ae7-9cd4-d3c1b44042f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604352767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.604352767
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.1520292215
Short name T597
Test name
Test status
Simulation time 389224364 ps
CPU time 10.7 seconds
Started May 05 02:36:00 PM PDT 24
Finished May 05 02:36:12 PM PDT 24
Peak memory 222412 kb
Host smart-56cfd6f7-9c6b-4926-9c20-2d4bcd9e8214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520292215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.1520292215
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.1188321456
Short name T533
Test name
Test status
Simulation time 326593499 ps
CPU time 4.13 seconds
Started May 05 02:35:57 PM PDT 24
Finished May 05 02:36:02 PM PDT 24
Peak memory 214192 kb
Host smart-a0e1f466-3ba3-4efe-a454-c7a0067115f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188321456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.1188321456
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.3861458304
Short name T481
Test name
Test status
Simulation time 122137543 ps
CPU time 2.06 seconds
Started May 05 02:35:59 PM PDT 24
Finished May 05 02:36:01 PM PDT 24
Peak memory 222396 kb
Host smart-44792cfd-c4eb-4f45-901e-b2ba5f41c6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861458304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.3861458304
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.300264132
Short name T203
Test name
Test status
Simulation time 684230164 ps
CPU time 6.23 seconds
Started May 05 02:36:05 PM PDT 24
Finished May 05 02:36:11 PM PDT 24
Peak memory 208396 kb
Host smart-ca32330e-a578-431a-8687-a5beb1949325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300264132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.300264132
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.1368019441
Short name T281
Test name
Test status
Simulation time 104732769 ps
CPU time 4.3 seconds
Started May 05 02:35:58 PM PDT 24
Finished May 05 02:36:04 PM PDT 24
Peak memory 208480 kb
Host smart-ef04b2b7-1151-4c96-84a7-460c68b5a617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368019441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.1368019441
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.624147604
Short name T769
Test name
Test status
Simulation time 69181058 ps
CPU time 3.55 seconds
Started May 05 02:36:00 PM PDT 24
Finished May 05 02:36:04 PM PDT 24
Peak memory 208572 kb
Host smart-fa08a21f-ad06-49a3-8fc6-4b0e4b0cd9a0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624147604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.624147604
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.1368563738
Short name T340
Test name
Test status
Simulation time 67099042 ps
CPU time 3.27 seconds
Started May 05 02:35:57 PM PDT 24
Finished May 05 02:36:01 PM PDT 24
Peak memory 208320 kb
Host smart-8b227521-a09d-44aa-9dd7-e4d1726636af
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368563738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.1368563738
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.4258659925
Short name T473
Test name
Test status
Simulation time 266330484 ps
CPU time 6.24 seconds
Started May 05 02:36:00 PM PDT 24
Finished May 05 02:36:07 PM PDT 24
Peak memory 207956 kb
Host smart-f0e75845-de8e-4e10-887d-054c7716363a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258659925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.4258659925
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.3662474557
Short name T375
Test name
Test status
Simulation time 96894951 ps
CPU time 3.05 seconds
Started May 05 02:35:59 PM PDT 24
Finished May 05 02:36:02 PM PDT 24
Peak memory 218124 kb
Host smart-1a89c80c-82ee-4637-bc2f-42f5a01f9b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662474557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.3662474557
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.3108531635
Short name T407
Test name
Test status
Simulation time 175679400 ps
CPU time 3.12 seconds
Started May 05 02:35:59 PM PDT 24
Finished May 05 02:36:02 PM PDT 24
Peak memory 208260 kb
Host smart-d07265b4-c0e1-48e0-aceb-198876410e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108531635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.3108531635
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.2905332293
Short name T858
Test name
Test status
Simulation time 228698375 ps
CPU time 10.98 seconds
Started May 05 02:36:05 PM PDT 24
Finished May 05 02:36:16 PM PDT 24
Peak memory 219992 kb
Host smart-b9228116-9e2d-4316-8600-fa18595d9114
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905332293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.2905332293
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.3315374358
Short name T472
Test name
Test status
Simulation time 60187416 ps
CPU time 2.46 seconds
Started May 05 02:36:00 PM PDT 24
Finished May 05 02:36:03 PM PDT 24
Peak memory 207532 kb
Host smart-c0099ba6-2847-4081-b611-1a6c54a600f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315374358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.3315374358
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.2722113647
Short name T811
Test name
Test status
Simulation time 15259312 ps
CPU time 0.73 seconds
Started May 05 02:36:08 PM PDT 24
Finished May 05 02:36:09 PM PDT 24
Peak memory 205860 kb
Host smart-6a24667c-3d76-460a-a18e-0425048b569e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722113647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.2722113647
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.954845369
Short name T596
Test name
Test status
Simulation time 67844857 ps
CPU time 1.61 seconds
Started May 05 02:36:10 PM PDT 24
Finished May 05 02:36:12 PM PDT 24
Peak memory 207608 kb
Host smart-12f69f9a-2da8-40b3-b523-bb47f274cc3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954845369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.954845369
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.2964790419
Short name T326
Test name
Test status
Simulation time 617722120 ps
CPU time 5.18 seconds
Started May 05 02:36:07 PM PDT 24
Finished May 05 02:36:12 PM PDT 24
Peak memory 214272 kb
Host smart-42a5a8e7-309b-4c52-b74c-c7dd979c49f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964790419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.2964790419
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.3279614002
Short name T89
Test name
Test status
Simulation time 67976769 ps
CPU time 3.62 seconds
Started May 05 02:36:05 PM PDT 24
Finished May 05 02:36:09 PM PDT 24
Peak memory 208524 kb
Host smart-896fac3f-826f-44af-865d-3050e12fb053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279614002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.3279614002
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.3301382531
Short name T384
Test name
Test status
Simulation time 117934119 ps
CPU time 2.66 seconds
Started May 05 02:36:08 PM PDT 24
Finished May 05 02:36:11 PM PDT 24
Peak memory 207152 kb
Host smart-6595adf3-bbd3-4cab-9b05-e53c6f83e2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301382531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.3301382531
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.4076647587
Short name T581
Test name
Test status
Simulation time 971007795 ps
CPU time 3.95 seconds
Started May 05 02:36:05 PM PDT 24
Finished May 05 02:36:10 PM PDT 24
Peak memory 208680 kb
Host smart-76a16fba-0773-4db7-bdc0-9a9397e881c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076647587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.4076647587
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.2847461731
Short name T885
Test name
Test status
Simulation time 213660982 ps
CPU time 5.03 seconds
Started May 05 02:36:06 PM PDT 24
Finished May 05 02:36:12 PM PDT 24
Peak memory 208816 kb
Host smart-ae986969-d7f2-48bf-8672-4dd02f05d03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847461731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.2847461731
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.3882320916
Short name T918
Test name
Test status
Simulation time 191435348 ps
CPU time 2.8 seconds
Started May 05 02:36:04 PM PDT 24
Finished May 05 02:36:08 PM PDT 24
Peak memory 208336 kb
Host smart-7abf88e6-7808-477c-a6af-4bd66153041d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882320916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.3882320916
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.1568039475
Short name T485
Test name
Test status
Simulation time 207634620 ps
CPU time 2.98 seconds
Started May 05 02:36:05 PM PDT 24
Finished May 05 02:36:09 PM PDT 24
Peak memory 206692 kb
Host smart-b3d3b7ab-2a71-4697-abe9-1c7c1dbb73d9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568039475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.1568039475
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.2201786012
Short name T575
Test name
Test status
Simulation time 38874230 ps
CPU time 1.83 seconds
Started May 05 02:36:03 PM PDT 24
Finished May 05 02:36:06 PM PDT 24
Peak memory 207176 kb
Host smart-a201c356-f14e-4325-b46f-d1b4d97b498b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201786012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.2201786012
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.3844082981
Short name T461
Test name
Test status
Simulation time 107174685 ps
CPU time 3.6 seconds
Started May 05 02:36:02 PM PDT 24
Finished May 05 02:36:06 PM PDT 24
Peak memory 208356 kb
Host smart-df25a36e-7ee9-4251-8331-d63280896568
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844082981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.3844082981
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.4036504560
Short name T491
Test name
Test status
Simulation time 470987299 ps
CPU time 8.27 seconds
Started May 05 02:36:14 PM PDT 24
Finished May 05 02:36:23 PM PDT 24
Peak memory 220380 kb
Host smart-f1a467a6-fb3d-4ad6-a9fa-a767b94eacf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036504560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.4036504560
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.933653228
Short name T434
Test name
Test status
Simulation time 205458612 ps
CPU time 6.9 seconds
Started May 05 02:36:06 PM PDT 24
Finished May 05 02:36:14 PM PDT 24
Peak memory 206644 kb
Host smart-3d768381-e1c0-483b-91f0-532f810fe31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933653228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.933653228
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.667434754
Short name T341
Test name
Test status
Simulation time 230971527 ps
CPU time 8.65 seconds
Started May 05 02:36:11 PM PDT 24
Finished May 05 02:36:21 PM PDT 24
Peak memory 221212 kb
Host smart-7f3c9888-2bf0-4875-ad08-af9b977d6595
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667434754 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.667434754
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.4225901586
Short name T670
Test name
Test status
Simulation time 1774164375 ps
CPU time 48.28 seconds
Started May 05 02:36:11 PM PDT 24
Finished May 05 02:37:00 PM PDT 24
Peak memory 209680 kb
Host smart-8e040dc0-cf40-4263-a494-83f37cf5e778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225901586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.4225901586
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.247567091
Short name T467
Test name
Test status
Simulation time 366340649 ps
CPU time 8.56 seconds
Started May 05 02:36:10 PM PDT 24
Finished May 05 02:36:19 PM PDT 24
Peak memory 210636 kb
Host smart-5fd57083-5a39-4130-84a1-c671ad26676b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247567091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.247567091
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.3400867412
Short name T517
Test name
Test status
Simulation time 14333767 ps
CPU time 0.65 seconds
Started May 05 02:36:16 PM PDT 24
Finished May 05 02:36:17 PM PDT 24
Peak memory 205756 kb
Host smart-c47c0cc2-85c3-4e22-a22e-288171598684
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400867412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.3400867412
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.372880987
Short name T31
Test name
Test status
Simulation time 455042587 ps
CPU time 4.73 seconds
Started May 05 02:36:13 PM PDT 24
Finished May 05 02:36:19 PM PDT 24
Peak memory 214552 kb
Host smart-21fc06e6-c1a4-47f1-b349-de5492a66fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372880987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.372880987
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.3582310229
Short name T746
Test name
Test status
Simulation time 736150877 ps
CPU time 4.16 seconds
Started May 05 02:36:11 PM PDT 24
Finished May 05 02:36:16 PM PDT 24
Peak memory 208080 kb
Host smart-95547373-d107-40b4-b57a-070e3664638d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582310229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.3582310229
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.3963905554
Short name T682
Test name
Test status
Simulation time 170971475 ps
CPU time 4.28 seconds
Started May 05 02:36:13 PM PDT 24
Finished May 05 02:36:18 PM PDT 24
Peak memory 215340 kb
Host smart-1a0ff0ed-814a-44e2-9fb8-df4d413d7cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963905554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.3963905554
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.1389983337
Short name T295
Test name
Test status
Simulation time 95435104 ps
CPU time 3.49 seconds
Started May 05 02:36:15 PM PDT 24
Finished May 05 02:36:19 PM PDT 24
Peak memory 222284 kb
Host smart-d1edcedf-bd5f-481e-8eb1-cb3991c8f133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389983337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.1389983337
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.3114243887
Short name T557
Test name
Test status
Simulation time 609765382 ps
CPU time 4.94 seconds
Started May 05 02:36:13 PM PDT 24
Finished May 05 02:36:19 PM PDT 24
Peak memory 222292 kb
Host smart-d810d78f-0fbd-4c4f-a096-63b4e55d254d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114243887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.3114243887
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.3342241288
Short name T909
Test name
Test status
Simulation time 279534277 ps
CPU time 5.81 seconds
Started May 05 02:36:12 PM PDT 24
Finished May 05 02:36:19 PM PDT 24
Peak memory 214292 kb
Host smart-2ed4eeb5-6237-424c-8d7c-ac331c14b13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342241288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.3342241288
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.1737123837
Short name T737
Test name
Test status
Simulation time 115120282 ps
CPU time 5.06 seconds
Started May 05 02:36:08 PM PDT 24
Finished May 05 02:36:14 PM PDT 24
Peak memory 208252 kb
Host smart-b44c4e8a-7c5a-457c-aea7-04678e4e0620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737123837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.1737123837
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.4287201803
Short name T905
Test name
Test status
Simulation time 118675853 ps
CPU time 3.31 seconds
Started May 05 02:36:11 PM PDT 24
Finished May 05 02:36:15 PM PDT 24
Peak memory 207244 kb
Host smart-646dd8ef-dfdb-467c-8de7-4b68e67f3cd2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287201803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.4287201803
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.3256535855
Short name T408
Test name
Test status
Simulation time 33256182 ps
CPU time 2.33 seconds
Started May 05 02:36:09 PM PDT 24
Finished May 05 02:36:12 PM PDT 24
Peak memory 207368 kb
Host smart-557f4206-8bb4-4109-9015-42de07cccb25
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256535855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.3256535855
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.2030437302
Short name T454
Test name
Test status
Simulation time 323379938 ps
CPU time 5.05 seconds
Started May 05 02:36:12 PM PDT 24
Finished May 05 02:36:18 PM PDT 24
Peak memory 207792 kb
Host smart-cbc2f3f7-eed5-4d3f-bde0-ad4645d660ea
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030437302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.2030437302
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.2060485500
Short name T714
Test name
Test status
Simulation time 61593207 ps
CPU time 3.19 seconds
Started May 05 02:36:12 PM PDT 24
Finished May 05 02:36:16 PM PDT 24
Peak memory 214264 kb
Host smart-7a5076cc-bf4b-4bd1-8292-1a9e4d08363b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060485500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.2060485500
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.203306613
Short name T674
Test name
Test status
Simulation time 71404167 ps
CPU time 3.25 seconds
Started May 05 02:36:07 PM PDT 24
Finished May 05 02:36:11 PM PDT 24
Peak memory 208616 kb
Host smart-0caa171c-3c85-49e6-acde-5a6be778dc67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203306613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.203306613
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.3811707670
Short name T279
Test name
Test status
Simulation time 50959902 ps
CPU time 2.94 seconds
Started May 05 02:36:12 PM PDT 24
Finished May 05 02:36:16 PM PDT 24
Peak memory 219688 kb
Host smart-629e4473-0ac1-46cf-9c6f-fc0db995538a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811707670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.3811707670
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.2376647761
Short name T751
Test name
Test status
Simulation time 76734580 ps
CPU time 1.56 seconds
Started May 05 02:36:12 PM PDT 24
Finished May 05 02:36:15 PM PDT 24
Peak memory 209448 kb
Host smart-d540237f-ca51-48ae-be8d-12863b46008f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376647761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.2376647761
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.245679752
Short name T910
Test name
Test status
Simulation time 13702722 ps
CPU time 0.74 seconds
Started May 05 02:36:21 PM PDT 24
Finished May 05 02:36:22 PM PDT 24
Peak memory 205900 kb
Host smart-bbdecd7f-e280-44d4-9bd1-679049a9fae1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245679752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.245679752
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.4287403628
Short name T285
Test name
Test status
Simulation time 273357416 ps
CPU time 7.92 seconds
Started May 05 02:36:17 PM PDT 24
Finished May 05 02:36:25 PM PDT 24
Peak memory 214268 kb
Host smart-3192d427-173d-4b6e-8e74-0d60d45ba492
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4287403628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.4287403628
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.2507545931
Short name T856
Test name
Test status
Simulation time 936265600 ps
CPU time 19.14 seconds
Started May 05 02:36:22 PM PDT 24
Finished May 05 02:36:41 PM PDT 24
Peak memory 222712 kb
Host smart-42334051-9057-4f26-958a-347764216999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507545931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.2507545931
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.1189617129
Short name T739
Test name
Test status
Simulation time 51713679 ps
CPU time 2.64 seconds
Started May 05 02:36:17 PM PDT 24
Finished May 05 02:36:20 PM PDT 24
Peak memory 214160 kb
Host smart-5b3d142e-93c7-4192-b67c-bb8642bd4f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189617129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.1189617129
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.1411790583
Short name T774
Test name
Test status
Simulation time 83455280 ps
CPU time 2.04 seconds
Started May 05 02:36:18 PM PDT 24
Finished May 05 02:36:20 PM PDT 24
Peak memory 206928 kb
Host smart-1b6abca1-9ca3-4129-9008-93774e574372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411790583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.1411790583
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.3491852504
Short name T71
Test name
Test status
Simulation time 125043509 ps
CPU time 5.41 seconds
Started May 05 02:36:19 PM PDT 24
Finished May 05 02:36:25 PM PDT 24
Peak memory 220416 kb
Host smart-c1ea3846-fc9a-4655-8409-abe94e848907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491852504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.3491852504
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.2307136034
Short name T818
Test name
Test status
Simulation time 211533383 ps
CPU time 5.54 seconds
Started May 05 02:36:17 PM PDT 24
Finished May 05 02:36:24 PM PDT 24
Peak memory 208944 kb
Host smart-e3cabd84-5ad4-4055-a02d-535fe2595603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307136034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.2307136034
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.1624177464
Short name T795
Test name
Test status
Simulation time 218704938 ps
CPU time 6.61 seconds
Started May 05 02:36:17 PM PDT 24
Finished May 05 02:36:24 PM PDT 24
Peak memory 206532 kb
Host smart-d8c78dcf-c6ab-4c7e-a27a-b75ed88047b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624177464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.1624177464
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.1203659056
Short name T663
Test name
Test status
Simulation time 1529600117 ps
CPU time 5.95 seconds
Started May 05 02:36:19 PM PDT 24
Finished May 05 02:36:25 PM PDT 24
Peak memory 208576 kb
Host smart-41acf3e5-d4e0-4798-ae20-d90dbc64287a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203659056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.1203659056
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.226503031
Short name T339
Test name
Test status
Simulation time 240714680 ps
CPU time 3.17 seconds
Started May 05 02:36:16 PM PDT 24
Finished May 05 02:36:20 PM PDT 24
Peak memory 206672 kb
Host smart-188fbb60-fbf7-4eeb-96ec-d432953e0c93
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226503031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.226503031
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.3654559915
Short name T198
Test name
Test status
Simulation time 57991822 ps
CPU time 1.81 seconds
Started May 05 02:36:18 PM PDT 24
Finished May 05 02:36:21 PM PDT 24
Peak memory 206660 kb
Host smart-5d00c33c-e194-47e9-890d-05e54eec87da
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654559915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.3654559915
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.239465666
Short name T822
Test name
Test status
Simulation time 522087568 ps
CPU time 3.98 seconds
Started May 05 02:36:20 PM PDT 24
Finished May 05 02:36:24 PM PDT 24
Peak memory 209824 kb
Host smart-02b051e1-d394-4dc7-aa3f-53b4a80311cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239465666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.239465666
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.856843171
Short name T535
Test name
Test status
Simulation time 159455038 ps
CPU time 3.26 seconds
Started May 05 02:36:17 PM PDT 24
Finished May 05 02:36:20 PM PDT 24
Peak memory 208432 kb
Host smart-bb7c4b50-3f12-4883-9e79-fd4f81132a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856843171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.856843171
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.1367514708
Short name T895
Test name
Test status
Simulation time 2152156934 ps
CPU time 42.65 seconds
Started May 05 02:36:21 PM PDT 24
Finished May 05 02:37:04 PM PDT 24
Peak memory 216668 kb
Host smart-f9181e2a-b5b1-4595-8be5-81b851db144c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367514708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.1367514708
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.2543320503
Short name T904
Test name
Test status
Simulation time 199762849 ps
CPU time 2.68 seconds
Started May 05 02:36:18 PM PDT 24
Finished May 05 02:36:22 PM PDT 24
Peak memory 214180 kb
Host smart-ceb343f7-7786-4743-8119-7fea84f83860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543320503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.2543320503
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.2288806136
Short name T57
Test name
Test status
Simulation time 82997864 ps
CPU time 3.19 seconds
Started May 05 02:36:21 PM PDT 24
Finished May 05 02:36:25 PM PDT 24
Peak memory 210084 kb
Host smart-6a207d3d-6a44-440d-ac33-399aab9cb25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288806136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.2288806136
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.3917453434
Short name T665
Test name
Test status
Simulation time 21101904 ps
CPU time 0.82 seconds
Started May 05 02:30:27 PM PDT 24
Finished May 05 02:30:28 PM PDT 24
Peak memory 205824 kb
Host smart-fdf4ab78-5e10-46ed-b72f-f05c6b8b0ffe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917453434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.3917453434
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.1989315843
Short name T424
Test name
Test status
Simulation time 737539644 ps
CPU time 9.8 seconds
Started May 05 02:30:22 PM PDT 24
Finished May 05 02:30:32 PM PDT 24
Peak memory 215100 kb
Host smart-6e1f6849-9a5e-4360-a114-db86106f5be0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1989315843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.1989315843
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.2268349218
Short name T897
Test name
Test status
Simulation time 140643633 ps
CPU time 5.45 seconds
Started May 05 02:30:25 PM PDT 24
Finished May 05 02:30:31 PM PDT 24
Peak memory 218208 kb
Host smart-badd41c5-de65-4dce-9462-d1b12a59c250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268349218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.2268349218
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.3872683476
Short name T609
Test name
Test status
Simulation time 94885190 ps
CPU time 2.76 seconds
Started May 05 02:30:20 PM PDT 24
Finished May 05 02:30:24 PM PDT 24
Peak memory 208464 kb
Host smart-0a70c1ad-1d48-4335-8556-28ae1f1551a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872683476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.3872683476
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.697214939
Short name T845
Test name
Test status
Simulation time 217238395 ps
CPU time 5.4 seconds
Started May 05 02:30:33 PM PDT 24
Finished May 05 02:30:39 PM PDT 24
Peak memory 222400 kb
Host smart-f9784374-b9c5-44a2-9c82-20a68acfa22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697214939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.697214939
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.146158739
Short name T797
Test name
Test status
Simulation time 71334011 ps
CPU time 3.65 seconds
Started May 05 02:30:23 PM PDT 24
Finished May 05 02:30:27 PM PDT 24
Peak memory 214220 kb
Host smart-9e62641f-9b13-4a84-9504-7079b3379854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146158739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.146158739
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.525436938
Short name T318
Test name
Test status
Simulation time 1106666322 ps
CPU time 9.47 seconds
Started May 05 02:30:17 PM PDT 24
Finished May 05 02:30:27 PM PDT 24
Peak memory 214360 kb
Host smart-0db7ed03-ef69-4471-9550-44bd6eff89ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525436938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.525436938
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.2048073485
Short name T588
Test name
Test status
Simulation time 132235549 ps
CPU time 4.21 seconds
Started May 05 02:30:18 PM PDT 24
Finished May 05 02:30:22 PM PDT 24
Peak memory 206624 kb
Host smart-18491be6-ae5b-4355-b7fd-b349dd72bda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048073485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.2048073485
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.4085236625
Short name T706
Test name
Test status
Simulation time 145233124 ps
CPU time 5.17 seconds
Started May 05 02:30:17 PM PDT 24
Finished May 05 02:30:23 PM PDT 24
Peak memory 208644 kb
Host smart-4016de56-98b1-4320-9475-2df6e6195484
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085236625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.4085236625
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.1958090563
Short name T732
Test name
Test status
Simulation time 21159804 ps
CPU time 1.85 seconds
Started May 05 02:30:16 PM PDT 24
Finished May 05 02:30:18 PM PDT 24
Peak memory 207144 kb
Host smart-8eb9ff6a-931f-492e-ac0c-e87956df1dcd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958090563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.1958090563
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.2620691588
Short name T704
Test name
Test status
Simulation time 868970094 ps
CPU time 25.11 seconds
Started May 05 02:30:16 PM PDT 24
Finished May 05 02:30:41 PM PDT 24
Peak memory 208936 kb
Host smart-772178ec-d433-42f1-8f22-f9c70b9d3263
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620691588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.2620691588
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.2072403638
Short name T590
Test name
Test status
Simulation time 552129336 ps
CPU time 4.42 seconds
Started May 05 02:30:26 PM PDT 24
Finished May 05 02:30:31 PM PDT 24
Peak memory 215696 kb
Host smart-c81c840d-c3ab-49bf-81a0-a449a9b2cf39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072403638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.2072403638
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.2381336198
Short name T582
Test name
Test status
Simulation time 235037395 ps
CPU time 2.74 seconds
Started May 05 02:30:14 PM PDT 24
Finished May 05 02:30:17 PM PDT 24
Peak memory 205940 kb
Host smart-97655c7a-b49e-421e-8a24-a81aa83cdb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381336198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.2381336198
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.1839785291
Short name T206
Test name
Test status
Simulation time 148724250 ps
CPU time 8.04 seconds
Started May 05 02:30:25 PM PDT 24
Finished May 05 02:30:33 PM PDT 24
Peak memory 208084 kb
Host smart-75c5f145-f197-4432-a132-dcdacc34f098
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839785291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.1839785291
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.1773343269
Short name T124
Test name
Test status
Simulation time 156390578 ps
CPU time 4.83 seconds
Started May 05 02:30:34 PM PDT 24
Finished May 05 02:30:39 PM PDT 24
Peak memory 222656 kb
Host smart-062ef3ea-3d40-4ebe-b222-d69792bfcf8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773343269 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.1773343269
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.2433707928
Short name T212
Test name
Test status
Simulation time 123491759 ps
CPU time 5.37 seconds
Started May 05 02:30:22 PM PDT 24
Finished May 05 02:30:28 PM PDT 24
Peak memory 218152 kb
Host smart-cc830cfd-9f4f-430e-a038-3ef1a1fcd7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433707928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.2433707928
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.4163378385
Short name T508
Test name
Test status
Simulation time 234369676 ps
CPU time 2.13 seconds
Started May 05 02:30:33 PM PDT 24
Finished May 05 02:30:36 PM PDT 24
Peak memory 210136 kb
Host smart-e6942744-3ab2-459a-bc66-a55a9e63214f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163378385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.4163378385
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.1464738775
Short name T688
Test name
Test status
Simulation time 38976886 ps
CPU time 0.7 seconds
Started May 05 02:30:38 PM PDT 24
Finished May 05 02:30:40 PM PDT 24
Peak memory 205888 kb
Host smart-aaa724ac-0b75-49da-a307-f3c86ccad792
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464738775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.1464738775
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.1857542221
Short name T11
Test name
Test status
Simulation time 203588366 ps
CPU time 4.51 seconds
Started May 05 02:30:35 PM PDT 24
Finished May 05 02:30:40 PM PDT 24
Peak memory 210592 kb
Host smart-db7d1651-4ce4-4a87-8d59-5fa71635b154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857542221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.1857542221
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.3054636143
Short name T422
Test name
Test status
Simulation time 4319445487 ps
CPU time 26.16 seconds
Started May 05 02:30:31 PM PDT 24
Finished May 05 02:30:57 PM PDT 24
Peak memory 214296 kb
Host smart-4f76588d-411e-4ee1-a561-2339a18afe88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054636143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.3054636143
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.3521081239
Short name T236
Test name
Test status
Simulation time 479150575 ps
CPU time 4.5 seconds
Started May 05 02:30:34 PM PDT 24
Finished May 05 02:30:39 PM PDT 24
Peak memory 214256 kb
Host smart-fb6f51a8-958e-4a44-9ddf-db2408208791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521081239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.3521081239
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.1327651753
Short name T323
Test name
Test status
Simulation time 109001215 ps
CPU time 4.33 seconds
Started May 05 02:30:38 PM PDT 24
Finished May 05 02:30:43 PM PDT 24
Peak memory 206092 kb
Host smart-85beef69-1ad0-435f-8561-64b9c1282c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327651753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.1327651753
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.250893565
Short name T233
Test name
Test status
Simulation time 205467494 ps
CPU time 3.46 seconds
Started May 05 02:30:29 PM PDT 24
Finished May 05 02:30:33 PM PDT 24
Peak memory 208004 kb
Host smart-1b6ff8e4-c5da-490f-ac13-c4673d7c91fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250893565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.250893565
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.486431018
Short name T453
Test name
Test status
Simulation time 460954010 ps
CPU time 12.41 seconds
Started May 05 02:30:32 PM PDT 24
Finished May 05 02:30:45 PM PDT 24
Peak memory 209124 kb
Host smart-23b0170d-9aad-4e0c-94e5-d20c8875f69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486431018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.486431018
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.3744821035
Short name T283
Test name
Test status
Simulation time 92719716 ps
CPU time 2.16 seconds
Started May 05 02:30:32 PM PDT 24
Finished May 05 02:30:35 PM PDT 24
Peak memory 208568 kb
Host smart-1b26fe2f-1836-4f8a-b60d-9833191b31ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744821035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.3744821035
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.662358404
Short name T87
Test name
Test status
Simulation time 319613316 ps
CPU time 10.09 seconds
Started May 05 02:30:32 PM PDT 24
Finished May 05 02:30:42 PM PDT 24
Peak memory 207872 kb
Host smart-13af624c-b25e-42d9-8c72-e4c2ef27d991
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662358404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.662358404
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.2991514655
Short name T443
Test name
Test status
Simulation time 43117425 ps
CPU time 1.87 seconds
Started May 05 02:30:30 PM PDT 24
Finished May 05 02:30:32 PM PDT 24
Peak memory 206808 kb
Host smart-9676524f-4ccc-4ecc-9cc6-1aa84f25c020
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991514655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.2991514655
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.954048352
Short name T558
Test name
Test status
Simulation time 148523901 ps
CPU time 5.69 seconds
Started May 05 02:30:30 PM PDT 24
Finished May 05 02:30:36 PM PDT 24
Peak memory 208600 kb
Host smart-f52bb5c6-8ce9-4608-8c8c-0fcd150da1bd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954048352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.954048352
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.1640608128
Short name T917
Test name
Test status
Simulation time 351119029 ps
CPU time 1.98 seconds
Started May 05 02:30:39 PM PDT 24
Finished May 05 02:30:42 PM PDT 24
Peak memory 206752 kb
Host smart-cdc1fbca-5a7d-4d13-aba1-27f61d5bb5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640608128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.1640608128
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.4088675770
Short name T464
Test name
Test status
Simulation time 27363946 ps
CPU time 2.17 seconds
Started May 05 02:30:34 PM PDT 24
Finished May 05 02:30:36 PM PDT 24
Peak memory 208576 kb
Host smart-baa00e96-d3a7-43de-9220-5f800fb4118c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088675770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.4088675770
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.251435324
Short name T190
Test name
Test status
Simulation time 8115797689 ps
CPU time 22.31 seconds
Started May 05 02:30:39 PM PDT 24
Finished May 05 02:31:02 PM PDT 24
Peak memory 216892 kb
Host smart-aebd15b0-32f8-438d-8a91-b826576e1e21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251435324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.251435324
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.3742848749
Short name T360
Test name
Test status
Simulation time 205438590 ps
CPU time 13.6 seconds
Started May 05 02:30:35 PM PDT 24
Finished May 05 02:30:49 PM PDT 24
Peak memory 222552 kb
Host smart-44765267-c183-4d5c-b263-fbc1ec6a5452
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742848749 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.3742848749
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.3228716185
Short name T304
Test name
Test status
Simulation time 533824282 ps
CPU time 4.12 seconds
Started May 05 02:30:35 PM PDT 24
Finished May 05 02:30:40 PM PDT 24
Peak memory 214260 kb
Host smart-0a657e8b-293b-4229-8847-91a36fa27251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228716185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.3228716185
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.1234183858
Short name T166
Test name
Test status
Simulation time 369187215 ps
CPU time 2.67 seconds
Started May 05 02:30:36 PM PDT 24
Finished May 05 02:30:39 PM PDT 24
Peak memory 210052 kb
Host smart-468e954d-cfb9-45c6-a99e-8188c393b2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234183858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.1234183858
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.1754202181
Short name T768
Test name
Test status
Simulation time 53001265 ps
CPU time 0.94 seconds
Started May 05 02:30:50 PM PDT 24
Finished May 05 02:30:51 PM PDT 24
Peak memory 205984 kb
Host smart-b0d25fec-0991-4bef-8cf8-6a1b3dadb694
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754202181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.1754202181
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.2350886038
Short name T415
Test name
Test status
Simulation time 8233292094 ps
CPU time 57.95 seconds
Started May 05 02:30:39 PM PDT 24
Finished May 05 02:31:38 PM PDT 24
Peak memory 214732 kb
Host smart-22e26d8c-14db-488c-bef2-7097a352fffb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2350886038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.2350886038
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.2623601190
Short name T837
Test name
Test status
Simulation time 1360791374 ps
CPU time 7.86 seconds
Started May 05 02:30:41 PM PDT 24
Finished May 05 02:30:49 PM PDT 24
Peak memory 218348 kb
Host smart-b9e972e9-fe86-472e-960f-7744c8752f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623601190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.2623601190
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.3822853509
Short name T91
Test name
Test status
Simulation time 780025687 ps
CPU time 5.36 seconds
Started May 05 02:30:44 PM PDT 24
Finished May 05 02:30:49 PM PDT 24
Peak memory 214200 kb
Host smart-fa70ade7-1406-4d33-bcb6-154078dc285c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822853509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.3822853509
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.2682280485
Short name T273
Test name
Test status
Simulation time 53095894 ps
CPU time 3.12 seconds
Started May 05 02:30:46 PM PDT 24
Finished May 05 02:30:49 PM PDT 24
Peak memory 214176 kb
Host smart-46415354-e443-4556-850c-9cae67cc4739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682280485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.2682280485
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.998173958
Short name T698
Test name
Test status
Simulation time 164451870 ps
CPU time 2.68 seconds
Started May 05 02:30:44 PM PDT 24
Finished May 05 02:30:47 PM PDT 24
Peak memory 219948 kb
Host smart-d6f358f5-3aad-4d08-99b6-c8925db94684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998173958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.998173958
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.1132154873
Short name T483
Test name
Test status
Simulation time 60788647 ps
CPU time 3.85 seconds
Started May 05 02:30:39 PM PDT 24
Finished May 05 02:30:44 PM PDT 24
Peak memory 210196 kb
Host smart-c6bee66f-112a-4df3-8d43-2dbb80720ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132154873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.1132154873
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.1072827538
Short name T857
Test name
Test status
Simulation time 1587414088 ps
CPU time 10.32 seconds
Started May 05 02:30:39 PM PDT 24
Finished May 05 02:30:50 PM PDT 24
Peak memory 208472 kb
Host smart-efe1397a-24ac-498f-899e-e071335a848f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072827538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.1072827538
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.3626515760
Short name T506
Test name
Test status
Simulation time 725559387 ps
CPU time 5.56 seconds
Started May 05 02:30:40 PM PDT 24
Finished May 05 02:30:46 PM PDT 24
Peak memory 208344 kb
Host smart-17606648-a719-467b-8e11-d2d92a8daad4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626515760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.3626515760
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.4272503759
Short name T103
Test name
Test status
Simulation time 116306269 ps
CPU time 2.39 seconds
Started May 05 02:30:39 PM PDT 24
Finished May 05 02:30:42 PM PDT 24
Peak memory 206672 kb
Host smart-98bd511a-1b94-4f7f-8081-885c45f52a29
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272503759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.4272503759
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.3722369743
Short name T338
Test name
Test status
Simulation time 106118444 ps
CPU time 1.75 seconds
Started May 05 02:30:40 PM PDT 24
Finished May 05 02:30:42 PM PDT 24
Peak memory 206808 kb
Host smart-036c27e6-b1fa-44ce-b93c-fa15332c4e2b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722369743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.3722369743
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.3131062840
Short name T395
Test name
Test status
Simulation time 111325814 ps
CPU time 2.22 seconds
Started May 05 02:30:45 PM PDT 24
Finished May 05 02:30:47 PM PDT 24
Peak memory 206788 kb
Host smart-8c68a52f-7899-4d94-a02d-ed247d6e4e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131062840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.3131062840
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.1600602608
Short name T440
Test name
Test status
Simulation time 332547177 ps
CPU time 2.52 seconds
Started May 05 02:30:40 PM PDT 24
Finished May 05 02:30:43 PM PDT 24
Peak memory 206864 kb
Host smart-44ea1d95-aea4-4fd5-afb1-6ecf46f02053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600602608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.1600602608
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.1895415276
Short name T834
Test name
Test status
Simulation time 7431343832 ps
CPU time 237.49 seconds
Started May 05 02:30:45 PM PDT 24
Finished May 05 02:34:43 PM PDT 24
Peak memory 222612 kb
Host smart-9dcfa2f2-2cc9-4afd-a8e4-9101611da398
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895415276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.1895415276
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.2527020096
Short name T255
Test name
Test status
Simulation time 608090978 ps
CPU time 4.77 seconds
Started May 05 02:30:43 PM PDT 24
Finished May 05 02:30:48 PM PDT 24
Peak memory 222456 kb
Host smart-91bc2f96-f2a5-4522-9333-07f0122759f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527020096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2527020096
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.1017278143
Short name T411
Test name
Test status
Simulation time 205652587 ps
CPU time 2.34 seconds
Started May 05 02:30:44 PM PDT 24
Finished May 05 02:30:47 PM PDT 24
Peak memory 210616 kb
Host smart-393a5d03-3b0d-4c6c-b6d5-db91f5f76450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017278143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.1017278143
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.1991395752
Short name T525
Test name
Test status
Simulation time 59999289 ps
CPU time 0.83 seconds
Started May 05 02:31:00 PM PDT 24
Finished May 05 02:31:01 PM PDT 24
Peak memory 205868 kb
Host smart-d4aff461-db42-4753-bab2-3ebfd3447c3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991395752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.1991395752
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.3173267809
Short name T26
Test name
Test status
Simulation time 398342305 ps
CPU time 2.56 seconds
Started May 05 02:30:59 PM PDT 24
Finished May 05 02:31:02 PM PDT 24
Peak memory 222724 kb
Host smart-724c61da-3f76-4ea6-af9a-65cf3b6d96d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173267809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.3173267809
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.733580772
Short name T587
Test name
Test status
Simulation time 87453850 ps
CPU time 4.11 seconds
Started May 05 02:30:55 PM PDT 24
Finished May 05 02:31:00 PM PDT 24
Peak memory 209220 kb
Host smart-6c6ff0ef-c19e-40d1-a79e-b90ce9beb8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733580772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.733580772
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.2503588087
Short name T95
Test name
Test status
Simulation time 6788290756 ps
CPU time 38.22 seconds
Started May 05 02:30:54 PM PDT 24
Finished May 05 02:31:33 PM PDT 24
Peak memory 214384 kb
Host smart-073fd1aa-d207-42fd-ab70-92fe7b8eca56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503588087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.2503588087
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.2564685352
Short name T385
Test name
Test status
Simulation time 279345525 ps
CPU time 3.77 seconds
Started May 05 02:30:56 PM PDT 24
Finished May 05 02:31:01 PM PDT 24
Peak memory 214216 kb
Host smart-10fae6a7-5813-41a6-92c7-8d8364f8f8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564685352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.2564685352
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.2120466089
Short name T767
Test name
Test status
Simulation time 69440196 ps
CPU time 3.31 seconds
Started May 05 02:30:56 PM PDT 24
Finished May 05 02:31:00 PM PDT 24
Peak memory 215372 kb
Host smart-8fb01128-afbe-4f97-a14c-888aacf89955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120466089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.2120466089
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.1746813841
Short name T187
Test name
Test status
Simulation time 185430374 ps
CPU time 3.19 seconds
Started May 05 02:30:55 PM PDT 24
Finished May 05 02:30:59 PM PDT 24
Peak memory 207780 kb
Host smart-7d865932-00e2-4eba-bc01-33a43567bf5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746813841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.1746813841
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.3525152696
Short name T477
Test name
Test status
Simulation time 503652498 ps
CPU time 3.77 seconds
Started May 05 02:30:52 PM PDT 24
Finished May 05 02:30:56 PM PDT 24
Peak memory 206600 kb
Host smart-d75a3140-2acf-4e53-8cc3-c6dbfbb0d5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525152696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.3525152696
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.3438062434
Short name T713
Test name
Test status
Simulation time 191524637 ps
CPU time 2.59 seconds
Started May 05 02:30:52 PM PDT 24
Finished May 05 02:30:55 PM PDT 24
Peak memory 208540 kb
Host smart-1f54f851-a632-4206-b35d-8c9dc58eee87
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438062434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.3438062434
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.3912690633
Short name T655
Test name
Test status
Simulation time 475794378 ps
CPU time 7.49 seconds
Started May 05 02:30:50 PM PDT 24
Finished May 05 02:30:57 PM PDT 24
Peak memory 207772 kb
Host smart-4e0b0ba6-cd26-4afc-8789-5454524c78de
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912690633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.3912690633
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.3914552941
Short name T702
Test name
Test status
Simulation time 5066575458 ps
CPU time 39.8 seconds
Started May 05 02:30:54 PM PDT 24
Finished May 05 02:31:34 PM PDT 24
Peak memory 208368 kb
Host smart-03b63b35-9ae3-4e7e-8b48-5b3a436c72ff
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914552941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.3914552941
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.3562266543
Short name T266
Test name
Test status
Simulation time 122969609 ps
CPU time 2.29 seconds
Started May 05 02:30:58 PM PDT 24
Finished May 05 02:31:00 PM PDT 24
Peak memory 215964 kb
Host smart-58238ccf-48f5-489a-98e0-f8619d30f4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562266543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.3562266543
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.2396605853
Short name T618
Test name
Test status
Simulation time 81372515 ps
CPU time 2.98 seconds
Started May 05 02:30:49 PM PDT 24
Finished May 05 02:30:53 PM PDT 24
Peak memory 206464 kb
Host smart-ec958e27-1b8b-4d50-a782-7545d74d739c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396605853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.2396605853
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.3415588169
Short name T869
Test name
Test status
Simulation time 91095376 ps
CPU time 5.77 seconds
Started May 05 02:30:58 PM PDT 24
Finished May 05 02:31:05 PM PDT 24
Peak memory 222540 kb
Host smart-77125983-3a21-4504-b152-b77d513097ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415588169 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.3415588169
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.3547302284
Short name T205
Test name
Test status
Simulation time 46762358 ps
CPU time 3.07 seconds
Started May 05 02:30:55 PM PDT 24
Finished May 05 02:30:59 PM PDT 24
Peak memory 207212 kb
Host smart-f8d10089-0870-4845-b8a1-344a80dd9a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547302284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.3547302284
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.1441473327
Short name T56
Test name
Test status
Simulation time 54396674 ps
CPU time 2.42 seconds
Started May 05 02:30:59 PM PDT 24
Finished May 05 02:31:02 PM PDT 24
Peak memory 210184 kb
Host smart-ad87d105-24d4-4eed-a60d-f9fe3bf75e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441473327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.1441473327
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.3589952833
Short name T661
Test name
Test status
Simulation time 35857708 ps
CPU time 0.74 seconds
Started May 05 02:31:10 PM PDT 24
Finished May 05 02:31:11 PM PDT 24
Peak memory 205772 kb
Host smart-0413ee50-f636-4d55-8a12-329716580890
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589952833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.3589952833
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.936580651
Short name T127
Test name
Test status
Simulation time 48432703 ps
CPU time 3.55 seconds
Started May 05 02:31:04 PM PDT 24
Finished May 05 02:31:08 PM PDT 24
Peak memory 215164 kb
Host smart-fb2686bf-96aa-40c7-9cdf-1d3da390ebb1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=936580651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.936580651
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.568108172
Short name T815
Test name
Test status
Simulation time 112468424 ps
CPU time 2.84 seconds
Started May 05 02:31:02 PM PDT 24
Finished May 05 02:31:05 PM PDT 24
Peak memory 222264 kb
Host smart-21b53d60-d97c-47d3-a720-68a40dd9a2f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568108172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.568108172
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.789208204
Short name T331
Test name
Test status
Simulation time 75148992 ps
CPU time 3.73 seconds
Started May 05 02:31:01 PM PDT 24
Finished May 05 02:31:05 PM PDT 24
Peak memory 209940 kb
Host smart-edfcd893-e6bf-4274-a47c-f9d39099fe5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789208204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.789208204
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.1443605775
Short name T428
Test name
Test status
Simulation time 407610155 ps
CPU time 5.2 seconds
Started May 05 02:31:02 PM PDT 24
Finished May 05 02:31:08 PM PDT 24
Peak memory 209224 kb
Host smart-179529c9-d2eb-4210-b7fd-e219cf83c7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443605775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.1443605775
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.3961490366
Short name T146
Test name
Test status
Simulation time 77078101 ps
CPU time 1.7 seconds
Started May 05 02:30:56 PM PDT 24
Finished May 05 02:30:58 PM PDT 24
Peak memory 206660 kb
Host smart-c4f6d80f-c8ed-4d04-a397-774e6127f46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961490366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.3961490366
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.1926740522
Short name T534
Test name
Test status
Simulation time 1889378569 ps
CPU time 9.14 seconds
Started May 05 02:31:04 PM PDT 24
Finished May 05 02:31:13 PM PDT 24
Peak memory 208608 kb
Host smart-336976d9-f3ce-4164-90f9-459b1086db02
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926740522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.1926740522
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.1345751770
Short name T782
Test name
Test status
Simulation time 163224048 ps
CPU time 2.49 seconds
Started May 05 02:30:58 PM PDT 24
Finished May 05 02:31:01 PM PDT 24
Peak memory 208700 kb
Host smart-0973a20e-8655-43d0-a48e-80e98c88918f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345751770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.1345751770
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.1587206596
Short name T753
Test name
Test status
Simulation time 54120039 ps
CPU time 2.95 seconds
Started May 05 02:31:04 PM PDT 24
Finished May 05 02:31:07 PM PDT 24
Peak memory 208412 kb
Host smart-e04bef19-a6fe-4425-b067-68863721e9cc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587206596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.1587206596
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.3802338957
Short name T552
Test name
Test status
Simulation time 125760734 ps
CPU time 3.94 seconds
Started May 05 02:31:10 PM PDT 24
Finished May 05 02:31:14 PM PDT 24
Peak memory 214228 kb
Host smart-b8695544-c131-4fbf-9eb7-58523ced6a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802338957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.3802338957
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.1396951710
Short name T437
Test name
Test status
Simulation time 30757594 ps
CPU time 1.91 seconds
Started May 05 02:30:58 PM PDT 24
Finished May 05 02:31:01 PM PDT 24
Peak memory 208068 kb
Host smart-e28aeb73-9815-4763-8b3e-348c2c41cee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396951710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.1396951710
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.2172437873
Short name T781
Test name
Test status
Simulation time 177526386 ps
CPU time 5.15 seconds
Started May 05 02:31:03 PM PDT 24
Finished May 05 02:31:08 PM PDT 24
Peak memory 218248 kb
Host smart-a9a8dd6a-c6db-4707-b58f-e6d6ea51c8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172437873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.2172437873
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.1507652045
Short name T388
Test name
Test status
Simulation time 103265525 ps
CPU time 2.34 seconds
Started May 05 02:31:08 PM PDT 24
Finished May 05 02:31:10 PM PDT 24
Peak memory 209748 kb
Host smart-8c08b2fc-3d7d-4f50-9960-ce8d8d8c0b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507652045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.1507652045
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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