Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.58	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	74	256	77.58

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	55	225	80.36	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4931

1

T1

3

T3

4

T13

6

auto[1]

531

1

T13

2

T18

1

T27

1

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4931

1

T1

3

T3

4

T13

6

auto[1]

531

1

T13

2

T18

1

T27

1

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4888

1

T1

3

T3

4

T13

8

auto[1]

574

1

T16

1

T18

2

T27

1

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4888

1

T1

3

T3

4

T13

8

auto[1]

574

1

T16

1

T18

2

T27

1

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	450	1			T35	1		T49	9		T86	1
auto[OpGenId]	1119	1			T18	5		T25	1		T27	1
auto[OpGenSwOut]	1231	1			T1	1		T3	2		T17	3
auto[OpGenHwOut]	2605	1			T1	2		T3	2		T13	8
auto[OpDisable]	57	1			T16	1		T17	1		T48	3

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	450	1			T35	1		T49	9		T86	1
auto[OpGenId]	1119	1			T18	5		T25	1		T27	1
auto[OpGenSwOut]	1231	1			T1	1		T3	2		T17	3
auto[OpGenHwOut]	2605	1			T1	2		T3	2		T13	8
auto[OpDisable]	57	1			T16	1		T17	1		T48	3

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4891

1

T1

3

T3

3

T13

8

auto[1]

571

1

T3

1

T17

1

T80

3

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4891

1

T1

3

T3

3

T13

8

auto[1]

571

1

T3

1

T17

1

T80

3

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5143

1

T1

3

T3

4

T13

8

auto[1]

319

1

T132

6

T134

10

T172

3

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1908	1			T1	2		T3	1		T13	2
auto[1]	696	1			T3	1		T13	2		T16	1
auto[2]	733	1			T1	1		T3	1		T13	1
auto[3]	724	1			T3	1		T16	1		T18	2
auto[4]	374	1			T13	1		T17	1		T27	1
auto[5]	359	1			T13	1		T25	1		T35	2
auto[6]	324	1			T81	1		T48	1		T23	1
auto[7]	344	1			T13	1		T18	1		T35	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1401	1			T13	3		T17	1		T18	1
clear_one[1]	696	1			T3	1		T13	2		T16	1
clear_one[2]	733	1			T1	1		T3	1		T13	1
clear_one[3]	724	1			T3	1		T16	1		T18	2
clear_none	1908	1			T1	2		T3	1		T13	2

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1007	1			T1	3		T16	1		T18	7
auto[StInit]	682	1			T3	1		T13	1		T17	1
auto[StCreatorRootKey]	577	1			T13	1		T17	1		T18	1
auto[StOwnerIntKey]	534	1			T3	1		T13	1		T17	1
auto[StOwnerKey]	472	1			T13	1		T27	1		T81	1
auto[StDisabled]	1880	1			T3	2		T13	4		T16	2
auto[StInvalid]	310	1			T35	6		T36	7		T46	4

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1007	1			T1	3		T16	1		T18	7
auto[StInit]	682	1			T3	1		T13	1		T17	1
auto[StCreatorRootKey]	577	1			T13	1		T17	1		T18	1
auto[StOwnerIntKey]	534	1			T3	1		T13	1		T17	1
auto[StOwnerKey]	472	1			T13	1		T27	1		T81	1
auto[StDisabled]	1880	1			T3	2		T13	4		T16	2
auto[StInvalid]	310	1			T35	6		T36	7		T46	4

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	55	225	80.36	55

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	7
[auto[1] - auto[7]]	[auto[StReset]]	[auto[OpDisable]]	--	--	7
[auto[1] - auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	28
[auto[1] - auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	7

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	4	1			T219	1		T220	1		T221	1
auto[0]	auto[StReset]	auto[OpGenId]	153	1			T18	3		T48	1		T82	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	169	1			T1	1		T27	1		T98	3
auto[0]	auto[StReset]	auto[OpGenHwOut]	257	1			T1	1		T16	1		T18	1
auto[0]	auto[StInit]	auto[OpAdvance]	43	1			T49	1		T100	1		T24	1
auto[0]	auto[StInit]	auto[OpGenId]	90	1			T22	1		T49	1		T185	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	101	1			T17	1		T183	1		T23	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	191	1			T3	1		T13	1		T25	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	33	1			T49	1		T100	1		T70	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	59	1			T116	1		T117	1		T222	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	57	1			T49	1		T33	1		T100	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	80	1			T18	1		T223	1		T49	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	19	1			T19	1		T224	1		T202	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	25	1			T100	1		T115	1		T202	2
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	41	1			T17	1		T225	1		T226	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	50	1			T13	1		T86	1		T52	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	9	1			T181	1		T20	1		T227	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	15	1			T49	1		T98	1		T205	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	22	1			T49	1		T116	1		T177	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	52	1			T100	1		T175	1		T178	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	40	1			T49	4		T83	1		T100	1
auto[0]	auto[StDisabled]	auto[OpGenId]	61	1			T80	1		T116	1		T52	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	67	1			T80	1		T48	1		T179	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	166	1			T81	1		T193	2		T223	1
auto[0]	auto[StDisabled]	auto[OpDisable]	14	1			T48	1		T228	1		T73	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	15	1			T229	1		T85	1		T230	1
auto[0]	auto[StInvalid]	auto[OpGenId]	26	1			T35	1		T36	1		T46	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	24	1			T36	1		T229	1		T88	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	25	1			T46	2		T88	1		T231	1
auto[1]	auto[StReset]	auto[OpGenId]	21	1			T179	1		T68	1		T232	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	25	1			T18	1		T48	1		T52	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	38	1			T27	1		T193	1		T52	1
auto[1]	auto[StInit]	auto[OpAdvance]	7	1			T190	1		T29	1		T233	1
auto[1]	auto[StInit]	auto[OpGenId]	7	1			T224	1		T234	1		T93	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	7	1			T121	1		T76	1		T203	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	25	1			T48	1		T54	1		T235	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	8	1			T134	2		T189	1		T112	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T184	1		T98	1		T236	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	17	1			T183	1		T23	1		T237	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	39	1			T81	1		T178	1		T185	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	8	1			T190	1		T134	1		T112	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	13	1			T238	1		T239	1		T240	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	16	1			T63	1		T237	1		T241	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	34	1			T18	1		T116	1		T178	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T242	1		T243	1		T244	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	19	1			T134	1		T115	1		T245	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	14	1			T49	1		T68	1		T112	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	33	1			T223	1		T49	1		T63	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	25	1			T49	1		T100	2		T179	1
auto[1]	auto[StDisabled]	auto[OpGenId]	57	1			T49	1		T100	1		T94	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	73	1			T80	1		T82	1		T49	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	151	1			T3	1		T13	2		T48	1
auto[1]	auto[StDisabled]	auto[OpDisable]	9	1			T16	1		T202	1		T203	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	3	1			T246	1		T247	1		T248	1
auto[1]	auto[StInvalid]	auto[OpGenId]	13	1			T36	1		T37	1		T88	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	11	1			T35	1		T249	1		T250	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T87	1		T99	1		T251	1
auto[2]	auto[StReset]	auto[OpGenId]	26	1			T18	1		T49	1		T46	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	14	1			T119	1		T252	1		T253	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	58	1			T1	1		T193	1		T49	1
auto[2]	auto[StInit]	auto[OpAdvance]	4	1			T244	1		T216	1		T254	1
auto[2]	auto[StInit]	auto[OpGenId]	13	1			T30	1		T255	1		T5	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	14	1			T18	1		T136	1		T256	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	25	1			T23	1		T257	1		T8	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T216	1		T258	1		-	-
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	12	1			T27	1		T49	1		T6	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	14	1			T17	1		T48	1		T190	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	35	1			T193	1		T259	1		T260	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T49	1		T261	1		T262	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	12	1			T263	1		T112	1		T264	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	14	1			T3	1		T265	1		T112	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	45	1			T176	1		T259	1		T266	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	10	1			T132	1		T267	1		T236	3
auto[2]	auto[StOwnerKey]	auto[OpGenId]	8	1			T132	2		T268	1		T236	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	14	1			T190	1		T100	1		T115	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	40	1			T13	1		T193	1		T49	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	29	1			T86	1		T63	1		T132	1
auto[2]	auto[StDisabled]	auto[OpGenId]	45	1			T49	1		T98	1		T222	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	69	1			T98	1		T52	2		T113	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	163	1			T81	1		T183	1		T193	1
auto[2]	auto[StDisabled]	auto[OpDisable]	6	1			T232	1		T76	1		T203	2
auto[2]	auto[StInvalid]	auto[OpAdvance]	7	1			T35	1		T269	1		T270	1
auto[2]	auto[StInvalid]	auto[OpGenId]	14	1			T24	1		T271	1		T272	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	19	1			T24	1		T249	1		T250	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	15	1			T46	1		T249	1		T273	1
auto[3]	auto[StReset]	auto[OpGenId]	10	1			T18	1		T52	1		T228	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	17	1			T184	1		T52	1		T63	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	55	1			T26	1		T64	1		T178	2
auto[3]	auto[StInit]	auto[OpAdvance]	8	1			T185	1		T132	1		T122	1
auto[3]	auto[StInit]	auto[OpGenId]	12	1			T28	1		T228	1		T274	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	14	1			T26	1		T114	1		T252	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	28	1			T193	1		T98	1		T55	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	9	1			T275	1		T276	1		T59	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	14	1			T61	1		T52	1		T203	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	13	1			T52	1		T64	1		T4	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	38	1			T48	1		T195	1		T132	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T132	1		T171	1		T252	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	20	1			T49	1		T64	1		T100	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	20	1			T22	1		T100	1		T187	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	39	1			T48	1		T63	1		T194	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	9	1			T277	1		T122	1		T276	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	15	1			T6	1		T278	1		T279	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	18	1			T112	1		T76	1		T58	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	41	1			T27	1		T52	1		T100	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	22	1			T49	1		T100	1		T256	1
auto[3]	auto[StDisabled]	auto[OpGenId]	63	1			T22	1		T184	1		T49	2
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	70	1			T3	1		T80	1		T49	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	138	1			T16	1		T18	1		T223	1
auto[3]	auto[StDisabled]	auto[OpDisable]	9	1			T113	1		T5	2		T59	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	9	1			T199	1		T271	1		T85	1
auto[3]	auto[StInvalid]	auto[OpGenId]	7	1			T271	1		T280	1		T281	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T24	1		T55	1		T84	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	14	1			T88	1		T84	1		T230	1
auto[4]	auto[StReset]	auto[OpGenId]	10	1			T282	1		T283	1		T160	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	11	1			T232	1		T282	1		T239	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	25	1			T27	1		T113	1		T284	1
auto[4]	auto[StInit]	auto[OpAdvance]	3	1			T159	1		T203	1		T285	1
auto[4]	auto[StInit]	auto[OpGenId]	4	1			T100	1		T240	1		T286	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	6	1			T49	1		T236	1		T34	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	14	1			T48	1		T49	1		T63	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T287	1		T217	1		T288	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T112	1		T202	1		T181	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T289	1		T115	1		T76	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	20	1			T49	1		T187	1		T290	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T261	1		T291	1		T292	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	9	1			T293	1		T112	1		T294	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T203	1		T204	1		T60	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	18	1			T81	1		T295	1		T260	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	1	1			T296	1		-	-		-	-
auto[4]	auto[StOwnerKey]	auto[OpGenId]	11	1			T295	1		T297	1		T181	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T86	1		T261	1		T181	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	19	1			T259	1		T257	1		T68	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	11	1			T186	1		T121	1		T122	1
auto[4]	auto[StDisabled]	auto[OpGenId]	27	1			T185	1		T171	1		T118	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	36	1			T22	1		T98	1		T185	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	87	1			T13	1		T81	1		T223	1
auto[4]	auto[StDisabled]	auto[OpDisable]	4	1			T17	1		T298	1		T240	2
auto[4]	auto[StInvalid]	auto[OpAdvance]	2	1			T231	1		T299	1		-	-
auto[4]	auto[StInvalid]	auto[OpGenId]	5	1			T36	1		T229	1		T247	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T88	1		T300	1		T301	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	12	1			T229	1		T249	1		T99	1
auto[5]	auto[StReset]	auto[OpGenId]	10	1			T25	1		T49	1		T53	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	5	1			T32	1		T5	1		T236	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	19	1			T100	1		T179	1		T235	1
auto[5]	auto[StInit]	auto[OpAdvance]	2	1			T302	1		T303	1		-	-
auto[5]	auto[StInit]	auto[OpGenId]	7	1			T210	1		T304	1		T60	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	5	1			T240	1		T305	1		T306	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	12	1			T175	1		T307	1		T261	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T308	1		T60	1		T309	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	6	1			T54	1		T279	1		T208	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T48	1		T232	1		T34	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	18	1			T175	1		T310	1		T311	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T279	1		T312	1		T302	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	11	1			T183	1		T8	1		T283	2
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	4	1			T120	1		T240	1		T313	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	26	1			T80	1		T223	1		T314	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T59	1		T315	1		T316	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	10	1			T113	1		T5	1		T202	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T49	1		T317	1		T244	2
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	16	1			T318	1		T310	1		T314	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	8	1			T224	1		T160	1		T233	1
auto[5]	auto[StDisabled]	auto[OpGenId]	34	1			T49	1		T52	1		T177	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	29	1			T49	1		T319	1		T320	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	78	1			T13	1		T81	1		T117	1
auto[5]	auto[StDisabled]	auto[OpDisable]	5	1			T100	1		T240	1		T321	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	5	1			T36	1		T99	1		T282	1
auto[5]	auto[StInvalid]	auto[OpGenId]	7	1			T35	2		T272	1		T246	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	10	1			T36	1		T55	1		T322	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T323	1		T324	1		T325	1
auto[6]	auto[StReset]	auto[OpGenId]	5	1			T29	1		T326	1		T217	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	8	1			T63	1		T55	1		T327	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	29	1			T49	1		T175	1		T5	1
auto[6]	auto[StInit]	auto[OpAdvance]	3	1			T189	1		T224	1		T328	1
auto[6]	auto[StInit]	auto[OpGenId]	6	1			T52	1		T212	1		T329	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	7	1			T23	1		T100	1		T4	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	6	1			T290	1		T268	1		T330	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	1	1			T331	1		-	-		-	-
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	3	1			T332	1		T59	1		T333	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T115	1		T5	1		T206	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	13	1			T334	1		T335	1		T336	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T100	1		T196	1		T219	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T49	1		T76	1		T224	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	9	1			T48	1		T98	1		T179	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	26	1			T193	1		T195	1		T310	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T4	1		T121	1		T181	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	7	1			T64	1		T185	1		T71	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T185	1		T263	1		T4	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	20	1			T81	1		T260	1		T266	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	8	1			T337	1		T181	1		T338	1
auto[6]	auto[StDisabled]	auto[OpGenId]	27	1			T53	1		T187	1		T172	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	11	1			T239	1		T203	2		T279	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	77	1			T116	1		T100	3		T175	1
auto[6]	auto[StDisabled]	auto[OpDisable]	4	1			T60	1		T339	1		T340	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	2	1			T341	1		T342	1		-	-
auto[6]	auto[StInvalid]	auto[OpGenId]	10	1			T36	1		T37	1		T84	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T84	2		T269	1		T343	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T322	1		T90	1		T344	1
auto[7]	auto[StReset]	auto[OpGenId]	11	1			T8	1		T4	1		T5	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	6	1			T99	1		T30	1		T5	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	21	1			T193	1		T49	1		T178	2
auto[7]	auto[StInit]	auto[OpAdvance]	2	1			T58	1		T248	1		-	-
auto[7]	auto[StInit]	auto[OpGenId]	4	1			T58	1		T345	1		T254	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	4	1			T18	1		T115	1		T66	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	8	1			T178	1		T203	2		T283	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T43	1		T346	1		T216	2
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T5	1		T240	1		T60	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T98	1		T59	1		T328	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	19	1			T13	1		T176	1		T347	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T186	1		T90	1		T315	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	5	1			T202	1		T286	1		T212	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	10	1			T5	1		T121	1		T181	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	21	1			T311	1		T348	1		T180	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T289	1		T349	1		T221	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	2	1			T98	1		T5	1		-	-
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T49	1		T350	1		T351	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	23	1			T195	1		T290	1		T226	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	18	1			T83	1		T225	1		T76	2
auto[7]	auto[StDisabled]	auto[OpGenId]	22	1			T183	1		T237	1		T297	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	30	1			T86	2		T177	1		T173	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	81	1			T63	1		T195	2		T100	1
auto[7]	auto[StDisabled]	auto[OpDisable]	6	1			T48	2		T76	1		T203	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	5	1			T272	1		T352	1		T353	1
auto[7]	auto[StInvalid]	auto[OpGenId]	4	1			T35	1		T354	1		T355	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T269	1		T356	2		T281	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T87	1		T273	1		T357	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1401

1

T13

3

T17

1

T18

1

clear_one[1]

auto[0]

auto[0]

auto[0]

402

1

T13

2

T16

1

T18

1

clear_one[1]

auto[0]

auto[0]

auto[1]

123

1

T3

1

T80

1

T82

1

clear_one[1]

auto[0]

auto[1]

auto[0]

116

1

T18

1

T49

1

T63

1

clear_one[1]

auto[0]

auto[1]

auto[1]

55

1

T48

1

T49

1

T63

1

clear_one[2]

auto[0]

auto[0]

auto[0]

438

1

T1

1

T3

1

T17

1

clear_one[2]

auto[0]

auto[0]

auto[1]

126

1

T48

1

T49

1

T190

3

clear_one[2]

auto[1]

auto[0]

auto[0]

125

1

T13

1

T81

1

T193

3

clear_one[2]

auto[1]

auto[0]

auto[1]

44

1

T98

1

T222

1

T119

2

clear_one[3]

auto[0]

auto[0]

auto[0]

450

1

T3

1

T18

1

T26

2

clear_one[3]

auto[0]

auto[1]

auto[0]

120

1

T16

1

T48

1

T49

1

clear_one[3]

auto[1]

auto[0]

auto[0]

102

1

T48

1

T223

1

T49

1

clear_one[3]

auto[1]

auto[1]

auto[0]

52

1

T18

1

T27

1

T184

1

clear_none

auto[0]

auto[0]

auto[0]

1389

1

T1

2

T3

1

T13

1

clear_none

auto[0]

auto[0]

auto[1]

137

1

T17

1

T80

2

T49

1

clear_none

auto[0]

auto[1]

auto[0]

144

1

T48

1

T49

2

T52

2

clear_none

auto[0]

auto[1]

auto[1]

30

1

T189

1

T203

1

T90

1

clear_none

auto[1]

auto[0]

auto[0]

117

1

T13

1

T81

1

T193

2

clear_none

auto[1]

auto[0]

auto[1]

34

1

T33

1

T319

1

T4

1

clear_none

auto[1]

auto[1]

auto[0]

35

1

T185

1

T319

1

T4

1

clear_none

auto[1]

auto[1]

auto[1]

22

1

T49

1

T186

1

T4

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1318	1			T13	3		T17	1		T18	1
clear_all	auto[1]	83	1			T134	2		T172	3		T118	2
clear_one[1]	auto[0]	654	1			T3	1		T13	2		T16	1
clear_one[1]	auto[1]	42	1			T134	8		T119	2		T358	4
clear_one[2]	auto[0]	687	1			T1	1		T3	1		T13	1
clear_one[2]	auto[1]	46	1			T132	4		T119	2		T120	1
clear_one[3]	auto[0]	660	1			T3	1		T16	1		T18	2
clear_one[3]	auto[1]	64	1			T132	2		T122	4		T236	3
clear_none	auto[0]	1824	1			T1	2		T3	1		T13	2
clear_none	auto[1]	84	1			T118	3		T119	4		T122	6