Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11197

1

T1

17

T2

6

T3

3

auto[Attestation]

7815

1

T1

6

T2

5

T3

5

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2781	1			T1	1		T2	2		T16	3
auto[Aes]	3513	1			T1	4		T2	2		T3	1
auto[Kmac]	3377	1			T1	4		T2	1		T3	1
auto[Otbn]	3444	1			T1	5		T3	4		T16	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7803	1			T1	8		T2	3		T3	8
auto[OpGenId]	5897	1			T1	9		T2	6		T3	2
auto[OpGenSwOut]	6099	1			T1	8		T2	2		T3	4
auto[OpGenHwOut]	7016	1			T1	6		T2	3		T3	2
auto[OpDisable]	130	1			T16	1		T17	1		T26	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10749

1

T1

8

T2

8

T3

8

auto[OpDoneFail]

16196

1

T1

23

T2

6

T3

8

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6414	1			T1	16		T2	5		T3	1
auto[StInit]	3848	1			T1	2		T2	3		T3	2
auto[StCreatorRootKey]	3100	1			T1	2		T2	2		T3	2
auto[StOwnerIntKey]	2827	1			T1	2		T2	4		T3	2
auto[StOwnerKey]	2583	1			T1	2		T3	2		T13	2
auto[StDisabled]	8173	1			T1	7		T3	7		T13	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	297	1			T2	1		T18	1		T26	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	130	1			T18	2		T26	1		T82	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	77	1			T48	1		T183	1		T49	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	86	1			T17	1		T25	1		T184	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	75	1			T48	1		T49	1		T98	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	228	1			T17	1		T27	1		T48	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	303	1			T1	2		T18	2		T27	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	106	1			T16	1		T80	1		T48	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	101	1			T17	1		T49	3		T185	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	83	1			T48	1		T184	1		T117	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	73	1			T48	2		T184	1		T49	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	256	1			T27	1		T48	3		T22	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	329	1			T1	4		T2	1		T16	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	107	1			T17	2		T26	1		T49	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	84	1			T48	1		T49	2		T186	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	72	1			T3	1		T183	1		T61	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	70	1			T80	1		T22	1		T183	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	241	1			T27	1		T48	1		T82	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	292	1			T1	1		T16	1		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	95	1			T25	1		T80	2		T48	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	82	1			T48	1		T82	1		T49	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	64	1			T184	1		T49	1		T187	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	52	1			T48	1		T49	2		T188	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	213	1			T27	1		T48	2		T82	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	78	1			T48	1		T71	1		T114	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	108	1			T23	1		T186	1		T24	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	78	1			T48	1		T183	1		T49	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	73	1			T22	1		T49	1		T63	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	64	1			T100	1		T177	1		T70	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	229	1			T48	2		T184	1		T49	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	69	1			T48	2		T49	1		T113	4
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	104	1			T183	1		T23	1		T49	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	79	1			T48	1		T23	1		T98	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	71	1			T18	1		T98	1		T54	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	61	1			T49	1		T189	1		T112	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	242	1			T3	1		T18	1		T80	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	73	1			T48	2		T49	2		T185	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	103	1			T48	1		T23	2		T49	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	92	1			T17	1		T27	1		T48	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	80	1			T25	1		T48	1		T98	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	51	1			T22	1		T49	1		T100	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	213	1			T27	1		T80	3		T49	5
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	88	1			T48	1		T55	2		T185	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	109	1			T184	1		T23	1		T49	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	97	1			T17	1		T98	1		T52	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	92	1			T18	1		T25	1		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	76	1			T80	1		T48	2		T49	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	253	1			T1	1		T3	2		T26	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	297	1			T16	3		T18	1		T26	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	110	1			T25	1		T61	1		T23	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	79	1			T27	1		T98	1		T190	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	59	1			T49	1		T191	1		T115	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	53	1			T98	1		T86	1		T52	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	169	1			T1	1		T48	1		T183	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	509	1			T1	1		T18	2		T26	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	129	1			T13	1		T81	1		T61	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	93	1			T25	1		T49	2		T192	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	89	1			T2	1		T13	1		T25	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	87	1			T13	1		T193	1		T49	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	266	1			T13	1		T18	1		T27	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	431	1			T16	1		T18	1		T26	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	122	1			T80	1		T48	1		T61	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	81	1			T48	1		T49	1		T192	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	97	1			T18	1		T27	1		T23	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	102	1			T48	2		T184	1		T194	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	302	1			T27	1		T49	7		T98	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	472	1			T1	3		T18	1		T25	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	123	1			T3	1		T184	1		T49	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	100	1			T192	1		T33	1		T195	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	93	1			T17	1		T80	1		T82	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	93	1			T27	1		T80	1		T184	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	271	1			T27	1		T80	2		T48	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	50	1			T48	1		T55	1		T4	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	87	1			T48	1		T23	1		T49	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	59	1			T18	1		T49	1		T196	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	71	1			T2	1		T49	1		T98	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	44	1			T27	1		T49	2		T98	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	180	1			T17	1		T18	1		T48	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	52	1			T48	1		T49	1		T55	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	138	1			T2	1		T18	1		T48	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	117	1			T13	1		T81	1		T48	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	108	1			T25	1		T81	1		T48	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	93	1			T27	1		T81	1		T22	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	284	1			T1	1		T13	3		T27	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	61	1			T71	1		T113	2		T4	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	112	1			T27	2		T49	1		T63	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	100	1			T49	3		T192	1		T186	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	87	1			T27	1		T23	1		T52	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	85	1			T18	1		T49	2		T63	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	282	1			T16	1		T22	1		T183	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	50	1			T49	2		T185	1		T71	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	135	1			T80	1		T48	1		T22	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	114	1			T48	1		T49	1		T192	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	81	1			T86	1		T52	1		T63	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	100	1			T184	1		T49	3		T100	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	299	1			T3	1		T27	2		T48	2

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	222	1			T17	1		T25	1		T48	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	671	1			T2	1		T17	1		T18	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	230	1			T17	1		T48	3		T184	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	692	1			T1	2		T16	1		T18	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	209	1			T3	1		T80	1		T48	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	694	1			T1	4		T2	1		T16	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	186	1			T48	2		T82	1		T184	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	612	1			T1	1		T16	1		T25	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	200	1			T48	1		T22	1		T183	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	430	1			T48	3		T184	1		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	189	1			T18	1		T48	1		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	437	1			T3	1		T18	1		T80	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	207	1			T17	1		T25	1		T27	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	405	1			T27	1		T80	3		T48	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	242	1			T17	1		T18	1		T25	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	473	1			T1	1		T3	2		T26	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	177	1			T49	1		T98	2		T86	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	590	1			T1	1		T16	3		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	256	1			T2	1		T13	2		T25	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	917	1			T1	1		T13	2		T18	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	265	1			T18	1		T27	1		T48	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	870	1			T16	1		T18	1		T26	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	269	1			T17	1		T27	1		T80	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	883	1			T1	3		T3	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	161	1			T2	1		T18	1		T27	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	330	1			T17	1		T18	1		T48	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	297	1			T13	1		T25	1		T27	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	495	1			T1	1		T2	1		T13	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	262	1			T18	1		T27	1		T23	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	465	1			T16	1		T27	2		T22	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	281	1			T48	1		T184	1		T49	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	498	1			T3	1		T27	2		T80	1