Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33281

1

T1

33

T2

15

T3

20

auto[1]

341

1

T132

9

T134

9

T172

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	33287	1			T1	33		T2	15		T3	20
auto[134217728:268435455]	14	1			T132	1		T119	2		T122	1
auto[268435456:402653183]	12	1			T132	1		T134	3		T122	1
auto[402653184:536870911]	13	1			T134	1		T119	1		T122	2
auto[536870912:671088639]	17	1			T132	3		T283	1		T219	1
auto[671088640:805306367]	10	1			T119	1		T122	1		T219	1
auto[805306368:939524095]	7	1			T118	1		T283	1		T349	1
auto[939524096:1073741823]	8	1			T219	1		T358	1		T398	1
auto[1073741824:1207959551]	12	1			T399	2		T308	1		T400	1
auto[1207959552:1342177279]	7	1			T349	1		T401	1		T381	1
auto[1342177280:1476395007]	10	1			T119	1		T283	1		T233	1
auto[1476395008:1610612735]	11	1			T132	1		T236	1		T219	1
auto[1610612736:1744830463]	11	1			T308	1		T220	1		T401	1
auto[1744830464:1879048191]	11	1			T172	1		T122	1		T236	1
auto[1879048192:2013265919]	10	1			T134	1		T122	1		T399	1
auto[2013265920:2147483647]	11	1			T132	1		T134	1		T122	1
auto[2147483648:2281701375]	16	1			T134	1		T119	1		T122	1
auto[2281701376:2415919103]	12	1			T236	1		T224	1		T256	1
auto[2415919104:2550136831]	10	1			T233	2		T402	1		T291	1
auto[2550136832:2684354559]	8	1			T278	1		T308	2		T381	1
auto[2684354560:2818572287]	10	1			T132	1		T119	1		T120	1
auto[2818572288:2952790015]	12	1			T399	1		T308	1		T219	1
auto[2952790016:3087007743]	7	1			T119	1		T233	3		T403	1
auto[3087007744:3221225471]	13	1			T120	1		T236	1		T358	1
auto[3221225472:3355443199]	13	1			T118	1		T122	1		T399	3
auto[3355443200:3489660927]	6	1			T134	1		T404	1		T382	1
auto[3489660928:3623878655]	7	1			T120	1		T308	1		T405	1
auto[3623878656:3758096383]	10	1			T134	1		T172	1		T236	1
auto[3758096384:3892314111]	14	1			T119	1		T224	1		T399	1
auto[3892314112:4026531839]	12	1			T122	1		T236	1		T283	1
auto[4026531840:4160749567]	10	1			T132	1		T118	1		T119	1
auto[4160749568:4294967295]	11	1			T119	1		T236	1		T224	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	33281	1			T1	33		T2	15		T3	20
auto[0:134217727]	auto[1]	6	1			T401	1		T378	1		T406	1
auto[134217728:268435455]	auto[1]	14	1			T132	1		T119	2		T122	1
auto[268435456:402653183]	auto[1]	12	1			T132	1		T134	3		T122	1
auto[402653184:536870911]	auto[1]	13	1			T134	1		T119	1		T122	2
auto[536870912:671088639]	auto[1]	17	1			T132	3		T283	1		T219	1
auto[671088640:805306367]	auto[1]	10	1			T119	1		T122	1		T219	1
auto[805306368:939524095]	auto[1]	7	1			T118	1		T283	1		T349	1
auto[939524096:1073741823]	auto[1]	8	1			T219	1		T358	1		T398	1
auto[1073741824:1207959551]	auto[1]	12	1			T399	2		T308	1		T400	1
auto[1207959552:1342177279]	auto[1]	7	1			T349	1		T401	1		T381	1
auto[1342177280:1476395007]	auto[1]	10	1			T119	1		T283	1		T233	1
auto[1476395008:1610612735]	auto[1]	11	1			T132	1		T236	1		T219	1
auto[1610612736:1744830463]	auto[1]	11	1			T308	1		T220	1		T401	1
auto[1744830464:1879048191]	auto[1]	11	1			T172	1		T122	1		T236	1
auto[1879048192:2013265919]	auto[1]	10	1			T134	1		T122	1		T399	1
auto[2013265920:2147483647]	auto[1]	11	1			T132	1		T134	1		T122	1
auto[2147483648:2281701375]	auto[1]	16	1			T134	1		T119	1		T122	1
auto[2281701376:2415919103]	auto[1]	12	1			T236	1		T224	1		T256	1
auto[2415919104:2550136831]	auto[1]	10	1			T233	2		T402	1		T291	1
auto[2550136832:2684354559]	auto[1]	8	1			T278	1		T308	2		T381	1
auto[2684354560:2818572287]	auto[1]	10	1			T132	1		T119	1		T120	1
auto[2818572288:2952790015]	auto[1]	12	1			T399	1		T308	1		T219	1
auto[2952790016:3087007743]	auto[1]	7	1			T119	1		T233	3		T403	1
auto[3087007744:3221225471]	auto[1]	13	1			T120	1		T236	1		T358	1
auto[3221225472:3355443199]	auto[1]	13	1			T118	1		T122	1		T399	3
auto[3355443200:3489660927]	auto[1]	6	1			T134	1		T404	1		T382	1
auto[3489660928:3623878655]	auto[1]	7	1			T120	1		T308	1		T405	1
auto[3623878656:3758096383]	auto[1]	10	1			T134	1		T172	1		T236	1
auto[3758096384:3892314111]	auto[1]	14	1			T119	1		T224	1		T399	1
auto[3892314112:4026531839]	auto[1]	12	1			T122	1		T236	1		T283	1
auto[4026531840:4160749567]	auto[1]	10	1			T132	1		T118	1		T119	1
auto[4160749568:4294967295]	auto[1]	11	1			T119	1		T236	1		T224	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1659

1

T18

3

T25

1

T26

2

auto[1]

1827

1

T15

1

T25

2

T26

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	103	1			T49	2		T52	1		T46	1
auto[134217728:268435455]	123	1			T35	1		T80	1		T184	2
auto[268435456:402653183]	109	1			T80	1		T48	1		T49	3
auto[402653184:536870911]	119	1			T49	2		T83	1		T46	1
auto[536870912:671088639]	96	1			T49	1		T52	1		T54	1
auto[671088640:805306367]	106	1			T27	1		T48	1		T184	2
auto[805306368:939524095]	123	1			T25	1		T35	1		T48	1
auto[939524096:1073741823]	100	1			T49	1		T52	1		T100	1
auto[1073741824:1207959551]	113	1			T48	1		T23	1		T49	3
auto[1207959552:1342177279]	87	1			T18	1		T48	1		T49	1
auto[1342177280:1476395007]	107	1			T49	1		T98	1		T63	1
auto[1476395008:1610612735]	107	1			T48	1		T184	1		T23	1
auto[1610612736:1744830463]	90	1			T49	1		T63	2		T186	1
auto[1744830464:1879048191]	109	1			T26	1		T27	1		T48	1
auto[1879048192:2013265919]	112	1			T48	1		T49	2		T98	1
auto[2013265920:2147483647]	114	1			T26	1		T48	1		T86	1
auto[2147483648:2281701375]	113	1			T18	1		T48	1		T61	1
auto[2281701376:2415919103]	115	1			T80	1		T49	3		T98	1
auto[2415919104:2550136831]	95	1			T35	2		T48	1		T183	1
auto[2550136832:2684354559]	117	1			T25	1		T22	1		T49	2
auto[2684354560:2818572287]	109	1			T35	1		T49	4		T98	1
auto[2818572288:2952790015]	92	1			T18	1		T48	2		T49	1
auto[2952790016:3087007743]	117	1			T48	2		T22	1		T49	1
auto[3087007744:3221225471]	115	1			T22	1		T184	1		T52	1
auto[3221225472:3355443199]	119	1			T15	1		T25	1		T48	1
auto[3355443200:3489660927]	104	1			T183	1		T184	1		T49	3
auto[3489660928:3623878655]	115	1			T35	1		T184	1		T63	1
auto[3623878656:3758096383]	109	1			T26	1		T48	1		T49	3
auto[3758096384:3892314111]	113	1			T26	1		T80	1		T184	1
auto[3892314112:4026531839]	112	1			T48	1		T184	1		T23	1
auto[4026531840:4160749567]	120	1			T27	1		T49	2		T52	1
auto[4160749568:4294967295]	103	1			T184	1		T49	1		T83	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	42	1			T46	1		T64	1		T43	1
auto[0:134217727]	auto[1]	61	1			T49	2		T52	1		T32	1
auto[134217728:268435455]	auto[0]	64	1			T35	1		T80	1		T184	1
auto[134217728:268435455]	auto[1]	59	1			T184	1		T98	2		T71	1
auto[268435456:402653183]	auto[0]	50	1			T80	1		T49	1		T52	1
auto[268435456:402653183]	auto[1]	59	1			T48	1		T49	2		T190	1
auto[402653184:536870911]	auto[0]	62	1			T49	1		T46	1		T54	1
auto[402653184:536870911]	auto[1]	57	1			T49	1		T83	1		T190	1
auto[536870912:671088639]	auto[0]	51	1			T49	1		T54	1		T229	1
auto[536870912:671088639]	auto[1]	45	1			T52	1		T273	1		T337	1
auto[671088640:805306367]	auto[0]	44	1			T184	2		T100	1		T54	1
auto[671088640:805306367]	auto[1]	62	1			T27	1		T48	1		T49	4
auto[805306368:939524095]	auto[0]	54	1			T35	1		T49	1		T98	1
auto[805306368:939524095]	auto[1]	69	1			T25	1		T48	1		T63	1
auto[939524096:1073741823]	auto[0]	46	1			T70	1		T185	2		T187	1
auto[939524096:1073741823]	auto[1]	54	1			T49	1		T52	1		T100	1
auto[1073741824:1207959551]	auto[0]	48	1			T23	1		T49	2		T199	1
auto[1073741824:1207959551]	auto[1]	65	1			T48	1		T49	1		T37	2
auto[1207959552:1342177279]	auto[0]	45	1			T18	1		T49	1		T98	1
auto[1207959552:1342177279]	auto[1]	42	1			T48	1		T98	1		T100	1
auto[1342177280:1476395007]	auto[0]	43	1			T98	1		T179	1		T187	1
auto[1342177280:1476395007]	auto[1]	64	1			T49	1		T63	1		T55	1
auto[1476395008:1610612735]	auto[0]	60	1			T23	1		T24	1		T50	1
auto[1476395008:1610612735]	auto[1]	47	1			T48	1		T184	1		T52	1
auto[1610612736:1744830463]	auto[0]	45	1			T63	2		T186	1		T179	1
auto[1610612736:1744830463]	auto[1]	45	1			T49	1		T237	1		T88	1
auto[1744830464:1879048191]	auto[0]	50	1			T22	1		T86	1		T63	1
auto[1744830464:1879048191]	auto[1]	59	1			T26	1		T27	1		T48	1
auto[1879048192:2013265919]	auto[0]	55	1			T186	2		T33	1		T64	1
auto[1879048192:2013265919]	auto[1]	57	1			T48	1		T49	2		T98	1
auto[2013265920:2147483647]	auto[0]	64	1			T26	1		T48	1		T192	1
auto[2013265920:2147483647]	auto[1]	50	1			T86	1		T117	1		T100	1
auto[2147483648:2281701375]	auto[0]	55	1			T18	1		T100	1		T179	1
auto[2147483648:2281701375]	auto[1]	58	1			T48	1		T61	1		T43	1
auto[2281701376:2415919103]	auto[0]	59	1			T80	1		T49	1		T53	1
auto[2281701376:2415919103]	auto[1]	56	1			T49	2		T98	1		T56	1
auto[2415919104:2550136831]	auto[0]	46	1			T35	2		T98	1		T64	1
auto[2415919104:2550136831]	auto[1]	49	1			T48	1		T183	1		T49	1
auto[2550136832:2684354559]	auto[0]	49	1			T22	1		T49	2		T32	1
auto[2550136832:2684354559]	auto[1]	68	1			T25	1		T100	2		T54	1
auto[2684354560:2818572287]	auto[0]	53	1			T35	1		T86	1		T36	1
auto[2684354560:2818572287]	auto[1]	56	1			T49	4		T98	1		T52	1
auto[2818572288:2952790015]	auto[0]	35	1			T18	1		T55	1		T50	1
auto[2818572288:2952790015]	auto[1]	57	1			T48	2		T49	1		T100	3
auto[2952790016:3087007743]	auto[0]	57	1			T48	1		T98	1		T179	1
auto[2952790016:3087007743]	auto[1]	60	1			T48	1		T22	1		T49	1
auto[3087007744:3221225471]	auto[0]	56	1			T184	1		T186	1		T100	3
auto[3087007744:3221225471]	auto[1]	59	1			T22	1		T52	1		T100	1
auto[3221225472:3355443199]	auto[0]	47	1			T25	1		T23	1		T49	2
auto[3221225472:3355443199]	auto[1]	72	1			T15	1		T48	1		T63	2
auto[3355443200:3489660927]	auto[0]	55	1			T183	1		T184	1		T49	1
auto[3355443200:3489660927]	auto[1]	49	1			T49	2		T63	1		T188	1
auto[3489660928:3623878655]	auto[0]	55	1			T35	1		T184	1		T63	1
auto[3489660928:3623878655]	auto[1]	60	1			T92	1		T99	2		T71	1
auto[3623878656:3758096383]	auto[0]	57	1			T26	1		T49	1		T190	1
auto[3623878656:3758096383]	auto[1]	52	1			T48	1		T49	2		T86	1
auto[3758096384:3892314111]	auto[0]	55	1			T80	1		T52	1		T63	1
auto[3758096384:3892314111]	auto[1]	58	1			T26	1		T184	1		T49	1
auto[3892314112:4026531839]	auto[0]	54	1			T48	1		T23	1		T49	1
auto[3892314112:4026531839]	auto[1]	58	1			T184	1		T54	1		T55	1
auto[4026531840:4160749567]	auto[0]	52	1			T36	1		T46	1		T37	1
auto[4026531840:4160749567]	auto[1]	68	1			T27	1		T49	2		T52	1
auto[4160749568:4294967295]	auto[0]	51	1			T184	1		T49	1		T56	1
auto[4160749568:4294967295]	auto[1]	52	1			T83	1		T187	1		T30	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1601

1

T18

3

T25

2

T26

2

auto[1]

1886

1

T15

1

T25

1

T26

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	111	1			T80	1		T184	1		T23	1
auto[134217728:268435455]	103	1			T86	1		T192	1		T190	1
auto[268435456:402653183]	106	1			T48	1		T49	1		T37	1
auto[402653184:536870911]	113	1			T80	1		T48	1		T49	1
auto[536870912:671088639]	111	1			T49	1		T52	1		T188	1
auto[671088640:805306367]	109	1			T49	3		T98	2		T190	1
auto[805306368:939524095]	119	1			T48	1		T23	1		T98	2
auto[939524096:1073741823]	104	1			T22	1		T49	2		T98	1
auto[1073741824:1207959551]	106	1			T18	1		T49	3		T186	1
auto[1207959552:1342177279]	95	1			T80	1		T183	1		T86	1
auto[1342177280:1476395007]	110	1			T15	1		T48	2		T183	1
auto[1476395008:1610612735]	112	1			T35	1		T48	1		T184	2
auto[1610612736:1744830463]	104	1			T63	1		T100	1		T55	1
auto[1744830464:1879048191]	104	1			T25	1		T26	1		T48	1
auto[1879048192:2013265919]	104	1			T18	1		T48	1		T49	2
auto[2013265920:2147483647]	126	1			T25	1		T27	1		T35	1
auto[2147483648:2281701375]	111	1			T184	2		T49	2		T98	1
auto[2281701376:2415919103]	95	1			T26	1		T48	1		T49	3
auto[2415919104:2550136831]	108	1			T184	1		T23	1		T49	1
auto[2550136832:2684354559]	131	1			T25	1		T52	1		T32	1
auto[2684354560:2818572287]	109	1			T46	1		T186	1		T100	2
auto[2818572288:2952790015]	100	1			T27	1		T35	1		T49	2
auto[2952790016:3087007743]	119	1			T48	1		T49	2		T63	1
auto[3087007744:3221225471]	112	1			T35	1		T184	1		T49	1
auto[3221225472:3355443199]	101	1			T48	1		T22	1		T49	1
auto[3355443200:3489660927]	114	1			T18	1		T22	2		T49	1
auto[3489660928:3623878655]	111	1			T49	5		T63	1		T43	2
auto[3623878656:3758096383]	104	1			T26	1		T27	1		T61	1
auto[3758096384:3892314111]	94	1			T35	2		T80	1		T48	1
auto[3892314112:4026531839]	103	1			T48	1		T23	1		T98	1
auto[4026531840:4160749567]	126	1			T26	1		T49	2		T98	1
auto[4160749568:4294967295]	112	1			T48	2		T184	1		T49	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	56	1			T23	1		T49	2		T46	1
auto[0:134217727]	auto[1]	55	1			T80	1		T184	1		T49	2
auto[134217728:268435455]	auto[0]	42	1			T64	1		T43	1		T99	1
auto[134217728:268435455]	auto[1]	61	1			T86	1		T192	1		T190	1
auto[268435456:402653183]	auto[0]	40	1			T49	1		T180	1		T71	1
auto[268435456:402653183]	auto[1]	66	1			T48	1		T37	1		T179	1
auto[402653184:536870911]	auto[0]	47	1			T80	1		T36	1		T199	1
auto[402653184:536870911]	auto[1]	66	1			T48	1		T49	1		T98	2
auto[536870912:671088639]	auto[0]	53	1			T272	1		T112	1		T119	1
auto[536870912:671088639]	auto[1]	58	1			T49	1		T52	1		T188	1
auto[671088640:805306367]	auto[0]	52	1			T49	2		T98	2		T99	1
auto[671088640:805306367]	auto[1]	57	1			T49	1		T190	1		T100	2
auto[805306368:939524095]	auto[0]	55	1			T23	1		T98	1		T86	1
auto[805306368:939524095]	auto[1]	64	1			T48	1		T98	1		T188	1
auto[939524096:1073741823]	auto[0]	46	1			T49	2		T98	1		T100	1
auto[939524096:1073741823]	auto[1]	58	1			T22	1		T188	1		T187	1
auto[1073741824:1207959551]	auto[0]	43	1			T18	1		T100	1		T179	1
auto[1073741824:1207959551]	auto[1]	63	1			T49	3		T186	1		T177	1
auto[1207959552:1342177279]	auto[0]	35	1			T80	1		T100	1		T43	1
auto[1207959552:1342177279]	auto[1]	60	1			T183	1		T86	1		T63	2
auto[1342177280:1476395007]	auto[0]	42	1			T48	1		T183	1		T33	1
auto[1342177280:1476395007]	auto[1]	68	1			T15	1		T48	1		T184	1
auto[1476395008:1610612735]	auto[0]	58	1			T35	1		T48	1		T184	1
auto[1476395008:1610612735]	auto[1]	54	1			T184	1		T49	1		T52	1
auto[1610612736:1744830463]	auto[0]	55	1			T100	1		T55	1		T51	1
auto[1610612736:1744830463]	auto[1]	49	1			T63	1		T118	1		T4	1
auto[1744830464:1879048191]	auto[0]	49	1			T184	1		T49	2		T53	1
auto[1744830464:1879048191]	auto[1]	55	1			T25	1		T26	1		T48	1
auto[1879048192:2013265919]	auto[0]	58	1			T18	1		T49	1		T46	1
auto[1879048192:2013265919]	auto[1]	46	1			T48	1		T49	1		T100	1
auto[2013265920:2147483647]	auto[0]	63	1			T25	1		T35	1		T48	1
auto[2013265920:2147483647]	auto[1]	63	1			T27	1		T48	2		T49	1
auto[2147483648:2281701375]	auto[0]	52	1			T184	2		T49	1		T63	1
auto[2147483648:2281701375]	auto[1]	59	1			T49	1		T98	1		T63	1
auto[2281701376:2415919103]	auto[0]	40	1			T100	1		T50	1		T319	1
auto[2281701376:2415919103]	auto[1]	55	1			T26	1		T48	1		T49	3
auto[2415919104:2550136831]	auto[0]	50	1			T184	1		T23	1		T63	1
auto[2415919104:2550136831]	auto[1]	58	1			T49	1		T52	1		T63	1
auto[2550136832:2684354559]	auto[0]	60	1			T25	1		T32	1		T100	1
auto[2550136832:2684354559]	auto[1]	71	1			T52	1		T132	1		T187	1
auto[2684354560:2818572287]	auto[0]	57	1			T46	1		T186	1		T100	1
auto[2684354560:2818572287]	auto[1]	52	1			T100	1		T71	1		T73	1
auto[2818572288:2952790015]	auto[0]	41	1			T35	1		T49	1		T179	2
auto[2818572288:2952790015]	auto[1]	59	1			T27	1		T49	1		T83	1
auto[2952790016:3087007743]	auto[0]	55	1			T49	2		T46	2		T100	1
auto[2952790016:3087007743]	auto[1]	64	1			T48	1		T63	1		T222	1
auto[3087007744:3221225471]	auto[0]	54	1			T184	1		T49	1		T32	1
auto[3087007744:3221225471]	auto[1]	58	1			T35	1		T186	1		T37	1
auto[3221225472:3355443199]	auto[0]	52	1			T22	1		T185	1		T113	1
auto[3221225472:3355443199]	auto[1]	49	1			T48	1		T49	1		T83	1
auto[3355443200:3489660927]	auto[0]	52	1			T18	1		T22	2		T64	1
auto[3355443200:3489660927]	auto[1]	62	1			T49	1		T37	1		T53	1
auto[3489660928:3623878655]	auto[0]	47	1			T49	1		T185	2		T132	1
auto[3489660928:3623878655]	auto[1]	64	1			T49	4		T63	1		T43	2
auto[3623878656:3758096383]	auto[0]	40	1			T26	1		T184	1		T98	1
auto[3623878656:3758096383]	auto[1]	64	1			T27	1		T61	1		T49	2
auto[3758096384:3892314111]	auto[0]	52	1			T35	2		T80	1		T37	1
auto[3758096384:3892314111]	auto[1]	42	1			T48	1		T49	1		T52	1
auto[3892314112:4026531839]	auto[0]	49	1			T23	1		T86	1		T52	1
auto[3892314112:4026531839]	auto[1]	54	1			T48	1		T98	1		T37	1
auto[4026531840:4160749567]	auto[0]	59	1			T26	1		T64	1		T24	1
auto[4026531840:4160749567]	auto[1]	67	1			T49	2		T98	1		T37	1
auto[4160749568:4294967295]	auto[0]	47	1			T186	1		T70	1		T44	1
auto[4160749568:4294967295]	auto[1]	65	1			T48	2		T184	1		T49	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1601

1

T18

3

T25

1

T26

2

auto[1]

1885

1

T15

1

T25

2

T26

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	125	1			T25	1		T49	2		T98	1
auto[134217728:268435455]	98	1			T23	1		T49	1		T98	2
auto[268435456:402653183]	105	1			T48	1		T98	1		T86	1
auto[402653184:536870911]	106	1			T49	1		T86	1		T190	1
auto[536870912:671088639]	107	1			T184	1		T49	1		T100	1
auto[671088640:805306367]	126	1			T80	1		T48	2		T86	1
auto[805306368:939524095]	106	1			T48	1		T184	1		T49	1
auto[939524096:1073741823]	103	1			T48	1		T49	2		T52	1
auto[1073741824:1207959551]	96	1			T26	1		T27	1		T80	1
auto[1207959552:1342177279]	117	1			T49	2		T190	1		T37	1
auto[1342177280:1476395007]	124	1			T18	1		T26	2		T22	1
auto[1476395008:1610612735]	115	1			T18	1		T48	1		T184	1
auto[1610612736:1744830463]	101	1			T25	1		T48	1		T61	1
auto[1744830464:1879048191]	86	1			T80	1		T48	1		T49	2
auto[1879048192:2013265919]	119	1			T184	1		T49	1		T33	1
auto[2013265920:2147483647]	87	1			T35	1		T48	1		T184	1
auto[2147483648:2281701375]	130	1			T18	1		T48	1		T183	1
auto[2281701376:2415919103]	113	1			T46	1		T177	1		T199	1
auto[2415919104:2550136831]	92	1			T48	2		T23	1		T49	1
auto[2550136832:2684354559]	102	1			T35	1		T22	1		T184	1
auto[2684354560:2818572287]	101	1			T48	2		T49	3		T98	1
auto[2818572288:2952790015]	116	1			T49	2		T98	1		T100	2
auto[2952790016:3087007743]	120	1			T25	1		T49	1		T63	1
auto[3087007744:3221225471]	107	1			T27	1		T48	1		T22	1
auto[3221225472:3355443199]	116	1			T35	1		T48	1		T184	1
auto[3355443200:3489660927]	95	1			T80	1		T46	1		T100	1
auto[3489660928:3623878655]	105	1			T35	1		T184	3		T49	1
auto[3623878656:3758096383]	110	1			T48	1		T23	1		T49	2
auto[3758096384:3892314111]	104	1			T15	1		T48	1		T23	1
auto[3892314112:4026531839]	113	1			T26	1		T183	1		T49	3
auto[4026531840:4160749567]	117	1			T35	1		T49	1		T52	1
auto[4160749568:4294967295]	124	1			T27	1		T35	1		T49	3

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	60	1			T49	1		T46	1		T33	1
auto[0:134217727]	auto[1]	65	1			T25	1		T49	1		T98	1
auto[134217728:268435455]	auto[0]	42	1			T23	1		T49	1		T98	1
auto[134217728:268435455]	auto[1]	56	1			T98	1		T53	1		T187	1
auto[268435456:402653183]	auto[0]	46	1			T48	1		T86	1		T46	1
auto[268435456:402653183]	auto[1]	59	1			T98	1		T52	3		T100	2
auto[402653184:536870911]	auto[0]	41	1			T86	1		T185	1		T51	1
auto[402653184:536870911]	auto[1]	65	1			T49	1		T190	1		T37	2
auto[536870912:671088639]	auto[0]	54	1			T184	1		T49	1		T100	1
auto[536870912:671088639]	auto[1]	53	1			T99	1		T73	1		T273	1
auto[671088640:805306367]	auto[0]	62	1			T48	2		T100	2		T43	1
auto[671088640:805306367]	auto[1]	64	1			T80	1		T86	1		T63	3
auto[805306368:939524095]	auto[0]	51	1			T48	1		T94	1		T133	1
auto[805306368:939524095]	auto[1]	55	1			T184	1		T49	1		T37	1
auto[939524096:1073741823]	auto[0]	43	1			T49	2		T100	1		T185	1
auto[939524096:1073741823]	auto[1]	60	1			T48	1		T52	1		T68	1
auto[1073741824:1207959551]	auto[0]	39	1			T80	1		T49	2		T237	1
auto[1073741824:1207959551]	auto[1]	57	1			T26	1		T27	1		T22	1
auto[1207959552:1342177279]	auto[0]	52	1			T43	1		T229	1		T71	1
auto[1207959552:1342177279]	auto[1]	65	1			T49	2		T190	1		T37	1
auto[1342177280:1476395007]	auto[0]	62	1			T18	1		T26	1		T22	1
auto[1342177280:1476395007]	auto[1]	62	1			T26	1		T49	1		T52	1
auto[1476395008:1610612735]	auto[0]	54	1			T18	1		T49	1		T98	1
auto[1476395008:1610612735]	auto[1]	61	1			T48	1		T184	1		T49	2
auto[1610612736:1744830463]	auto[0]	45	1			T49	1		T64	1		T55	1
auto[1610612736:1744830463]	auto[1]	56	1			T25	1		T48	1		T61	1
auto[1744830464:1879048191]	auto[0]	41	1			T80	1		T46	1		T100	1
auto[1744830464:1879048191]	auto[1]	45	1			T48	1		T49	2		T83	1
auto[1879048192:2013265919]	auto[0]	46	1			T33	1		T24	1		T199	2
auto[1879048192:2013265919]	auto[1]	73	1			T184	1		T49	1		T190	1
auto[2013265920:2147483647]	auto[0]	38	1			T35	1		T184	1		T49	1
auto[2013265920:2147483647]	auto[1]	49	1			T48	1		T70	1		T229	1
auto[2147483648:2281701375]	auto[0]	48	1			T18	1		T183	1		T184	1
auto[2147483648:2281701375]	auto[1]	82	1			T48	1		T49	3		T83	1
auto[2281701376:2415919103]	auto[0]	59	1			T46	1		T199	1		T54	1
auto[2281701376:2415919103]	auto[1]	54	1			T177	1		T112	1		T171	1
auto[2415919104:2550136831]	auto[0]	53	1			T23	1		T49	1		T63	1
auto[2415919104:2550136831]	auto[1]	39	1			T48	2		T98	1		T187	1
auto[2550136832:2684354559]	auto[0]	51	1			T35	1		T184	1		T63	1
auto[2550136832:2684354559]	auto[1]	51	1			T22	1		T63	1		T83	1
auto[2684354560:2818572287]	auto[0]	39	1			T49	2		T186	1		T70	1
auto[2684354560:2818572287]	auto[1]	62	1			T48	2		T49	1		T98	1
auto[2818572288:2952790015]	auto[0]	52	1			T98	1		T100	1		T185	1
auto[2818572288:2952790015]	auto[1]	64	1			T49	2		T100	1		T19	1
auto[2952790016:3087007743]	auto[0]	61	1			T25	1		T32	1		T100	2
auto[2952790016:3087007743]	auto[1]	59	1			T49	1		T63	1		T117	1
auto[3087007744:3221225471]	auto[0]	40	1			T64	1		T53	1		T133	1
auto[3087007744:3221225471]	auto[1]	67	1			T27	1		T48	1		T22	1
auto[3221225472:3355443199]	auto[0]	48	1			T35	1		T184	1		T63	1
auto[3221225472:3355443199]	auto[1]	68	1			T48	1		T49	2		T100	1
auto[3355443200:3489660927]	auto[0]	47	1			T80	1		T46	1		T94	1
auto[3355443200:3489660927]	auto[1]	48	1			T100	1		T54	1		T94	1
auto[3489660928:3623878655]	auto[0]	55	1			T35	1		T184	2		T49	1
auto[3489660928:3623878655]	auto[1]	50	1			T184	1		T98	1		T188	1
auto[3623878656:3758096383]	auto[0]	55	1			T23	1		T49	1		T100	1
auto[3623878656:3758096383]	auto[1]	55	1			T48	1		T49	1		T98	1
auto[3758096384:3892314111]	auto[0]	54	1			T23	1		T49	1		T63	1
auto[3758096384:3892314111]	auto[1]	50	1			T15	1		T48	1		T33	1
auto[3892314112:4026531839]	auto[0]	50	1			T26	1		T183	1		T98	1
auto[3892314112:4026531839]	auto[1]	63	1			T49	3		T100	1		T54	1
auto[4026531840:4160749567]	auto[0]	57	1			T35	1		T49	1		T52	1
auto[4026531840:4160749567]	auto[1]	60	1			T55	1		T62	1		T88	1
auto[4160749568:4294967295]	auto[0]	56	1			T35	1		T49	1		T46	2
auto[4160749568:4294967295]	auto[1]	68	1			T27	1		T49	2		T98	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1646

1

T18

2

T25

1

T26

2

auto[1]

1840

1

T15

1

T18

1

T25

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	122	1			T80	1		T48	1		T61	1
auto[134217728:268435455]	126	1			T49	2		T46	2		T37	1
auto[268435456:402653183]	92	1			T35	1		T48	1		T49	2
auto[402653184:536870911]	110	1			T49	1		T63	1		T36	1
auto[536870912:671088639]	104	1			T49	3		T52	2		T190	1
auto[671088640:805306367]	97	1			T183	1		T49	1		T86	1
auto[805306368:939524095]	107	1			T48	1		T49	2		T52	2
auto[939524096:1073741823]	104	1			T26	1		T184	1		T98	1
auto[1073741824:1207959551]	126	1			T18	1		T184	1		T49	4
auto[1207959552:1342177279]	119	1			T35	1		T48	1		T183	1
auto[1342177280:1476395007]	109	1			T48	1		T49	3		T63	1
auto[1476395008:1610612735]	114	1			T184	1		T49	4		T33	1
auto[1610612736:1744830463]	105	1			T48	1		T22	1		T184	1
auto[1744830464:1879048191]	111	1			T27	1		T48	1		T98	1
auto[1879048192:2013265919]	109	1			T35	1		T49	1		T63	1
auto[2013265920:2147483647]	106	1			T18	1		T22	1		T49	2
auto[2147483648:2281701375]	120	1			T80	1		T184	1		T49	1
auto[2281701376:2415919103]	106	1			T184	1		T49	4		T46	1
auto[2415919104:2550136831]	110	1			T48	3		T184	1		T49	2
auto[2550136832:2684354559]	97	1			T25	1		T27	1		T23	1
auto[2684354560:2818572287]	99	1			T18	1		T48	1		T23	1
auto[2818572288:2952790015]	97	1			T35	1		T48	1		T49	2
auto[2952790016:3087007743]	108	1			T26	1		T35	1		T49	1
auto[3087007744:3221225471]	111	1			T48	3		T22	1		T49	3
auto[3221225472:3355443199]	103	1			T25	1		T35	1		T48	1
auto[3355443200:3489660927]	110	1			T98	1		T86	1		T100	1
auto[3489660928:3623878655]	122	1			T15	1		T48	1		T49	1
auto[3623878656:3758096383]	109	1			T27	1		T23	1		T49	4
auto[3758096384:3892314111]	121	1			T80	1		T48	1		T98	1
auto[3892314112:4026531839]	92	1			T26	2		T184	1		T98	1
auto[4026531840:4160749567]	105	1			T25	1		T80	1		T184	1
auto[4160749568:4294967295]	115	1			T22	1		T184	1		T49	2