Unified Coverage Report :: Group Instance : salt_2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3070

1

T18

3

T25

3

T26

4

auto[1]

319

1

T132

4

T134

7

T172

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	123	1			T25	1		T80	1		T48	1
auto[134217728:268435455]	93	1			T26	1		T48	2		T49	1
auto[268435456:402653183]	90	1			T26	1		T48	2		T49	1
auto[402653184:536870911]	114	1			T22	1		T184	1		T23	1
auto[536870912:671088639]	114	1			T27	1		T183	1		T184	1
auto[671088640:805306367]	124	1			T49	1		T64	1		T100	3
auto[805306368:939524095]	114	1			T80	1		T23	1		T49	3
auto[939524096:1073741823]	92	1			T18	1		T27	1		T80	1
auto[1073741824:1207959551]	117	1			T35	1		T48	1		T184	1
auto[1207959552:1342177279]	103	1			T18	1		T22	1		T49	2
auto[1342177280:1476395007]	112	1			T48	1		T184	2		T98	1
auto[1476395008:1610612735]	99	1			T48	2		T184	2		T36	1
auto[1610612736:1744830463]	94	1			T48	1		T49	2		T46	1
auto[1744830464:1879048191]	105	1			T26	1		T49	2		T86	2
auto[1879048192:2013265919]	109	1			T49	1		T98	1		T52	1
auto[2013265920:2147483647]	101	1			T27	1		T32	1		T37	1
auto[2147483648:2281701375]	106	1			T26	1		T61	1		T49	3
auto[2281701376:2415919103]	102	1			T49	1		T64	1		T100	2
auto[2415919104:2550136831]	116	1			T25	1		T80	1		T98	1
auto[2550136832:2684354559]	125	1			T35	1		T49	1		T52	1
auto[2684354560:2818572287]	103	1			T48	1		T183	1		T49	3
auto[2818572288:2952790015]	93	1			T35	1		T23	1		T49	1
auto[2952790016:3087007743]	105	1			T48	1		T49	2		T98	1
auto[3087007744:3221225471]	90	1			T18	1		T49	1		T33	1
auto[3221225472:3355443199]	111	1			T22	1		T98	1		T52	1
auto[3355443200:3489660927]	110	1			T22	1		T49	2		T98	1
auto[3489660928:3623878655]	95	1			T35	1		T49	2		T98	1
auto[3623878656:3758096383]	114	1			T48	1		T184	1		T23	1
auto[3758096384:3892314111]	113	1			T25	1		T35	1		T48	1
auto[3892314112:4026531839]	112	1			T48	1		T184	1		T49	3
auto[4026531840:4160749567]	100	1			T48	2		T184	1		T98	1
auto[4160749568:4294967295]	90	1			T35	1		T184	1		T49	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	116	1			T25	1		T80	1		T48	1
auto[0:134217727]	auto[1]	7	1			T308	1		T220	1		T233	1
auto[134217728:268435455]	auto[0]	88	1			T26	1		T48	2		T49	1
auto[134217728:268435455]	auto[1]	5	1			T119	1		T381	1		T398	1
auto[268435456:402653183]	auto[0]	81	1			T26	1		T48	2		T49	1
auto[268435456:402653183]	auto[1]	9	1			T122	1		T399	1		T219	1
auto[402653184:536870911]	auto[0]	102	1			T22	1		T184	1		T23	1
auto[402653184:536870911]	auto[1]	12	1			T118	1		T283	1		T308	1
auto[536870912:671088639]	auto[0]	101	1			T27	1		T183	1		T184	1
auto[536870912:671088639]	auto[1]	13	1			T134	2		T405	2		T402	1
auto[671088640:805306367]	auto[0]	111	1			T49	1		T64	1		T100	3
auto[671088640:805306367]	auto[1]	13	1			T172	1		T119	1		T399	1
auto[805306368:939524095]	auto[0]	105	1			T80	1		T23	1		T49	3
auto[805306368:939524095]	auto[1]	9	1			T132	1		T380	1		T349	3
auto[939524096:1073741823]	auto[0]	83	1			T18	1		T27	1		T80	1
auto[939524096:1073741823]	auto[1]	9	1			T134	1		T119	1		T349	1
auto[1073741824:1207959551]	auto[0]	108	1			T35	1		T48	1		T184	1
auto[1073741824:1207959551]	auto[1]	9	1			T236	1		T224	1		T399	1
auto[1207959552:1342177279]	auto[0]	91	1			T18	1		T22	1		T49	2
auto[1207959552:1342177279]	auto[1]	12	1			T401	2		T233	1		T411	1
auto[1342177280:1476395007]	auto[0]	101	1			T48	1		T184	2		T98	1
auto[1342177280:1476395007]	auto[1]	11	1			T122	1		T236	1		T405	1
auto[1476395008:1610612735]	auto[0]	90	1			T48	2		T184	2		T36	1
auto[1476395008:1610612735]	auto[1]	9	1			T134	1		T236	1		T380	1
auto[1610612736:1744830463]	auto[0]	81	1			T48	1		T49	2		T46	1
auto[1610612736:1744830463]	auto[1]	13	1			T132	1		T120	1		T278	1
auto[1744830464:1879048191]	auto[0]	97	1			T26	1		T49	2		T86	2
auto[1744830464:1879048191]	auto[1]	8	1			T308	1		T220	1		T233	1
auto[1879048192:2013265919]	auto[0]	101	1			T49	1		T98	1		T52	1
auto[1879048192:2013265919]	auto[1]	8	1			T283	1		T349	1		T398	1
auto[2013265920:2147483647]	auto[0]	87	1			T27	1		T32	1		T37	1
auto[2013265920:2147483647]	auto[1]	14	1			T132	1		T118	1		T122	1
auto[2147483648:2281701375]	auto[0]	94	1			T26	1		T61	1		T49	3
auto[2147483648:2281701375]	auto[1]	12	1			T132	1		T236	1		T358	1
auto[2281701376:2415919103]	auto[0]	96	1			T49	1		T64	1		T100	2
auto[2281701376:2415919103]	auto[1]	6	1			T172	1		T224	1		T349	1
auto[2415919104:2550136831]	auto[0]	101	1			T25	1		T80	1		T98	1
auto[2415919104:2550136831]	auto[1]	15	1			T134	1		T119	2		T122	1
auto[2550136832:2684354559]	auto[0]	114	1			T35	1		T49	1		T52	1
auto[2550136832:2684354559]	auto[1]	11	1			T119	1		T219	1		T401	1
auto[2684354560:2818572287]	auto[0]	91	1			T48	1		T183	1		T49	3
auto[2684354560:2818572287]	auto[1]	12	1			T236	2		T308	1		T358	1
auto[2818572288:2952790015]	auto[0]	85	1			T35	1		T23	1		T49	1
auto[2818572288:2952790015]	auto[1]	8	1			T256	1		T219	1		T405	2
auto[2952790016:3087007743]	auto[0]	96	1			T48	1		T49	2		T98	1
auto[2952790016:3087007743]	auto[1]	9	1			T118	1		T233	2		T384	2
auto[3087007744:3221225471]	auto[0]	81	1			T18	1		T49	1		T33	1
auto[3087007744:3221225471]	auto[1]	9	1			T236	1		T220	1		T401	1
auto[3221225472:3355443199]	auto[0]	100	1			T22	1		T98	1		T52	1
auto[3221225472:3355443199]	auto[1]	11	1			T118	1		T278	1		T283	1
auto[3355443200:3489660927]	auto[0]	103	1			T22	1		T49	2		T98	1
auto[3355443200:3489660927]	auto[1]	7	1			T172	1		T120	1		T406	1
auto[3489660928:3623878655]	auto[0]	80	1			T35	1		T49	2		T98	1
auto[3489660928:3623878655]	auto[1]	15	1			T236	1		T256	1		T380	1
auto[3623878656:3758096383]	auto[0]	106	1			T48	1		T184	1		T23	1
auto[3623878656:3758096383]	auto[1]	8	1			T134	1		T399	1		T308	2
auto[3758096384:3892314111]	auto[0]	106	1			T25	1		T35	1		T48	1
auto[3758096384:3892314111]	auto[1]	7	1			T134	1		T236	1		T405	1
auto[3892314112:4026531839]	auto[0]	102	1			T48	1		T184	1		T49	3
auto[3892314112:4026531839]	auto[1]	10	1			T119	1		T405	1		T381	1
auto[4026531840:4160749567]	auto[0]	94	1			T48	2		T184	1		T98	1
auto[4026531840:4160749567]	auto[1]	6	1			T308	1		T405	1		T400	1
auto[4160749568:4294967295]	auto[0]	78	1			T35	1		T184	1		T49	1
auto[4160749568:4294967295]	auto[1]	12	1			T172	1		T120	1		T236	1