Unified Coverage Report :: Group Instance : sealing_sw_binding_6

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1624

1

T18

3

T25

1

T26

2

auto[1]

1862

1

T15

1

T25

2

T26

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	105	1			T35	1		T80	1		T63	2
auto[134217728:268435455]	117	1			T48	1		T184	1		T23	1
auto[268435456:402653183]	93	1			T23	1		T49	2		T24	1
auto[402653184:536870911]	130	1			T22	1		T183	1		T49	5
auto[536870912:671088639]	102	1			T48	1		T184	1		T190	1
auto[671088640:805306367]	114	1			T80	1		T49	2		T100	1
auto[805306368:939524095]	106	1			T48	1		T98	1		T33	1
auto[939524096:1073741823]	97	1			T86	1		T52	1		T63	2
auto[1073741824:1207959551]	126	1			T25	1		T26	1		T27	1
auto[1207959552:1342177279]	98	1			T48	2		T183	1		T184	1
auto[1342177280:1476395007]	107	1			T61	1		T49	2		T37	1
auto[1476395008:1610612735]	101	1			T35	1		T48	1		T184	1
auto[1610612736:1744830463]	112	1			T27	1		T184	1		T49	1
auto[1744830464:1879048191]	106	1			T18	1		T48	2		T49	3
auto[1879048192:2013265919]	122	1			T22	1		T184	1		T49	4
auto[2013265920:2147483647]	99	1			T26	1		T98	1		T86	1
auto[2147483648:2281701375]	119	1			T49	1		T98	1		T100	1
auto[2281701376:2415919103]	110	1			T49	2		T190	1		T43	1
auto[2415919104:2550136831]	103	1			T49	2		T100	2		T53	2
auto[2550136832:2684354559]	113	1			T48	1		T49	2		T46	2
auto[2684354560:2818572287]	97	1			T48	1		T184	1		T98	1
auto[2818572288:2952790015]	103	1			T26	1		T27	1		T22	1
auto[2952790016:3087007743]	97	1			T18	1		T48	1		T49	2
auto[3087007744:3221225471]	116	1			T15	1		T25	1		T35	1
auto[3221225472:3355443199]	123	1			T18	1		T80	1		T48	2
auto[3355443200:3489660927]	96	1			T80	1		T49	1		T52	1
auto[3489660928:3623878655]	126	1			T184	2		T23	1		T49	1
auto[3623878656:3758096383]	112	1			T35	1		T184	2		T49	2
auto[3758096384:3892314111]	101	1			T23	1		T49	1		T100	2
auto[3892314112:4026531839]	114	1			T26	1		T35	1		T48	1
auto[4026531840:4160749567]	118	1			T25	1		T49	3		T98	1
auto[4160749568:4294967295]	103	1			T35	1		T48	3		T49	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	46	1			T35	1		T80	1		T44	1
auto[0:134217727]	auto[1]	59	1			T63	2		T192	1		T100	1
auto[134217728:268435455]	auto[0]	65	1			T184	1		T23	1		T98	1
auto[134217728:268435455]	auto[1]	52	1			T48	1		T49	2		T132	1
auto[268435456:402653183]	auto[0]	42	1			T49	2		T112	1		T196	1
auto[268435456:402653183]	auto[1]	51	1			T23	1		T24	1		T222	1
auto[402653184:536870911]	auto[0]	67	1			T22	1		T49	2		T86	1
auto[402653184:536870911]	auto[1]	63	1			T183	1		T49	3		T37	1
auto[536870912:671088639]	auto[0]	52	1			T184	1		T185	1		T62	2
auto[536870912:671088639]	auto[1]	50	1			T48	1		T190	1		T100	2
auto[671088640:805306367]	auto[0]	58	1			T80	1		T100	1		T199	1
auto[671088640:805306367]	auto[1]	56	1			T49	2		T189	1		T113	1
auto[805306368:939524095]	auto[0]	53	1			T48	1		T98	1		T199	1
auto[805306368:939524095]	auto[1]	53	1			T33	1		T188	1		T56	1
auto[939524096:1073741823]	auto[0]	53	1			T86	1		T63	1		T32	1
auto[939524096:1073741823]	auto[1]	44	1			T52	1		T63	1		T83	1
auto[1073741824:1207959551]	auto[0]	53	1			T185	2		T272	1		T45	1
auto[1073741824:1207959551]	auto[1]	73	1			T25	1		T26	1		T27	1
auto[1207959552:1342177279]	auto[0]	48	1			T183	1		T184	1		T46	1
auto[1207959552:1342177279]	auto[1]	50	1			T48	2		T86	2		T83	1
auto[1342177280:1476395007]	auto[0]	51	1			T61	1		T49	1		T100	2
auto[1342177280:1476395007]	auto[1]	56	1			T49	1		T37	1		T43	1
auto[1476395008:1610612735]	auto[0]	43	1			T35	1		T43	1		T51	1
auto[1476395008:1610612735]	auto[1]	58	1			T48	1		T184	1		T49	2
auto[1610612736:1744830463]	auto[0]	53	1			T184	1		T98	1		T37	1
auto[1610612736:1744830463]	auto[1]	59	1			T27	1		T49	1		T100	1
auto[1744830464:1879048191]	auto[0]	43	1			T18	1		T48	1		T49	1
auto[1744830464:1879048191]	auto[1]	63	1			T48	1		T49	2		T37	2
auto[1879048192:2013265919]	auto[0]	46	1			T49	1		T53	1		T199	1
auto[1879048192:2013265919]	auto[1]	76	1			T22	1		T184	1		T49	3
auto[2013265920:2147483647]	auto[0]	41	1			T249	1		T271	1		T197	1
auto[2013265920:2147483647]	auto[1]	58	1			T26	1		T98	1		T86	1
auto[2147483648:2281701375]	auto[0]	42	1			T98	1		T55	1		T50	2
auto[2147483648:2281701375]	auto[1]	77	1			T49	1		T100	1		T179	1
auto[2281701376:2415919103]	auto[0]	52	1			T49	1		T24	1		T54	1
auto[2281701376:2415919103]	auto[1]	58	1			T49	1		T190	1		T43	1
auto[2415919104:2550136831]	auto[0]	44	1			T100	2		T53	1		T132	1
auto[2415919104:2550136831]	auto[1]	59	1			T49	2		T53	1		T180	1
auto[2550136832:2684354559]	auto[0]	58	1			T49	2		T46	2		T50	1
auto[2550136832:2684354559]	auto[1]	55	1			T48	1		T100	1		T177	1
auto[2684354560:2818572287]	auto[0]	47	1			T52	1		T186	1		T64	1
auto[2684354560:2818572287]	auto[1]	50	1			T48	1		T184	1		T98	1
auto[2818572288:2952790015]	auto[0]	55	1			T26	1		T22	1		T49	1
auto[2818572288:2952790015]	auto[1]	48	1			T27	1		T98	1		T177	1
auto[2952790016:3087007743]	auto[0]	48	1			T18	1		T49	1		T63	1
auto[2952790016:3087007743]	auto[1]	49	1			T48	1		T49	1		T52	1
auto[3087007744:3221225471]	auto[0]	49	1			T35	1		T52	1		T46	1
auto[3087007744:3221225471]	auto[1]	67	1			T15	1		T25	1		T48	1
auto[3221225472:3355443199]	auto[0]	61	1			T18	1		T80	1		T48	1
auto[3221225472:3355443199]	auto[1]	62	1			T48	1		T49	1		T100	1
auto[3355443200:3489660927]	auto[0]	40	1			T80	1		T186	2		T24	1
auto[3355443200:3489660927]	auto[1]	56	1			T49	1		T52	1		T46	1
auto[3489660928:3623878655]	auto[0]	55	1			T184	1		T23	1		T49	1
auto[3489660928:3623878655]	auto[1]	71	1			T184	1		T98	1		T52	1
auto[3623878656:3758096383]	auto[0]	59	1			T35	1		T184	2		T49	1
auto[3623878656:3758096383]	auto[1]	53	1			T49	1		T98	2		T63	1
auto[3758096384:3892314111]	auto[0]	40	1			T23	1		T49	1		T100	1
auto[3758096384:3892314111]	auto[1]	61	1			T100	1		T187	2		T88	1
auto[3892314112:4026531839]	auto[0]	52	1			T26	1		T35	1		T22	1
auto[3892314112:4026531839]	auto[1]	62	1			T48	1		T49	1		T63	2
auto[4026531840:4160749567]	auto[0]	56	1			T25	1		T98	1		T63	1
auto[4026531840:4160749567]	auto[1]	62	1			T49	3		T63	1		T37	1
auto[4160749568:4294967295]	auto[0]	52	1			T35	1		T86	1		T100	1
auto[4160749568:4294967295]	auto[1]	51	1			T48	3		T49	2		T63	1