Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7168

1

T18

7

T25

5

T26

8

auto[1]

309

1

T132

5

T134

9

T172

6

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	3006	1			T18	3		T25	2		T26	4
auto[134217728:268435455]	166	1			T25	1		T183	1		T49	1
auto[268435456:402653183]	168	1			T27	1		T48	2		T184	1
auto[402653184:536870911]	167	1			T48	1		T83	1		T54	2
auto[536870912:671088639]	158	1			T48	2		T49	4		T98	1
auto[671088640:805306367]	166	1			T184	1		T49	2		T46	1
auto[805306368:939524095]	143	1			T27	1		T35	1		T49	4
auto[939524096:1073741823]	121	1			T26	1		T27	2		T183	1
auto[1073741824:1207959551]	129	1			T48	1		T22	1		T49	4
auto[1207959552:1342177279]	143	1			T27	1		T35	1		T183	1
auto[1342177280:1476395007]	129	1			T27	1		T35	1		T48	1
auto[1476395008:1610612735]	131	1			T25	1		T48	1		T23	1
auto[1610612736:1744830463]	144	1			T35	1		T23	1		T49	1
auto[1744830464:1879048191]	139	1			T80	1		T48	1		T22	1
auto[1879048192:2013265919]	116	1			T27	1		T49	1		T52	1
auto[2013265920:2147483647]	151	1			T18	1		T35	1		T183	1
auto[2147483648:2281701375]	133	1			T48	1		T49	2		T52	1
auto[2281701376:2415919103]	137	1			T183	1		T184	2		T49	1
auto[2415919104:2550136831]	139	1			T26	1		T27	1		T48	1
auto[2550136832:2684354559]	140	1			T26	1		T80	1		T48	1
auto[2684354560:2818572287]	171	1			T22	2		T184	1		T49	2
auto[2818572288:2952790015]	165	1			T35	1		T22	1		T184	1
auto[2952790016:3087007743]	133	1			T48	1		T183	1		T184	1
auto[3087007744:3221225471]	145	1			T18	1		T35	1		T184	2
auto[3221225472:3355443199]	150	1			T18	1		T61	1		T49	4
auto[3355443200:3489660927]	131	1			T49	2		T98	2		T63	1
auto[3489660928:3623878655]	147	1			T25	1		T80	1		T48	1
auto[3623878656:3758096383]	131	1			T18	1		T26	1		T35	1
auto[3758096384:3892314111]	136	1			T35	1		T49	5		T98	1
auto[3892314112:4026531839]	150	1			T27	1		T48	2		T23	1
auto[4026531840:4160749567]	152	1			T27	1		T184	1		T98	1
auto[4160749568:4294967295]	140	1			T27	1		T22	1		T49	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	2999	1			T18	3		T25	2		T26	4
auto[0:134217727]	auto[1]	7	1			T119	1		T401	1		T233	1
auto[134217728:268435455]	auto[0]	155	1			T25	1		T183	1		T49	1
auto[134217728:268435455]	auto[1]	11	1			T119	1		T224	1		T358	1
auto[268435456:402653183]	auto[0]	160	1			T27	1		T48	2		T184	1
auto[268435456:402653183]	auto[1]	8	1			T118	1		T283	1		T220	1
auto[402653184:536870911]	auto[0]	158	1			T48	1		T83	1		T54	2
auto[402653184:536870911]	auto[1]	9	1			T220	1		T233	1		T381	1
auto[536870912:671088639]	auto[0]	146	1			T48	2		T49	4		T98	1
auto[536870912:671088639]	auto[1]	12	1			T132	1		T134	1		T308	1
auto[671088640:805306367]	auto[0]	149	1			T184	1		T49	2		T46	1
auto[671088640:805306367]	auto[1]	17	1			T122	2		T283	1		T308	1
auto[805306368:939524095]	auto[0]	132	1			T27	1		T35	1		T49	4
auto[805306368:939524095]	auto[1]	11	1			T236	2		T219	1		T398	2
auto[939524096:1073741823]	auto[0]	119	1			T26	1		T27	2		T183	1
auto[939524096:1073741823]	auto[1]	2	1			T278	1		T308	1		-	-
auto[1073741824:1207959551]	auto[0]	123	1			T48	1		T22	1		T49	4
auto[1073741824:1207959551]	auto[1]	6	1			T134	1		T120	1		T405	2
auto[1207959552:1342177279]	auto[0]	133	1			T27	1		T35	1		T183	1
auto[1207959552:1342177279]	auto[1]	10	1			T224	1		T278	1		T308	1
auto[1342177280:1476395007]	auto[0]	124	1			T27	1		T35	1		T48	1
auto[1342177280:1476395007]	auto[1]	5	1			T220	1		T233	1		T404	2
auto[1476395008:1610612735]	auto[0]	123	1			T25	1		T48	1		T23	1
auto[1476395008:1610612735]	auto[1]	8	1			T308	2		T405	1		T312	1
auto[1610612736:1744830463]	auto[0]	129	1			T35	1		T23	1		T49	1
auto[1610612736:1744830463]	auto[1]	15	1			T132	1		T122	1		T399	1
auto[1744830464:1879048191]	auto[0]	131	1			T80	1		T48	1		T22	1
auto[1744830464:1879048191]	auto[1]	8	1			T119	1		T399	1		T405	1
auto[1879048192:2013265919]	auto[0]	112	1			T27	1		T49	1		T52	1
auto[1879048192:2013265919]	auto[1]	4	1			T308	1		T220	1		T378	1
auto[2013265920:2147483647]	auto[0]	144	1			T18	1		T35	1		T183	1
auto[2013265920:2147483647]	auto[1]	7	1			T172	1		T122	1		T278	1
auto[2147483648:2281701375]	auto[0]	126	1			T48	1		T49	2		T52	1
auto[2147483648:2281701375]	auto[1]	7	1			T349	1		T233	1		T291	1
auto[2281701376:2415919103]	auto[0]	127	1			T183	1		T184	2		T49	1
auto[2281701376:2415919103]	auto[1]	10	1			T120	1		T122	1		T380	1
auto[2415919104:2550136831]	auto[0]	135	1			T26	1		T27	1		T48	1
auto[2415919104:2550136831]	auto[1]	4	1			T118	1		T358	1		T401	1
auto[2550136832:2684354559]	auto[0]	130	1			T26	1		T80	1		T48	1
auto[2550136832:2684354559]	auto[1]	10	1			T119	1		T219	1		T358	1
auto[2684354560:2818572287]	auto[0]	160	1			T22	2		T184	1		T49	2
auto[2684354560:2818572287]	auto[1]	11	1			T134	1		T236	1		T224	1
auto[2818572288:2952790015]	auto[0]	152	1			T35	1		T22	1		T184	1
auto[2818572288:2952790015]	auto[1]	13	1			T134	1		T172	1		T118	1
auto[2952790016:3087007743]	auto[0]	122	1			T48	1		T183	1		T184	1
auto[2952790016:3087007743]	auto[1]	11	1			T134	1		T172	1		T119	1
auto[3087007744:3221225471]	auto[0]	135	1			T18	1		T35	1		T184	2
auto[3087007744:3221225471]	auto[1]	10	1			T172	1		T122	1		T401	1
auto[3221225472:3355443199]	auto[0]	141	1			T18	1		T61	1		T49	4
auto[3221225472:3355443199]	auto[1]	9	1			T119	1		T283	1		T378	1
auto[3355443200:3489660927]	auto[0]	118	1			T49	2		T98	2		T63	1
auto[3355443200:3489660927]	auto[1]	13	1			T132	2		T118	1		T308	1
auto[3489660928:3623878655]	auto[0]	138	1			T25	1		T80	1		T48	1
auto[3489660928:3623878655]	auto[1]	9	1			T122	1		T224	1		T405	2
auto[3623878656:3758096383]	auto[0]	124	1			T18	1		T26	1		T35	1
auto[3623878656:3758096383]	auto[1]	7	1			T172	1		T349	1		T220	1
auto[3758096384:3892314111]	auto[0]	116	1			T35	1		T49	5		T98	1
auto[3758096384:3892314111]	auto[1]	20	1			T134	1		T172	1		T118	1
auto[3892314112:4026531839]	auto[0]	142	1			T27	1		T48	2		T23	1
auto[3892314112:4026531839]	auto[1]	8	1			T399	1		T219	1		T349	1
auto[4026531840:4160749567]	auto[0]	133	1			T27	1		T184	1		T98	1
auto[4026531840:4160749567]	auto[1]	19	1			T132	1		T134	3		T118	1
auto[4160749568:4294967295]	auto[0]	132	1			T27	1		T22	1		T49	2
auto[4160749568:4294967295]	auto[1]	8	1			T122	1		T224	1		T399	1