Unified Coverage Report :: Group Instance : max_creator_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4558

1

T15

2

T18

6

T25

6

auto[1]

2414

1

T26

8

T27

4

T35

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	210	1			T48	2		T49	2		T53	2
auto[134217728:268435455]	200	1			T18	2		T80	2		T49	2
auto[268435456:402653183]	246	1			T48	2		T22	2		T49	2
auto[402653184:536870911]	210	1			T48	2		T184	2		T23	2
auto[536870912:671088639]	228	1			T49	8		T100	4		T43	2
auto[671088640:805306367]	212	1			T48	2		T98	2		T86	4
auto[805306368:939524095]	208	1			T15	2		T18	2		T25	2
auto[939524096:1073741823]	236	1			T25	2		T184	4		T23	2
auto[1073741824:1207959551]	208	1			T27	2		T49	8		T98	6
auto[1207959552:1342177279]	178	1			T26	2		T48	2		T184	2
auto[1342177280:1476395007]	194	1			T48	2		T61	2		T184	2
auto[1476395008:1610612735]	230	1			T25	2		T48	2		T49	2
auto[1610612736:1744830463]	222	1			T183	2		T184	2		T49	6
auto[1744830464:1879048191]	208	1			T80	2		T49	4		T98	2
auto[1879048192:2013265919]	226	1			T35	2		T183	2		T63	2
auto[2013265920:2147483647]	252	1			T48	2		T49	4		T63	2
auto[2147483648:2281701375]	204	1			T35	4		T184	2		T46	2
auto[2281701376:2415919103]	212	1			T26	2		T48	2		T22	2
auto[2415919104:2550136831]	218	1			T35	2		T48	2		T49	6
auto[2550136832:2684354559]	228	1			T48	4		T49	8		T98	6
auto[2684354560:2818572287]	256	1			T23	2		T49	6		T94	2
auto[2818572288:2952790015]	256	1			T49	6		T52	2		T46	2
auto[2952790016:3087007743]	224	1			T35	2		T86	2		T52	2
auto[3087007744:3221225471]	254	1			T22	4		T49	2		T98	2
auto[3221225472:3355443199]	280	1			T26	2		T48	2		T184	2
auto[3355443200:3489660927]	188	1			T26	2		T52	4		T186	2
auto[3489660928:3623878655]	186	1			T48	2		T98	2		T63	2
auto[3623878656:3758096383]	188	1			T80	2		T184	2		T98	2
auto[3758096384:3892314111]	206	1			T49	6		T63	2		T36	2
auto[3892314112:4026531839]	218	1			T27	2		T48	6		T49	4
auto[4026531840:4160749567]	178	1			T27	2		T80	2		T46	2
auto[4160749568:4294967295]	208	1			T18	2		T184	2		T63	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	122	1			T49	2		T53	2		T188	2
auto[0:134217727]	auto[1]	88	1			T48	2		T229	2		T407	2
auto[134217728:268435455]	auto[0]	130	1			T18	2		T80	2		T86	2
auto[134217728:268435455]	auto[1]	70	1			T49	2		T32	2		T92	2
auto[268435456:402653183]	auto[0]	160	1			T48	2		T22	2		T63	2
auto[268435456:402653183]	auto[1]	86	1			T49	2		T179	2		T53	4
auto[402653184:536870911]	auto[0]	134	1			T184	2		T23	2		T49	4
auto[402653184:536870911]	auto[1]	76	1			T48	2		T49	2		T98	2
auto[536870912:671088639]	auto[0]	182	1			T49	8		T100	4		T43	2
auto[536870912:671088639]	auto[1]	46	1			T180	2		T230	4		T197	2
auto[671088640:805306367]	auto[0]	124	1			T48	2		T98	2		T86	2
auto[671088640:805306367]	auto[1]	88	1			T86	2		T32	2		T186	2
auto[805306368:939524095]	auto[0]	136	1			T15	2		T18	2		T25	2
auto[805306368:939524095]	auto[1]	72	1			T35	2		T48	2		T64	2
auto[939524096:1073741823]	auto[0]	164	1			T25	2		T184	4		T23	2
auto[939524096:1073741823]	auto[1]	72	1			T49	2		T63	2		T185	2
auto[1073741824:1207959551]	auto[0]	126	1			T49	4		T98	2		T46	2
auto[1073741824:1207959551]	auto[1]	82	1			T27	2		T49	4		T98	4
auto[1207959552:1342177279]	auto[0]	96	1			T184	2		T23	2		T37	2
auto[1207959552:1342177279]	auto[1]	82	1			T26	2		T48	2		T46	2
auto[1342177280:1476395007]	auto[0]	128	1			T49	4		T33	2		T54	2
auto[1342177280:1476395007]	auto[1]	66	1			T48	2		T61	2		T184	2
auto[1476395008:1610612735]	auto[0]	150	1			T25	2		T48	2		T86	2
auto[1476395008:1610612735]	auto[1]	80	1			T49	2		T180	2		T5	4
auto[1610612736:1744830463]	auto[0]	144	1			T184	2		T49	4		T46	2
auto[1610612736:1744830463]	auto[1]	78	1			T183	2		T49	2		T63	2
auto[1744830464:1879048191]	auto[0]	138	1			T49	2		T100	2		T50	2
auto[1744830464:1879048191]	auto[1]	70	1			T80	2		T49	2		T98	2
auto[1879048192:2013265919]	auto[0]	150	1			T35	2		T183	2		T63	2
auto[1879048192:2013265919]	auto[1]	76	1			T53	2		T55	2		T185	4
auto[2013265920:2147483647]	auto[0]	168	1			T49	4		T63	2		T83	2
auto[2013265920:2147483647]	auto[1]	84	1			T48	2		T117	2		T54	2
auto[2147483648:2281701375]	auto[0]	138	1			T35	2		T184	2		T46	2
auto[2147483648:2281701375]	auto[1]	66	1			T35	2		T33	2		T51	2
auto[2281701376:2415919103]	auto[0]	144	1			T22	2		T49	4		T63	2
auto[2281701376:2415919103]	auto[1]	68	1			T26	2		T48	2		T52	2
auto[2415919104:2550136831]	auto[0]	156	1			T35	2		T49	6		T186	2
auto[2415919104:2550136831]	auto[1]	62	1			T48	2		T408	2		T229	2
auto[2550136832:2684354559]	auto[0]	142	1			T49	6		T98	2		T52	2
auto[2550136832:2684354559]	auto[1]	86	1			T48	4		T49	2		T98	4
auto[2684354560:2818572287]	auto[0]	156	1			T23	2		T49	4		T132	2
auto[2684354560:2818572287]	auto[1]	100	1			T49	2		T94	2		T132	2
auto[2818572288:2952790015]	auto[0]	158	1			T49	6		T52	2		T46	2
auto[2818572288:2952790015]	auto[1]	98	1			T70	2		T99	2		T71	2
auto[2952790016:3087007743]	auto[0]	142	1			T35	2		T86	2		T52	2
auto[2952790016:3087007743]	auto[1]	82	1			T188	2		T51	2		T133	2
auto[3087007744:3221225471]	auto[0]	164	1			T22	4		T49	2		T86	2
auto[3087007744:3221225471]	auto[1]	90	1			T98	2		T70	2		T94	2
auto[3221225472:3355443199]	auto[0]	176	1			T184	2		T63	2		T190	2
auto[3221225472:3355443199]	auto[1]	104	1			T26	2		T48	2		T98	2
auto[3355443200:3489660927]	auto[0]	122	1			T186	2		T100	4		T50	2
auto[3355443200:3489660927]	auto[1]	66	1			T26	2		T52	4		T112	2
auto[3489660928:3623878655]	auto[0]	112	1			T48	2		T83	2		T100	4
auto[3489660928:3623878655]	auto[1]	74	1			T98	2		T63	2		T187	2
auto[3623878656:3758096383]	auto[0]	126	1			T80	2		T184	2		T52	4
auto[3623878656:3758096383]	auto[1]	62	1			T98	2		T64	2		T56	2
auto[3758096384:3892314111]	auto[0]	140	1			T49	6		T63	2		T36	2
auto[3758096384:3892314111]	auto[1]	66	1			T62	2		T111	2		T410	2
auto[3892314112:4026531839]	auto[0]	134	1			T48	2		T100	2		T43	2
auto[3892314112:4026531839]	auto[1]	84	1			T27	2		T48	4		T49	4
auto[4026531840:4160749567]	auto[0]	140	1			T27	2		T80	2		T54	2
auto[4026531840:4160749567]	auto[1]	38	1			T46	2		T64	2		T185	2
auto[4160749568:4294967295]	auto[0]	156	1			T18	2		T63	2		T199	2
auto[4160749568:4294967295]	auto[1]	52	1			T184	2		T100	2		T24	2