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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.71 99.03 98.07 98.28 100.00 99.02 98.41 91.14


Total test records in report: 1085
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T1006 /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.2166323575 May 07 01:06:56 PM PDT 24 May 07 01:06:58 PM PDT 24 30030072 ps
T1007 /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2066361903 May 07 01:06:40 PM PDT 24 May 07 01:06:45 PM PDT 24 195434668 ps
T1008 /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1497906409 May 07 01:06:49 PM PDT 24 May 07 01:06:53 PM PDT 24 87718197 ps
T1009 /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.3931078574 May 07 01:07:16 PM PDT 24 May 07 01:07:19 PM PDT 24 288958994 ps
T1010 /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1361887412 May 07 01:06:59 PM PDT 24 May 07 01:07:01 PM PDT 24 109313134 ps
T1011 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.1343009591 May 07 01:07:05 PM PDT 24 May 07 01:07:09 PM PDT 24 176832949 ps
T1012 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.715573862 May 07 01:06:27 PM PDT 24 May 07 01:06:37 PM PDT 24 1649954714 ps
T1013 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.117531717 May 07 01:06:49 PM PDT 24 May 07 01:06:55 PM PDT 24 304680246 ps
T1014 /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.4220596938 May 07 01:06:38 PM PDT 24 May 07 01:06:43 PM PDT 24 84629853 ps
T1015 /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2006423544 May 07 01:06:19 PM PDT 24 May 07 01:06:21 PM PDT 24 60821542 ps
T1016 /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.612704094 May 07 01:07:17 PM PDT 24 May 07 01:07:19 PM PDT 24 13831043 ps
T149 /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.2864198247 May 07 01:07:05 PM PDT 24 May 07 01:07:10 PM PDT 24 600985793 ps
T1017 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1192947539 May 07 01:07:00 PM PDT 24 May 07 01:07:02 PM PDT 24 48616350 ps
T1018 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.798657579 May 07 01:06:31 PM PDT 24 May 07 01:06:37 PM PDT 24 380053330 ps
T1019 /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.3520896060 May 07 01:06:41 PM PDT 24 May 07 01:06:45 PM PDT 24 85771794 ps
T1020 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.4280735571 May 07 01:06:57 PM PDT 24 May 07 01:06:59 PM PDT 24 27181369 ps
T1021 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.2490730108 May 07 01:06:20 PM PDT 24 May 07 01:06:26 PM PDT 24 132902943 ps
T1022 /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.11777375 May 07 01:06:40 PM PDT 24 May 07 01:06:42 PM PDT 24 26719846 ps
T1023 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.1097927825 May 07 01:07:13 PM PDT 24 May 07 01:07:16 PM PDT 24 119453956 ps
T1024 /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.971358350 May 07 01:06:33 PM PDT 24 May 07 01:06:36 PM PDT 24 100750147 ps
T145 /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.3991585865 May 07 01:06:40 PM PDT 24 May 07 01:06:43 PM PDT 24 51438973 ps
T1025 /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.435488655 May 07 01:06:43 PM PDT 24 May 07 01:06:47 PM PDT 24 115266022 ps
T1026 /workspace/coverage/cover_reg_top/13.keymgr_intr_test.692824898 May 07 01:07:02 PM PDT 24 May 07 01:07:04 PM PDT 24 8797297 ps
T1027 /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.623560145 May 07 01:07:03 PM PDT 24 May 07 01:07:05 PM PDT 24 34594905 ps
T1028 /workspace/coverage/cover_reg_top/15.keymgr_intr_test.561783433 May 07 01:07:08 PM PDT 24 May 07 01:07:10 PM PDT 24 10832555 ps
T1029 /workspace/coverage/cover_reg_top/25.keymgr_intr_test.798659591 May 07 01:07:16 PM PDT 24 May 07 01:07:18 PM PDT 24 15612323 ps
T140 /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.3075418498 May 07 01:06:25 PM PDT 24 May 07 01:06:37 PM PDT 24 966808691 ps
T1030 /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.2265537249 May 07 01:07:14 PM PDT 24 May 07 01:07:17 PM PDT 24 14090045 ps
T1031 /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.1872855901 May 07 01:07:04 PM PDT 24 May 07 01:07:07 PM PDT 24 251983426 ps
T1032 /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2413108034 May 07 01:06:35 PM PDT 24 May 07 01:06:55 PM PDT 24 5337689112 ps
T1033 /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1398100425 May 07 01:06:27 PM PDT 24 May 07 01:06:30 PM PDT 24 185215904 ps
T1034 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2109470069 May 07 01:06:58 PM PDT 24 May 07 01:07:01 PM PDT 24 117919826 ps
T1035 /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.717206512 May 07 01:06:58 PM PDT 24 May 07 01:07:04 PM PDT 24 112004217 ps
T1036 /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.2639584348 May 07 01:07:05 PM PDT 24 May 07 01:07:08 PM PDT 24 40661777 ps
T1037 /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.1270542948 May 07 01:07:15 PM PDT 24 May 07 01:07:19 PM PDT 24 270454198 ps
T1038 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2015542132 May 07 01:06:50 PM PDT 24 May 07 01:06:57 PM PDT 24 752786620 ps
T1039 /workspace/coverage/cover_reg_top/11.keymgr_intr_test.781168491 May 07 01:06:58 PM PDT 24 May 07 01:07:00 PM PDT 24 37466421 ps
T1040 /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.1942296870 May 07 01:06:19 PM PDT 24 May 07 01:06:30 PM PDT 24 730463836 ps
T1041 /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1567678045 May 07 01:06:31 PM PDT 24 May 07 01:06:33 PM PDT 24 18911213 ps
T1042 /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.281568500 May 07 01:06:42 PM PDT 24 May 07 01:06:46 PM PDT 24 222289046 ps
T1043 /workspace/coverage/cover_reg_top/26.keymgr_intr_test.761576740 May 07 01:07:17 PM PDT 24 May 07 01:07:19 PM PDT 24 14157169 ps
T1044 /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.933597873 May 07 01:07:05 PM PDT 24 May 07 01:07:10 PM PDT 24 214304365 ps
T1045 /workspace/coverage/cover_reg_top/35.keymgr_intr_test.1383081074 May 07 01:07:18 PM PDT 24 May 07 01:07:20 PM PDT 24 10877723 ps
T1046 /workspace/coverage/cover_reg_top/48.keymgr_intr_test.3663477198 May 07 01:07:22 PM PDT 24 May 07 01:07:24 PM PDT 24 10434033 ps
T1047 /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.1419042353 May 07 01:06:20 PM PDT 24 May 07 01:06:23 PM PDT 24 17147185 ps
T1048 /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.2029497782 May 07 01:06:31 PM PDT 24 May 07 01:06:37 PM PDT 24 791024406 ps
T1049 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1518468443 May 07 01:06:37 PM PDT 24 May 07 01:06:42 PM PDT 24 199934848 ps
T1050 /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.597598036 May 07 01:07:14 PM PDT 24 May 07 01:07:16 PM PDT 24 46034159 ps
T1051 /workspace/coverage/cover_reg_top/49.keymgr_intr_test.1751071267 May 07 01:07:21 PM PDT 24 May 07 01:07:22 PM PDT 24 31119714 ps
T1052 /workspace/coverage/cover_reg_top/36.keymgr_intr_test.2317757772 May 07 01:07:13 PM PDT 24 May 07 01:07:15 PM PDT 24 31618115 ps
T1053 /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.284890023 May 07 01:06:35 PM PDT 24 May 07 01:06:38 PM PDT 24 192430235 ps
T1054 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3744437030 May 07 01:07:03 PM PDT 24 May 07 01:07:08 PM PDT 24 345718381 ps
T1055 /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.2216035105 May 07 01:07:17 PM PDT 24 May 07 01:07:19 PM PDT 24 582084702 ps
T1056 /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.3930819258 May 07 01:06:35 PM PDT 24 May 07 01:06:38 PM PDT 24 36713171 ps
T1057 /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.1156064759 May 07 01:06:36 PM PDT 24 May 07 01:06:41 PM PDT 24 515954184 ps
T146 /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.828879074 May 07 01:07:14 PM PDT 24 May 07 01:07:21 PM PDT 24 518892630 ps
T1058 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.501188395 May 07 01:07:26 PM PDT 24 May 07 01:07:27 PM PDT 24 16969049 ps
T1059 /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.2048560420 May 07 01:06:42 PM PDT 24 May 07 01:06:44 PM PDT 24 82741135 ps
T1060 /workspace/coverage/cover_reg_top/28.keymgr_intr_test.492064272 May 07 01:07:13 PM PDT 24 May 07 01:07:15 PM PDT 24 15708246 ps
T1061 /workspace/coverage/cover_reg_top/9.keymgr_intr_test.4203224136 May 07 01:06:49 PM PDT 24 May 07 01:06:51 PM PDT 24 10130160 ps
T1062 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2981313677 May 07 01:07:21 PM PDT 24 May 07 01:07:23 PM PDT 24 30802723 ps
T1063 /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2601236277 May 07 01:06:27 PM PDT 24 May 07 01:06:30 PM PDT 24 126037994 ps
T1064 /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.2539962796 May 07 01:07:04 PM PDT 24 May 07 01:07:10 PM PDT 24 117343144 ps
T1065 /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.3056825909 May 07 01:07:07 PM PDT 24 May 07 01:07:15 PM PDT 24 160680817 ps
T1066 /workspace/coverage/cover_reg_top/32.keymgr_intr_test.2741925005 May 07 01:07:12 PM PDT 24 May 07 01:07:13 PM PDT 24 47991656 ps
T1067 /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1147581031 May 07 01:06:50 PM PDT 24 May 07 01:06:55 PM PDT 24 67911910 ps
T1068 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.3286924919 May 07 01:07:17 PM PDT 24 May 07 01:07:18 PM PDT 24 38539528 ps
T1069 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.4162835562 May 07 01:06:28 PM PDT 24 May 07 01:06:34 PM PDT 24 833583672 ps
T1070 /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.1099783088 May 07 01:06:27 PM PDT 24 May 07 01:06:36 PM PDT 24 1784110634 ps
T1071 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.401697277 May 07 01:06:35 PM PDT 24 May 07 01:06:38 PM PDT 24 299295666 ps
T1072 /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.4003101219 May 07 01:07:00 PM PDT 24 May 07 01:07:03 PM PDT 24 164282842 ps
T1073 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1764799643 May 07 01:07:14 PM PDT 24 May 07 01:07:22 PM PDT 24 2885100982 ps
T1074 /workspace/coverage/cover_reg_top/37.keymgr_intr_test.1994513648 May 07 01:07:15 PM PDT 24 May 07 01:07:17 PM PDT 24 9307389 ps
T1075 /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.765002342 May 07 01:07:04 PM PDT 24 May 07 01:07:09 PM PDT 24 81863000 ps
T1076 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1018717361 May 07 01:06:58 PM PDT 24 May 07 01:07:01 PM PDT 24 166350441 ps
T150 /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.1155636247 May 07 01:06:57 PM PDT 24 May 07 01:07:03 PM PDT 24 1298650167 ps
T1077 /workspace/coverage/cover_reg_top/30.keymgr_intr_test.706785668 May 07 01:07:18 PM PDT 24 May 07 01:07:20 PM PDT 24 34552951 ps
T1078 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.3299845786 May 07 01:06:41 PM PDT 24 May 07 01:06:43 PM PDT 24 19314536 ps
T1079 /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.2073150837 May 07 01:06:19 PM PDT 24 May 07 01:06:24 PM PDT 24 106831212 ps
T1080 /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.25267245 May 07 01:07:05 PM PDT 24 May 07 01:07:11 PM PDT 24 649165406 ps
T1081 /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.2138616634 May 07 01:06:28 PM PDT 24 May 07 01:06:30 PM PDT 24 35283210 ps
T1082 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.3672823274 May 07 01:06:49 PM PDT 24 May 07 01:06:53 PM PDT 24 63956199 ps
T1083 /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.1244821877 May 07 01:07:17 PM PDT 24 May 07 01:07:21 PM PDT 24 89219943 ps
T1084 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.861665223 May 07 01:06:38 PM PDT 24 May 07 01:06:46 PM PDT 24 237840916 ps
T1085 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.4116175613 May 07 01:07:03 PM PDT 24 May 07 01:07:13 PM PDT 24 728684549 ps

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.661522333
Short name T18
Test name
Test status
Simulation time 403917267 ps
CPU time 9.36 seconds
Started May 07 12:37:40 PM PDT 24
Finished May 07 12:37:51 PM PDT 24
Peak memory 219944 kb
Host smart-e2276ab9-5ee0-43d2-bc13-e08e561c004b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661522333 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.661522333
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.813627760
Short name T49
Test name
Test status
Simulation time 3615901895 ps
CPU time 81.46 seconds
Started May 07 12:37:09 PM PDT 24
Finished May 07 12:38:33 PM PDT 24
Peak memory 222568 kb
Host smart-bb684801-7708-40d9-ba81-f75ff528f1a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813627760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.813627760
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.2932293493
Short name T10
Test name
Test status
Simulation time 504805461 ps
CPU time 7.37 seconds
Started May 07 12:36:19 PM PDT 24
Finished May 07 12:36:29 PM PDT 24
Peak memory 234344 kb
Host smart-4b73fb64-9b29-4eb9-be5f-bd7dcecfba54
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932293493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.2932293493
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.870014592
Short name T5
Test name
Test status
Simulation time 678837001 ps
CPU time 33.47 seconds
Started May 07 12:36:53 PM PDT 24
Finished May 07 12:37:29 PM PDT 24
Peak memory 222112 kb
Host smart-4a1de815-2e75-4b25-b5c1-031f92190195
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870014592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.870014592
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.4056748379
Short name T100
Test name
Test status
Simulation time 1338089168 ps
CPU time 44.67 seconds
Started May 07 12:37:09 PM PDT 24
Finished May 07 12:37:56 PM PDT 24
Peak memory 222384 kb
Host smart-b3959142-4572-45c3-987a-f5598904860a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056748379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.4056748379
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.378761455
Short name T113
Test name
Test status
Simulation time 632796285 ps
CPU time 19.79 seconds
Started May 07 12:36:48 PM PDT 24
Finished May 07 12:37:11 PM PDT 24
Peak memory 222576 kb
Host smart-4df8441c-38e3-4093-af8b-0b6ee6d66339
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378761455 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.378761455
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.508843439
Short name T7
Test name
Test status
Simulation time 96379976 ps
CPU time 2.91 seconds
Started May 07 12:37:57 PM PDT 24
Finished May 07 12:38:01 PM PDT 24
Peak memory 219224 kb
Host smart-3596648d-14da-4e37-bee6-02ff74917b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508843439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.508843439
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.1919219193
Short name T35
Test name
Test status
Simulation time 62307943 ps
CPU time 2.49 seconds
Started May 07 12:37:59 PM PDT 24
Finished May 07 12:38:03 PM PDT 24
Peak memory 214224 kb
Host smart-940833b8-0c8c-4841-8cfe-e3b2a73e8b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919219193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.1919219193
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.3966978451
Short name T56
Test name
Test status
Simulation time 1038852410 ps
CPU time 5.63 seconds
Started May 07 12:36:49 PM PDT 24
Finished May 07 12:36:58 PM PDT 24
Peak memory 222700 kb
Host smart-87477209-6ffb-404d-868c-2256f735ae70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966978451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.3966978451
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.3873065062
Short name T132
Test name
Test status
Simulation time 158553506 ps
CPU time 8.19 seconds
Started May 07 12:38:07 PM PDT 24
Finished May 07 12:38:19 PM PDT 24
Peak memory 214200 kb
Host smart-c89186e6-cfeb-4dc4-86dc-15245cb5121a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3873065062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.3873065062
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.747747872
Short name T102
Test name
Test status
Simulation time 314949252 ps
CPU time 3.83 seconds
Started May 07 01:06:19 PM PDT 24
Finished May 07 01:06:25 PM PDT 24
Peak memory 214324 kb
Host smart-3353a3ac-6392-4673-950a-85ca8dfa224e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747747872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.k
eymgr_shadow_reg_errors_with_csr_rw.747747872
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.2241020694
Short name T112
Test name
Test status
Simulation time 285759016 ps
CPU time 18.95 seconds
Started May 07 12:36:30 PM PDT 24
Finished May 07 12:36:51 PM PDT 24
Peak memory 222420 kb
Host smart-75ef4b15-74b0-4495-998f-1eb3aa2d3052
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241020694 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.2241020694
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.967227282
Short name T23
Test name
Test status
Simulation time 3209430759 ps
CPU time 20.18 seconds
Started May 07 12:37:16 PM PDT 24
Finished May 07 12:37:40 PM PDT 24
Peak memory 214396 kb
Host smart-0f937504-aa49-4937-b2d2-48e7121ae39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967227282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.967227282
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.264125716
Short name T398
Test name
Test status
Simulation time 2675236816 ps
CPU time 67.91 seconds
Started May 07 12:37:46 PM PDT 24
Finished May 07 12:38:55 PM PDT 24
Peak memory 215132 kb
Host smart-cc197dd9-cc5b-4a57-9100-33138cc05ec8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=264125716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.264125716
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.1023832095
Short name T233
Test name
Test status
Simulation time 1383973947 ps
CPU time 71.71 seconds
Started May 07 12:37:41 PM PDT 24
Finished May 07 12:38:54 PM PDT 24
Peak memory 215580 kb
Host smart-79b31f07-6bbc-4e63-89db-d41dc534d024
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1023832095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.1023832095
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.781225830
Short name T48
Test name
Test status
Simulation time 194187622 ps
CPU time 9.67 seconds
Started May 07 12:37:14 PM PDT 24
Finished May 07 12:37:28 PM PDT 24
Peak memory 222448 kb
Host smart-56385b82-9a9a-4a8f-a3ad-d464b872f593
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781225830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.781225830
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.1485971811
Short name T63
Test name
Test status
Simulation time 1012238069 ps
CPU time 10.68 seconds
Started May 07 12:38:14 PM PDT 24
Finished May 07 12:38:28 PM PDT 24
Peak memory 219064 kb
Host smart-d38208c1-c2f3-4905-821e-77feb675ac00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485971811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.1485971811
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.3252825410
Short name T219
Test name
Test status
Simulation time 272521457 ps
CPU time 7.92 seconds
Started May 07 12:37:38 PM PDT 24
Finished May 07 12:37:47 PM PDT 24
Peak memory 214288 kb
Host smart-aa3c8e46-8d59-4760-871a-a9240ad5b7e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3252825410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.3252825410
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1494905787
Short name T107
Test name
Test status
Simulation time 219629813 ps
CPU time 2.55 seconds
Started May 07 01:06:26 PM PDT 24
Finished May 07 01:06:30 PM PDT 24
Peak memory 214208 kb
Host smart-8d4796aa-4b3e-40da-bd36-e99d13d24967
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494905787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.1494905787
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.3409195762
Short name T24
Test name
Test status
Simulation time 171976627 ps
CPU time 3.92 seconds
Started May 07 12:37:15 PM PDT 24
Finished May 07 12:37:22 PM PDT 24
Peak memory 221200 kb
Host smart-33ac4808-78e8-4bbf-ba93-51f5fa2062f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409195762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.3409195762
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.3893434240
Short name T119
Test name
Test status
Simulation time 873439641 ps
CPU time 10.05 seconds
Started May 07 12:37:43 PM PDT 24
Finished May 07 12:37:54 PM PDT 24
Peak memory 222400 kb
Host smart-c7fa35a0-56e5-4f09-9301-fba0f24037b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3893434240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.3893434240
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.2618872130
Short name T4
Test name
Test status
Simulation time 1709032158 ps
CPU time 26.96 seconds
Started May 07 12:37:15 PM PDT 24
Finished May 07 12:37:46 PM PDT 24
Peak memory 221576 kb
Host smart-204f554e-ac1b-4732-96ca-c69bf7f7e480
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618872130 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.2618872130
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.2369052080
Short name T411
Test name
Test status
Simulation time 12502426267 ps
CPU time 78.02 seconds
Started May 07 12:38:02 PM PDT 24
Finished May 07 12:39:22 PM PDT 24
Peak memory 216268 kb
Host smart-18a8f090-20d0-4be7-ac5c-76001daefeeb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2369052080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.2369052080
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.1960576009
Short name T19
Test name
Test status
Simulation time 157144892 ps
CPU time 3.16 seconds
Started May 07 12:37:10 PM PDT 24
Finished May 07 12:37:16 PM PDT 24
Peak memory 219244 kb
Host smart-9d14bd9d-370e-4a85-b0f5-db66d5856d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960576009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.1960576009
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.4086801674
Short name T39
Test name
Test status
Simulation time 134231935 ps
CPU time 2.46 seconds
Started May 07 12:37:13 PM PDT 24
Finished May 07 12:37:19 PM PDT 24
Peak memory 209552 kb
Host smart-9b295955-2840-491b-a4c6-20784458ee3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086801674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.4086801674
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.1525057211
Short name T209
Test name
Test status
Simulation time 139866417 ps
CPU time 2.15 seconds
Started May 07 12:38:00 PM PDT 24
Finished May 07 12:38:04 PM PDT 24
Peak memory 220204 kb
Host smart-61a40036-a38b-4535-a7a6-b888a26198ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525057211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.1525057211
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.2524651790
Short name T308
Test name
Test status
Simulation time 753168960 ps
CPU time 32.65 seconds
Started May 07 12:38:10 PM PDT 24
Finished May 07 12:38:46 PM PDT 24
Peak memory 215108 kb
Host smart-27b80d80-9aa0-46e8-bb47-cc2dddb063f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2524651790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.2524651790
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.1084357995
Short name T203
Test name
Test status
Simulation time 1369188049 ps
CPU time 51.69 seconds
Started May 07 12:37:14 PM PDT 24
Finished May 07 12:38:09 PM PDT 24
Peak memory 216684 kb
Host smart-adcc0eb6-491d-4e09-b9cc-cc6539a65576
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084357995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.1084357995
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.2915535974
Short name T91
Test name
Test status
Simulation time 40315818 ps
CPU time 2.97 seconds
Started May 07 12:37:16 PM PDT 24
Finished May 07 12:37:23 PM PDT 24
Peak memory 208564 kb
Host smart-6762b0f5-b439-4101-8fbd-f09bd8514850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915535974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.2915535974
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.52874056
Short name T185
Test name
Test status
Simulation time 201620020 ps
CPU time 9.29 seconds
Started May 07 12:36:46 PM PDT 24
Finished May 07 12:36:58 PM PDT 24
Peak memory 219832 kb
Host smart-44051828-2732-4aea-8518-1e6d845c46ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52874056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.52874056
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.607560533
Short name T88
Test name
Test status
Simulation time 98465968 ps
CPU time 3.18 seconds
Started May 07 12:38:08 PM PDT 24
Finished May 07 12:38:15 PM PDT 24
Peak memory 214272 kb
Host smart-c664f6e7-e555-43ed-ba69-ac7a885e60c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607560533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.607560533
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.3897548008
Short name T399
Test name
Test status
Simulation time 290303345 ps
CPU time 14.39 seconds
Started May 07 12:38:04 PM PDT 24
Finished May 07 12:38:22 PM PDT 24
Peak memory 215592 kb
Host smart-9ebbc6a7-a0f0-4f09-8263-1820a67653b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3897548008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.3897548008
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.1835812975
Short name T366
Test name
Test status
Simulation time 275853590 ps
CPU time 1.46 seconds
Started May 07 12:36:52 PM PDT 24
Finished May 07 12:36:56 PM PDT 24
Peak memory 209948 kb
Host smart-255e5657-b7ce-4919-a2a7-adcaaaf7f10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835812975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.1835812975
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.1683280260
Short name T59
Test name
Test status
Simulation time 835026927 ps
CPU time 33.15 seconds
Started May 07 12:36:42 PM PDT 24
Finished May 07 12:37:18 PM PDT 24
Peak memory 222376 kb
Host smart-8f4e60c6-7c2a-4628-a132-40efe1d01ead
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683280260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.1683280260
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.851091834
Short name T139
Test name
Test status
Simulation time 572927957 ps
CPU time 3.75 seconds
Started May 07 01:07:03 PM PDT 24
Finished May 07 01:07:08 PM PDT 24
Peak memory 213904 kb
Host smart-cd7c7f72-bf6c-4aab-80c0-7df2e4cfc22a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851091834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_err
.851091834
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.1604590223
Short name T443
Test name
Test status
Simulation time 16888538 ps
CPU time 0.95 seconds
Started May 07 12:37:04 PM PDT 24
Finished May 07 12:37:06 PM PDT 24
Peak memory 206076 kb
Host smart-64ae0f06-f664-4c03-94e6-74550fba4a41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604590223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.1604590223
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.2322883031
Short name T76
Test name
Test status
Simulation time 1346080811 ps
CPU time 37.67 seconds
Started May 07 12:37:08 PM PDT 24
Finished May 07 12:37:48 PM PDT 24
Peak memory 216440 kb
Host smart-271dd6b8-d3e2-4900-bd08-caeb4ce47b03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322883031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.2322883031
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.1973006501
Short name T142
Test name
Test status
Simulation time 584365436 ps
CPU time 12.94 seconds
Started May 07 01:07:16 PM PDT 24
Finished May 07 01:07:30 PM PDT 24
Peak memory 216476 kb
Host smart-2e359071-f496-44d5-8779-ceacf7a20c03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973006501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.1973006501
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.2491191105
Short name T122
Test name
Test status
Simulation time 1053994654 ps
CPU time 14.8 seconds
Started May 07 12:36:52 PM PDT 24
Finished May 07 12:37:10 PM PDT 24
Peak memory 214272 kb
Host smart-8ab04ec1-85a9-48e8-bde7-098ad6301ca5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2491191105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.2491191105
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.4013154096
Short name T29
Test name
Test status
Simulation time 273135283 ps
CPU time 3.87 seconds
Started May 07 12:38:08 PM PDT 24
Finished May 07 12:38:16 PM PDT 24
Peak memory 222716 kb
Host smart-0e565df5-6e54-4164-8e01-945c48cff4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013154096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.4013154096
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.524357324
Short name T52
Test name
Test status
Simulation time 470855361 ps
CPU time 18.26 seconds
Started May 07 12:37:09 PM PDT 24
Finished May 07 12:37:30 PM PDT 24
Peak memory 220844 kb
Host smart-1c75e650-d38e-4f04-bc58-2799e7585ad5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524357324 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.524357324
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.1089400196
Short name T216
Test name
Test status
Simulation time 3063954415 ps
CPU time 45.34 seconds
Started May 07 12:37:42 PM PDT 24
Finished May 07 12:38:29 PM PDT 24
Peak memory 222556 kb
Host smart-bec5ff73-0778-4a57-9903-ee79db7d5c6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089400196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.1089400196
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.2723132568
Short name T121
Test name
Test status
Simulation time 3535847922 ps
CPU time 34.72 seconds
Started May 07 12:36:58 PM PDT 24
Finished May 07 12:37:35 PM PDT 24
Peak memory 222472 kb
Host smart-2e3e23d7-a0e9-4512-8001-49a78baa5eb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723132568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.2723132568
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.820377570
Short name T110
Test name
Test status
Simulation time 1114330512 ps
CPU time 3.06 seconds
Started May 07 01:06:31 PM PDT 24
Finished May 07 01:06:35 PM PDT 24
Peak memory 214312 kb
Host smart-f3237396-91d9-4d1b-809c-fbcf128e74d7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820377570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow
_reg_errors.820377570
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.1560431998
Short name T358
Test name
Test status
Simulation time 214142598 ps
CPU time 11.58 seconds
Started May 07 12:37:15 PM PDT 24
Finished May 07 12:37:30 PM PDT 24
Peak memory 214408 kb
Host smart-7e1f42af-af79-4946-90cb-52c1f00f5342
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1560431998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.1560431998
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.3075418498
Short name T140
Test name
Test status
Simulation time 966808691 ps
CPU time 9.86 seconds
Started May 07 01:06:25 PM PDT 24
Finished May 07 01:06:37 PM PDT 24
Peak memory 213948 kb
Host smart-4f0bb3a1-1e42-447d-8980-f295ba698669
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075418498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.3075418498
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.3534497586
Short name T86
Test name
Test status
Simulation time 231935796 ps
CPU time 8.41 seconds
Started May 07 12:38:07 PM PDT 24
Finished May 07 12:38:19 PM PDT 24
Peak memory 218220 kb
Host smart-8f085d2f-a89c-4489-99d6-6d61f8f80dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534497586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.3534497586
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.742116137
Short name T47
Test name
Test status
Simulation time 723911484 ps
CPU time 2.81 seconds
Started May 07 12:36:51 PM PDT 24
Finished May 07 12:36:56 PM PDT 24
Peak memory 214320 kb
Host smart-3b90519d-e45e-4003-b255-706b7953db2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742116137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.742116137
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.3906219204
Short name T135
Test name
Test status
Simulation time 76197412 ps
CPU time 2.78 seconds
Started May 07 12:38:05 PM PDT 24
Finished May 07 12:38:12 PM PDT 24
Peak memory 222516 kb
Host smart-d74c5f6b-4a23-4ea6-9410-8785f88e1c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906219204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.3906219204
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.446453962
Short name T138
Test name
Test status
Simulation time 390485976 ps
CPU time 3.73 seconds
Started May 07 12:37:58 PM PDT 24
Finished May 07 12:38:03 PM PDT 24
Peak memory 218292 kb
Host smart-def5a517-2c38-49bc-9122-34629e038ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446453962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.446453962
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.1103086303
Short name T36
Test name
Test status
Simulation time 447079119 ps
CPU time 3.47 seconds
Started May 07 12:37:10 PM PDT 24
Finished May 07 12:37:16 PM PDT 24
Peak memory 214348 kb
Host smart-8497a97c-f272-4d0c-9f51-65f6238a830e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103086303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.1103086303
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.3950690588
Short name T299
Test name
Test status
Simulation time 94707523 ps
CPU time 4.44 seconds
Started May 07 12:37:17 PM PDT 24
Finished May 07 12:37:25 PM PDT 24
Peak memory 214284 kb
Host smart-89731c7d-1440-4fbb-8749-9627fc21d9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950690588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.3950690588
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.3384936975
Short name T404
Test name
Test status
Simulation time 1840093164 ps
CPU time 49.96 seconds
Started May 07 12:38:07 PM PDT 24
Finished May 07 12:39:01 PM PDT 24
Peak memory 222528 kb
Host smart-b8eefbe0-744a-4fc3-8348-d127b3376708
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3384936975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.3384936975
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_random.354662509
Short name T184
Test name
Test status
Simulation time 698981842 ps
CPU time 4.99 seconds
Started May 07 12:36:29 PM PDT 24
Finished May 07 12:36:36 PM PDT 24
Peak memory 210592 kb
Host smart-caa51b56-a49c-4716-a1b7-8d1387e33b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354662509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.354662509
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.361121330
Short name T120
Test name
Test status
Simulation time 61093829 ps
CPU time 2.87 seconds
Started May 07 12:36:43 PM PDT 24
Finished May 07 12:36:48 PM PDT 24
Peak memory 214264 kb
Host smart-e1bf6445-015f-4b37-917c-a037f5c2f435
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=361121330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.361121330
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.1688158932
Short name T60
Test name
Test status
Simulation time 8919649079 ps
CPU time 93.91 seconds
Started May 07 12:37:12 PM PDT 24
Finished May 07 12:38:49 PM PDT 24
Peak memory 215988 kb
Host smart-89a8b258-e602-4306-9767-23a15bbaa6b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688158932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.1688158932
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.2113787454
Short name T208
Test name
Test status
Simulation time 3647170397 ps
CPU time 121.8 seconds
Started May 07 12:38:00 PM PDT 24
Finished May 07 12:40:04 PM PDT 24
Peak memory 216640 kb
Host smart-557be5ff-23b9-4d83-8033-eace6d74e004
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113787454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.2113787454
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.946611901
Short name T153
Test name
Test status
Simulation time 1089461161 ps
CPU time 7.52 seconds
Started May 07 01:06:19 PM PDT 24
Finished May 07 01:06:28 PM PDT 24
Peak memory 205752 kb
Host smart-4fb85d42-13a3-4781-9346-124c1aa429d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946611901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.
946611901
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.950275379
Short name T152
Test name
Test status
Simulation time 953110975 ps
CPU time 9.47 seconds
Started May 07 01:07:18 PM PDT 24
Finished May 07 01:07:29 PM PDT 24
Peak memory 213964 kb
Host smart-c188b932-2945-4aa3-be84-a0c9a5cfb5a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950275379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_err
.950275379
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.1039102219
Short name T11
Test name
Test status
Simulation time 1066124777 ps
CPU time 13.13 seconds
Started May 07 12:36:21 PM PDT 24
Finished May 07 12:36:37 PM PDT 24
Peak memory 238984 kb
Host smart-0cc6b476-3f58-4654-b7e0-33d8de3b15bf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039102219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.1039102219
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.3289671508
Short name T248
Test name
Test status
Simulation time 106570737 ps
CPU time 2.79 seconds
Started May 07 12:36:27 PM PDT 24
Finished May 07 12:36:32 PM PDT 24
Peak memory 222340 kb
Host smart-122e4af3-cf18-45d6-899e-bf9c8349aab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289671508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.3289671508
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.3827847068
Short name T281
Test name
Test status
Simulation time 72861891 ps
CPU time 3.93 seconds
Started May 07 12:36:52 PM PDT 24
Finished May 07 12:36:59 PM PDT 24
Peak memory 220872 kb
Host smart-0858b00f-c514-4c3a-ba7f-81593e3d2190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827847068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.3827847068
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.1024471726
Short name T254
Test name
Test status
Simulation time 208646879 ps
CPU time 5.87 seconds
Started May 07 12:37:09 PM PDT 24
Finished May 07 12:37:17 PM PDT 24
Peak memory 209384 kb
Host smart-9b70ba4c-3343-46b6-8205-34dbef5400f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024471726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.1024471726
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.3241366919
Short name T324
Test name
Test status
Simulation time 220293597 ps
CPU time 2.6 seconds
Started May 07 12:37:05 PM PDT 24
Finished May 07 12:37:10 PM PDT 24
Peak memory 214360 kb
Host smart-332ea0d0-5cbf-4d5b-a4fc-6cc94338af5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241366919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.3241366919
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.1196897575
Short name T221
Test name
Test status
Simulation time 2217236694 ps
CPU time 110.98 seconds
Started May 07 12:37:29 PM PDT 24
Finished May 07 12:39:22 PM PDT 24
Peak memory 214396 kb
Host smart-8fbd4efd-8cdf-44a3-ade5-b87a14ddd3ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1196897575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.1196897575
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.1039412074
Short name T389
Test name
Test status
Simulation time 84761463 ps
CPU time 3.24 seconds
Started May 07 12:38:02 PM PDT 24
Finished May 07 12:38:08 PM PDT 24
Peak memory 208804 kb
Host smart-a996bc20-8e9e-44a6-9929-867ab66b414d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039412074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.1039412074
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.2566460000
Short name T2
Test name
Test status
Simulation time 88857073 ps
CPU time 2.59 seconds
Started May 07 12:37:21 PM PDT 24
Finished May 07 12:37:27 PM PDT 24
Peak memory 210320 kb
Host smart-df98615d-52ca-4009-9923-4ff29d9a7a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566460000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.2566460000
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.2893871308
Short name T143
Test name
Test status
Simulation time 109550670 ps
CPU time 2.93 seconds
Started May 07 12:37:33 PM PDT 24
Finished May 07 12:37:38 PM PDT 24
Peak memory 210880 kb
Host smart-44ecf28e-7100-44d9-94f5-75e65cc0f8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893871308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.2893871308
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.1615623283
Short name T137
Test name
Test status
Simulation time 52835370 ps
CPU time 2.38 seconds
Started May 07 12:37:40 PM PDT 24
Finished May 07 12:37:44 PM PDT 24
Peak memory 222524 kb
Host smart-597e17c8-f741-4262-ad90-2ecd0cb4b34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615623283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.1615623283
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.1858470988
Short name T306
Test name
Test status
Simulation time 3278481420 ps
CPU time 14.93 seconds
Started May 07 12:36:29 PM PDT 24
Finished May 07 12:36:46 PM PDT 24
Peak memory 220760 kb
Host smart-9d0e3ec3-d462-4b4d-950d-f1f5ae66f2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858470988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.1858470988
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.2128372492
Short name T296
Test name
Test status
Simulation time 1636007515 ps
CPU time 49.85 seconds
Started May 07 12:36:57 PM PDT 24
Finished May 07 12:37:49 PM PDT 24
Peak memory 216136 kb
Host smart-5d522014-9162-4593-a81d-9a4071afb2f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128372492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.2128372492
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.3897230132
Short name T217
Test name
Test status
Simulation time 5073048311 ps
CPU time 37.12 seconds
Started May 07 12:36:50 PM PDT 24
Finished May 07 12:37:30 PM PDT 24
Peak memory 215580 kb
Host smart-c4ab7cae-8c22-4d0b-a381-ba9796229b22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897230132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.3897230132
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.3379067599
Short name T405
Test name
Test status
Simulation time 118844217 ps
CPU time 6.65 seconds
Started May 07 12:37:17 PM PDT 24
Finished May 07 12:37:27 PM PDT 24
Peak memory 215400 kb
Host smart-67b44ef5-def6-40c8-8170-0aa59a076f66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3379067599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.3379067599
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_random.3513965831
Short name T302
Test name
Test status
Simulation time 1911885243 ps
CPU time 6.16 seconds
Started May 07 12:37:15 PM PDT 24
Finished May 07 12:37:25 PM PDT 24
Peak memory 209880 kb
Host smart-22440897-20bf-459a-aad4-5dbf7dc1b1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513965831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.3513965831
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.3546534293
Short name T205
Test name
Test status
Simulation time 377179723 ps
CPU time 15.14 seconds
Started May 07 12:37:13 PM PDT 24
Finished May 07 12:37:32 PM PDT 24
Peak memory 222324 kb
Host smart-aba3cd3b-35f4-4c67-b214-0b1d71188a5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546534293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.3546534293
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.2513241162
Short name T341
Test name
Test status
Simulation time 81276688 ps
CPU time 3.17 seconds
Started May 07 12:37:37 PM PDT 24
Finished May 07 12:37:41 PM PDT 24
Peak memory 222380 kb
Host smart-77940198-7021-4246-bb63-23e2a17d63d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513241162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.2513241162
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_random.843974027
Short name T189
Test name
Test status
Simulation time 191967800 ps
CPU time 3.38 seconds
Started May 07 12:37:56 PM PDT 24
Finished May 07 12:38:01 PM PDT 24
Peak memory 218316 kb
Host smart-7cb06bc3-190f-4ab9-8ca8-4a97548e48b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843974027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.843974027
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.96384919
Short name T90
Test name
Test status
Simulation time 82788204 ps
CPU time 2.86 seconds
Started May 07 12:37:46 PM PDT 24
Finished May 07 12:37:50 PM PDT 24
Peak memory 220724 kb
Host smart-3ad5595e-fec9-457d-9f1e-1fcdbeab74b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96384919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.96384919
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.2725829938
Short name T357
Test name
Test status
Simulation time 59698695 ps
CPU time 2.88 seconds
Started May 07 12:37:45 PM PDT 24
Finished May 07 12:37:49 PM PDT 24
Peak memory 214188 kb
Host smart-066d970c-77df-4b4e-882a-df75a26b5710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725829938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.2725829938
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.1155636247
Short name T150
Test name
Test status
Simulation time 1298650167 ps
CPU time 5.11 seconds
Started May 07 01:06:57 PM PDT 24
Finished May 07 01:07:03 PM PDT 24
Peak memory 213904 kb
Host smart-9e5c7068-fe02-4ffc-8c96-376e7d2edc67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155636247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.1155636247
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.3899767154
Short name T157
Test name
Test status
Simulation time 260066840 ps
CPU time 3.85 seconds
Started May 07 01:06:26 PM PDT 24
Finished May 07 01:06:31 PM PDT 24
Peak memory 205776 kb
Host smart-2a96b6f8-d111-491f-bce7-c8a8e9b0d0d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899767154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.3899767154
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.3018915496
Short name T147
Test name
Test status
Simulation time 120226075 ps
CPU time 3.35 seconds
Started May 07 01:06:48 PM PDT 24
Finished May 07 01:06:53 PM PDT 24
Peak memory 205840 kb
Host smart-6e59939d-f81d-4439-bce6-ad717573ef1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018915496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.3018915496
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.1086474528
Short name T21
Test name
Test status
Simulation time 602814591 ps
CPU time 6.22 seconds
Started May 07 12:36:52 PM PDT 24
Finished May 07 12:37:01 PM PDT 24
Peak memory 214512 kb
Host smart-31e4d8bf-3d86-4fa2-9592-306c59d8da11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086474528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.1086474528
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.4286720718
Short name T62
Test name
Test status
Simulation time 96164183 ps
CPU time 4.5 seconds
Started May 07 12:36:15 PM PDT 24
Finished May 07 12:36:22 PM PDT 24
Peak memory 215744 kb
Host smart-43e179c9-ba44-4abe-8782-ae5cbc087639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286720718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.4286720718
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.2241701928
Short name T292
Test name
Test status
Simulation time 5145985950 ps
CPU time 37.98 seconds
Started May 07 12:36:22 PM PDT 24
Finished May 07 12:37:02 PM PDT 24
Peak memory 215180 kb
Host smart-4734a46e-8177-4b15-bdf4-69d4931993ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2241701928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.2241701928
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.3939172218
Short name T391
Test name
Test status
Simulation time 201239004 ps
CPU time 2.86 seconds
Started May 07 12:36:16 PM PDT 24
Finished May 07 12:36:21 PM PDT 24
Peak memory 207340 kb
Host smart-f28288a0-a90f-4368-b0ed-3bf8a21c9e41
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939172218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.3939172218
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.218524228
Short name T141
Test name
Test status
Simulation time 362049481 ps
CPU time 1.68 seconds
Started May 07 12:36:27 PM PDT 24
Finished May 07 12:36:35 PM PDT 24
Peak memory 210084 kb
Host smart-bb3293dc-b5fa-4a05-a52a-5578d437af12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218524228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.218524228
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.434435477
Short name T268
Test name
Test status
Simulation time 1664020494 ps
CPU time 3.69 seconds
Started May 07 12:36:44 PM PDT 24
Finished May 07 12:36:51 PM PDT 24
Peak memory 209680 kb
Host smart-edbb4e0a-15f1-4d4e-92a2-c36fa867033c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434435477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.434435477
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.2124713864
Short name T361
Test name
Test status
Simulation time 440002976 ps
CPU time 4.89 seconds
Started May 07 12:37:14 PM PDT 24
Finished May 07 12:37:23 PM PDT 24
Peak memory 214308 kb
Host smart-c8fab3e1-0537-4f77-9bc5-5306aa0afb09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124713864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.2124713864
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.1347880029
Short name T84
Test name
Test status
Simulation time 99136905 ps
CPU time 3.87 seconds
Started May 07 12:36:53 PM PDT 24
Finished May 07 12:36:59 PM PDT 24
Peak memory 214284 kb
Host smart-c8234d74-2e4b-4cae-a49e-1469f3e822cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347880029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.1347880029
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.1148315452
Short name T240
Test name
Test status
Simulation time 37513529852 ps
CPU time 73.95 seconds
Started May 07 12:36:21 PM PDT 24
Finished May 07 12:37:38 PM PDT 24
Peak memory 217652 kb
Host smart-5927bcde-7400-4cb1-a21b-f49c773541f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148315452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.1148315452
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.2737905023
Short name T331
Test name
Test status
Simulation time 1704665825 ps
CPU time 45.5 seconds
Started May 07 12:37:20 PM PDT 24
Finished May 07 12:38:09 PM PDT 24
Peak memory 215784 kb
Host smart-e234398f-4363-4ffc-ae5b-a9e2312caad4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737905023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.2737905023
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.704629851
Short name T214
Test name
Test status
Simulation time 2945681658 ps
CPU time 20.1 seconds
Started May 07 12:37:58 PM PDT 24
Finished May 07 12:38:19 PM PDT 24
Peak memory 214908 kb
Host smart-b2c19b4f-df61-40a2-a50c-1416bb736ba6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704629851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.704629851
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.1090546408
Short name T58
Test name
Test status
Simulation time 2484895447 ps
CPU time 25.03 seconds
Started May 07 12:38:20 PM PDT 24
Finished May 07 12:38:46 PM PDT 24
Peak memory 222672 kb
Host smart-a0da3305-46f9-467e-b409-63829d9b2ee0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090546408 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.1090546408
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.2031933563
Short name T136
Test name
Test status
Simulation time 286013380 ps
CPU time 3.03 seconds
Started May 07 12:38:10 PM PDT 24
Finished May 07 12:38:18 PM PDT 24
Peak memory 222444 kb
Host smart-725e4768-53c4-4b2f-a5f4-db5df016de7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031933563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.2031933563
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.2029497782
Short name T1048
Test name
Test status
Simulation time 791024406 ps
CPU time 4.77 seconds
Started May 07 01:06:31 PM PDT 24
Finished May 07 01:06:37 PM PDT 24
Peak memory 205804 kb
Host smart-ea72704d-4b78-4a72-a983-6f4b83c1342f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029497782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.2
029497782
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.3595931311
Short name T981
Test name
Test status
Simulation time 1661334578 ps
CPU time 12.77 seconds
Started May 07 01:06:21 PM PDT 24
Finished May 07 01:06:35 PM PDT 24
Peak memory 205744 kb
Host smart-bb8326fb-0360-4c05-8f5e-a1503fb3ebc9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595931311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.3
595931311
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.2010612916
Short name T990
Test name
Test status
Simulation time 29293171 ps
CPU time 1.13 seconds
Started May 07 01:06:20 PM PDT 24
Finished May 07 01:06:23 PM PDT 24
Peak memory 205812 kb
Host smart-f0a34ddc-2f27-415d-8de1-f64c6e6a58d1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010612916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.2
010612916
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.1860409618
Short name T983
Test name
Test status
Simulation time 117459117 ps
CPU time 1.07 seconds
Started May 07 01:06:20 PM PDT 24
Finished May 07 01:06:23 PM PDT 24
Peak memory 205704 kb
Host smart-9ee24d71-c8d6-414b-af76-0061302993bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860409618 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.1860409618
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.1419042353
Short name T1047
Test name
Test status
Simulation time 17147185 ps
CPU time 1.02 seconds
Started May 07 01:06:20 PM PDT 24
Finished May 07 01:06:23 PM PDT 24
Peak memory 205752 kb
Host smart-a139d33b-0233-49f5-85f9-06cb2ce3599a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419042353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.1419042353
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.1422739453
Short name T949
Test name
Test status
Simulation time 11932199 ps
CPU time 0.81 seconds
Started May 07 01:06:30 PM PDT 24
Finished May 07 01:06:33 PM PDT 24
Peak memory 205432 kb
Host smart-f39ad4f7-7bbb-4f5a-9d9e-21b5804f4d25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422739453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.1422739453
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.1821546778
Short name T955
Test name
Test status
Simulation time 701878583 ps
CPU time 2.23 seconds
Started May 07 01:06:20 PM PDT 24
Finished May 07 01:06:24 PM PDT 24
Peak memory 205748 kb
Host smart-eccb0eaf-e8ec-4449-b555-207dacb9c0ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821546778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.1821546778
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.2490730108
Short name T1021
Test name
Test status
Simulation time 132902943 ps
CPU time 4.09 seconds
Started May 07 01:06:20 PM PDT 24
Finished May 07 01:06:26 PM PDT 24
Peak memory 214232 kb
Host smart-f781a758-4411-4390-84c8-e9db7a61495b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490730108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.2490730108
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.798657579
Short name T1018
Test name
Test status
Simulation time 380053330 ps
CPU time 4.67 seconds
Started May 07 01:06:31 PM PDT 24
Finished May 07 01:06:37 PM PDT 24
Peak memory 214252 kb
Host smart-a91dee1d-1b07-4f3b-8316-807c648f0836
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798657579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.k
eymgr_shadow_reg_errors_with_csr_rw.798657579
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.2073150837
Short name T1079
Test name
Test status
Simulation time 106831212 ps
CPU time 2.83 seconds
Started May 07 01:06:19 PM PDT 24
Finished May 07 01:06:24 PM PDT 24
Peak memory 214024 kb
Host smart-54d9e7fa-ea71-4467-b98f-30df7ecb79e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073150837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.2073150837
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.4275259849
Short name T156
Test name
Test status
Simulation time 200250827 ps
CPU time 3.29 seconds
Started May 07 01:06:31 PM PDT 24
Finished May 07 01:06:36 PM PDT 24
Peak memory 205144 kb
Host smart-f22c2dd2-6bf3-4616-8102-6e88be5e4e8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275259849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.4275259849
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.1942296870
Short name T1040
Test name
Test status
Simulation time 730463836 ps
CPU time 9.66 seconds
Started May 07 01:06:19 PM PDT 24
Finished May 07 01:06:30 PM PDT 24
Peak memory 205840 kb
Host smart-ff8e3e67-3765-4b14-bd6a-08b4f06cb06c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942296870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.1
942296870
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.511683119
Short name T966
Test name
Test status
Simulation time 2700772724 ps
CPU time 12.73 seconds
Started May 07 01:06:21 PM PDT 24
Finished May 07 01:06:35 PM PDT 24
Peak memory 205800 kb
Host smart-07868475-7fdf-46bb-8d29-d67d8e444d20
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511683119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.511683119
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2006423544
Short name T1015
Test name
Test status
Simulation time 60821542 ps
CPU time 0.91 seconds
Started May 07 01:06:19 PM PDT 24
Finished May 07 01:06:21 PM PDT 24
Peak memory 205568 kb
Host smart-ea0886b7-c1d1-4f18-87fc-fa5da092276c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006423544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.2
006423544
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1398100425
Short name T1033
Test name
Test status
Simulation time 185215904 ps
CPU time 1.26 seconds
Started May 07 01:06:27 PM PDT 24
Finished May 07 01:06:30 PM PDT 24
Peak memory 214032 kb
Host smart-0cb380fe-a4cd-437f-b85a-65630af994f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398100425 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.1398100425
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.3659467937
Short name T124
Test name
Test status
Simulation time 31056458 ps
CPU time 1.08 seconds
Started May 07 01:06:20 PM PDT 24
Finished May 07 01:06:23 PM PDT 24
Peak memory 205640 kb
Host smart-9d774002-0091-4a75-8cf6-2692ee1404fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659467937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.3659467937
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1567678045
Short name T1041
Test name
Test status
Simulation time 18911213 ps
CPU time 0.78 seconds
Started May 07 01:06:31 PM PDT 24
Finished May 07 01:06:33 PM PDT 24
Peak memory 204784 kb
Host smart-e2044625-ca74-4a38-b9a1-ce0664d7d113
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567678045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.1567678045
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.89969416
Short name T987
Test name
Test status
Simulation time 55878546 ps
CPU time 2.07 seconds
Started May 07 01:06:20 PM PDT 24
Finished May 07 01:06:24 PM PDT 24
Peak memory 205756 kb
Host smart-d0c0d17b-0d5f-4f77-94e7-98a4bd7cdecb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89969416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_same
_csr_outstanding.89969416
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1976163581
Short name T1005
Test name
Test status
Simulation time 61109199 ps
CPU time 1.95 seconds
Started May 07 01:06:20 PM PDT 24
Finished May 07 01:06:23 PM PDT 24
Peak memory 213832 kb
Host smart-dd286bd9-8813-4a21-88d9-23c6ada8ef29
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976163581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.1976163581
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1361887412
Short name T1010
Test name
Test status
Simulation time 109313134 ps
CPU time 1.39 seconds
Started May 07 01:06:59 PM PDT 24
Finished May 07 01:07:01 PM PDT 24
Peak memory 205840 kb
Host smart-7856bad1-3f05-4afd-bd65-6f22f9ea005d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361887412 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.1361887412
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.4280735571
Short name T1020
Test name
Test status
Simulation time 27181369 ps
CPU time 1.15 seconds
Started May 07 01:06:57 PM PDT 24
Finished May 07 01:06:59 PM PDT 24
Peak memory 205740 kb
Host smart-da05d91e-0351-430f-b4ab-81ed4f9d02ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280735571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.4280735571
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1192947539
Short name T1017
Test name
Test status
Simulation time 48616350 ps
CPU time 0.84 seconds
Started May 07 01:07:00 PM PDT 24
Finished May 07 01:07:02 PM PDT 24
Peak memory 205444 kb
Host smart-fad3d8fd-0663-4fe0-b900-9c1a3041b580
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192947539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.1192947539
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2635464742
Short name T929
Test name
Test status
Simulation time 954542426 ps
CPU time 2.62 seconds
Started May 07 01:06:57 PM PDT 24
Finished May 07 01:07:01 PM PDT 24
Peak memory 205708 kb
Host smart-6275f1ae-7fe9-4c80-8955-ec90d97041e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635464742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.2635464742
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.438395810
Short name T109
Test name
Test status
Simulation time 408341350 ps
CPU time 2.04 seconds
Started May 07 01:06:50 PM PDT 24
Finished May 07 01:06:53 PM PDT 24
Peak memory 214380 kb
Host smart-6337404c-5cbe-447b-a048-98610670d1ab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438395810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shado
w_reg_errors.438395810
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.117531717
Short name T1013
Test name
Test status
Simulation time 304680246 ps
CPU time 4.35 seconds
Started May 07 01:06:49 PM PDT 24
Finished May 07 01:06:55 PM PDT 24
Peak memory 214324 kb
Host smart-b0b596ee-db6a-4396-bbf2-1b125e9f65ce
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117531717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
keymgr_shadow_reg_errors_with_csr_rw.117531717
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1018717361
Short name T1076
Test name
Test status
Simulation time 166350441 ps
CPU time 1.65 seconds
Started May 07 01:06:58 PM PDT 24
Finished May 07 01:07:01 PM PDT 24
Peak memory 213872 kb
Host smart-44c49dbf-2641-46df-be82-ff7f429ca222
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018717361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.1018717361
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.717206512
Short name T1035
Test name
Test status
Simulation time 112004217 ps
CPU time 4.47 seconds
Started May 07 01:06:58 PM PDT 24
Finished May 07 01:07:04 PM PDT 24
Peak memory 213976 kb
Host smart-69451247-d6bd-4603-88ba-ac0c9d8ce8ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717206512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err
.717206512
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.2103430746
Short name T376
Test name
Test status
Simulation time 50431006 ps
CPU time 1.64 seconds
Started May 07 01:07:01 PM PDT 24
Finished May 07 01:07:04 PM PDT 24
Peak memory 213992 kb
Host smart-1b534eb5-62e9-4348-af46-f2bf5951f33d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103430746 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.2103430746
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.2166323575
Short name T1006
Test name
Test status
Simulation time 30030072 ps
CPU time 1.1 seconds
Started May 07 01:06:56 PM PDT 24
Finished May 07 01:06:58 PM PDT 24
Peak memory 205720 kb
Host smart-a7c97f16-325c-4894-9a31-d583592b5356
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166323575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.2166323575
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.781168491
Short name T1039
Test name
Test status
Simulation time 37466421 ps
CPU time 0.82 seconds
Started May 07 01:06:58 PM PDT 24
Finished May 07 01:07:00 PM PDT 24
Peak memory 205276 kb
Host smart-b6186c21-4587-43ca-8cf6-2bcd8064b2d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781168491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.781168491
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.977304452
Short name T129
Test name
Test status
Simulation time 443138004 ps
CPU time 2.39 seconds
Started May 07 01:06:58 PM PDT 24
Finished May 07 01:07:01 PM PDT 24
Peak memory 205712 kb
Host smart-9e935eb9-7ce2-4e99-a2dc-75076be21ec0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977304452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_sa
me_csr_outstanding.977304452
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.4058529892
Short name T944
Test name
Test status
Simulation time 162992325 ps
CPU time 2.95 seconds
Started May 07 01:06:58 PM PDT 24
Finished May 07 01:07:02 PM PDT 24
Peak memory 214340 kb
Host smart-0a83271b-a1af-4f2e-8b3b-8b368d4d37b1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058529892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.4058529892
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2821717006
Short name T1003
Test name
Test status
Simulation time 1754248890 ps
CPU time 10.68 seconds
Started May 07 01:06:57 PM PDT 24
Finished May 07 01:07:09 PM PDT 24
Peak memory 214288 kb
Host smart-1e7894fa-65dc-45b2-9ebd-00faa33824fa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821717006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.2821717006
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.4003101219
Short name T1072
Test name
Test status
Simulation time 164282842 ps
CPU time 1.71 seconds
Started May 07 01:07:00 PM PDT 24
Finished May 07 01:07:03 PM PDT 24
Peak memory 213852 kb
Host smart-82fb4a4b-5960-40a1-b424-62212e6b9fe2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003101219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.4003101219
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.623560145
Short name T1027
Test name
Test status
Simulation time 34594905 ps
CPU time 1.28 seconds
Started May 07 01:07:03 PM PDT 24
Finished May 07 01:07:05 PM PDT 24
Peak memory 205704 kb
Host smart-bb3baf21-17a2-459b-ad27-2770b0053403
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623560145 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.623560145
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.3526089068
Short name T123
Test name
Test status
Simulation time 17957341 ps
CPU time 1.26 seconds
Started May 07 01:07:01 PM PDT 24
Finished May 07 01:07:04 PM PDT 24
Peak memory 205796 kb
Host smart-86fb7592-03fe-488b-abb0-bd9e702b01b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526089068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.3526089068
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.726318701
Short name T960
Test name
Test status
Simulation time 16328713 ps
CPU time 0.71 seconds
Started May 07 01:06:59 PM PDT 24
Finished May 07 01:07:01 PM PDT 24
Peak memory 205300 kb
Host smart-c1a2654c-ee67-435e-b8f1-b3dcd7a08c0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726318701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.726318701
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3126520670
Short name T127
Test name
Test status
Simulation time 244969778 ps
CPU time 1.72 seconds
Started May 07 01:06:57 PM PDT 24
Finished May 07 01:07:00 PM PDT 24
Peak memory 205724 kb
Host smart-196931bf-1119-42ac-9750-2f325077aef7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126520670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.3126520670
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2109470069
Short name T1034
Test name
Test status
Simulation time 117919826 ps
CPU time 2.25 seconds
Started May 07 01:06:58 PM PDT 24
Finished May 07 01:07:01 PM PDT 24
Peak memory 214156 kb
Host smart-79101af5-f8ea-47f6-9833-3d0937a55a80
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109470069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.2109470069
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.4179276040
Short name T948
Test name
Test status
Simulation time 371154756 ps
CPU time 11.62 seconds
Started May 07 01:06:57 PM PDT 24
Finished May 07 01:07:09 PM PDT 24
Peak memory 220360 kb
Host smart-37b739b0-865c-4880-9c77-ccb8d236990a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179276040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.4179276040
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.2591597376
Short name T930
Test name
Test status
Simulation time 204927093 ps
CPU time 3.55 seconds
Started May 07 01:06:57 PM PDT 24
Finished May 07 01:07:02 PM PDT 24
Peak memory 213880 kb
Host smart-167bee25-f177-49b4-b5b9-327058be501c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591597376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.2591597376
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.1872855901
Short name T1031
Test name
Test status
Simulation time 251983426 ps
CPU time 1.59 seconds
Started May 07 01:07:04 PM PDT 24
Finished May 07 01:07:07 PM PDT 24
Peak memory 213972 kb
Host smart-36f854a0-1400-4c08-b904-cdc05864abde
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872855901 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.1872855901
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.3915463622
Short name T932
Test name
Test status
Simulation time 131312502 ps
CPU time 1.28 seconds
Started May 07 01:07:04 PM PDT 24
Finished May 07 01:07:07 PM PDT 24
Peak memory 205644 kb
Host smart-3c400329-06a8-4c04-a6c8-e779989fbf46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915463622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.3915463622
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.692824898
Short name T1026
Test name
Test status
Simulation time 8797297 ps
CPU time 0.84 seconds
Started May 07 01:07:02 PM PDT 24
Finished May 07 01:07:04 PM PDT 24
Peak memory 205372 kb
Host smart-3cb91fed-433c-42d8-a7d8-a728c719e36f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692824898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.692824898
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.3473768402
Short name T126
Test name
Test status
Simulation time 325458412 ps
CPU time 3.24 seconds
Started May 07 01:07:04 PM PDT 24
Finished May 07 01:07:09 PM PDT 24
Peak memory 205756 kb
Host smart-7ab7acf5-cb91-4818-82b4-67424ed36b8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473768402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.3473768402
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2240504718
Short name T984
Test name
Test status
Simulation time 274039548 ps
CPU time 2.76 seconds
Started May 07 01:07:00 PM PDT 24
Finished May 07 01:07:04 PM PDT 24
Peak memory 214224 kb
Host smart-58fe8469-0588-4b4b-8004-bc536188111f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240504718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.2240504718
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.973277060
Short name T936
Test name
Test status
Simulation time 247655272 ps
CPU time 3.25 seconds
Started May 07 01:06:58 PM PDT 24
Finished May 07 01:07:03 PM PDT 24
Peak memory 214196 kb
Host smart-01f9159f-f322-46e3-8a13-04d94492d099
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973277060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
keymgr_shadow_reg_errors_with_csr_rw.973277060
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.4015991244
Short name T991
Test name
Test status
Simulation time 25031710 ps
CPU time 1.68 seconds
Started May 07 01:07:00 PM PDT 24
Finished May 07 01:07:02 PM PDT 24
Peak memory 214980 kb
Host smart-b55946ac-e40d-4b80-a528-c7c71dbacd02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015991244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.4015991244
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.2727992923
Short name T151
Test name
Test status
Simulation time 875459239 ps
CPU time 3 seconds
Started May 07 01:06:58 PM PDT 24
Finished May 07 01:07:02 PM PDT 24
Peak memory 213888 kb
Host smart-900135e0-8816-4680-a911-b53fd1541fd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727992923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.2727992923
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.754569339
Short name T995
Test name
Test status
Simulation time 40832853 ps
CPU time 1.51 seconds
Started May 07 01:07:07 PM PDT 24
Finished May 07 01:07:10 PM PDT 24
Peak memory 213752 kb
Host smart-69954fd6-0705-4fff-a6da-fb9f68ae3762
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754569339 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.754569339
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.688993464
Short name T950
Test name
Test status
Simulation time 24829928 ps
CPU time 0.92 seconds
Started May 07 01:07:03 PM PDT 24
Finished May 07 01:07:04 PM PDT 24
Peak memory 205660 kb
Host smart-2b7fd7c8-708e-4b72-a851-8e81b3728735
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688993464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.688993464
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.1495662692
Short name T923
Test name
Test status
Simulation time 22546192 ps
CPU time 0.97 seconds
Started May 07 01:07:06 PM PDT 24
Finished May 07 01:07:09 PM PDT 24
Peak memory 205624 kb
Host smart-0ba56098-cd0a-4568-b529-4d135bf2b4fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495662692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.1495662692
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.2639584348
Short name T1036
Test name
Test status
Simulation time 40661777 ps
CPU time 1.56 seconds
Started May 07 01:07:05 PM PDT 24
Finished May 07 01:07:08 PM PDT 24
Peak memory 205616 kb
Host smart-07dc7240-3713-4fb7-abfd-3efcccd8a623
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639584348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.2639584348
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.1343009591
Short name T1011
Test name
Test status
Simulation time 176832949 ps
CPU time 2.12 seconds
Started May 07 01:07:05 PM PDT 24
Finished May 07 01:07:09 PM PDT 24
Peak memory 214244 kb
Host smart-b82291ac-c01e-44b4-ac37-438fb9687789
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343009591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.1343009591
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.4116175613
Short name T1085
Test name
Test status
Simulation time 728684549 ps
CPU time 8.27 seconds
Started May 07 01:07:03 PM PDT 24
Finished May 07 01:07:13 PM PDT 24
Peak memory 220084 kb
Host smart-13eab852-a9ed-4f87-a0f4-5a57f7c71ccf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116175613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.4116175613
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.25267245
Short name T1080
Test name
Test status
Simulation time 649165406 ps
CPU time 4.33 seconds
Started May 07 01:07:05 PM PDT 24
Finished May 07 01:07:11 PM PDT 24
Peak memory 217016 kb
Host smart-856a37a0-f858-4a86-bcbb-e273a694eaa3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25267245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.25267245
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.3056825909
Short name T1065
Test name
Test status
Simulation time 160680817 ps
CPU time 6.03 seconds
Started May 07 01:07:07 PM PDT 24
Finished May 07 01:07:15 PM PDT 24
Peak memory 214928 kb
Host smart-36dafd96-6af6-4ecf-a0cc-4938080c6c2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056825909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.3056825909
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3050665395
Short name T377
Test name
Test status
Simulation time 21901181 ps
CPU time 1.28 seconds
Started May 07 01:07:03 PM PDT 24
Finished May 07 01:07:06 PM PDT 24
Peak memory 205852 kb
Host smart-57343589-1138-48bd-b2db-0dbd5f4551ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050665395 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.3050665395
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.623382501
Short name T379
Test name
Test status
Simulation time 64636369 ps
CPU time 1.13 seconds
Started May 07 01:07:05 PM PDT 24
Finished May 07 01:07:07 PM PDT 24
Peak memory 205604 kb
Host smart-502be753-e5da-445c-bfec-02369d9e5dbf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623382501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.623382501
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.561783433
Short name T1028
Test name
Test status
Simulation time 10832555 ps
CPU time 0.72 seconds
Started May 07 01:07:08 PM PDT 24
Finished May 07 01:07:10 PM PDT 24
Peak memory 205356 kb
Host smart-7395e1bd-9739-4e08-8278-a2d6cb48cdec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561783433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.561783433
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3458166828
Short name T933
Test name
Test status
Simulation time 508072668 ps
CPU time 2.93 seconds
Started May 07 01:07:08 PM PDT 24
Finished May 07 01:07:12 PM PDT 24
Peak memory 205728 kb
Host smart-7ae7de40-746a-4bef-8c4d-9b9c64af4592
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458166828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.3458166828
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.3508753536
Short name T106
Test name
Test status
Simulation time 127743497 ps
CPU time 2.31 seconds
Started May 07 01:07:07 PM PDT 24
Finished May 07 01:07:11 PM PDT 24
Peak memory 214304 kb
Host smart-25ed144a-c091-4b4b-8002-e44883871368
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508753536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.3508753536
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.4034038219
Short name T956
Test name
Test status
Simulation time 2379350251 ps
CPU time 6.69 seconds
Started May 07 01:07:05 PM PDT 24
Finished May 07 01:07:13 PM PDT 24
Peak memory 220372 kb
Host smart-554a8c44-649d-4c12-8451-522a5a22d91b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034038219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.4034038219
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.1256316902
Short name T943
Test name
Test status
Simulation time 199325423 ps
CPU time 2.92 seconds
Started May 07 01:07:04 PM PDT 24
Finished May 07 01:07:08 PM PDT 24
Peak memory 214008 kb
Host smart-7fac520d-ac43-4eaf-90fd-12f24d6bb0cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256316902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.1256316902
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.2864198247
Short name T149
Test name
Test status
Simulation time 600985793 ps
CPU time 4.21 seconds
Started May 07 01:07:05 PM PDT 24
Finished May 07 01:07:10 PM PDT 24
Peak memory 206108 kb
Host smart-20686689-9da0-499d-94f1-87eca363644f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864198247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.2864198247
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.3208622606
Short name T982
Test name
Test status
Simulation time 283012006 ps
CPU time 1.81 seconds
Started May 07 01:07:05 PM PDT 24
Finished May 07 01:07:09 PM PDT 24
Peak memory 213996 kb
Host smart-3012580f-38be-480a-a406-95dc4b917d46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208622606 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.3208622606
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.4252778510
Short name T970
Test name
Test status
Simulation time 215203716 ps
CPU time 1.21 seconds
Started May 07 01:07:04 PM PDT 24
Finished May 07 01:07:07 PM PDT 24
Peak memory 205676 kb
Host smart-b45ceb20-0252-4bcb-8c29-1a9641c522fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252778510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.4252778510
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3391535614
Short name T954
Test name
Test status
Simulation time 38004755 ps
CPU time 0.72 seconds
Started May 07 01:07:06 PM PDT 24
Finished May 07 01:07:09 PM PDT 24
Peak memory 205440 kb
Host smart-4eaf10d4-12e5-40e8-a63e-0c611dc6a599
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391535614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.3391535614
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.2539962796
Short name T1064
Test name
Test status
Simulation time 117343144 ps
CPU time 4.68 seconds
Started May 07 01:07:04 PM PDT 24
Finished May 07 01:07:10 PM PDT 24
Peak memory 205724 kb
Host smart-47958192-4936-45cd-834a-6b8966b5ddab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539962796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.2539962796
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3389221899
Short name T985
Test name
Test status
Simulation time 108865102 ps
CPU time 3.17 seconds
Started May 07 01:07:04 PM PDT 24
Finished May 07 01:07:09 PM PDT 24
Peak memory 214312 kb
Host smart-34195906-6416-4670-b1ab-b78aa239284b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389221899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.3389221899
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3744437030
Short name T1054
Test name
Test status
Simulation time 345718381 ps
CPU time 4.48 seconds
Started May 07 01:07:03 PM PDT 24
Finished May 07 01:07:08 PM PDT 24
Peak memory 214316 kb
Host smart-f4729707-aaae-4f34-a3b2-476df7f452e4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744437030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.3744437030
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.765002342
Short name T1075
Test name
Test status
Simulation time 81863000 ps
CPU time 3.12 seconds
Started May 07 01:07:04 PM PDT 24
Finished May 07 01:07:09 PM PDT 24
Peak memory 213948 kb
Host smart-744e500b-3870-42fa-bf35-8faf7d7876ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765002342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.765002342
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.2467162548
Short name T957
Test name
Test status
Simulation time 160055027 ps
CPU time 3.71 seconds
Started May 07 01:07:04 PM PDT 24
Finished May 07 01:07:09 PM PDT 24
Peak memory 214996 kb
Host smart-f5f0d43f-c533-4335-8d37-f67b7078c0cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467162548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.2467162548
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3750488340
Short name T937
Test name
Test status
Simulation time 46039324 ps
CPU time 2.09 seconds
Started May 07 01:07:14 PM PDT 24
Finished May 07 01:07:17 PM PDT 24
Peak memory 213988 kb
Host smart-267e9642-0114-4e89-9ada-3686c93b0d7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750488340 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.3750488340
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.2265537249
Short name T1030
Test name
Test status
Simulation time 14090045 ps
CPU time 1.3 seconds
Started May 07 01:07:14 PM PDT 24
Finished May 07 01:07:17 PM PDT 24
Peak memory 205800 kb
Host smart-0c322902-a196-4289-a6b6-782fedb5deaf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265537249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.2265537249
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.1607829657
Short name T980
Test name
Test status
Simulation time 14658394 ps
CPU time 0.76 seconds
Started May 07 01:07:19 PM PDT 24
Finished May 07 01:07:21 PM PDT 24
Peak memory 205352 kb
Host smart-ea2a1d22-c375-48be-b23d-9283487f271d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607829657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.1607829657
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.597598036
Short name T1050
Test name
Test status
Simulation time 46034159 ps
CPU time 1.46 seconds
Started May 07 01:07:14 PM PDT 24
Finished May 07 01:07:16 PM PDT 24
Peak memory 205804 kb
Host smart-6921c504-6b89-42dd-a43d-40d8dd14f970
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597598036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_sa
me_csr_outstanding.597598036
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.3470911820
Short name T939
Test name
Test status
Simulation time 711217629 ps
CPU time 2.09 seconds
Started May 07 01:07:07 PM PDT 24
Finished May 07 01:07:11 PM PDT 24
Peak memory 214228 kb
Host smart-b671ba04-1fa4-4292-909b-08c246fb757a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470911820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.3470911820
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.4241558909
Short name T972
Test name
Test status
Simulation time 169645570 ps
CPU time 8.37 seconds
Started May 07 01:07:08 PM PDT 24
Finished May 07 01:07:18 PM PDT 24
Peak memory 220904 kb
Host smart-9db46abb-b67b-4f02-9511-1867971cb475
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241558909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.4241558909
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.933597873
Short name T1044
Test name
Test status
Simulation time 214304365 ps
CPU time 2.75 seconds
Started May 07 01:07:05 PM PDT 24
Finished May 07 01:07:10 PM PDT 24
Peak memory 213980 kb
Host smart-b6869955-ca04-451f-be77-3821b3377722
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933597873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.933597873
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.828879074
Short name T146
Test name
Test status
Simulation time 518892630 ps
CPU time 5.45 seconds
Started May 07 01:07:14 PM PDT 24
Finished May 07 01:07:21 PM PDT 24
Peak memory 215152 kb
Host smart-98ca0d0d-e5a0-415c-aad4-299cf0f074e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828879074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_err
.828879074
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.1270542948
Short name T1037
Test name
Test status
Simulation time 270454198 ps
CPU time 2.17 seconds
Started May 07 01:07:15 PM PDT 24
Finished May 07 01:07:19 PM PDT 24
Peak memory 213940 kb
Host smart-109eaac2-690c-4de6-b433-22977454f4b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270542948 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.1270542948
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.612704094
Short name T1016
Test name
Test status
Simulation time 13831043 ps
CPU time 0.99 seconds
Started May 07 01:07:17 PM PDT 24
Finished May 07 01:07:19 PM PDT 24
Peak memory 205496 kb
Host smart-7f8830ad-57fb-41c6-8401-8478bdf700fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612704094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.612704094
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.346614260
Short name T947
Test name
Test status
Simulation time 40846661 ps
CPU time 0.84 seconds
Started May 07 01:07:15 PM PDT 24
Finished May 07 01:07:18 PM PDT 24
Peak memory 205456 kb
Host smart-df3de1bb-72e4-4cfd-a9bf-837cea445cb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346614260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.346614260
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.3974943931
Short name T130
Test name
Test status
Simulation time 118853819 ps
CPU time 3.86 seconds
Started May 07 01:07:15 PM PDT 24
Finished May 07 01:07:20 PM PDT 24
Peak memory 205776 kb
Host smart-40f79e7d-835f-4b6f-b463-3f7552a95468
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974943931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.3974943931
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.1097927825
Short name T1023
Test name
Test status
Simulation time 119453956 ps
CPU time 2.15 seconds
Started May 07 01:07:13 PM PDT 24
Finished May 07 01:07:16 PM PDT 24
Peak memory 214376 kb
Host smart-fa84bd04-16b3-41dc-bbe7-ffb616d95e0b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097927825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.1097927825
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3854822572
Short name T935
Test name
Test status
Simulation time 280551808 ps
CPU time 5.04 seconds
Started May 07 01:07:19 PM PDT 24
Finished May 07 01:07:25 PM PDT 24
Peak memory 220924 kb
Host smart-01fd1d0d-a7f5-4f09-8566-280e3a45ac04
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854822572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.3854822572
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.1244821877
Short name T1083
Test name
Test status
Simulation time 89219943 ps
CPU time 3.18 seconds
Started May 07 01:07:17 PM PDT 24
Finished May 07 01:07:21 PM PDT 24
Peak memory 213932 kb
Host smart-dcac4795-95e9-445d-9567-6253910039b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244821877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.1244821877
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.2216035105
Short name T1055
Test name
Test status
Simulation time 582084702 ps
CPU time 1.66 seconds
Started May 07 01:07:17 PM PDT 24
Finished May 07 01:07:19 PM PDT 24
Peak memory 213868 kb
Host smart-76f79abb-623e-4389-a10d-49f77439cd19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216035105 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.2216035105
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.2352948130
Short name T989
Test name
Test status
Simulation time 34041871 ps
CPU time 1.1 seconds
Started May 07 01:07:17 PM PDT 24
Finished May 07 01:07:19 PM PDT 24
Peak memory 205672 kb
Host smart-f6fdb3c5-b2fd-4b39-8f1b-f03da1d2c8ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352948130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.2352948130
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.2261177405
Short name T934
Test name
Test status
Simulation time 11614290 ps
CPU time 0.7 seconds
Started May 07 01:07:17 PM PDT 24
Finished May 07 01:07:19 PM PDT 24
Peak memory 205368 kb
Host smart-d4431d26-196a-4c15-a57b-42485d64233c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261177405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.2261177405
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.522787821
Short name T1001
Test name
Test status
Simulation time 87692347 ps
CPU time 1.47 seconds
Started May 07 01:07:13 PM PDT 24
Finished May 07 01:07:16 PM PDT 24
Peak memory 205764 kb
Host smart-8a7351f3-6fc1-47a8-bf30-51194b581f7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522787821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_sa
me_csr_outstanding.522787821
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.2474940024
Short name T996
Test name
Test status
Simulation time 135449422 ps
CPU time 2.11 seconds
Started May 07 01:07:19 PM PDT 24
Finished May 07 01:07:22 PM PDT 24
Peak memory 214272 kb
Host smart-a9104b08-98a4-4eb7-96df-fa2d7bfb4c66
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474940024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.2474940024
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1764799643
Short name T1073
Test name
Test status
Simulation time 2885100982 ps
CPU time 6.9 seconds
Started May 07 01:07:14 PM PDT 24
Finished May 07 01:07:22 PM PDT 24
Peak memory 214424 kb
Host smart-7378b48c-8676-4ff2-a1b0-92228256aaef
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764799643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.1764799643
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.3931078574
Short name T1009
Test name
Test status
Simulation time 288958994 ps
CPU time 2.12 seconds
Started May 07 01:07:16 PM PDT 24
Finished May 07 01:07:19 PM PDT 24
Peak memory 216020 kb
Host smart-f3363db1-e38e-4b50-9924-8f2a1f34c6bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931078574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.3931078574
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.715573862
Short name T1012
Test name
Test status
Simulation time 1649954714 ps
CPU time 8.24 seconds
Started May 07 01:06:27 PM PDT 24
Finished May 07 01:06:37 PM PDT 24
Peak memory 205756 kb
Host smart-f2990d9c-5d75-40a0-b4da-4d83cb319911
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715573862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.715573862
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.1099783088
Short name T1070
Test name
Test status
Simulation time 1784110634 ps
CPU time 7.81 seconds
Started May 07 01:06:27 PM PDT 24
Finished May 07 01:06:36 PM PDT 24
Peak memory 205704 kb
Host smart-da0dae7b-ce64-4b76-a72f-3464870e39e2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099783088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.1
099783088
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.366953602
Short name T994
Test name
Test status
Simulation time 63132954 ps
CPU time 1.05 seconds
Started May 07 01:06:26 PM PDT 24
Finished May 07 01:06:28 PM PDT 24
Peak memory 205732 kb
Host smart-8878d6cd-5ea0-4095-857c-939faefb9191
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366953602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.366953602
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.3193790179
Short name T997
Test name
Test status
Simulation time 61136093 ps
CPU time 1.62 seconds
Started May 07 01:06:28 PM PDT 24
Finished May 07 01:06:31 PM PDT 24
Peak memory 214008 kb
Host smart-b363bc4d-b096-4574-a1b1-95091f915bae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193790179 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.3193790179
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.1915273074
Short name T128
Test name
Test status
Simulation time 16825323 ps
CPU time 0.9 seconds
Started May 07 01:06:26 PM PDT 24
Finished May 07 01:06:29 PM PDT 24
Peak memory 205528 kb
Host smart-6ffd0b51-db63-4f4f-9676-d82b4985934d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915273074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.1915273074
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.3001340214
Short name T979
Test name
Test status
Simulation time 12390738 ps
CPU time 0.85 seconds
Started May 07 01:06:28 PM PDT 24
Finished May 07 01:06:30 PM PDT 24
Peak memory 205448 kb
Host smart-aebfb90c-2116-4c47-bdc4-e4abc9ec5dc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001340214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.3001340214
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2601236277
Short name T1063
Test name
Test status
Simulation time 126037994 ps
CPU time 1.47 seconds
Started May 07 01:06:27 PM PDT 24
Finished May 07 01:06:30 PM PDT 24
Peak memory 205636 kb
Host smart-b8528a1d-d7f7-41cf-8f08-37286c67f265
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601236277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.2601236277
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.4026601529
Short name T103
Test name
Test status
Simulation time 726798773 ps
CPU time 5.32 seconds
Started May 07 01:06:27 PM PDT 24
Finished May 07 01:06:34 PM PDT 24
Peak memory 218556 kb
Host smart-038dda58-04e7-49a4-b450-7ea00eef7434
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026601529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.4026601529
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.4162835562
Short name T1069
Test name
Test status
Simulation time 833583672 ps
CPU time 4.78 seconds
Started May 07 01:06:28 PM PDT 24
Finished May 07 01:06:34 PM PDT 24
Peak memory 214272 kb
Host smart-d1886f03-e545-4a7a-b162-1b2c404a3c06
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162835562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.4162835562
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.2049773705
Short name T916
Test name
Test status
Simulation time 61026113 ps
CPU time 1.89 seconds
Started May 07 01:06:29 PM PDT 24
Finished May 07 01:06:31 PM PDT 24
Peak memory 214032 kb
Host smart-e3982533-e6fc-4252-a36c-2e71b2cf3cdb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049773705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.2049773705
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.2597957297
Short name T924
Test name
Test status
Simulation time 14524672 ps
CPU time 0.72 seconds
Started May 07 01:07:13 PM PDT 24
Finished May 07 01:07:15 PM PDT 24
Peak memory 205428 kb
Host smart-2c8a2818-1ccf-4163-ba38-8c96eed03786
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597957297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.2597957297
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.2388288659
Short name T938
Test name
Test status
Simulation time 35479850 ps
CPU time 0.81 seconds
Started May 07 01:07:14 PM PDT 24
Finished May 07 01:07:16 PM PDT 24
Peak memory 205448 kb
Host smart-d86053fc-6260-4d10-b4ad-e5cf7094a904
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388288659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.2388288659
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.3455890782
Short name T974
Test name
Test status
Simulation time 13547823 ps
CPU time 0.76 seconds
Started May 07 01:07:18 PM PDT 24
Finished May 07 01:07:20 PM PDT 24
Peak memory 205308 kb
Host smart-572341a5-4efc-4d5e-a8f4-26eb2f4a767b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455890782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.3455890782
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.1244103315
Short name T952
Test name
Test status
Simulation time 9982338 ps
CPU time 0.71 seconds
Started May 07 01:07:15 PM PDT 24
Finished May 07 01:07:17 PM PDT 24
Peak memory 205452 kb
Host smart-daa7f45f-9b07-4150-9e7a-79fe993aec27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244103315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.1244103315
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.1642506715
Short name T922
Test name
Test status
Simulation time 16730746 ps
CPU time 0.7 seconds
Started May 07 01:07:17 PM PDT 24
Finished May 07 01:07:18 PM PDT 24
Peak memory 205276 kb
Host smart-1ced5974-92a3-41d1-ba34-6b36565f0261
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642506715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.1642506715
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.798659591
Short name T1029
Test name
Test status
Simulation time 15612323 ps
CPU time 0.72 seconds
Started May 07 01:07:16 PM PDT 24
Finished May 07 01:07:18 PM PDT 24
Peak memory 205432 kb
Host smart-bce257cd-1b51-4b74-bada-096f6fb9fecd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798659591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.798659591
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.761576740
Short name T1043
Test name
Test status
Simulation time 14157169 ps
CPU time 0.89 seconds
Started May 07 01:07:17 PM PDT 24
Finished May 07 01:07:19 PM PDT 24
Peak memory 205724 kb
Host smart-6137ec3f-d916-4bd6-a5b1-1cecc802d029
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761576740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.761576740
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.4248998808
Short name T915
Test name
Test status
Simulation time 15516419 ps
CPU time 0.71 seconds
Started May 07 01:07:13 PM PDT 24
Finished May 07 01:07:15 PM PDT 24
Peak memory 205428 kb
Host smart-d1070714-d55a-40c1-803a-7597edd966e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248998808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.4248998808
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.492064272
Short name T1060
Test name
Test status
Simulation time 15708246 ps
CPU time 0.77 seconds
Started May 07 01:07:13 PM PDT 24
Finished May 07 01:07:15 PM PDT 24
Peak memory 205220 kb
Host smart-afa1ec0c-2b01-4738-bffe-b26afcf3d011
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492064272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.492064272
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.1998353692
Short name T931
Test name
Test status
Simulation time 242487704 ps
CPU time 0.88 seconds
Started May 07 01:07:15 PM PDT 24
Finished May 07 01:07:17 PM PDT 24
Peak memory 205344 kb
Host smart-4ef4e2a6-920c-4fc9-8c06-462212626df3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998353692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.1998353692
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.4215365247
Short name T964
Test name
Test status
Simulation time 493189660 ps
CPU time 8.77 seconds
Started May 07 01:06:38 PM PDT 24
Finished May 07 01:06:48 PM PDT 24
Peak memory 205728 kb
Host smart-370304ec-e8aa-45c9-bb77-ead6c3048fdb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215365247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.4
215365247
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2292139137
Short name T973
Test name
Test status
Simulation time 898929926 ps
CPU time 15.15 seconds
Started May 07 01:06:34 PM PDT 24
Finished May 07 01:06:50 PM PDT 24
Peak memory 205744 kb
Host smart-a794f8e2-bf1b-4f35-bde8-4ff9cd21b594
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292139137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.2
292139137
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.2138616634
Short name T1081
Test name
Test status
Simulation time 35283210 ps
CPU time 1.16 seconds
Started May 07 01:06:28 PM PDT 24
Finished May 07 01:06:30 PM PDT 24
Peak memory 205760 kb
Host smart-0e4bddb5-a508-4ae2-be92-971945206628
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138616634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.2
138616634
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.971358350
Short name T1024
Test name
Test status
Simulation time 100750147 ps
CPU time 1.53 seconds
Started May 07 01:06:33 PM PDT 24
Finished May 07 01:06:36 PM PDT 24
Peak memory 213988 kb
Host smart-03bcf4d2-4629-44c8-b958-ddeb121b58e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971358350 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.971358350
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.3159556777
Short name T967
Test name
Test status
Simulation time 85359823 ps
CPU time 1.16 seconds
Started May 07 01:06:36 PM PDT 24
Finished May 07 01:06:38 PM PDT 24
Peak memory 205812 kb
Host smart-9c50c474-bae0-49ce-bb38-46a6bc434c50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159556777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.3159556777
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.2020842891
Short name T925
Test name
Test status
Simulation time 19362862 ps
CPU time 0.79 seconds
Started May 07 01:06:28 PM PDT 24
Finished May 07 01:06:30 PM PDT 24
Peak memory 205452 kb
Host smart-500b68ae-6aeb-496d-aebb-7e81ceadaa27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020842891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.2020842891
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.284890023
Short name T1053
Test name
Test status
Simulation time 192430235 ps
CPU time 2.15 seconds
Started May 07 01:06:35 PM PDT 24
Finished May 07 01:06:38 PM PDT 24
Peak memory 205760 kb
Host smart-d0ef5cdd-933d-4153-aede-49ad45f2624f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284890023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sam
e_csr_outstanding.284890023
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.2327192467
Short name T959
Test name
Test status
Simulation time 1651186931 ps
CPU time 14.85 seconds
Started May 07 01:06:28 PM PDT 24
Finished May 07 01:06:44 PM PDT 24
Peak memory 214272 kb
Host smart-291e417b-a604-48a9-9c45-501b043d10d0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327192467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.2327192467
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.1401954033
Short name T946
Test name
Test status
Simulation time 154375323 ps
CPU time 3.85 seconds
Started May 07 01:06:26 PM PDT 24
Finished May 07 01:06:31 PM PDT 24
Peak memory 216096 kb
Host smart-581aa363-2661-41ba-b8dc-ea1f3c992bd3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401954033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.1401954033
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.706785668
Short name T1077
Test name
Test status
Simulation time 34552951 ps
CPU time 0.75 seconds
Started May 07 01:07:18 PM PDT 24
Finished May 07 01:07:20 PM PDT 24
Peak memory 205440 kb
Host smart-0a3c953c-517c-4b97-8b73-25bdea3d21d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706785668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.706785668
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.197377918
Short name T920
Test name
Test status
Simulation time 35513828 ps
CPU time 0.81 seconds
Started May 07 01:07:15 PM PDT 24
Finished May 07 01:07:17 PM PDT 24
Peak memory 205444 kb
Host smart-60d3e0bf-4a83-497c-8e4b-b28fb64be3c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197377918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.197377918
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.2741925005
Short name T1066
Test name
Test status
Simulation time 47991656 ps
CPU time 0.73 seconds
Started May 07 01:07:12 PM PDT 24
Finished May 07 01:07:13 PM PDT 24
Peak memory 205452 kb
Host smart-3e5a339e-d548-4c75-936a-12919334f39a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741925005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.2741925005
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3395720586
Short name T919
Test name
Test status
Simulation time 8214885 ps
CPU time 0.71 seconds
Started May 07 01:07:15 PM PDT 24
Finished May 07 01:07:17 PM PDT 24
Peak memory 205440 kb
Host smart-bd44d2e9-c35e-45a6-b55e-bfb1c8dd3915
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395720586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.3395720586
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.3286924919
Short name T1068
Test name
Test status
Simulation time 38539528 ps
CPU time 0.7 seconds
Started May 07 01:07:17 PM PDT 24
Finished May 07 01:07:18 PM PDT 24
Peak memory 205444 kb
Host smart-90f33a90-6550-4e2a-907d-748663da4934
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286924919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.3286924919
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.1383081074
Short name T1045
Test name
Test status
Simulation time 10877723 ps
CPU time 0.83 seconds
Started May 07 01:07:18 PM PDT 24
Finished May 07 01:07:20 PM PDT 24
Peak memory 205316 kb
Host smart-88cea860-0494-422d-b00e-4590dd510a47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383081074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.1383081074
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.2317757772
Short name T1052
Test name
Test status
Simulation time 31618115 ps
CPU time 0.78 seconds
Started May 07 01:07:13 PM PDT 24
Finished May 07 01:07:15 PM PDT 24
Peak memory 205420 kb
Host smart-936f64d3-95ef-4d58-97a5-59bea377ecca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317757772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.2317757772
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.1994513648
Short name T1074
Test name
Test status
Simulation time 9307389 ps
CPU time 0.78 seconds
Started May 07 01:07:15 PM PDT 24
Finished May 07 01:07:17 PM PDT 24
Peak memory 205344 kb
Host smart-ab03510e-5f87-44c8-8473-36b32031a49e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994513648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.1994513648
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.3676163179
Short name T999
Test name
Test status
Simulation time 15498443 ps
CPU time 0.89 seconds
Started May 07 01:07:17 PM PDT 24
Finished May 07 01:07:19 PM PDT 24
Peak memory 205612 kb
Host smart-3112e87e-14c8-49f8-86df-fcb34c5b5a10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676163179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.3676163179
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.3197956198
Short name T965
Test name
Test status
Simulation time 12363360 ps
CPU time 0.73 seconds
Started May 07 01:07:18 PM PDT 24
Finished May 07 01:07:20 PM PDT 24
Peak memory 205436 kb
Host smart-a28e12cd-08f1-4dee-9d26-229fd876c81c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197956198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.3197956198
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.3953460278
Short name T986
Test name
Test status
Simulation time 483516599 ps
CPU time 6.44 seconds
Started May 07 01:06:34 PM PDT 24
Finished May 07 01:06:42 PM PDT 24
Peak memory 205756 kb
Host smart-bc95cb36-a5d0-4bb7-a2ad-9df0cddae77d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953460278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.3
953460278
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2413108034
Short name T1032
Test name
Test status
Simulation time 5337689112 ps
CPU time 18.96 seconds
Started May 07 01:06:35 PM PDT 24
Finished May 07 01:06:55 PM PDT 24
Peak memory 205920 kb
Host smart-285fddd7-754e-4988-a123-140888619f7f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413108034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.2
413108034
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.664297636
Short name T945
Test name
Test status
Simulation time 40060217 ps
CPU time 1.53 seconds
Started May 07 01:06:34 PM PDT 24
Finished May 07 01:06:36 PM PDT 24
Peak memory 205812 kb
Host smart-038104a9-ab22-40a7-98fa-365fbf21ba5b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664297636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.664297636
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.3797007140
Short name T928
Test name
Test status
Simulation time 33266769 ps
CPU time 1.55 seconds
Started May 07 01:06:36 PM PDT 24
Finished May 07 01:06:39 PM PDT 24
Peak memory 213948 kb
Host smart-ceaad6b9-b044-4fa1-b85c-e2159a03a31a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797007140 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.3797007140
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.19096879
Short name T941
Test name
Test status
Simulation time 29992835 ps
CPU time 1.22 seconds
Started May 07 01:06:33 PM PDT 24
Finished May 07 01:06:35 PM PDT 24
Peak memory 205604 kb
Host smart-6a76c956-506c-4957-b626-c5a20ab643b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19096879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.19096879
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.2472365973
Short name T921
Test name
Test status
Simulation time 76311324 ps
CPU time 0.72 seconds
Started May 07 01:06:38 PM PDT 24
Finished May 07 01:06:39 PM PDT 24
Peak memory 205348 kb
Host smart-da46d7eb-ceeb-4f65-9d56-f51f030502ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472365973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.2472365973
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.4220596938
Short name T1014
Test name
Test status
Simulation time 84629853 ps
CPU time 3.54 seconds
Started May 07 01:06:38 PM PDT 24
Finished May 07 01:06:43 PM PDT 24
Peak memory 205760 kb
Host smart-71dd3a01-f7c1-450b-9f9a-129e81098627
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220596938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.4220596938
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.401697277
Short name T1071
Test name
Test status
Simulation time 299295666 ps
CPU time 1.82 seconds
Started May 07 01:06:35 PM PDT 24
Finished May 07 01:06:38 PM PDT 24
Peak memory 214304 kb
Host smart-1600d16d-ef2d-4af0-9e47-9fd5dc7198ed
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401697277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow
_reg_errors.401697277
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.321720696
Short name T958
Test name
Test status
Simulation time 769217443 ps
CPU time 7.01 seconds
Started May 07 01:06:35 PM PDT 24
Finished May 07 01:06:43 PM PDT 24
Peak memory 220180 kb
Host smart-8e3ca7df-2d90-4a55-95d5-560d2408791f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321720696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.k
eymgr_shadow_reg_errors_with_csr_rw.321720696
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.1156064759
Short name T1057
Test name
Test status
Simulation time 515954184 ps
CPU time 3.55 seconds
Started May 07 01:06:36 PM PDT 24
Finished May 07 01:06:41 PM PDT 24
Peak memory 213876 kb
Host smart-7f0f293a-c9ee-443c-b8d1-e403722d66dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156064759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.1156064759
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.2320446062
Short name T998
Test name
Test status
Simulation time 2372688285 ps
CPU time 8.51 seconds
Started May 07 01:06:34 PM PDT 24
Finished May 07 01:06:44 PM PDT 24
Peak memory 214044 kb
Host smart-e0405d1f-b6f8-4729-88f8-08fc516e7a1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320446062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.2320446062
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.1469480338
Short name T988
Test name
Test status
Simulation time 14299296 ps
CPU time 0.75 seconds
Started May 07 01:07:12 PM PDT 24
Finished May 07 01:07:14 PM PDT 24
Peak memory 205348 kb
Host smart-a3bcfd6c-5c27-443b-80ed-34a38961bbb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469480338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.1469480338
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.104199891
Short name T968
Test name
Test status
Simulation time 27043604 ps
CPU time 0.76 seconds
Started May 07 01:07:27 PM PDT 24
Finished May 07 01:07:29 PM PDT 24
Peak memory 205420 kb
Host smart-c5ab0cd5-af91-4b59-84d0-2d1b33233148
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104199891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.104199891
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.2050022944
Short name T969
Test name
Test status
Simulation time 31246725 ps
CPU time 0.76 seconds
Started May 07 01:07:24 PM PDT 24
Finished May 07 01:07:26 PM PDT 24
Peak memory 205532 kb
Host smart-84913ec8-62d3-407b-a444-6868d76da052
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050022944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.2050022944
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.718459476
Short name T918
Test name
Test status
Simulation time 17281235 ps
CPU time 0.8 seconds
Started May 07 01:07:22 PM PDT 24
Finished May 07 01:07:24 PM PDT 24
Peak memory 205444 kb
Host smart-d5001f1e-402b-444d-87e5-919c14fc0c80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718459476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.718459476
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.501188395
Short name T1058
Test name
Test status
Simulation time 16969049 ps
CPU time 0.71 seconds
Started May 07 01:07:26 PM PDT 24
Finished May 07 01:07:27 PM PDT 24
Peak memory 205444 kb
Host smart-f626da2a-2f3e-44d1-854a-40cefd562b30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501188395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.501188395
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.4287809997
Short name T940
Test name
Test status
Simulation time 57605856 ps
CPU time 0.79 seconds
Started May 07 01:07:21 PM PDT 24
Finished May 07 01:07:23 PM PDT 24
Peak memory 205404 kb
Host smart-522f3807-6406-4d8a-a6f8-92e4e6883514
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287809997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.4287809997
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2981313677
Short name T1062
Test name
Test status
Simulation time 30802723 ps
CPU time 0.75 seconds
Started May 07 01:07:21 PM PDT 24
Finished May 07 01:07:23 PM PDT 24
Peak memory 205416 kb
Host smart-b554a58e-3b2e-4bc3-8ee4-4511b54e9bce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981313677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.2981313677
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.3546821492
Short name T961
Test name
Test status
Simulation time 9785576 ps
CPU time 0.71 seconds
Started May 07 01:07:22 PM PDT 24
Finished May 07 01:07:24 PM PDT 24
Peak memory 205436 kb
Host smart-8622cbb7-9917-4379-a504-71b79c8d9b20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546821492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.3546821492
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.3663477198
Short name T1046
Test name
Test status
Simulation time 10434033 ps
CPU time 0.85 seconds
Started May 07 01:07:22 PM PDT 24
Finished May 07 01:07:24 PM PDT 24
Peak memory 205332 kb
Host smart-255b3aa9-b081-4752-9c0e-3b7cfe14a2b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663477198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.3663477198
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.1751071267
Short name T1051
Test name
Test status
Simulation time 31119714 ps
CPU time 0.7 seconds
Started May 07 01:07:21 PM PDT 24
Finished May 07 01:07:22 PM PDT 24
Peak memory 205348 kb
Host smart-268cb82b-2d6e-4ad9-81bf-5cb76eeeb3f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751071267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.1751071267
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.2908998058
Short name T976
Test name
Test status
Simulation time 55486418 ps
CPU time 1.61 seconds
Started May 07 01:06:43 PM PDT 24
Finished May 07 01:06:45 PM PDT 24
Peak memory 213976 kb
Host smart-ffca85af-5812-4e0b-bde4-6dd21a67ff6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908998058 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.2908998058
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.562637979
Short name T962
Test name
Test status
Simulation time 198980331 ps
CPU time 0.89 seconds
Started May 07 01:06:47 PM PDT 24
Finished May 07 01:06:48 PM PDT 24
Peak memory 205488 kb
Host smart-a1d15530-e951-4f75-982c-863a3aac2280
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562637979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.562637979
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.624541198
Short name T927
Test name
Test status
Simulation time 101801878 ps
CPU time 0.75 seconds
Started May 07 01:06:38 PM PDT 24
Finished May 07 01:06:40 PM PDT 24
Peak memory 205356 kb
Host smart-5e3aab2d-69e5-4fb3-b562-33b682e84e7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624541198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.624541198
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.281568500
Short name T1042
Test name
Test status
Simulation time 222289046 ps
CPU time 3.07 seconds
Started May 07 01:06:42 PM PDT 24
Finished May 07 01:06:46 PM PDT 24
Peak memory 205688 kb
Host smart-94dbaf57-2b07-4e04-8b39-d62559288fe2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281568500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sam
e_csr_outstanding.281568500
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1518468443
Short name T1049
Test name
Test status
Simulation time 199934848 ps
CPU time 3 seconds
Started May 07 01:06:37 PM PDT 24
Finished May 07 01:06:42 PM PDT 24
Peak memory 218000 kb
Host smart-141fb47f-5098-4e2d-bb56-93fbe1356029
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518468443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.1518468443
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.861665223
Short name T1084
Test name
Test status
Simulation time 237840916 ps
CPU time 7.53 seconds
Started May 07 01:06:38 PM PDT 24
Finished May 07 01:06:46 PM PDT 24
Peak memory 214376 kb
Host smart-1d72e4b0-1296-4fb0-aa89-d9f0063176d3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861665223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.k
eymgr_shadow_reg_errors_with_csr_rw.861665223
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.3930819258
Short name T1056
Test name
Test status
Simulation time 36713171 ps
CPU time 2.45 seconds
Started May 07 01:06:35 PM PDT 24
Finished May 07 01:06:38 PM PDT 24
Peak memory 213856 kb
Host smart-7bdf31bd-b9fb-4936-a561-8c9f0428ad21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930819258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.3930819258
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.2696956135
Short name T992
Test name
Test status
Simulation time 154008359 ps
CPU time 6.21 seconds
Started May 07 01:06:36 PM PDT 24
Finished May 07 01:06:43 PM PDT 24
Peak memory 215260 kb
Host smart-7ecd2404-1011-4b0f-828f-66bb88442c5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696956135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.2696956135
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.3520896060
Short name T1019
Test name
Test status
Simulation time 85771794 ps
CPU time 2.69 seconds
Started May 07 01:06:41 PM PDT 24
Finished May 07 01:06:45 PM PDT 24
Peak memory 222176 kb
Host smart-83aa9566-e85e-4558-af9c-57bca9b6dcde
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520896060 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.3520896060
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.11777375
Short name T1022
Test name
Test status
Simulation time 26719846 ps
CPU time 1.54 seconds
Started May 07 01:06:40 PM PDT 24
Finished May 07 01:06:42 PM PDT 24
Peak memory 205736 kb
Host smart-f6bd1a14-2a04-4431-a85d-db8586ce46cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11777375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.11777375
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.2672723323
Short name T975
Test name
Test status
Simulation time 15605691 ps
CPU time 0.73 seconds
Started May 07 01:06:40 PM PDT 24
Finished May 07 01:06:42 PM PDT 24
Peak memory 205436 kb
Host smart-f0f8e915-1576-45ff-b3eb-c2301bc4e0ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672723323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.2672723323
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.2048560420
Short name T1059
Test name
Test status
Simulation time 82741135 ps
CPU time 1.38 seconds
Started May 07 01:06:42 PM PDT 24
Finished May 07 01:06:44 PM PDT 24
Peak memory 205640 kb
Host smart-1b7b1900-caa8-4563-ab68-0276ca34064b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048560420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.2048560420
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.2035369842
Short name T1000
Test name
Test status
Simulation time 480060205 ps
CPU time 1.74 seconds
Started May 07 01:06:42 PM PDT 24
Finished May 07 01:06:45 PM PDT 24
Peak memory 214300 kb
Host smart-abe81150-0aee-4bdc-b165-821e5ec81b71
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035369842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.2035369842
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.2798292739
Short name T104
Test name
Test status
Simulation time 580192717 ps
CPU time 6.69 seconds
Started May 07 01:06:43 PM PDT 24
Finished May 07 01:06:51 PM PDT 24
Peak memory 214316 kb
Host smart-de78661f-9ce0-4f89-af12-79da71bee7fd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798292739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.2798292739
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2066361903
Short name T1007
Test name
Test status
Simulation time 195434668 ps
CPU time 4.12 seconds
Started May 07 01:06:40 PM PDT 24
Finished May 07 01:06:45 PM PDT 24
Peak memory 213860 kb
Host smart-6054d559-efe8-44f6-b8a2-9f6a4bac4656
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066361903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.2066361903
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.3991585865
Short name T145
Test name
Test status
Simulation time 51438973 ps
CPU time 2.61 seconds
Started May 07 01:06:40 PM PDT 24
Finished May 07 01:06:43 PM PDT 24
Peak memory 205720 kb
Host smart-6ba97e19-cc6f-4a4d-83d0-453399c4105e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991585865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.3991585865
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3622425287
Short name T951
Test name
Test status
Simulation time 202837189 ps
CPU time 1.65 seconds
Started May 07 01:06:42 PM PDT 24
Finished May 07 01:06:45 PM PDT 24
Peak memory 213916 kb
Host smart-e5688c91-d3e5-4c3c-b98e-82a01ba6e706
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622425287 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.3622425287
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.3299845786
Short name T1078
Test name
Test status
Simulation time 19314536 ps
CPU time 1.22 seconds
Started May 07 01:06:41 PM PDT 24
Finished May 07 01:06:43 PM PDT 24
Peak memory 205720 kb
Host smart-133dccec-ce1b-47ad-ac98-fbfbbaec7957
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299845786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.3299845786
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.177176795
Short name T926
Test name
Test status
Simulation time 42508477 ps
CPU time 0.7 seconds
Started May 07 01:06:41 PM PDT 24
Finished May 07 01:06:43 PM PDT 24
Peak memory 205408 kb
Host smart-8084bc5f-282e-4e4b-babd-ed1d9fdb3018
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177176795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.177176795
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.435488655
Short name T1025
Test name
Test status
Simulation time 115266022 ps
CPU time 2.65 seconds
Started May 07 01:06:43 PM PDT 24
Finished May 07 01:06:47 PM PDT 24
Peak memory 205772 kb
Host smart-f70ae196-c357-465b-adc8-743849fbfa82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435488655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sam
e_csr_outstanding.435488655
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.621098096
Short name T108
Test name
Test status
Simulation time 85923122 ps
CPU time 2.67 seconds
Started May 07 01:06:42 PM PDT 24
Finished May 07 01:06:46 PM PDT 24
Peak memory 218148 kb
Host smart-6f556551-15dd-476a-9f50-173dbe5c3ca4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621098096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow
_reg_errors.621098096
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.2435811958
Short name T993
Test name
Test status
Simulation time 3731401401 ps
CPU time 10.54 seconds
Started May 07 01:06:41 PM PDT 24
Finished May 07 01:06:52 PM PDT 24
Peak memory 214360 kb
Host smart-71065668-0181-41f6-aa56-0c09eb421b1a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435811958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.2435811958
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.3742604892
Short name T1002
Test name
Test status
Simulation time 142668869 ps
CPU time 3.27 seconds
Started May 07 01:06:43 PM PDT 24
Finished May 07 01:06:47 PM PDT 24
Peak memory 213872 kb
Host smart-0f0ec75e-59f7-4fd7-abd4-f240a2c994b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742604892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.3742604892
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.3553140231
Short name T148
Test name
Test status
Simulation time 439152997 ps
CPU time 3.64 seconds
Started May 07 01:06:42 PM PDT 24
Finished May 07 01:06:47 PM PDT 24
Peak memory 213952 kb
Host smart-465b73db-172b-4341-98c8-a98b7c519297
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553140231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.3553140231
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1412982245
Short name T971
Test name
Test status
Simulation time 44128456 ps
CPU time 1.34 seconds
Started May 07 01:06:48 PM PDT 24
Finished May 07 01:06:50 PM PDT 24
Peak memory 205664 kb
Host smart-657afb02-5201-4c29-95f6-54e3f812c66b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412982245 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.1412982245
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.2465215886
Short name T942
Test name
Test status
Simulation time 149853443 ps
CPU time 1.05 seconds
Started May 07 01:06:49 PM PDT 24
Finished May 07 01:06:52 PM PDT 24
Peak memory 205688 kb
Host smart-75eb745f-a12e-402a-9d0e-7d86d7171590
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465215886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.2465215886
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.3099444137
Short name T917
Test name
Test status
Simulation time 14393959 ps
CPU time 0.76 seconds
Started May 07 01:06:49 PM PDT 24
Finished May 07 01:06:51 PM PDT 24
Peak memory 205456 kb
Host smart-ab50a87e-b026-44c1-ac93-4ac24c313dc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099444137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.3099444137
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.2456726355
Short name T125
Test name
Test status
Simulation time 124205174 ps
CPU time 1.61 seconds
Started May 07 01:06:49 PM PDT 24
Finished May 07 01:06:52 PM PDT 24
Peak memory 205572 kb
Host smart-1072a438-b1f1-4a38-976e-9a6aff4a62a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456726355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.2456726355
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2406815555
Short name T963
Test name
Test status
Simulation time 403336260 ps
CPU time 3.72 seconds
Started May 07 01:06:51 PM PDT 24
Finished May 07 01:06:56 PM PDT 24
Peak memory 214304 kb
Host smart-5dac8701-39f4-4f3b-9a02-cacc8cf0268c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406815555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.2406815555
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.3591337057
Short name T977
Test name
Test status
Simulation time 2203979921 ps
CPU time 13.52 seconds
Started May 07 01:06:49 PM PDT 24
Finished May 07 01:07:04 PM PDT 24
Peak memory 214288 kb
Host smart-40a661b6-6ccf-49fc-8b83-9aa0307bdf89
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591337057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.3591337057
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1497906409
Short name T1008
Test name
Test status
Simulation time 87718197 ps
CPU time 2.12 seconds
Started May 07 01:06:49 PM PDT 24
Finished May 07 01:06:53 PM PDT 24
Peak memory 213860 kb
Host smart-f20ac70b-bbb4-4259-8517-96a55fded702
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497906409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.1497906409
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.1281813010
Short name T978
Test name
Test status
Simulation time 223174358 ps
CPU time 6.2 seconds
Started May 07 01:06:49 PM PDT 24
Finished May 07 01:06:57 PM PDT 24
Peak memory 214024 kb
Host smart-b0e6f692-ffca-41a3-bc27-df87f986a89a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281813010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.1281813010
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1147581031
Short name T1067
Test name
Test status
Simulation time 67911910 ps
CPU time 2.58 seconds
Started May 07 01:06:50 PM PDT 24
Finished May 07 01:06:55 PM PDT 24
Peak memory 219732 kb
Host smart-ab5aa2b8-2ab9-4b17-b502-0ca4df8c8392
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147581031 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.1147581031
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.1759777302
Short name T131
Test name
Test status
Simulation time 11517108 ps
CPU time 1.09 seconds
Started May 07 01:06:51 PM PDT 24
Finished May 07 01:06:53 PM PDT 24
Peak memory 205688 kb
Host smart-c439cecb-fb26-4c1d-b61d-c95d5b6d89b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759777302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.1759777302
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.4203224136
Short name T1061
Test name
Test status
Simulation time 10130160 ps
CPU time 0.8 seconds
Started May 07 01:06:49 PM PDT 24
Finished May 07 01:06:51 PM PDT 24
Peak memory 205456 kb
Host smart-57ffde3a-0c0b-438d-9f72-8cd780374659
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203224136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.4203224136
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.573714528
Short name T1004
Test name
Test status
Simulation time 1664154362 ps
CPU time 5.46 seconds
Started May 07 01:06:49 PM PDT 24
Finished May 07 01:06:56 PM PDT 24
Peak memory 205676 kb
Host smart-701b7130-dc2c-45e5-a6c0-4d09d288980c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573714528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sam
e_csr_outstanding.573714528
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.3672823274
Short name T1082
Test name
Test status
Simulation time 63956199 ps
CPU time 2.5 seconds
Started May 07 01:06:49 PM PDT 24
Finished May 07 01:06:53 PM PDT 24
Peak memory 214380 kb
Host smart-7c3d3383-9aed-4add-bf4f-5818437d7308
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672823274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.3672823274
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2015542132
Short name T1038
Test name
Test status
Simulation time 752786620 ps
CPU time 4.86 seconds
Started May 07 01:06:50 PM PDT 24
Finished May 07 01:06:57 PM PDT 24
Peak memory 214344 kb
Host smart-421e1f59-8347-4df5-bb71-af80a18f3931
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015542132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.2015542132
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.2344925761
Short name T953
Test name
Test status
Simulation time 180216188 ps
CPU time 2.58 seconds
Started May 07 01:06:49 PM PDT 24
Finished May 07 01:06:53 PM PDT 24
Peak memory 216024 kb
Host smart-3a522d51-1236-4d60-a44a-dd107e9ef237
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344925761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.2344925761
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.172509907
Short name T832
Test name
Test status
Simulation time 18180283 ps
CPU time 0.76 seconds
Started May 07 12:37:21 PM PDT 24
Finished May 07 12:37:25 PM PDT 24
Peak memory 205640 kb
Host smart-1c8ad457-70ef-4fd1-bc1a-b2616aa47d05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172509907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.172509907
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.2272863975
Short name T349
Test name
Test status
Simulation time 669308426 ps
CPU time 9.6 seconds
Started May 07 12:36:18 PM PDT 24
Finished May 07 12:36:31 PM PDT 24
Peak memory 214768 kb
Host smart-0e21d62a-8148-4292-b8bf-830eacef543a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2272863975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.2272863975
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.1782111123
Short name T211
Test name
Test status
Simulation time 183068325 ps
CPU time 3.15 seconds
Started May 07 12:36:22 PM PDT 24
Finished May 07 12:36:28 PM PDT 24
Peak memory 220336 kb
Host smart-85bfada0-d154-45da-b7a5-1369b8493e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782111123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.1782111123
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.3929769606
Short name T575
Test name
Test status
Simulation time 45419261 ps
CPU time 2.4 seconds
Started May 07 12:36:19 PM PDT 24
Finished May 07 12:36:24 PM PDT 24
Peak memory 214292 kb
Host smart-d8b8c737-4da6-45e9-81e7-5178a22e0065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929769606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.3929769606
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.1009697527
Short name T249
Test name
Test status
Simulation time 388181880 ps
CPU time 3.34 seconds
Started May 07 12:36:19 PM PDT 24
Finished May 07 12:36:25 PM PDT 24
Peak memory 214260 kb
Host smart-992b4e60-2a82-4c31-9e9a-80b31818eb8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009697527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.1009697527
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.958858436
Short name T467
Test name
Test status
Simulation time 113501807 ps
CPU time 2.45 seconds
Started May 07 12:36:19 PM PDT 24
Finished May 07 12:36:24 PM PDT 24
Peak memory 221860 kb
Host smart-3694c803-71e5-46ee-923e-a218db918ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958858436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.958858436
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_random.3237921635
Short name T662
Test name
Test status
Simulation time 766257953 ps
CPU time 3.3 seconds
Started May 07 12:36:17 PM PDT 24
Finished May 07 12:36:22 PM PDT 24
Peak memory 214176 kb
Host smart-3b4168d5-074c-4ef7-adfd-b69043ccbc96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237921635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.3237921635
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload.2712012710
Short name T652
Test name
Test status
Simulation time 3019086395 ps
CPU time 31.34 seconds
Started May 07 12:36:17 PM PDT 24
Finished May 07 12:36:50 PM PDT 24
Peak memory 208780 kb
Host smart-a61cc595-f23b-4bc7-af74-0ebdca59cd23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712012710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.2712012710
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.3359447259
Short name T767
Test name
Test status
Simulation time 154339219 ps
CPU time 3.2 seconds
Started May 07 12:36:21 PM PDT 24
Finished May 07 12:36:27 PM PDT 24
Peak memory 207376 kb
Host smart-a69607a4-c23d-462a-8a7f-0720b8482854
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359447259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.3359447259
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.300174426
Short name T284
Test name
Test status
Simulation time 120385274 ps
CPU time 2.95 seconds
Started May 07 12:37:21 PM PDT 24
Finished May 07 12:37:27 PM PDT 24
Peak memory 208688 kb
Host smart-9f754ce7-2387-4bd5-9749-df45787c933f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300174426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.300174426
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.3565117093
Short name T711
Test name
Test status
Simulation time 54620652 ps
CPU time 2.81 seconds
Started May 07 12:36:20 PM PDT 24
Finished May 07 12:36:26 PM PDT 24
Peak memory 208700 kb
Host smart-256970e3-acbc-4f84-9c96-3aa4a8c7ce69
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565117093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.3565117093
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.243400938
Short name T715
Test name
Test status
Simulation time 260086161 ps
CPU time 4.35 seconds
Started May 07 12:36:19 PM PDT 24
Finished May 07 12:36:26 PM PDT 24
Peak memory 218240 kb
Host smart-71ae2ecc-f223-4048-8ccf-f00364b06600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243400938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.243400938
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.1771960693
Short name T437
Test name
Test status
Simulation time 331033261 ps
CPU time 2.81 seconds
Started May 07 12:36:16 PM PDT 24
Finished May 07 12:36:21 PM PDT 24
Peak memory 206712 kb
Host smart-b6a4340d-0ca2-4a64-8a29-068c5c16334a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771960693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.1771960693
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.3953850737
Short name T239
Test name
Test status
Simulation time 13379670453 ps
CPU time 363.71 seconds
Started May 07 12:37:21 PM PDT 24
Finished May 07 12:43:28 PM PDT 24
Peak memory 219452 kb
Host smart-3c779e79-f9b6-43fc-b48e-638862fd6f08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953850737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.3953850737
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.186294546
Short name T54
Test name
Test status
Simulation time 1254649738 ps
CPU time 13.42 seconds
Started May 07 12:36:18 PM PDT 24
Finished May 07 12:36:33 PM PDT 24
Peak memory 222548 kb
Host smart-2d501f4f-74eb-420c-a885-b0d160a18cf8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186294546 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.186294546
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.3709769347
Short name T222
Test name
Test status
Simulation time 355383418 ps
CPU time 5.38 seconds
Started May 07 12:36:27 PM PDT 24
Finished May 07 12:36:34 PM PDT 24
Peak memory 207292 kb
Host smart-83e4d17b-2b5a-46fb-b962-e33e21edf0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709769347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.3709769347
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.4060584907
Short name T363
Test name
Test status
Simulation time 739089171 ps
CPU time 10.1 seconds
Started May 07 12:36:17 PM PDT 24
Finished May 07 12:36:29 PM PDT 24
Peak memory 210744 kb
Host smart-58d1f277-1a68-4e11-b49c-5157586b36d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060584907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.4060584907
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.2319302371
Short name T821
Test name
Test status
Simulation time 28608132 ps
CPU time 0.86 seconds
Started May 07 12:36:17 PM PDT 24
Finished May 07 12:36:19 PM PDT 24
Peak memory 205884 kb
Host smart-6889ce5d-c231-44e5-abda-54a1d24fcc3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319302371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.2319302371
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.4014474497
Short name T784
Test name
Test status
Simulation time 228415643 ps
CPU time 2.78 seconds
Started May 07 12:36:15 PM PDT 24
Finished May 07 12:36:19 PM PDT 24
Peak memory 210144 kb
Host smart-b43baa3f-ac57-4724-9941-2bb9e43f221c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014474497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.4014474497
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.111208925
Short name T563
Test name
Test status
Simulation time 128798108 ps
CPU time 2.08 seconds
Started May 07 12:36:16 PM PDT 24
Finished May 07 12:36:20 PM PDT 24
Peak memory 208028 kb
Host smart-f436f812-20cf-4b83-8043-a2830d7d7546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111208925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.111208925
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.1447952709
Short name T599
Test name
Test status
Simulation time 199561030 ps
CPU time 4.45 seconds
Started May 07 12:37:21 PM PDT 24
Finished May 07 12:37:29 PM PDT 24
Peak memory 221920 kb
Host smart-1391acb3-f450-4e78-a927-2e1ddd267b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447952709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.1447952709
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.3481656004
Short name T803
Test name
Test status
Simulation time 83701333 ps
CPU time 3.99 seconds
Started May 07 12:36:20 PM PDT 24
Finished May 07 12:36:29 PM PDT 24
Peak memory 209096 kb
Host smart-cf9f5d38-9d1a-4dce-b7fd-7f954ad36242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481656004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.3481656004
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.3635213593
Short name T101
Test name
Test status
Simulation time 794952261 ps
CPU time 6.69 seconds
Started May 07 12:36:22 PM PDT 24
Finished May 07 12:36:31 PM PDT 24
Peak memory 230372 kb
Host smart-0f210607-9343-4091-82d2-16138ec173de
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635213593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.3635213593
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.1061795576
Short name T729
Test name
Test status
Simulation time 985508810 ps
CPU time 6.25 seconds
Started May 07 12:36:17 PM PDT 24
Finished May 07 12:36:26 PM PDT 24
Peak memory 208588 kb
Host smart-30ebbb32-4dc5-4b27-8a3f-fd8819bcb825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061795576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.1061795576
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.3478044939
Short name T866
Test name
Test status
Simulation time 644425620 ps
CPU time 7.01 seconds
Started May 07 12:37:19 PM PDT 24
Finished May 07 12:37:30 PM PDT 24
Peak memory 207732 kb
Host smart-cfe8e6be-c000-4cbe-aa20-b7620b5d9ca2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478044939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.3478044939
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.2066533633
Short name T842
Test name
Test status
Simulation time 1448275617 ps
CPU time 7.26 seconds
Started May 07 12:36:22 PM PDT 24
Finished May 07 12:36:33 PM PDT 24
Peak memory 208468 kb
Host smart-23e8eca3-c076-40a9-8483-5cb90fff97ca
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066533633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.2066533633
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.2641170259
Short name T756
Test name
Test status
Simulation time 411615200 ps
CPU time 13.06 seconds
Started May 07 12:36:24 PM PDT 24
Finished May 07 12:36:40 PM PDT 24
Peak memory 209604 kb
Host smart-5ccaf267-db61-4df0-bad1-f5029463aacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641170259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.2641170259
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.3622244640
Short name T551
Test name
Test status
Simulation time 743546524 ps
CPU time 3.6 seconds
Started May 07 12:36:19 PM PDT 24
Finished May 07 12:36:26 PM PDT 24
Peak memory 206756 kb
Host smart-2a2cef78-eb2a-47a5-ba8b-bd841c9b5a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622244640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.3622244640
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.3174820315
Short name T883
Test name
Test status
Simulation time 838625571 ps
CPU time 34.27 seconds
Started May 07 12:36:27 PM PDT 24
Finished May 07 12:37:04 PM PDT 24
Peak memory 222416 kb
Host smart-7aa689ef-478d-45c6-8e16-2ba840563d36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174820315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.3174820315
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.854098751
Short name T277
Test name
Test status
Simulation time 669178236 ps
CPU time 7.66 seconds
Started May 07 12:36:30 PM PDT 24
Finished May 07 12:36:40 PM PDT 24
Peak memory 214356 kb
Host smart-b7bf081d-c76b-4dfb-9900-7005104fd495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854098751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.854098751
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.449204979
Short name T888
Test name
Test status
Simulation time 14708019 ps
CPU time 0.85 seconds
Started May 07 12:36:29 PM PDT 24
Finished May 07 12:36:37 PM PDT 24
Peak memory 205964 kb
Host smart-5be8f1eb-53f7-49a7-847a-fbe64814f30b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449204979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.449204979
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.273067840
Short name T401
Test name
Test status
Simulation time 239477918 ps
CPU time 13.18 seconds
Started May 07 12:36:46 PM PDT 24
Finished May 07 12:37:02 PM PDT 24
Peak memory 215600 kb
Host smart-fd94d097-4e25-44af-b128-f8205c23325b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=273067840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.273067840
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.3545731198
Short name T255
Test name
Test status
Simulation time 116284477 ps
CPU time 4.12 seconds
Started May 07 12:36:57 PM PDT 24
Finished May 07 12:37:03 PM PDT 24
Peak memory 221708 kb
Host smart-e7dd02d5-9f2c-4d91-9969-f93714e39e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545731198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.3545731198
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.1463275926
Short name T511
Test name
Test status
Simulation time 31833814 ps
CPU time 1.73 seconds
Started May 07 12:36:34 PM PDT 24
Finished May 07 12:36:37 PM PDT 24
Peak memory 207564 kb
Host smart-317ab450-0512-4e4f-83b7-d88d6d132a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463275926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.1463275926
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.1285238188
Short name T536
Test name
Test status
Simulation time 45981176 ps
CPU time 1.73 seconds
Started May 07 12:36:28 PM PDT 24
Finished May 07 12:36:32 PM PDT 24
Peak memory 214344 kb
Host smart-4114b7b0-ff11-4d0a-89d1-41b8fe1f1fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285238188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.1285238188
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.4039139304
Short name T325
Test name
Test status
Simulation time 204146787 ps
CPU time 2.44 seconds
Started May 07 12:36:40 PM PDT 24
Finished May 07 12:36:43 PM PDT 24
Peak memory 214180 kb
Host smart-45930c90-9894-4dac-ab4f-15767c236a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039139304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.4039139304
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.2478528983
Short name T719
Test name
Test status
Simulation time 114432981 ps
CPU time 3.48 seconds
Started May 07 12:36:43 PM PDT 24
Finished May 07 12:36:49 PM PDT 24
Peak memory 208864 kb
Host smart-349cd65a-5e56-472a-b782-2a3af6ede37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478528983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.2478528983
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_sideload.2569710137
Short name T333
Test name
Test status
Simulation time 1418740524 ps
CPU time 33.6 seconds
Started May 07 12:36:34 PM PDT 24
Finished May 07 12:37:10 PM PDT 24
Peak memory 208784 kb
Host smart-a581bc62-e6c7-4f1c-a175-ce49216caebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569710137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.2569710137
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.4095189761
Short name T390
Test name
Test status
Simulation time 133881070 ps
CPU time 2.17 seconds
Started May 07 12:36:34 PM PDT 24
Finished May 07 12:36:43 PM PDT 24
Peak memory 206912 kb
Host smart-8d0c3bf6-0f14-4257-85e6-261dd5da64e8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095189761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.4095189761
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.1401570632
Short name T676
Test name
Test status
Simulation time 581134516 ps
CPU time 6.75 seconds
Started May 07 12:36:42 PM PDT 24
Finished May 07 12:36:51 PM PDT 24
Peak memory 207700 kb
Host smart-8be5e407-7a63-4455-8641-43bd3d7208a0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401570632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.1401570632
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.245677271
Short name T481
Test name
Test status
Simulation time 1684963100 ps
CPU time 16.94 seconds
Started May 07 12:36:51 PM PDT 24
Finished May 07 12:37:11 PM PDT 24
Peak memory 206996 kb
Host smart-02ae9546-cacb-496b-8504-ef17e5570376
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245677271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.245677271
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.1978545869
Short name T644
Test name
Test status
Simulation time 83659761 ps
CPU time 2.84 seconds
Started May 07 12:36:56 PM PDT 24
Finished May 07 12:37:01 PM PDT 24
Peak memory 218128 kb
Host smart-68bc0885-2b9c-4dc9-86ef-e5c61a0c5819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978545869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.1978545869
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.1707337019
Short name T642
Test name
Test status
Simulation time 36242572 ps
CPU time 1.65 seconds
Started May 07 12:36:56 PM PDT 24
Finished May 07 12:36:59 PM PDT 24
Peak memory 206728 kb
Host smart-05b22cc3-6f70-43b4-b94c-d52d6f315728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707337019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.1707337019
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.1055716776
Short name T326
Test name
Test status
Simulation time 372315052 ps
CPU time 14.41 seconds
Started May 07 12:36:49 PM PDT 24
Finished May 07 12:37:06 PM PDT 24
Peak memory 222040 kb
Host smart-44193f64-8b8e-4aa3-aa83-ebfdd7be7998
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055716776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.1055716776
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.3391984062
Short name T490
Test name
Test status
Simulation time 244577770 ps
CPU time 4.37 seconds
Started May 07 12:36:27 PM PDT 24
Finished May 07 12:36:34 PM PDT 24
Peak memory 208044 kb
Host smart-c0f7e913-f774-427e-9db9-bf5a14e23857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391984062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.3391984062
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.2522507579
Short name T372
Test name
Test status
Simulation time 159503202 ps
CPU time 2.61 seconds
Started May 07 12:36:30 PM PDT 24
Finished May 07 12:36:35 PM PDT 24
Peak memory 209932 kb
Host smart-fe5529a2-d0be-4653-af44-8c518f26e3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522507579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.2522507579
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.1363668592
Short name T871
Test name
Test status
Simulation time 32888054 ps
CPU time 0.73 seconds
Started May 07 12:36:45 PM PDT 24
Finished May 07 12:36:49 PM PDT 24
Peak memory 205912 kb
Host smart-a0e6c06b-1a45-47ac-894c-099f7aa57e79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363668592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.1363668592
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.1419814705
Short name T415
Test name
Test status
Simulation time 1235670349 ps
CPU time 59.58 seconds
Started May 07 12:37:06 PM PDT 24
Finished May 07 12:38:08 PM PDT 24
Peak memory 214596 kb
Host smart-c7272916-530e-483f-ab42-4c6741361596
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1419814705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.1419814705
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.2686673377
Short name T354
Test name
Test status
Simulation time 1628517780 ps
CPU time 4.86 seconds
Started May 07 12:36:28 PM PDT 24
Finished May 07 12:36:35 PM PDT 24
Peak memory 214248 kb
Host smart-ea56882c-0b96-4d5c-b70a-56a77954435a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686673377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.2686673377
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.3071161656
Short name T89
Test name
Test status
Simulation time 103977746 ps
CPU time 3.18 seconds
Started May 07 12:36:50 PM PDT 24
Finished May 07 12:36:56 PM PDT 24
Peak memory 222284 kb
Host smart-9eed66f2-9e9f-4e94-a0f4-fcaa343cc7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071161656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.3071161656
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.3710176439
Short name T741
Test name
Test status
Simulation time 119889162 ps
CPU time 3.14 seconds
Started May 07 12:36:45 PM PDT 24
Finished May 07 12:36:50 PM PDT 24
Peak memory 210072 kb
Host smart-612396d5-a974-415c-880c-9171d024b3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710176439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.3710176439
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.943039485
Short name T646
Test name
Test status
Simulation time 1805662274 ps
CPU time 60.6 seconds
Started May 07 12:36:34 PM PDT 24
Finished May 07 12:37:36 PM PDT 24
Peak memory 208208 kb
Host smart-eed6f058-3151-4796-ab9b-6eed93bf7f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943039485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.943039485
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.3813553935
Short name T116
Test name
Test status
Simulation time 80752682 ps
CPU time 2.12 seconds
Started May 07 12:37:06 PM PDT 24
Finished May 07 12:37:10 PM PDT 24
Peak memory 206824 kb
Host smart-b5d6264d-8683-4784-b867-9234f925041e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813553935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.3813553935
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.2358218676
Short name T175
Test name
Test status
Simulation time 60660897 ps
CPU time 2.23 seconds
Started May 07 12:36:38 PM PDT 24
Finished May 07 12:36:42 PM PDT 24
Peak memory 209180 kb
Host smart-3fa90e90-49d7-4d69-9bc7-921ebe76ec82
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358218676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.2358218676
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.4251246371
Short name T434
Test name
Test status
Simulation time 40465892 ps
CPU time 1.85 seconds
Started May 07 12:36:50 PM PDT 24
Finished May 07 12:36:55 PM PDT 24
Peak memory 207368 kb
Host smart-192b661e-36fc-46ee-9d12-e8ba822f1ea8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251246371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.4251246371
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.1511784709
Short name T607
Test name
Test status
Simulation time 10187272330 ps
CPU time 74.64 seconds
Started May 07 12:36:39 PM PDT 24
Finished May 07 12:37:54 PM PDT 24
Peak memory 209020 kb
Host smart-c49e05b3-786f-4273-84e5-2a83fa844268
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511784709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.1511784709
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.2053028745
Short name T853
Test name
Test status
Simulation time 105975776 ps
CPU time 4.22 seconds
Started May 07 12:36:46 PM PDT 24
Finished May 07 12:36:53 PM PDT 24
Peak memory 214184 kb
Host smart-07dc07c7-aeb2-41b1-8d45-ca3782988ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053028745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.2053028745
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.3807314952
Short name T643
Test name
Test status
Simulation time 45274802 ps
CPU time 2.28 seconds
Started May 07 12:36:52 PM PDT 24
Finished May 07 12:36:57 PM PDT 24
Peak memory 208420 kb
Host smart-d618261d-4c10-489c-8b17-8ac19e83a888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807314952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.3807314952
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.2792155559
Short name T328
Test name
Test status
Simulation time 1856263716 ps
CPU time 17.76 seconds
Started May 07 12:36:54 PM PDT 24
Finished May 07 12:37:20 PM PDT 24
Peak memory 220972 kb
Host smart-77a5a4c3-cade-42a7-b761-a9321556d04d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792155559 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.2792155559
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.3647997054
Short name T183
Test name
Test status
Simulation time 488063988 ps
CPU time 7.56 seconds
Started May 07 12:36:52 PM PDT 24
Finished May 07 12:37:03 PM PDT 24
Peak memory 208988 kb
Host smart-965cb558-7da7-48ac-8355-4f193ed2c788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647997054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.3647997054
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.3862032926
Short name T872
Test name
Test status
Simulation time 90836603 ps
CPU time 1.71 seconds
Started May 07 12:36:59 PM PDT 24
Finished May 07 12:37:03 PM PDT 24
Peak memory 210208 kb
Host smart-b3fd4ce2-1f5a-4ae6-a74d-07f5e618d5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862032926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.3862032926
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.3568785092
Short name T660
Test name
Test status
Simulation time 8246781 ps
CPU time 0.81 seconds
Started May 07 12:36:50 PM PDT 24
Finished May 07 12:36:54 PM PDT 24
Peak memory 205876 kb
Host smart-9abdfd7f-3b1d-4750-8e63-d3a51136a6f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568785092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.3568785092
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.1332190224
Short name T74
Test name
Test status
Simulation time 162611270 ps
CPU time 2.3 seconds
Started May 07 12:37:02 PM PDT 24
Finished May 07 12:37:06 PM PDT 24
Peak memory 207076 kb
Host smart-b37b6182-bf88-4947-aed1-67590d74dcd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332190224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.1332190224
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.1021666712
Short name T526
Test name
Test status
Simulation time 84250826 ps
CPU time 3.15 seconds
Started May 07 12:37:04 PM PDT 24
Finished May 07 12:37:09 PM PDT 24
Peak memory 214204 kb
Host smart-b5a1c18f-5777-4b7f-989b-107d818e8fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021666712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.1021666712
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.501230874
Short name T706
Test name
Test status
Simulation time 67198165 ps
CPU time 2.14 seconds
Started May 07 12:36:59 PM PDT 24
Finished May 07 12:37:03 PM PDT 24
Peak memory 207732 kb
Host smart-f41b6977-bf26-4873-9ce2-983da8231af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501230874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.501230874
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.1613011917
Short name T648
Test name
Test status
Simulation time 303589349 ps
CPU time 7.64 seconds
Started May 07 12:36:59 PM PDT 24
Finished May 07 12:37:08 PM PDT 24
Peak memory 214296 kb
Host smart-b6d9af21-5e86-43b9-b783-3a089aeb384e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613011917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.1613011917
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.3458633071
Short name T517
Test name
Test status
Simulation time 412494050 ps
CPU time 5.55 seconds
Started May 07 12:36:43 PM PDT 24
Finished May 07 12:36:51 PM PDT 24
Peak memory 208068 kb
Host smart-25f41b61-bce2-494c-8341-e60ab78d9e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458633071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.3458633071
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.3104076523
Short name T193
Test name
Test status
Simulation time 7759954436 ps
CPU time 55.58 seconds
Started May 07 12:37:03 PM PDT 24
Finished May 07 12:38:00 PM PDT 24
Peak memory 209180 kb
Host smart-bd8ba5db-b7de-423b-b46c-5dd4f894e1e7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104076523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.3104076523
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.274349996
Short name T335
Test name
Test status
Simulation time 240382387 ps
CPU time 7.93 seconds
Started May 07 12:36:48 PM PDT 24
Finished May 07 12:36:59 PM PDT 24
Peak memory 207900 kb
Host smart-11f5ef9a-ce3c-4c89-9316-122e4fed03b2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274349996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.274349996
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.3389556840
Short name T647
Test name
Test status
Simulation time 2165085511 ps
CPU time 44.97 seconds
Started May 07 12:37:01 PM PDT 24
Finished May 07 12:37:48 PM PDT 24
Peak memory 208944 kb
Host smart-54f7a2a7-e11f-4098-97db-2009130be1af
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389556840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.3389556840
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.2181418973
Short name T649
Test name
Test status
Simulation time 112770384 ps
CPU time 2.16 seconds
Started May 07 12:36:52 PM PDT 24
Finished May 07 12:36:57 PM PDT 24
Peak memory 208324 kb
Host smart-fb787bbf-73f3-4d30-88ac-acf1b978be5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181418973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.2181418973
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.3606794009
Short name T512
Test name
Test status
Simulation time 205034757 ps
CPU time 2.42 seconds
Started May 07 12:36:50 PM PDT 24
Finished May 07 12:36:55 PM PDT 24
Peak memory 207020 kb
Host smart-cf98bc9d-db10-47ae-8acc-7f04e5e0563d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606794009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.3606794009
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.1180589442
Short name T276
Test name
Test status
Simulation time 2474422904 ps
CPU time 12.25 seconds
Started May 07 12:36:56 PM PDT 24
Finished May 07 12:37:11 PM PDT 24
Peak memory 222720 kb
Host smart-0c10e84a-ce40-480f-921f-d2b2b242cc9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180589442 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.1180589442
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.3564003184
Short name T488
Test name
Test status
Simulation time 1437275183 ps
CPU time 3.5 seconds
Started May 07 12:36:56 PM PDT 24
Finished May 07 12:37:01 PM PDT 24
Peak memory 209356 kb
Host smart-4be5e19f-3db1-43c4-8268-7054ed2390dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564003184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.3564003184
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.4216744984
Short name T57
Test name
Test status
Simulation time 1285381579 ps
CPU time 19.31 seconds
Started May 07 12:36:59 PM PDT 24
Finished May 07 12:37:20 PM PDT 24
Peak memory 210840 kb
Host smart-5ddf1ded-def0-49be-88b5-eb3165d44c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216744984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.4216744984
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.1761358993
Short name T750
Test name
Test status
Simulation time 134762620 ps
CPU time 1.03 seconds
Started May 07 12:36:54 PM PDT 24
Finished May 07 12:36:57 PM PDT 24
Peak memory 206068 kb
Host smart-e4c9eabb-48de-4aa6-8a63-446dd4f219f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761358993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.1761358993
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.11852011
Short name T903
Test name
Test status
Simulation time 1297624803 ps
CPU time 34.8 seconds
Started May 07 12:36:59 PM PDT 24
Finished May 07 12:37:36 PM PDT 24
Peak memory 215164 kb
Host smart-48f2601f-0da9-47f1-9de8-2209f2102bfe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=11852011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.11852011
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.2061491673
Short name T40
Test name
Test status
Simulation time 6742443378 ps
CPU time 36.52 seconds
Started May 07 12:37:04 PM PDT 24
Finished May 07 12:37:42 PM PDT 24
Peak memory 222460 kb
Host smart-6e170fbb-7126-4114-ad20-2f8e0cfc566c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061491673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.2061491673
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.3519847611
Short name T911
Test name
Test status
Simulation time 31833128 ps
CPU time 1.98 seconds
Started May 07 12:36:45 PM PDT 24
Finished May 07 12:36:50 PM PDT 24
Peak memory 214208 kb
Host smart-3cbcd40d-4f84-4e27-b35f-36860cc4309e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519847611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.3519847611
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.1243826566
Short name T746
Test name
Test status
Simulation time 104780558 ps
CPU time 3.36 seconds
Started May 07 12:36:59 PM PDT 24
Finished May 07 12:37:04 PM PDT 24
Peak memory 214308 kb
Host smart-6a65ea39-9715-4378-8600-1b97e3880b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243826566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.1243826566
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.3272082654
Short name T280
Test name
Test status
Simulation time 99512328 ps
CPU time 3.28 seconds
Started May 07 12:36:44 PM PDT 24
Finished May 07 12:36:50 PM PDT 24
Peak memory 222504 kb
Host smart-63785135-fa3a-4b32-9ee5-f56e75b3a802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272082654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.3272082654
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.1580940967
Short name T815
Test name
Test status
Simulation time 940717347 ps
CPU time 6.16 seconds
Started May 07 12:36:56 PM PDT 24
Finished May 07 12:37:04 PM PDT 24
Peak memory 209332 kb
Host smart-b4716421-6d5e-4f05-9e69-232d330de6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580940967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.1580940967
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.3592467040
Short name T548
Test name
Test status
Simulation time 839125394 ps
CPU time 6.26 seconds
Started May 07 12:36:41 PM PDT 24
Finished May 07 12:36:48 PM PDT 24
Peak memory 218292 kb
Host smart-e3128ffa-aa43-4edc-ad4c-6de4f7e8debc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592467040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.3592467040
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.3184797457
Short name T867
Test name
Test status
Simulation time 69683525 ps
CPU time 2.56 seconds
Started May 07 12:37:00 PM PDT 24
Finished May 07 12:37:05 PM PDT 24
Peak memory 208540 kb
Host smart-42cc91ab-f4d0-492a-9726-41b925a1213f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184797457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.3184797457
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.3990597093
Short name T793
Test name
Test status
Simulation time 142260028 ps
CPU time 2.46 seconds
Started May 07 12:37:01 PM PDT 24
Finished May 07 12:37:06 PM PDT 24
Peak memory 207540 kb
Host smart-c1e70394-1625-4be8-91e5-024951305ddc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990597093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.3990597093
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.1776737352
Short name T591
Test name
Test status
Simulation time 91758279 ps
CPU time 3.16 seconds
Started May 07 12:36:45 PM PDT 24
Finished May 07 12:36:50 PM PDT 24
Peak memory 206820 kb
Host smart-0490cce0-0ce3-4c39-bd5c-d7fa0aded862
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776737352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.1776737352
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.3796989934
Short name T451
Test name
Test status
Simulation time 160172042 ps
CPU time 5 seconds
Started May 07 12:36:56 PM PDT 24
Finished May 07 12:37:03 PM PDT 24
Peak memory 208592 kb
Host smart-c916ca39-853a-4f96-b3ca-86fbdb83cbf7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796989934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.3796989934
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.1606586137
Short name T329
Test name
Test status
Simulation time 690823390 ps
CPU time 5.48 seconds
Started May 07 12:37:03 PM PDT 24
Finished May 07 12:37:10 PM PDT 24
Peak memory 209864 kb
Host smart-a8ba9df8-00cb-4bdf-9064-311466ca7aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606586137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.1606586137
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.795603892
Short name T426
Test name
Test status
Simulation time 234709529 ps
CPU time 2.77 seconds
Started May 07 12:37:04 PM PDT 24
Finished May 07 12:37:08 PM PDT 24
Peak memory 207004 kb
Host smart-cb2705fb-1e43-4abe-b69a-b759e6bd1422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795603892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.795603892
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.2310522937
Short name T540
Test name
Test status
Simulation time 740793630 ps
CPU time 5.98 seconds
Started May 07 12:36:48 PM PDT 24
Finished May 07 12:36:57 PM PDT 24
Peak memory 208404 kb
Host smart-9a5cfc82-31f5-47f4-8fad-edb58c0c48ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310522937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.2310522937
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.3534236396
Short name T468
Test name
Test status
Simulation time 171895114 ps
CPU time 4.81 seconds
Started May 07 12:37:12 PM PDT 24
Finished May 07 12:37:21 PM PDT 24
Peak memory 210568 kb
Host smart-85e2bd7a-033a-447b-abda-60e78f1ba07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534236396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.3534236396
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.1753234340
Short name T521
Test name
Test status
Simulation time 21712535 ps
CPU time 0.76 seconds
Started May 07 12:36:55 PM PDT 24
Finished May 07 12:36:58 PM PDT 24
Peak memory 205928 kb
Host smart-146e4a2a-7269-4a5c-a90d-5b430773f4e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753234340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.1753234340
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.331611563
Short name T312
Test name
Test status
Simulation time 6660407487 ps
CPU time 94.2 seconds
Started May 07 12:36:47 PM PDT 24
Finished May 07 12:38:24 PM PDT 24
Peak memory 215344 kb
Host smart-3e17be5e-57e0-4aed-87cf-b5e0ce5ae509
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=331611563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.331611563
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.3346194993
Short name T831
Test name
Test status
Simulation time 414702619 ps
CPU time 2.92 seconds
Started May 07 12:36:57 PM PDT 24
Finished May 07 12:37:02 PM PDT 24
Peak memory 217868 kb
Host smart-c52a9bfe-bbb5-4fd5-91f4-c0426d42419b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346194993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.3346194993
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.1955534438
Short name T897
Test name
Test status
Simulation time 34358816 ps
CPU time 2.06 seconds
Started May 07 12:37:03 PM PDT 24
Finished May 07 12:37:07 PM PDT 24
Peak memory 218292 kb
Host smart-fd7fc3ee-225b-45a3-b655-f90b561b3e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955534438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.1955534438
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.2438004536
Short name T509
Test name
Test status
Simulation time 754270485 ps
CPU time 10.72 seconds
Started May 07 12:36:54 PM PDT 24
Finished May 07 12:37:06 PM PDT 24
Peak memory 222512 kb
Host smart-5d662aa6-b01d-45da-b311-e05a8591e84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438004536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.2438004536
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.2462916261
Short name T702
Test name
Test status
Simulation time 348692762 ps
CPU time 1.72 seconds
Started May 07 12:36:56 PM PDT 24
Finished May 07 12:37:00 PM PDT 24
Peak memory 206056 kb
Host smart-6de2a299-411a-47c4-8824-2faef6d63b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462916261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.2462916261
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.4065794613
Short name T538
Test name
Test status
Simulation time 120296143 ps
CPU time 2.6 seconds
Started May 07 12:36:51 PM PDT 24
Finished May 07 12:36:56 PM PDT 24
Peak memory 207492 kb
Host smart-c7c1e3f7-724e-43ea-8117-8bec531aac20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065794613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.4065794613
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.1553217565
Short name T351
Test name
Test status
Simulation time 292619306 ps
CPU time 3.33 seconds
Started May 07 12:36:53 PM PDT 24
Finished May 07 12:36:59 PM PDT 24
Peak memory 208416 kb
Host smart-b9050992-87d1-411b-9076-fb5e2fdd56e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553217565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.1553217565
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.1745848023
Short name T604
Test name
Test status
Simulation time 141586353 ps
CPU time 4.42 seconds
Started May 07 12:36:39 PM PDT 24
Finished May 07 12:36:45 PM PDT 24
Peak memory 206868 kb
Host smart-9284025e-d548-4378-95a9-d97533260ab2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745848023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.1745848023
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.4015181349
Short name T672
Test name
Test status
Simulation time 919166475 ps
CPU time 9.85 seconds
Started May 07 12:36:58 PM PDT 24
Finished May 07 12:37:10 PM PDT 24
Peak memory 206884 kb
Host smart-33c6a6fa-2968-437e-adec-bbdd36f858ce
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015181349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.4015181349
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.3918845093
Short name T463
Test name
Test status
Simulation time 183111493 ps
CPU time 1.69 seconds
Started May 07 12:36:56 PM PDT 24
Finished May 07 12:36:59 PM PDT 24
Peak memory 206808 kb
Host smart-048d0501-245e-4c1d-b521-cc51fc582fa7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918845093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.3918845093
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.2271697634
Short name T681
Test name
Test status
Simulation time 157876948 ps
CPU time 3.05 seconds
Started May 07 12:36:53 PM PDT 24
Finished May 07 12:36:58 PM PDT 24
Peak memory 218348 kb
Host smart-45facc34-9b85-42f8-b362-b33351bf240a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271697634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.2271697634
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.3565880085
Short name T393
Test name
Test status
Simulation time 98215234 ps
CPU time 3.16 seconds
Started May 07 12:36:57 PM PDT 24
Finished May 07 12:37:02 PM PDT 24
Peak memory 208208 kb
Host smart-17f1d462-316e-4506-862f-d67c1ea858e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565880085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.3565880085
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.578236850
Short name T597
Test name
Test status
Simulation time 174892683 ps
CPU time 3.43 seconds
Started May 07 12:37:00 PM PDT 24
Finished May 07 12:37:06 PM PDT 24
Peak memory 210464 kb
Host smart-1f560b45-0ccf-4b2d-9860-cc315514df29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578236850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.578236850
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.2543191810
Short name T634
Test name
Test status
Simulation time 45426769 ps
CPU time 2.09 seconds
Started May 07 12:36:56 PM PDT 24
Finished May 07 12:37:01 PM PDT 24
Peak memory 209892 kb
Host smart-88e9b0a9-3c31-4a07-bf97-4542e11aa4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543191810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.2543191810
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.1149104897
Short name T736
Test name
Test status
Simulation time 50891337 ps
CPU time 0.89 seconds
Started May 07 12:37:07 PM PDT 24
Finished May 07 12:37:10 PM PDT 24
Peak memory 205860 kb
Host smart-0d90b521-5442-4712-8509-99ae78087420
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149104897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.1149104897
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.2304852907
Short name T172
Test name
Test status
Simulation time 174202172 ps
CPU time 3.5 seconds
Started May 07 12:37:06 PM PDT 24
Finished May 07 12:37:11 PM PDT 24
Peak memory 214184 kb
Host smart-4ac2b64d-32c3-44f0-a27c-ec12be1acb15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2304852907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.2304852907
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.2913338701
Short name T699
Test name
Test status
Simulation time 204663212 ps
CPU time 4.66 seconds
Started May 07 12:37:13 PM PDT 24
Finished May 07 12:37:21 PM PDT 24
Peak memory 218228 kb
Host smart-3b92acdf-18f7-45d9-bb70-53dc89ffdb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913338701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.2913338701
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.3586247373
Short name T78
Test name
Test status
Simulation time 1262548712 ps
CPU time 18.91 seconds
Started May 07 12:37:07 PM PDT 24
Finished May 07 12:37:28 PM PDT 24
Peak memory 209520 kb
Host smart-e49916e9-b81f-4273-bd8d-77c892042182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586247373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.3586247373
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.84873491
Short name T199
Test name
Test status
Simulation time 127096403 ps
CPU time 2.57 seconds
Started May 07 12:37:03 PM PDT 24
Finished May 07 12:37:07 PM PDT 24
Peak memory 206116 kb
Host smart-9199d3ae-0648-455a-ae1e-c44f9266c8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84873491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.84873491
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.2514502333
Short name T679
Test name
Test status
Simulation time 204940869 ps
CPU time 3.66 seconds
Started May 07 12:37:08 PM PDT 24
Finished May 07 12:37:14 PM PDT 24
Peak memory 214272 kb
Host smart-fb6ccb6c-bef7-4ef3-a71f-40816a236047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514502333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.2514502333
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.1915846087
Short name T682
Test name
Test status
Simulation time 110355257 ps
CPU time 4.65 seconds
Started May 07 12:37:08 PM PDT 24
Finished May 07 12:37:15 PM PDT 24
Peak memory 209356 kb
Host smart-6626155f-33d5-41fd-aefb-5b4dc1ab59cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915846087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.1915846087
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.1974810385
Short name T295
Test name
Test status
Simulation time 96049081 ps
CPU time 3.85 seconds
Started May 07 12:36:54 PM PDT 24
Finished May 07 12:37:00 PM PDT 24
Peak memory 208152 kb
Host smart-c439d3d7-a2a3-4be2-a65a-09ac76a78d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974810385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.1974810385
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.3536964978
Short name T235
Test name
Test status
Simulation time 97149371 ps
CPU time 3.84 seconds
Started May 07 12:37:14 PM PDT 24
Finished May 07 12:37:22 PM PDT 24
Peak memory 208820 kb
Host smart-a58f5a54-6355-4d75-a7ed-0fe245eddb2e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536964978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.3536964978
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.1028299791
Short name T683
Test name
Test status
Simulation time 89575194 ps
CPU time 1.78 seconds
Started May 07 12:37:06 PM PDT 24
Finished May 07 12:37:10 PM PDT 24
Peak memory 206872 kb
Host smart-9f69f994-b97a-4085-83ab-5a52c0423442
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028299791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.1028299791
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.3351761400
Short name T433
Test name
Test status
Simulation time 124556030 ps
CPU time 2.44 seconds
Started May 07 12:37:14 PM PDT 24
Finished May 07 12:37:20 PM PDT 24
Peak memory 207300 kb
Host smart-45321034-64db-4a00-86e8-aa090fd45177
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351761400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.3351761400
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.670458731
Short name T787
Test name
Test status
Simulation time 297824560 ps
CPU time 4.42 seconds
Started May 07 12:37:07 PM PDT 24
Finished May 07 12:37:13 PM PDT 24
Peak memory 208640 kb
Host smart-4c40701d-b935-4999-9b1a-8d6b1e9b76b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670458731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.670458731
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.3433296861
Short name T675
Test name
Test status
Simulation time 49189168 ps
CPU time 2.5 seconds
Started May 07 12:36:51 PM PDT 24
Finished May 07 12:36:56 PM PDT 24
Peak memory 208364 kb
Host smart-197c1f1e-024b-44f8-80d8-b419e823a66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433296861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.3433296861
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.1854086976
Short name T165
Test name
Test status
Simulation time 230382302 ps
CPU time 8.37 seconds
Started May 07 12:37:05 PM PDT 24
Finished May 07 12:37:16 PM PDT 24
Peak memory 219704 kb
Host smart-88dc0719-383b-4e75-b84d-bde99c69a051
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854086976 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.1854086976
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.1015172735
Short name T849
Test name
Test status
Simulation time 733403730 ps
CPU time 7.71 seconds
Started May 07 12:37:05 PM PDT 24
Finished May 07 12:37:15 PM PDT 24
Peak memory 214264 kb
Host smart-93d0005f-f99a-4c6b-82f8-062eec0dc3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015172735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.1015172735
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.4067530951
Short name T373
Test name
Test status
Simulation time 56821813 ps
CPU time 1.74 seconds
Started May 07 12:37:08 PM PDT 24
Finished May 07 12:37:12 PM PDT 24
Peak memory 208632 kb
Host smart-ec3d06f9-7e2a-46f7-948f-7ed073e21025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067530951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.4067530951
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.38362323
Short name T697
Test name
Test status
Simulation time 14354103 ps
CPU time 0.91 seconds
Started May 07 12:37:09 PM PDT 24
Finished May 07 12:37:13 PM PDT 24
Peak memory 205884 kb
Host smart-8cf0099d-86a5-401d-a834-e25c02fb2187
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38362323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.38362323
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.1281091713
Short name T236
Test name
Test status
Simulation time 489644465 ps
CPU time 6.93 seconds
Started May 07 12:37:07 PM PDT 24
Finished May 07 12:37:16 PM PDT 24
Peak memory 215320 kb
Host smart-ea78212a-e706-470d-b420-ab0930512cc2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1281091713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.1281091713
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.3161349767
Short name T69
Test name
Test status
Simulation time 2480779571 ps
CPU time 15.28 seconds
Started May 07 12:37:06 PM PDT 24
Finished May 07 12:37:23 PM PDT 24
Peak memory 214624 kb
Host smart-c76e8e4a-5435-4315-aa62-a91135e3c988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161349767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.3161349767
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.1835823311
Short name T574
Test name
Test status
Simulation time 127542100 ps
CPU time 2.44 seconds
Started May 07 12:37:15 PM PDT 24
Finished May 07 12:37:22 PM PDT 24
Peak memory 207908 kb
Host smart-2c3b8a46-bd80-48f0-b0e2-21ee71e4fc88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835823311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.1835823311
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.2990342456
Short name T498
Test name
Test status
Simulation time 855244281 ps
CPU time 3.07 seconds
Started May 07 12:36:54 PM PDT 24
Finished May 07 12:36:59 PM PDT 24
Peak memory 214280 kb
Host smart-c49d470d-7252-4dee-a865-ebb797d5a82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990342456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.2990342456
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.3406739610
Short name T813
Test name
Test status
Simulation time 350727522 ps
CPU time 3.08 seconds
Started May 07 12:37:03 PM PDT 24
Finished May 07 12:37:08 PM PDT 24
Peak memory 221776 kb
Host smart-4507850c-0d04-442e-8ace-129aa12c057c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406739610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.3406739610
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.4215122016
Short name T818
Test name
Test status
Simulation time 343602123 ps
CPU time 8.69 seconds
Started May 07 12:37:12 PM PDT 24
Finished May 07 12:37:24 PM PDT 24
Peak memory 210280 kb
Host smart-7552bb7a-852b-43a2-81dc-ee04a6437b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215122016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.4215122016
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.443383669
Short name T640
Test name
Test status
Simulation time 434677994 ps
CPU time 5.46 seconds
Started May 07 12:37:08 PM PDT 24
Finished May 07 12:37:16 PM PDT 24
Peak memory 209384 kb
Host smart-e03ebeed-5664-475c-ac2f-4922b1465d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443383669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.443383669
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.3455520682
Short name T896
Test name
Test status
Simulation time 5831036262 ps
CPU time 24.58 seconds
Started May 07 12:37:03 PM PDT 24
Finished May 07 12:37:29 PM PDT 24
Peak memory 208144 kb
Host smart-90ab7a43-c2f3-45f7-9939-afe028f9fc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455520682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.3455520682
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.335395302
Short name T446
Test name
Test status
Simulation time 575303003 ps
CPU time 4.76 seconds
Started May 07 12:36:47 PM PDT 24
Finished May 07 12:36:55 PM PDT 24
Peak memory 206848 kb
Host smart-36749390-058c-41c0-9294-b25f27310ed2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335395302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.335395302
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.1062004671
Short name T524
Test name
Test status
Simulation time 68707061 ps
CPU time 3.2 seconds
Started May 07 12:37:11 PM PDT 24
Finished May 07 12:37:17 PM PDT 24
Peak memory 206928 kb
Host smart-d78d2ba2-22fb-401b-880a-d8aa1327875c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062004671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.1062004671
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.4197389441
Short name T774
Test name
Test status
Simulation time 1200207385 ps
CPU time 3.09 seconds
Started May 07 12:37:12 PM PDT 24
Finished May 07 12:37:18 PM PDT 24
Peak memory 206932 kb
Host smart-5fe35352-3954-487a-a5e1-91295902bb04
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197389441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.4197389441
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.3560871079
Short name T710
Test name
Test status
Simulation time 25771588 ps
CPU time 1.81 seconds
Started May 07 12:37:08 PM PDT 24
Finished May 07 12:37:13 PM PDT 24
Peak memory 209296 kb
Host smart-8d05db66-2965-4694-9c00-08bf434cad8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560871079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.3560871079
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.3489766837
Short name T912
Test name
Test status
Simulation time 23418864 ps
CPU time 1.83 seconds
Started May 07 12:36:59 PM PDT 24
Finished May 07 12:37:02 PM PDT 24
Peak memory 206572 kb
Host smart-dc5958e0-96bd-49c6-8e81-724142c1381c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489766837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.3489766837
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.952233601
Short name T71
Test name
Test status
Simulation time 803250906 ps
CPU time 9.03 seconds
Started May 07 12:36:57 PM PDT 24
Finished May 07 12:37:08 PM PDT 24
Peak memory 215060 kb
Host smart-ff360978-2ca6-47d5-906a-68d25d2e1788
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952233601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.952233601
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.1573889852
Short name T337
Test name
Test status
Simulation time 705298241 ps
CPU time 5.94 seconds
Started May 07 12:36:59 PM PDT 24
Finished May 07 12:37:07 PM PDT 24
Peak memory 207952 kb
Host smart-98591436-61d0-4e4a-a208-782920c58c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573889852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.1573889852
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.1998659001
Short name T874
Test name
Test status
Simulation time 68007978 ps
CPU time 2.31 seconds
Started May 07 12:37:07 PM PDT 24
Finished May 07 12:37:12 PM PDT 24
Peak memory 209888 kb
Host smart-f6d6287f-6eda-4626-b171-556b317f9fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998659001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.1998659001
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.464129484
Short name T493
Test name
Test status
Simulation time 18819483 ps
CPU time 0.71 seconds
Started May 07 12:37:10 PM PDT 24
Finished May 07 12:37:14 PM PDT 24
Peak memory 205916 kb
Host smart-f92688d1-c0be-4f7d-83ec-59c1952bc784
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464129484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.464129484
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.2976192569
Short name T256
Test name
Test status
Simulation time 177155521 ps
CPU time 3.55 seconds
Started May 07 12:36:59 PM PDT 24
Finished May 07 12:37:05 PM PDT 24
Peak memory 215032 kb
Host smart-bc63aa98-34df-4130-823b-f8ed9a41db8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2976192569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.2976192569
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.3154076479
Short name T909
Test name
Test status
Simulation time 161606386 ps
CPU time 2.51 seconds
Started May 07 12:37:09 PM PDT 24
Finished May 07 12:37:15 PM PDT 24
Peak memory 218300 kb
Host smart-1263b9bf-d892-4109-b3e3-20fe422c32e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154076479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.3154076479
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.2454310673
Short name T238
Test name
Test status
Simulation time 82537730 ps
CPU time 3.69 seconds
Started May 07 12:36:55 PM PDT 24
Finished May 07 12:37:00 PM PDT 24
Peak memory 210104 kb
Host smart-dfee454e-8bf2-4f51-8667-9826cb90ff6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454310673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.2454310673
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.2237649367
Short name T590
Test name
Test status
Simulation time 236111992 ps
CPU time 2.96 seconds
Started May 07 12:37:07 PM PDT 24
Finished May 07 12:37:12 PM PDT 24
Peak memory 214300 kb
Host smart-4c0d7d49-260c-4502-ae6a-76dc8f5b0779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237649367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.2237649367
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.104031454
Short name T246
Test name
Test status
Simulation time 55028488 ps
CPU time 1.83 seconds
Started May 07 12:37:02 PM PDT 24
Finished May 07 12:37:05 PM PDT 24
Peak memory 214704 kb
Host smart-8b4aedb5-643d-43de-84c8-16f7cfa249b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104031454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.104031454
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.1400754655
Short name T489
Test name
Test status
Simulation time 367460052 ps
CPU time 2.78 seconds
Started May 07 12:36:50 PM PDT 24
Finished May 07 12:36:56 PM PDT 24
Peak memory 219728 kb
Host smart-645a1320-ad47-46fc-a574-bd73271e0e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400754655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.1400754655
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.1394121391
Short name T452
Test name
Test status
Simulation time 1642291782 ps
CPU time 48.87 seconds
Started May 07 12:36:59 PM PDT 24
Finished May 07 12:37:50 PM PDT 24
Peak memory 208324 kb
Host smart-b3db60ba-b510-41ee-b3c5-60cbbf509414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394121391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.1394121391
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.1958003042
Short name T632
Test name
Test status
Simulation time 1422587999 ps
CPU time 41.23 seconds
Started May 07 12:36:55 PM PDT 24
Finished May 07 12:37:38 PM PDT 24
Peak memory 207776 kb
Host smart-a6ec653e-5cda-45a4-ab60-14b5f5342b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958003042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.1958003042
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.818895580
Short name T666
Test name
Test status
Simulation time 609766292 ps
CPU time 7.26 seconds
Started May 07 12:37:14 PM PDT 24
Finished May 07 12:37:25 PM PDT 24
Peak memory 208596 kb
Host smart-2310a1c8-1f8d-4c0e-ba3d-871110f00e8d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818895580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.818895580
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.1150892221
Short name T718
Test name
Test status
Simulation time 117574960 ps
CPU time 4.35 seconds
Started May 07 12:37:14 PM PDT 24
Finished May 07 12:37:22 PM PDT 24
Peak memory 206744 kb
Host smart-8c4be51a-776f-484b-b349-48a3a8ddea79
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150892221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.1150892221
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.4169051662
Short name T257
Test name
Test status
Simulation time 524746471 ps
CPU time 6.84 seconds
Started May 07 12:37:07 PM PDT 24
Finished May 07 12:37:16 PM PDT 24
Peak memory 208968 kb
Host smart-48fb9bd3-f2b0-4890-95fd-f77f76b06d30
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169051662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.4169051662
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.3346272593
Short name T800
Test name
Test status
Simulation time 33701292 ps
CPU time 2.37 seconds
Started May 07 12:37:05 PM PDT 24
Finished May 07 12:37:09 PM PDT 24
Peak memory 214292 kb
Host smart-5861d21b-337d-42c9-99d7-795e4a59f40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346272593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.3346272593
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.2503599308
Short name T423
Test name
Test status
Simulation time 230750979 ps
CPU time 2.56 seconds
Started May 07 12:37:07 PM PDT 24
Finished May 07 12:37:12 PM PDT 24
Peak memory 206852 kb
Host smart-2726f5a6-515c-40d0-ba64-e8396a55ce8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503599308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.2503599308
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.1042147636
Short name T879
Test name
Test status
Simulation time 362074378 ps
CPU time 12.24 seconds
Started May 07 12:37:11 PM PDT 24
Finished May 07 12:37:26 PM PDT 24
Peak memory 222444 kb
Host smart-236034fb-9efc-4dff-9e18-fdfd2978011d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042147636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.1042147636
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.445029662
Short name T304
Test name
Test status
Simulation time 258921038 ps
CPU time 6.4 seconds
Started May 07 12:37:02 PM PDT 24
Finished May 07 12:37:10 PM PDT 24
Peak memory 218340 kb
Host smart-752361cb-24e4-4ae3-b47a-2a064299c99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445029662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.445029662
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.1801570526
Short name T528
Test name
Test status
Simulation time 99666742 ps
CPU time 2.51 seconds
Started May 07 12:36:56 PM PDT 24
Finished May 07 12:37:00 PM PDT 24
Peak memory 209984 kb
Host smart-70c53370-4947-4466-9e59-2a99be084edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801570526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.1801570526
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.3802187172
Short name T403
Test name
Test status
Simulation time 785906355 ps
CPU time 10.55 seconds
Started May 07 12:36:59 PM PDT 24
Finished May 07 12:37:11 PM PDT 24
Peak memory 214284 kb
Host smart-02ce807a-2d4c-4895-a66d-0b02ec0e83f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3802187172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.3802187172
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.1869784997
Short name T9
Test name
Test status
Simulation time 223957692 ps
CPU time 3.45 seconds
Started May 07 12:37:10 PM PDT 24
Finished May 07 12:37:16 PM PDT 24
Peak memory 209064 kb
Host smart-b0eb0521-4b84-43b0-9023-0937b934922f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869784997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.1869784997
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.1634684850
Short name T519
Test name
Test status
Simulation time 547312433 ps
CPU time 12.01 seconds
Started May 07 12:37:13 PM PDT 24
Finished May 07 12:37:29 PM PDT 24
Peak memory 218448 kb
Host smart-2c3f34cb-ac01-4d35-bfda-879c4ad9eecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634684850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.1634684850
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.4070684157
Short name T785
Test name
Test status
Simulation time 113091034 ps
CPU time 4.02 seconds
Started May 07 12:37:13 PM PDT 24
Finished May 07 12:37:21 PM PDT 24
Peak memory 220620 kb
Host smart-fb91a805-7fb7-4e3a-a993-3c8fe05272e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070684157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.4070684157
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.3620380949
Short name T557
Test name
Test status
Simulation time 778795737 ps
CPU time 3.37 seconds
Started May 07 12:37:13 PM PDT 24
Finished May 07 12:37:20 PM PDT 24
Peak memory 214280 kb
Host smart-12a76337-de74-42bc-a7bd-36a8a02e28ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620380949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.3620380949
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.2328301694
Short name T179
Test name
Test status
Simulation time 221900815 ps
CPU time 3.73 seconds
Started May 07 12:37:00 PM PDT 24
Finished May 07 12:37:06 PM PDT 24
Peak memory 210016 kb
Host smart-1ad4ea8a-73fe-45ae-95cb-4aae9faa024d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328301694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.2328301694
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.866223467
Short name T658
Test name
Test status
Simulation time 36374732 ps
CPU time 2.19 seconds
Started May 07 12:37:12 PM PDT 24
Finished May 07 12:37:17 PM PDT 24
Peak memory 206788 kb
Host smart-3690a7db-4991-478f-9eeb-dfe655eda444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866223467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.866223467
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.795342497
Short name T833
Test name
Test status
Simulation time 160792573 ps
CPU time 3.05 seconds
Started May 07 12:37:06 PM PDT 24
Finished May 07 12:37:11 PM PDT 24
Peak memory 209192 kb
Host smart-79569f4d-5af1-4131-b3ed-00bb3ad37af2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795342497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.795342497
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.1794739367
Short name T635
Test name
Test status
Simulation time 262273064 ps
CPU time 3.19 seconds
Started May 07 12:37:16 PM PDT 24
Finished May 07 12:37:23 PM PDT 24
Peak memory 206948 kb
Host smart-d853fba5-6d31-43ee-98a7-1cc52a28ec29
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794739367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.1794739367
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.131302579
Short name T904
Test name
Test status
Simulation time 107552074 ps
CPU time 3.1 seconds
Started May 07 12:37:11 PM PDT 24
Finished May 07 12:37:17 PM PDT 24
Peak memory 206968 kb
Host smart-664a626f-a5b1-4e00-8bb4-5e824d7de413
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131302579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.131302579
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.1121372768
Short name T484
Test name
Test status
Simulation time 103581812 ps
CPU time 2.85 seconds
Started May 07 12:37:11 PM PDT 24
Finished May 07 12:37:17 PM PDT 24
Peak memory 215864 kb
Host smart-a5c41736-be1c-4c96-a0bd-bfbe7850d3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121372768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.1121372768
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.3037324811
Short name T913
Test name
Test status
Simulation time 218240351 ps
CPU time 2.74 seconds
Started May 07 12:36:59 PM PDT 24
Finished May 07 12:37:04 PM PDT 24
Peak memory 208040 kb
Host smart-c366d5d6-3b3f-44b9-b1c2-57b9db86ed1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037324811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.3037324811
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.1415366317
Short name T6
Test name
Test status
Simulation time 2395223275 ps
CPU time 47.79 seconds
Started May 07 12:36:59 PM PDT 24
Finished May 07 12:37:49 PM PDT 24
Peak memory 222440 kb
Host smart-65c5d493-d6bc-4a72-853a-7640604d0972
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415366317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.1415366317
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.1422482955
Short name T748
Test name
Test status
Simulation time 7598323794 ps
CPU time 14.19 seconds
Started May 07 12:37:08 PM PDT 24
Finished May 07 12:37:25 PM PDT 24
Peak memory 222604 kb
Host smart-58cdfd82-11d8-402a-baa8-66a7159b21c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422482955 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.1422482955
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.305845394
Short name T775
Test name
Test status
Simulation time 80254266 ps
CPU time 4.19 seconds
Started May 07 12:37:05 PM PDT 24
Finished May 07 12:37:11 PM PDT 24
Peak memory 219844 kb
Host smart-35b74930-b6e6-49a0-bdee-e8b0b34d5d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305845394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.305845394
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.3654738248
Short name T105
Test name
Test status
Simulation time 95820595 ps
CPU time 1.69 seconds
Started May 07 12:37:11 PM PDT 24
Finished May 07 12:37:16 PM PDT 24
Peak memory 208480 kb
Host smart-f952ad03-f9c3-407f-b7d8-eba19cc40821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654738248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.3654738248
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.589215162
Short name T97
Test name
Test status
Simulation time 173375445 ps
CPU time 0.77 seconds
Started May 07 12:37:10 PM PDT 24
Finished May 07 12:37:14 PM PDT 24
Peak memory 205900 kb
Host smart-f276d961-1d07-44c7-bd33-b65691cb343c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589215162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.589215162
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.1578259193
Short name T382
Test name
Test status
Simulation time 384213990 ps
CPU time 5.33 seconds
Started May 07 12:37:07 PM PDT 24
Finished May 07 12:37:15 PM PDT 24
Peak memory 215504 kb
Host smart-bb12fe55-7d70-48c3-80d9-5861659772c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1578259193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.1578259193
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.1851167906
Short name T534
Test name
Test status
Simulation time 598454334 ps
CPU time 2.17 seconds
Started May 07 12:37:13 PM PDT 24
Finished May 07 12:37:19 PM PDT 24
Peak memory 208416 kb
Host smart-f3eff376-51f4-4e65-a3db-2a79a8d2018c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851167906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.1851167906
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.2448312487
Short name T584
Test name
Test status
Simulation time 266169080 ps
CPU time 7.41 seconds
Started May 07 12:37:10 PM PDT 24
Finished May 07 12:37:20 PM PDT 24
Peak memory 217664 kb
Host smart-6c209519-5096-458e-b1b6-4c85b3423659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448312487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.2448312487
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.2413674740
Short name T663
Test name
Test status
Simulation time 581003795 ps
CPU time 4.32 seconds
Started May 07 12:37:10 PM PDT 24
Finished May 07 12:37:17 PM PDT 24
Peak memory 206884 kb
Host smart-ce7c70c4-bc28-4a6a-9fd2-02f7863483d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413674740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.2413674740
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.3755958828
Short name T709
Test name
Test status
Simulation time 58245399 ps
CPU time 2.69 seconds
Started May 07 12:37:09 PM PDT 24
Finished May 07 12:37:14 PM PDT 24
Peak memory 209488 kb
Host smart-439d442f-e8b0-480a-b4e6-9dd131b469a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755958828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.3755958828
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.2118517940
Short name T274
Test name
Test status
Simulation time 174117361 ps
CPU time 4.12 seconds
Started May 07 12:37:13 PM PDT 24
Finished May 07 12:37:21 PM PDT 24
Peak memory 209896 kb
Host smart-c3f1d3e7-45fd-49e1-8379-6700829c8864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118517940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.2118517940
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.1509165015
Short name T708
Test name
Test status
Simulation time 187425454 ps
CPU time 3.63 seconds
Started May 07 12:37:07 PM PDT 24
Finished May 07 12:37:13 PM PDT 24
Peak memory 208744 kb
Host smart-88acf901-654a-4405-8b22-f69b20321b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509165015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.1509165015
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.3068464794
Short name T754
Test name
Test status
Simulation time 151645615 ps
CPU time 4.87 seconds
Started May 07 12:37:09 PM PDT 24
Finished May 07 12:37:16 PM PDT 24
Peak memory 208588 kb
Host smart-9b3b2bf5-7838-486d-b125-ad4483553e84
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068464794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.3068464794
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.567296515
Short name T608
Test name
Test status
Simulation time 205019195 ps
CPU time 4.73 seconds
Started May 07 12:37:07 PM PDT 24
Finished May 07 12:37:14 PM PDT 24
Peak memory 206852 kb
Host smart-1c9b5fd2-289f-4dad-9b9d-1adc65474804
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567296515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.567296515
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.3294101804
Short name T698
Test name
Test status
Simulation time 260029806 ps
CPU time 3.22 seconds
Started May 07 12:37:18 PM PDT 24
Finished May 07 12:37:25 PM PDT 24
Peak memory 206724 kb
Host smart-6a59c13a-6f22-49b1-88c6-e6c0cb2c72c0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294101804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.3294101804
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.505850895
Short name T417
Test name
Test status
Simulation time 215094396 ps
CPU time 2.83 seconds
Started May 07 12:37:00 PM PDT 24
Finished May 07 12:37:06 PM PDT 24
Peak memory 208832 kb
Host smart-190cb386-c6ac-461e-8fad-56e7db3f6efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505850895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.505850895
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.1100349114
Short name T418
Test name
Test status
Simulation time 273686244 ps
CPU time 2.19 seconds
Started May 07 12:37:13 PM PDT 24
Finished May 07 12:37:19 PM PDT 24
Peak memory 206372 kb
Host smart-d08decb2-84b6-49f5-9af4-efe03546b997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100349114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.1100349114
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.3234230931
Short name T166
Test name
Test status
Simulation time 1324209308 ps
CPU time 11.87 seconds
Started May 07 12:37:05 PM PDT 24
Finished May 07 12:37:18 PM PDT 24
Peak memory 219856 kb
Host smart-948a7fb4-5e66-46e0-a2e8-83a6d9e507c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234230931 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.3234230931
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.1998582003
Short name T863
Test name
Test status
Simulation time 123897732 ps
CPU time 4.07 seconds
Started May 07 12:37:13 PM PDT 24
Finished May 07 12:37:21 PM PDT 24
Peak memory 209732 kb
Host smart-2dc9e4d3-51f6-418a-bc18-a253b3a66f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998582003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.1998582003
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.3343006501
Short name T144
Test name
Test status
Simulation time 59739427 ps
CPU time 2.99 seconds
Started May 07 12:37:00 PM PDT 24
Finished May 07 12:37:06 PM PDT 24
Peak memory 210252 kb
Host smart-a44bbd55-406d-480f-8958-d968d004c68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343006501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.3343006501
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.1205754840
Short name T456
Test name
Test status
Simulation time 68678279 ps
CPU time 0.88 seconds
Started May 07 12:36:30 PM PDT 24
Finished May 07 12:36:33 PM PDT 24
Peak memory 205980 kb
Host smart-db634ffe-f28f-4bfd-bdc6-e983c8e61e91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205754840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.1205754840
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.1844071344
Short name T380
Test name
Test status
Simulation time 129834294 ps
CPU time 3.1 seconds
Started May 07 12:36:40 PM PDT 24
Finished May 07 12:36:44 PM PDT 24
Peak memory 215456 kb
Host smart-b6485a3b-0aca-48a8-9076-cd17c304cffc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1844071344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.1844071344
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.3865728479
Short name T15
Test name
Test status
Simulation time 147457418 ps
CPU time 2.57 seconds
Started May 07 12:36:17 PM PDT 24
Finished May 07 12:36:21 PM PDT 24
Peak memory 209648 kb
Host smart-b3705459-d43c-4b20-8721-a7378d3bb1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865728479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.3865728479
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.192963779
Short name T61
Test name
Test status
Simulation time 247934873 ps
CPU time 3 seconds
Started May 07 12:36:22 PM PDT 24
Finished May 07 12:36:28 PM PDT 24
Peak memory 207384 kb
Host smart-31477105-a022-43a6-bff2-0ba72048df30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192963779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.192963779
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.1168764596
Short name T850
Test name
Test status
Simulation time 143992273 ps
CPU time 4.23 seconds
Started May 07 12:36:29 PM PDT 24
Finished May 07 12:36:35 PM PDT 24
Peak memory 214192 kb
Host smart-a9e864bd-2ee1-423d-9420-94786cb5b600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168764596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.1168764596
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.2445306175
Short name T133
Test name
Test status
Simulation time 327254876 ps
CPU time 1.83 seconds
Started May 07 12:36:34 PM PDT 24
Finished May 07 12:36:38 PM PDT 24
Peak memory 206080 kb
Host smart-44870d36-304f-407c-85ae-601b38d50507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445306175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.2445306175
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.1016331854
Short name T891
Test name
Test status
Simulation time 1360016265 ps
CPU time 6.51 seconds
Started May 07 12:36:32 PM PDT 24
Finished May 07 12:36:40 PM PDT 24
Peak memory 208820 kb
Host smart-5f583266-60e2-400a-920b-e0d93150e76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016331854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.1016331854
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sideload.2491683190
Short name T553
Test name
Test status
Simulation time 80651629 ps
CPU time 3.42 seconds
Started May 07 12:36:36 PM PDT 24
Finished May 07 12:36:41 PM PDT 24
Peak memory 208656 kb
Host smart-5b33718c-1178-4fd2-b4ea-97c2f6c9b8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491683190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.2491683190
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.1779763626
Short name T168
Test name
Test status
Simulation time 177974053 ps
CPU time 4.57 seconds
Started May 07 12:36:48 PM PDT 24
Finished May 07 12:36:55 PM PDT 24
Peak memory 207920 kb
Host smart-e7fe36cd-f64c-4080-9842-fbcdf98db791
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779763626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.1779763626
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.736734925
Short name T259
Test name
Test status
Simulation time 48204396 ps
CPU time 2.79 seconds
Started May 07 12:36:23 PM PDT 24
Finished May 07 12:36:29 PM PDT 24
Peak memory 206864 kb
Host smart-8e4b82f1-69d0-4aa3-aab3-f8dc7a4edd26
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736734925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.736734925
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.1100175326
Short name T472
Test name
Test status
Simulation time 33204128 ps
CPU time 2.39 seconds
Started May 07 12:36:31 PM PDT 24
Finished May 07 12:36:35 PM PDT 24
Peak memory 206976 kb
Host smart-8873e2a4-42c4-4f54-8f58-685f7337cf6e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100175326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.1100175326
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.2245942442
Short name T621
Test name
Test status
Simulation time 391077063 ps
CPU time 3.73 seconds
Started May 07 12:36:22 PM PDT 24
Finished May 07 12:36:28 PM PDT 24
Peak memory 218352 kb
Host smart-8a57f609-9ee3-40a0-9c22-510f836a22e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245942442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.2245942442
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.3355885282
Short name T546
Test name
Test status
Simulation time 237975069 ps
CPU time 5.18 seconds
Started May 07 12:36:27 PM PDT 24
Finished May 07 12:36:34 PM PDT 24
Peak memory 208412 kb
Host smart-f36a6abe-f188-4fac-9ef0-c9fad606dc20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355885282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.3355885282
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.132591947
Short name T160
Test name
Test status
Simulation time 2373820654 ps
CPU time 23.76 seconds
Started May 07 12:36:28 PM PDT 24
Finished May 07 12:36:55 PM PDT 24
Peak memory 222772 kb
Host smart-8c9de58f-6487-4f68-aaf8-d1d68c1a6064
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132591947 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.132591947
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.2940877320
Short name T319
Test name
Test status
Simulation time 874792508 ps
CPU time 18.62 seconds
Started May 07 12:36:59 PM PDT 24
Finished May 07 12:37:20 PM PDT 24
Peak memory 208372 kb
Host smart-1c8e0e35-2470-49be-ad2e-7fb6b4e31f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940877320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.2940877320
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.3025336086
Short name T596
Test name
Test status
Simulation time 70603647 ps
CPU time 2.35 seconds
Started May 07 12:36:24 PM PDT 24
Finished May 07 12:36:29 PM PDT 24
Peak memory 210080 kb
Host smart-9e219c7c-2576-472e-bb7f-943386ed9b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025336086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.3025336086
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.2364092201
Short name T504
Test name
Test status
Simulation time 11221319 ps
CPU time 0.72 seconds
Started May 07 12:37:14 PM PDT 24
Finished May 07 12:37:18 PM PDT 24
Peak memory 205888 kb
Host smart-38161c64-0ff9-4818-a772-f79a6a7a796d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364092201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.2364092201
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.790740101
Short name T886
Test name
Test status
Simulation time 192652800 ps
CPU time 3.94 seconds
Started May 07 12:37:02 PM PDT 24
Finished May 07 12:37:08 PM PDT 24
Peak memory 214376 kb
Host smart-777e0f1e-37a7-4cb5-b96a-32d358584b2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=790740101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.790740101
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.1716768813
Short name T117
Test name
Test status
Simulation time 60285026 ps
CPU time 2.82 seconds
Started May 07 12:37:01 PM PDT 24
Finished May 07 12:37:06 PM PDT 24
Peak memory 207536 kb
Host smart-a5fbee69-7669-4675-9e31-8398535d275d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716768813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.1716768813
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.2657018866
Short name T327
Test name
Test status
Simulation time 81536303 ps
CPU time 2.95 seconds
Started May 07 12:37:06 PM PDT 24
Finished May 07 12:37:11 PM PDT 24
Peak memory 215148 kb
Host smart-d8b25082-e1e1-4549-b6a6-dd1f9ae13ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657018866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2657018866
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.2130154869
Short name T51
Test name
Test status
Simulation time 141809320 ps
CPU time 3.71 seconds
Started May 07 12:37:13 PM PDT 24
Finished May 07 12:37:20 PM PDT 24
Peak memory 209084 kb
Host smart-476223c1-e603-4af3-a57b-e9e6efa9965d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130154869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.2130154869
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.2500917063
Short name T846
Test name
Test status
Simulation time 443478296 ps
CPU time 4.64 seconds
Started May 07 12:37:13 PM PDT 24
Finished May 07 12:37:21 PM PDT 24
Peak memory 208656 kb
Host smart-e89ffda0-4190-450c-abbe-7bd06b7f4a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500917063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.2500917063
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.349602318
Short name T605
Test name
Test status
Simulation time 3409719930 ps
CPU time 36.82 seconds
Started May 07 12:37:03 PM PDT 24
Finished May 07 12:37:41 PM PDT 24
Peak memory 208056 kb
Host smart-8b93597f-d7fc-4dc2-9f71-39a4f524867b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349602318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.349602318
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.3018151274
Short name T430
Test name
Test status
Simulation time 93408804 ps
CPU time 3.74 seconds
Started May 07 12:37:02 PM PDT 24
Finished May 07 12:37:07 PM PDT 24
Peak memory 208860 kb
Host smart-745516d5-4a9e-4a89-93cf-97d2e6987f84
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018151274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.3018151274
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.834340452
Short name T873
Test name
Test status
Simulation time 663556267 ps
CPU time 5.49 seconds
Started May 07 12:36:58 PM PDT 24
Finished May 07 12:37:06 PM PDT 24
Peak memory 207832 kb
Host smart-4466272a-bc58-4d3f-a4a2-6d3acca45405
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834340452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.834340452
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.1867250086
Short name T516
Test name
Test status
Simulation time 1493233633 ps
CPU time 10.94 seconds
Started May 07 12:37:04 PM PDT 24
Finished May 07 12:37:16 PM PDT 24
Peak memory 208752 kb
Host smart-42457e3f-96c7-43e4-b9e2-b04ce1d3481d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867250086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.1867250086
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.3607031418
Short name T764
Test name
Test status
Simulation time 263621507 ps
CPU time 2.03 seconds
Started May 07 12:37:13 PM PDT 24
Finished May 07 12:37:18 PM PDT 24
Peak memory 209096 kb
Host smart-f203b516-60be-4fe5-98da-0001791c8846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607031418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.3607031418
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.2644287873
Short name T455
Test name
Test status
Simulation time 402787383 ps
CPU time 2.33 seconds
Started May 07 12:37:03 PM PDT 24
Finished May 07 12:37:06 PM PDT 24
Peak memory 206788 kb
Host smart-35a01dc8-793c-4be3-9607-63c549870d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644287873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.2644287873
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.2844881487
Short name T98
Test name
Test status
Simulation time 567097992 ps
CPU time 19.65 seconds
Started May 07 12:37:14 PM PDT 24
Finished May 07 12:37:37 PM PDT 24
Peak memory 222584 kb
Host smart-7772e25f-847e-4291-94f0-f911ef2af61e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844881487 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.2844881487
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.2585851305
Short name T558
Test name
Test status
Simulation time 96507754 ps
CPU time 2.2 seconds
Started May 07 12:37:08 PM PDT 24
Finished May 07 12:37:13 PM PDT 24
Peak memory 208304 kb
Host smart-8e1aa6e2-d749-46ce-a792-b9008a2b6680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585851305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.2585851305
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.2147464284
Short name T639
Test name
Test status
Simulation time 61343718 ps
CPU time 2.7 seconds
Started May 07 12:37:10 PM PDT 24
Finished May 07 12:37:15 PM PDT 24
Peak memory 209336 kb
Host smart-a3f4c720-9d0c-464e-a052-5a4a429a511c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147464284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.2147464284
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.1757502754
Short name T539
Test name
Test status
Simulation time 45407937 ps
CPU time 0.75 seconds
Started May 07 12:37:20 PM PDT 24
Finished May 07 12:37:24 PM PDT 24
Peak memory 205940 kb
Host smart-e1339def-db9f-4c86-87a9-9276b3db3d9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757502754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.1757502754
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.2385747494
Short name T158
Test name
Test status
Simulation time 153389888 ps
CPU time 3.67 seconds
Started May 07 12:37:06 PM PDT 24
Finished May 07 12:37:12 PM PDT 24
Peak memory 217472 kb
Host smart-bbd16c30-703f-43b1-8284-a2fdee437b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385747494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.2385747494
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.2158499146
Short name T740
Test name
Test status
Simulation time 368680108 ps
CPU time 2.37 seconds
Started May 07 12:37:14 PM PDT 24
Finished May 07 12:37:21 PM PDT 24
Peak memory 207520 kb
Host smart-2f7e5a85-b258-4a91-bc2a-895a80187594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158499146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.2158499146
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.3500103280
Short name T848
Test name
Test status
Simulation time 234642984 ps
CPU time 3.93 seconds
Started May 07 12:37:07 PM PDT 24
Finished May 07 12:37:13 PM PDT 24
Peak memory 220404 kb
Host smart-cdb922b9-9d12-4cd3-b82e-026dc65a4241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500103280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.3500103280
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.2736245864
Short name T757
Test name
Test status
Simulation time 2594577724 ps
CPU time 55.31 seconds
Started May 07 12:37:05 PM PDT 24
Finished May 07 12:38:02 PM PDT 24
Peak memory 209948 kb
Host smart-6f3f8bd1-1001-4dab-b6c3-7106c1a57245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736245864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.2736245864
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.1655272201
Short name T191
Test name
Test status
Simulation time 127023601 ps
CPU time 3.65 seconds
Started May 07 12:37:10 PM PDT 24
Finished May 07 12:37:16 PM PDT 24
Peak memory 208444 kb
Host smart-73355ad9-8d42-4b87-8697-47563f53dd4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655272201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.1655272201
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.799479787
Short name T625
Test name
Test status
Simulation time 77067855 ps
CPU time 1.77 seconds
Started May 07 12:37:15 PM PDT 24
Finished May 07 12:37:20 PM PDT 24
Peak memory 206696 kb
Host smart-acb3fa1c-c043-44a2-aa8f-793ddc7df6e6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799479787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.799479787
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.2048546842
Short name T508
Test name
Test status
Simulation time 111137325 ps
CPU time 2.9 seconds
Started May 07 12:37:06 PM PDT 24
Finished May 07 12:37:11 PM PDT 24
Peak memory 207432 kb
Host smart-e4fac669-a2aa-4ba1-997b-9e6bf361d9da
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048546842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.2048546842
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.3175431810
Short name T690
Test name
Test status
Simulation time 64945168 ps
CPU time 2.37 seconds
Started May 07 12:37:28 PM PDT 24
Finished May 07 12:37:32 PM PDT 24
Peak memory 206864 kb
Host smart-1c626067-4f01-4ac1-87a4-cf60f4415b34
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175431810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.3175431810
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.3729179769
Short name T464
Test name
Test status
Simulation time 129579194 ps
CPU time 3.1 seconds
Started May 07 12:37:16 PM PDT 24
Finished May 07 12:37:23 PM PDT 24
Peak memory 214276 kb
Host smart-7e0ece56-a2a2-4036-a401-f4afad4bfffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729179769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.3729179769
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.401901984
Short name T431
Test name
Test status
Simulation time 51397266 ps
CPU time 2.08 seconds
Started May 07 12:37:06 PM PDT 24
Finished May 07 12:37:10 PM PDT 24
Peak memory 208700 kb
Host smart-43e7915b-8a2e-402d-9b27-85f7d5d34381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401901984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.401901984
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.3975432533
Short name T908
Test name
Test status
Simulation time 269190974 ps
CPU time 10.65 seconds
Started May 07 12:37:12 PM PDT 24
Finished May 07 12:37:26 PM PDT 24
Peak memory 222552 kb
Host smart-61a4b333-952c-4c47-b4b4-53b0aed15a21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975432533 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.3975432533
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.1103635507
Short name T243
Test name
Test status
Simulation time 282372567 ps
CPU time 3.19 seconds
Started May 07 12:36:59 PM PDT 24
Finished May 07 12:37:05 PM PDT 24
Peak memory 208168 kb
Host smart-34b6543d-100c-4197-a371-a996838ef706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103635507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.1103635507
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.2311208647
Short name T369
Test name
Test status
Simulation time 985843461 ps
CPU time 7.53 seconds
Started May 07 12:37:15 PM PDT 24
Finished May 07 12:37:26 PM PDT 24
Peak memory 210492 kb
Host smart-e401e985-e757-4a00-9c3d-e4ed5b4a2079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311208647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.2311208647
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.473593414
Short name T527
Test name
Test status
Simulation time 13497918 ps
CPU time 0.84 seconds
Started May 07 12:37:17 PM PDT 24
Finished May 07 12:37:21 PM PDT 24
Peak memory 205832 kb
Host smart-cb93cbea-0814-498d-9f9f-148c53eb2a91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473593414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.473593414
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.935396066
Short name T381
Test name
Test status
Simulation time 80432299 ps
CPU time 3.37 seconds
Started May 07 12:37:04 PM PDT 24
Finished May 07 12:37:10 PM PDT 24
Peak memory 214368 kb
Host smart-c1bc10c5-22f7-4b9a-a8e7-ada530a651d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=935396066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.935396066
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.867822658
Short name T759
Test name
Test status
Simulation time 81219020 ps
CPU time 3.27 seconds
Started May 07 12:37:13 PM PDT 24
Finished May 07 12:37:20 PM PDT 24
Peak memory 209640 kb
Host smart-a5357efd-bf63-4ebf-ac8c-e7b5e7160615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867822658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.867822658
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.3069521283
Short name T530
Test name
Test status
Simulation time 55999770 ps
CPU time 2.93 seconds
Started May 07 12:37:18 PM PDT 24
Finished May 07 12:37:25 PM PDT 24
Peak memory 218488 kb
Host smart-05136f99-8978-4e6e-9417-a9c0754b3b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069521283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.3069521283
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.3505258205
Short name T22
Test name
Test status
Simulation time 463323963 ps
CPU time 7.08 seconds
Started May 07 12:37:16 PM PDT 24
Finished May 07 12:37:27 PM PDT 24
Peak memory 209752 kb
Host smart-423fee9f-294a-4301-b51b-a6d2154e5cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505258205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.3505258205
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.1564630637
Short name T352
Test name
Test status
Simulation time 136978658 ps
CPU time 2.88 seconds
Started May 07 12:37:13 PM PDT 24
Finished May 07 12:37:19 PM PDT 24
Peak memory 207052 kb
Host smart-a872546d-e7cf-4be9-b159-9b25448e6db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564630637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.1564630637
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.2139207186
Short name T45
Test name
Test status
Simulation time 436735591 ps
CPU time 3.61 seconds
Started May 07 12:37:18 PM PDT 24
Finished May 07 12:37:25 PM PDT 24
Peak memory 209472 kb
Host smart-f9b73f04-9665-4f92-a0ae-b744cf01eb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139207186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.2139207186
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.800490016
Short name T695
Test name
Test status
Simulation time 74972035 ps
CPU time 2.1 seconds
Started May 07 12:37:03 PM PDT 24
Finished May 07 12:37:06 PM PDT 24
Peak memory 207308 kb
Host smart-bfd68b2f-a633-4841-8121-a12e878c8aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800490016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.800490016
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.2609656737
Short name T320
Test name
Test status
Simulation time 38981551 ps
CPU time 2.49 seconds
Started May 07 12:37:09 PM PDT 24
Finished May 07 12:37:15 PM PDT 24
Peak memory 206928 kb
Host smart-012c7af5-49b6-408a-8a06-fa8d450378dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609656737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.2609656737
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.1541842120
Short name T778
Test name
Test status
Simulation time 270727244 ps
CPU time 2.63 seconds
Started May 07 12:37:09 PM PDT 24
Finished May 07 12:37:15 PM PDT 24
Peak memory 207344 kb
Host smart-42b5a03e-b1a7-4854-9137-54e502c3141c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541842120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.1541842120
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.967457038
Short name T194
Test name
Test status
Simulation time 811294373 ps
CPU time 22.93 seconds
Started May 07 12:37:12 PM PDT 24
Finished May 07 12:37:38 PM PDT 24
Peak memory 208524 kb
Host smart-7cdcbba8-2dba-45d4-818a-b116d712e3fe
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967457038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.967457038
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.2378594904
Short name T566
Test name
Test status
Simulation time 343638212 ps
CPU time 3.39 seconds
Started May 07 12:37:13 PM PDT 24
Finished May 07 12:37:19 PM PDT 24
Peak memory 208740 kb
Host smart-dfd7f63f-4ffd-4da2-bdcc-5ed23a9016fa
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378594904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.2378594904
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.468051333
Short name T457
Test name
Test status
Simulation time 50804233 ps
CPU time 2.44 seconds
Started May 07 12:37:13 PM PDT 24
Finished May 07 12:37:19 PM PDT 24
Peak memory 215612 kb
Host smart-7ab6253d-ce32-4f5c-a903-d258acb29df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468051333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.468051333
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.3111893244
Short name T670
Test name
Test status
Simulation time 812159466 ps
CPU time 23.3 seconds
Started May 07 12:37:13 PM PDT 24
Finished May 07 12:37:40 PM PDT 24
Peak memory 207744 kb
Host smart-fe6288c9-5e4e-4f8d-b80c-f72e5adf071c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111893244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.3111893244
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.4164182149
Short name T560
Test name
Test status
Simulation time 1683250686 ps
CPU time 19.19 seconds
Started May 07 12:37:09 PM PDT 24
Finished May 07 12:37:31 PM PDT 24
Peak memory 214368 kb
Host smart-a4f84384-c984-43a0-a813-aaa9c24bd878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164182149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.4164182149
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.4102173707
Short name T155
Test name
Test status
Simulation time 89798774 ps
CPU time 3.41 seconds
Started May 07 12:37:12 PM PDT 24
Finished May 07 12:37:19 PM PDT 24
Peak memory 210080 kb
Host smart-c0e9b2ae-0b05-48b0-ab14-a39e81e91d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102173707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.4102173707
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.3992512196
Short name T14
Test name
Test status
Simulation time 103935557 ps
CPU time 0.8 seconds
Started May 07 12:37:20 PM PDT 24
Finished May 07 12:37:28 PM PDT 24
Peak memory 205892 kb
Host smart-fcef99ab-63ad-4f9f-a76b-9f45f22b8a42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992512196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.3992512196
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.1818607773
Short name T224
Test name
Test status
Simulation time 130836419 ps
CPU time 7.17 seconds
Started May 07 12:37:12 PM PDT 24
Finished May 07 12:37:23 PM PDT 24
Peak memory 214924 kb
Host smart-e7f27734-3a5c-4f84-af9c-083967525520
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1818607773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.1818607773
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.2158676763
Short name T28
Test name
Test status
Simulation time 2791236483 ps
CPU time 14.05 seconds
Started May 07 12:37:09 PM PDT 24
Finished May 07 12:37:26 PM PDT 24
Peak memory 214712 kb
Host smart-966b1e7e-6fed-4fb7-9b4e-a7490e9ac1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158676763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.2158676763
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.2261630712
Short name T408
Test name
Test status
Simulation time 61095194 ps
CPU time 1.42 seconds
Started May 07 12:37:18 PM PDT 24
Finished May 07 12:37:24 PM PDT 24
Peak memory 207072 kb
Host smart-57fe1d45-8897-4b93-a122-1ed70d7e29f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261630712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.2261630712
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.5538388
Short name T92
Test name
Test status
Simulation time 400257498 ps
CPU time 4.82 seconds
Started May 07 12:37:11 PM PDT 24
Finished May 07 12:37:18 PM PDT 24
Peak memory 214188 kb
Host smart-54181711-bb42-45f5-823f-3552341c95fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5538388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.5538388
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.3480047049
Short name T636
Test name
Test status
Simulation time 232501246 ps
CPU time 4.9 seconds
Started May 07 12:37:28 PM PDT 24
Finished May 07 12:37:34 PM PDT 24
Peak memory 214172 kb
Host smart-88556827-50cf-49c5-9d55-6f840478a080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480047049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.3480047049
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.2063346655
Short name T638
Test name
Test status
Simulation time 230942861 ps
CPU time 5.09 seconds
Started May 07 12:37:11 PM PDT 24
Finished May 07 12:37:19 PM PDT 24
Peak memory 215032 kb
Host smart-5555ff57-437a-4aaa-9edb-40f9ec2edec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063346655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.2063346655
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.4085213234
Short name T705
Test name
Test status
Simulation time 219937268 ps
CPU time 3.39 seconds
Started May 07 12:37:07 PM PDT 24
Finished May 07 12:37:13 PM PDT 24
Peak memory 208172 kb
Host smart-ea4ef9de-d070-40ea-839b-250219e2ccb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085213234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.4085213234
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.3256807939
Short name T809
Test name
Test status
Simulation time 286929692 ps
CPU time 4 seconds
Started May 07 12:37:16 PM PDT 24
Finished May 07 12:37:24 PM PDT 24
Peak memory 208412 kb
Host smart-942e9c8b-5533-4008-9c6e-1c12512e91f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256807939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.3256807939
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.3327455315
Short name T884
Test name
Test status
Simulation time 55217947 ps
CPU time 2.07 seconds
Started May 07 12:37:08 PM PDT 24
Finished May 07 12:37:13 PM PDT 24
Peak memory 206832 kb
Host smart-0e264c68-cc0e-481c-b28d-48dc0002df6e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327455315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.3327455315
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.3088526484
Short name T581
Test name
Test status
Simulation time 20462967 ps
CPU time 1.95 seconds
Started May 07 12:37:15 PM PDT 24
Finished May 07 12:37:21 PM PDT 24
Peak memory 206984 kb
Host smart-df8d8779-750e-4de7-b0ea-4075fa97d4e0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088526484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.3088526484
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.1797115385
Short name T483
Test name
Test status
Simulation time 554265808 ps
CPU time 4.64 seconds
Started May 07 12:37:08 PM PDT 24
Finished May 07 12:37:15 PM PDT 24
Peak memory 208864 kb
Host smart-1c9532a8-d7ae-40ec-b335-96aa1d8b5f35
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797115385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.1797115385
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.2088198426
Short name T407
Test name
Test status
Simulation time 128294025 ps
CPU time 3.63 seconds
Started May 07 12:37:12 PM PDT 24
Finished May 07 12:37:18 PM PDT 24
Peak memory 209148 kb
Host smart-7d2d0c96-f8ee-4185-a225-54009e6b5a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088198426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.2088198426
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.2029161204
Short name T761
Test name
Test status
Simulation time 62854270 ps
CPU time 3.04 seconds
Started May 07 12:37:09 PM PDT 24
Finished May 07 12:37:15 PM PDT 24
Peak memory 206492 kb
Host smart-7e11e57d-e4ef-46f7-aed6-3d8578374947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029161204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.2029161204
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.1256842009
Short name T164
Test name
Test status
Simulation time 1541581060 ps
CPU time 12.81 seconds
Started May 07 12:37:10 PM PDT 24
Finished May 07 12:37:25 PM PDT 24
Peak memory 218680 kb
Host smart-04b0bffe-e887-4e4c-9e12-fed1dbb8105f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256842009 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.1256842009
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.46729391
Short name T190
Test name
Test status
Simulation time 265171191 ps
CPU time 3.4 seconds
Started May 07 12:37:19 PM PDT 24
Finished May 07 12:37:26 PM PDT 24
Peak memory 219608 kb
Host smart-8e5b3c12-69af-4d49-ad55-71a7387ca5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46729391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.46729391
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.1464823590
Short name T65
Test name
Test status
Simulation time 137645928 ps
CPU time 4.65 seconds
Started May 07 12:37:13 PM PDT 24
Finished May 07 12:37:26 PM PDT 24
Peak memory 210356 kb
Host smart-c1e50f3b-4c3a-463e-9c59-16b7d6062948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464823590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.1464823590
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.4292861402
Short name T533
Test name
Test status
Simulation time 20705593 ps
CPU time 0.84 seconds
Started May 07 12:37:10 PM PDT 24
Finished May 07 12:37:14 PM PDT 24
Peak memory 205836 kb
Host smart-55568f69-a903-4167-97c8-84c47acc2277
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292861402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.4292861402
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.1819714978
Short name T905
Test name
Test status
Simulation time 251123814 ps
CPU time 2.62 seconds
Started May 07 12:37:09 PM PDT 24
Finished May 07 12:37:14 PM PDT 24
Peak memory 208420 kb
Host smart-e3f8086f-5404-401d-becf-4a4e33de0fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819714978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.1819714978
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.3529617039
Short name T301
Test name
Test status
Simulation time 24382695 ps
CPU time 1.78 seconds
Started May 07 12:37:15 PM PDT 24
Finished May 07 12:37:21 PM PDT 24
Peak memory 214260 kb
Host smart-704bb39e-7048-4610-a77a-f11813d03d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529617039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.3529617039
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.245849217
Short name T270
Test name
Test status
Simulation time 226392782 ps
CPU time 3.29 seconds
Started May 07 12:37:26 PM PDT 24
Finished May 07 12:37:31 PM PDT 24
Peak memory 214220 kb
Host smart-0f2d2063-fd61-4c36-b717-73f5a82a7ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245849217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.245849217
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.4071043945
Short name T200
Test name
Test status
Simulation time 229385008 ps
CPU time 3.1 seconds
Started May 07 12:37:15 PM PDT 24
Finished May 07 12:37:22 PM PDT 24
Peak memory 215040 kb
Host smart-71165d6d-2b94-4541-a98a-49a478e90930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071043945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.4071043945
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_sideload.3934017019
Short name T902
Test name
Test status
Simulation time 271018934 ps
CPU time 2.83 seconds
Started May 07 12:37:17 PM PDT 24
Finished May 07 12:37:23 PM PDT 24
Peak memory 206880 kb
Host smart-b27f704d-7f47-4d6e-aeb0-e98fa4b44d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934017019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.3934017019
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.906171950
Short name T678
Test name
Test status
Simulation time 142491413 ps
CPU time 2.36 seconds
Started May 07 12:37:13 PM PDT 24
Finished May 07 12:37:18 PM PDT 24
Peak memory 207368 kb
Host smart-4e597a9c-f998-4c88-aad5-07b5b494ea09
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906171950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.906171950
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.4107754427
Short name T810
Test name
Test status
Simulation time 169992960 ps
CPU time 3.15 seconds
Started May 07 12:37:15 PM PDT 24
Finished May 07 12:37:22 PM PDT 24
Peak memory 206888 kb
Host smart-2c3c8845-6450-4733-a68d-2c8fe5794621
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107754427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.4107754427
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.1045366105
Short name T178
Test name
Test status
Simulation time 37927708 ps
CPU time 2.74 seconds
Started May 07 12:37:16 PM PDT 24
Finished May 07 12:37:23 PM PDT 24
Peak memory 208544 kb
Host smart-5f6d82e7-9d9d-44cb-965d-f8a71076278a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045366105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.1045366105
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.1241817961
Short name T395
Test name
Test status
Simulation time 54247249 ps
CPU time 2.51 seconds
Started May 07 12:37:14 PM PDT 24
Finished May 07 12:37:21 PM PDT 24
Peak memory 208276 kb
Host smart-8a5ede89-9e90-4c0a-bd40-234caea2794f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241817961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.1241817961
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.1784985695
Short name T680
Test name
Test status
Simulation time 1507139012 ps
CPU time 27.83 seconds
Started May 07 12:37:13 PM PDT 24
Finished May 07 12:37:45 PM PDT 24
Peak memory 207688 kb
Host smart-387b20a0-90c9-4735-9520-4c36b0bb549c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784985695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.1784985695
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.3645641331
Short name T686
Test name
Test status
Simulation time 564059519 ps
CPU time 4.27 seconds
Started May 07 12:37:10 PM PDT 24
Finished May 07 12:37:17 PM PDT 24
Peak memory 207216 kb
Host smart-b3265f68-1a97-4326-b4af-fef172fa2c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645641331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.3645641331
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.2588740548
Short name T362
Test name
Test status
Simulation time 65741147 ps
CPU time 1.65 seconds
Started May 07 12:37:18 PM PDT 24
Finished May 07 12:37:23 PM PDT 24
Peak memory 209692 kb
Host smart-288b81ca-0ce5-439f-9ae1-aaa15b72d9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588740548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.2588740548
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.699076029
Short name T542
Test name
Test status
Simulation time 24047576 ps
CPU time 0.88 seconds
Started May 07 12:37:13 PM PDT 24
Finished May 07 12:37:17 PM PDT 24
Peak memory 205908 kb
Host smart-84c30cf8-bb37-4142-b05f-62ba3659d59a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699076029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.699076029
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.705860104
Short name T291
Test name
Test status
Simulation time 221999432 ps
CPU time 3.86 seconds
Started May 07 12:37:18 PM PDT 24
Finished May 07 12:37:26 PM PDT 24
Peak memory 214252 kb
Host smart-2afb98bb-5af4-4bac-b835-003def14d9a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=705860104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.705860104
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.1486352093
Short name T720
Test name
Test status
Simulation time 137552176 ps
CPU time 5.6 seconds
Started May 07 12:37:17 PM PDT 24
Finished May 07 12:37:27 PM PDT 24
Peak memory 209232 kb
Host smart-896ebb1a-8221-456c-bf9b-feb246f06f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486352093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.1486352093
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.1895659070
Short name T893
Test name
Test status
Simulation time 87198086 ps
CPU time 3.41 seconds
Started May 07 12:37:13 PM PDT 24
Finished May 07 12:37:20 PM PDT 24
Peak memory 214268 kb
Host smart-83fce452-4eaf-4dfd-82d3-ccab897ed735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895659070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.1895659070
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.2823562936
Short name T722
Test name
Test status
Simulation time 83948673 ps
CPU time 4.37 seconds
Started May 07 12:37:15 PM PDT 24
Finished May 07 12:37:23 PM PDT 24
Peak memory 222432 kb
Host smart-2ca65bc5-12e3-49b1-a692-ed79c454194a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823562936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.2823562936
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.2785148158
Short name T343
Test name
Test status
Simulation time 288883826 ps
CPU time 2.79 seconds
Started May 07 12:37:15 PM PDT 24
Finished May 07 12:37:22 PM PDT 24
Peak memory 220252 kb
Host smart-00b2964e-1c85-4070-9d88-7f4b78b89631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785148158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.2785148158
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.373885353
Short name T197
Test name
Test status
Simulation time 358138409 ps
CPU time 4.97 seconds
Started May 07 12:37:10 PM PDT 24
Finished May 07 12:37:18 PM PDT 24
Peak memory 214264 kb
Host smart-6b895f45-fc77-41b7-a3e5-acd4e31e11f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373885353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.373885353
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.3645071697
Short name T865
Test name
Test status
Simulation time 384151211 ps
CPU time 5.26 seconds
Started May 07 12:37:26 PM PDT 24
Finished May 07 12:37:33 PM PDT 24
Peak memory 208912 kb
Host smart-ef993463-2f2d-4391-87af-7dcefccbc371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645071697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.3645071697
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.481025508
Short name T428
Test name
Test status
Simulation time 61074391 ps
CPU time 3.01 seconds
Started May 07 12:37:15 PM PDT 24
Finished May 07 12:37:22 PM PDT 24
Peak memory 207768 kb
Host smart-9a995764-775d-4d6e-8bfb-2936b4b7281c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481025508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.481025508
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.3856669389
Short name T619
Test name
Test status
Simulation time 412847588 ps
CPU time 5.82 seconds
Started May 07 12:37:17 PM PDT 24
Finished May 07 12:37:26 PM PDT 24
Peak memory 208512 kb
Host smart-5dafd13c-0332-428a-8d6a-a79c7fa03f70
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856669389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.3856669389
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.658860103
Short name T555
Test name
Test status
Simulation time 78800660 ps
CPU time 2.43 seconds
Started May 07 12:37:17 PM PDT 24
Finished May 07 12:37:23 PM PDT 24
Peak memory 206780 kb
Host smart-a653d5d7-902d-4cbd-8b37-aa3f8e50efaf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658860103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.658860103
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.2591225611
Short name T592
Test name
Test status
Simulation time 258745634 ps
CPU time 3.44 seconds
Started May 07 12:37:18 PM PDT 24
Finished May 07 12:37:25 PM PDT 24
Peak memory 206968 kb
Host smart-b2f88faf-f66e-4aeb-be46-13ec18c382d9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591225611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.2591225611
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.1478543235
Short name T253
Test name
Test status
Simulation time 356120757 ps
CPU time 2.5 seconds
Started May 07 12:37:12 PM PDT 24
Finished May 07 12:37:18 PM PDT 24
Peak memory 218184 kb
Host smart-fc2a9671-5d9d-4143-98d5-dd40d3646445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478543235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.1478543235
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.582263180
Short name T459
Test name
Test status
Simulation time 305581111 ps
CPU time 2.74 seconds
Started May 07 12:37:25 PM PDT 24
Finished May 07 12:37:29 PM PDT 24
Peak memory 206800 kb
Host smart-24846761-4ff6-43d6-9a3d-9fafdcfda3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582263180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.582263180
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.2401032040
Short name T799
Test name
Test status
Simulation time 172156383 ps
CPU time 4.51 seconds
Started May 07 12:37:18 PM PDT 24
Finished May 07 12:37:26 PM PDT 24
Peak memory 207188 kb
Host smart-339f6e70-db57-4210-9694-99f98786bbba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401032040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.2401032040
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.2985231854
Short name T370
Test name
Test status
Simulation time 59258790 ps
CPU time 2.16 seconds
Started May 07 12:37:14 PM PDT 24
Finished May 07 12:37:20 PM PDT 24
Peak memory 209832 kb
Host smart-fcbbabd6-e638-4f15-a4ba-f2c1217d7e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985231854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.2985231854
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.2772562424
Short name T801
Test name
Test status
Simulation time 22511763 ps
CPU time 0.83 seconds
Started May 07 12:37:16 PM PDT 24
Finished May 07 12:37:21 PM PDT 24
Peak memory 205900 kb
Host smart-e7cc3423-d91d-4974-9f2c-0a0f85dd54ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772562424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.2772562424
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.106902924
Short name T384
Test name
Test status
Simulation time 38878269 ps
CPU time 2.85 seconds
Started May 07 12:37:17 PM PDT 24
Finished May 07 12:37:23 PM PDT 24
Peak memory 214444 kb
Host smart-e1bad807-d873-498c-a0d2-36006f6a8321
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=106902924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.106902924
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.1633440888
Short name T791
Test name
Test status
Simulation time 55236949 ps
CPU time 3 seconds
Started May 07 12:37:17 PM PDT 24
Finished May 07 12:37:23 PM PDT 24
Peak memory 222604 kb
Host smart-ce8b759f-cc61-435b-b36e-cf49d846caa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633440888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.1633440888
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.1529674129
Short name T64
Test name
Test status
Simulation time 419292789 ps
CPU time 4.76 seconds
Started May 07 12:37:29 PM PDT 24
Finished May 07 12:37:35 PM PDT 24
Peak memory 218240 kb
Host smart-5052b785-48d0-45d7-b5d7-14846ae0e957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529674129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.1529674129
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.2215163757
Short name T766
Test name
Test status
Simulation time 89672749 ps
CPU time 3.89 seconds
Started May 07 12:37:12 PM PDT 24
Finished May 07 12:37:19 PM PDT 24
Peak memory 214288 kb
Host smart-921d69e2-9f42-45b4-8b88-63df86c239fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215163757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.2215163757
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.1372759072
Short name T633
Test name
Test status
Simulation time 345201240 ps
CPU time 3.86 seconds
Started May 07 12:37:20 PM PDT 24
Finished May 07 12:37:27 PM PDT 24
Peak memory 218656 kb
Host smart-f9785d4d-dc0a-443e-b7b8-42fbb6838b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372759072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.1372759072
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.2411181571
Short name T289
Test name
Test status
Simulation time 2847764624 ps
CPU time 47.99 seconds
Started May 07 12:37:09 PM PDT 24
Finished May 07 12:38:00 PM PDT 24
Peak memory 209304 kb
Host smart-84e3834b-e371-450b-9440-9f61746b4794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411181571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.2411181571
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.1634460071
Short name T3
Test name
Test status
Simulation time 89413062 ps
CPU time 1.68 seconds
Started May 07 12:37:17 PM PDT 24
Finished May 07 12:37:22 PM PDT 24
Peak memory 206640 kb
Host smart-848c921c-3485-4576-a16f-526c0b10c54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634460071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.1634460071
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.2266798110
Short name T653
Test name
Test status
Simulation time 428652200 ps
CPU time 3.09 seconds
Started May 07 12:37:26 PM PDT 24
Finished May 07 12:37:31 PM PDT 24
Peak memory 206692 kb
Host smart-48670202-bbe7-430e-b5ff-2a71568dc7b6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266798110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.2266798110
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.3684848991
Short name T473
Test name
Test status
Simulation time 33095793 ps
CPU time 2.35 seconds
Started May 07 12:37:10 PM PDT 24
Finished May 07 12:37:16 PM PDT 24
Peak memory 207328 kb
Host smart-a9531ab9-6fe9-4147-bcd9-4c47aa7e33fa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684848991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.3684848991
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.3423636920
Short name T514
Test name
Test status
Simulation time 373184890 ps
CPU time 3.6 seconds
Started May 07 12:37:31 PM PDT 24
Finished May 07 12:37:36 PM PDT 24
Peak memory 208388 kb
Host smart-a9acb78b-6ffb-4f22-8da1-0da7521dc324
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423636920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.3423636920
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.4210983339
Short name T507
Test name
Test status
Simulation time 51722716 ps
CPU time 2.48 seconds
Started May 07 12:37:18 PM PDT 24
Finished May 07 12:37:24 PM PDT 24
Peak memory 209100 kb
Host smart-1af59a8f-c57d-4bf2-af82-bb5587c75ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210983339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.4210983339
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.148229884
Short name T728
Test name
Test status
Simulation time 197449496 ps
CPU time 2.25 seconds
Started May 07 12:37:10 PM PDT 24
Finished May 07 12:37:15 PM PDT 24
Peak memory 206728 kb
Host smart-1935cbba-189a-4e53-a1d6-e4ebd42cad68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148229884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.148229884
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.633657033
Short name T181
Test name
Test status
Simulation time 1951560635 ps
CPU time 40.95 seconds
Started May 07 12:37:20 PM PDT 24
Finished May 07 12:38:05 PM PDT 24
Peak memory 222364 kb
Host smart-4a6ffa37-b094-45ec-ad25-30f7ff48d95a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633657033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.633657033
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.3346820033
Short name T114
Test name
Test status
Simulation time 670715543 ps
CPU time 4.4 seconds
Started May 07 12:37:23 PM PDT 24
Finished May 07 12:37:29 PM PDT 24
Peak memory 219888 kb
Host smart-5c875719-33e6-4754-9d64-6b6e05c524ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346820033 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.3346820033
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.2023467085
Short name T828
Test name
Test status
Simulation time 107011796 ps
CPU time 4.94 seconds
Started May 07 12:37:12 PM PDT 24
Finished May 07 12:37:20 PM PDT 24
Peak memory 208376 kb
Host smart-2878e711-2aca-4ab7-9140-6c10cb4bcd87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023467085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.2023467085
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.896896136
Short name T447
Test name
Test status
Simulation time 13218289 ps
CPU time 0.73 seconds
Started May 07 12:37:22 PM PDT 24
Finished May 07 12:37:25 PM PDT 24
Peak memory 205916 kb
Host smart-b0fcc3b9-faa8-4f98-a2c9-e548b28e87cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896896136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.896896136
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.1770595134
Short name T585
Test name
Test status
Simulation time 716163070 ps
CPU time 5.05 seconds
Started May 07 12:37:40 PM PDT 24
Finished May 07 12:37:46 PM PDT 24
Peak memory 214516 kb
Host smart-8bed7cb4-8291-4bf4-abd8-706c6992cb16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770595134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.1770595134
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.2088704738
Short name T626
Test name
Test status
Simulation time 577775636 ps
CPU time 3.9 seconds
Started May 07 12:37:48 PM PDT 24
Finished May 07 12:37:53 PM PDT 24
Peak memory 214312 kb
Host smart-89080b21-04c6-4f90-8f86-a6e2578c1ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088704738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.2088704738
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.1449942635
Short name T85
Test name
Test status
Simulation time 1320830496 ps
CPU time 3.43 seconds
Started May 07 12:37:32 PM PDT 24
Finished May 07 12:37:37 PM PDT 24
Peak memory 214544 kb
Host smart-d745da98-5073-4e95-a5da-496140d544af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449942635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.1449942635
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.2386309268
Short name T231
Test name
Test status
Simulation time 109121346 ps
CPU time 2.08 seconds
Started May 07 12:37:27 PM PDT 24
Finished May 07 12:37:31 PM PDT 24
Peak memory 206008 kb
Host smart-57a61ecc-c679-450d-9ed9-c465ca18bab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386309268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.2386309268
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.3595271767
Short name T207
Test name
Test status
Simulation time 108142107 ps
CPU time 3.76 seconds
Started May 07 12:37:34 PM PDT 24
Finished May 07 12:37:44 PM PDT 24
Peak memory 220048 kb
Host smart-3c30dd5a-91d6-4cb1-a4b3-87bdf9b5bbb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595271767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.3595271767
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.220267525
Short name T852
Test name
Test status
Simulation time 290385503 ps
CPU time 4 seconds
Started May 07 12:37:28 PM PDT 24
Finished May 07 12:37:34 PM PDT 24
Peak memory 208048 kb
Host smart-0d00e558-c02a-4a17-8916-b6076c7c6b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220267525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.220267525
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.1184330329
Short name T476
Test name
Test status
Simulation time 108623472 ps
CPU time 2.86 seconds
Started May 07 12:37:22 PM PDT 24
Finished May 07 12:37:27 PM PDT 24
Peak memory 206756 kb
Host smart-e2f0fdc0-2c68-45f8-a1f6-5e0e23e0000b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184330329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.1184330329
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.1703218550
Short name T432
Test name
Test status
Simulation time 1735035973 ps
CPU time 41.16 seconds
Started May 07 12:37:32 PM PDT 24
Finished May 07 12:38:15 PM PDT 24
Peak memory 208096 kb
Host smart-3c39e27a-1697-47ca-949c-4d5f0395531e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703218550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.1703218550
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.2632904871
Short name T334
Test name
Test status
Simulation time 237388510 ps
CPU time 4.14 seconds
Started May 07 12:37:20 PM PDT 24
Finished May 07 12:37:27 PM PDT 24
Peak memory 206896 kb
Host smart-3c251b38-0639-4380-908f-de588eb57821
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632904871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.2632904871
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.3228960742
Short name T290
Test name
Test status
Simulation time 582381151 ps
CPU time 5.89 seconds
Started May 07 12:37:35 PM PDT 24
Finished May 07 12:37:41 PM PDT 24
Peak memory 208796 kb
Host smart-8cd529d9-b675-49b6-817d-88fa035158c0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228960742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.3228960742
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.302049715
Short name T823
Test name
Test status
Simulation time 460970213 ps
CPU time 1.96 seconds
Started May 07 12:37:28 PM PDT 24
Finished May 07 12:37:32 PM PDT 24
Peak memory 208124 kb
Host smart-426051a9-38d4-487e-bd89-e930aefd2bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302049715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.302049715
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.3810358117
Short name T385
Test name
Test status
Simulation time 190108369 ps
CPU time 6.61 seconds
Started May 07 12:37:30 PM PDT 24
Finished May 07 12:37:38 PM PDT 24
Peak memory 208676 kb
Host smart-8633d2e9-1b4e-47f5-9234-2fbd9c5dae37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810358117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.3810358117
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.3100983591
Short name T202
Test name
Test status
Simulation time 1126725634 ps
CPU time 40.14 seconds
Started May 07 12:37:33 PM PDT 24
Finished May 07 12:38:14 PM PDT 24
Peak memory 222484 kb
Host smart-b6d81fb5-551f-47be-a752-fcc5617f43f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100983591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.3100983591
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.252578810
Short name T795
Test name
Test status
Simulation time 1144147990 ps
CPU time 8.52 seconds
Started May 07 12:37:21 PM PDT 24
Finished May 07 12:37:32 PM PDT 24
Peak memory 218660 kb
Host smart-d410a848-72c2-4716-bd00-8d387e474401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252578810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.252578810
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.1872184081
Short name T890
Test name
Test status
Simulation time 463159603 ps
CPU time 4.14 seconds
Started May 07 12:37:35 PM PDT 24
Finished May 07 12:37:40 PM PDT 24
Peak memory 210704 kb
Host smart-79f84ed5-6137-4c86-ba00-d1f92c9c2422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872184081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.1872184081
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.1721163689
Short name T561
Test name
Test status
Simulation time 58347435 ps
CPU time 0.77 seconds
Started May 07 12:37:39 PM PDT 24
Finished May 07 12:37:40 PM PDT 24
Peak memory 205940 kb
Host smart-7a6ab53d-97bd-45c8-ae0d-b266f458dec4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721163689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.1721163689
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.2611580290
Short name T416
Test name
Test status
Simulation time 61778669 ps
CPU time 4.08 seconds
Started May 07 12:37:25 PM PDT 24
Finished May 07 12:37:31 PM PDT 24
Peak memory 215284 kb
Host smart-1af319b0-f4bf-49e2-a71d-feb95251ba43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2611580290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.2611580290
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.1455449177
Short name T734
Test name
Test status
Simulation time 253384997 ps
CPU time 6.97 seconds
Started May 07 12:37:21 PM PDT 24
Finished May 07 12:37:31 PM PDT 24
Peak memory 214300 kb
Host smart-817af66b-26dd-4dc4-8a7e-865c8c7f86f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455449177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.1455449177
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.3863022543
Short name T271
Test name
Test status
Simulation time 83340634 ps
CPU time 1.66 seconds
Started May 07 12:37:32 PM PDT 24
Finished May 07 12:37:35 PM PDT 24
Peak memory 214108 kb
Host smart-0dd25d16-d52f-4977-8645-3300738c9f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863022543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.3863022543
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.1293995489
Short name T50
Test name
Test status
Simulation time 742981153 ps
CPU time 3.02 seconds
Started May 07 12:37:27 PM PDT 24
Finished May 07 12:37:31 PM PDT 24
Peak memory 205692 kb
Host smart-abd9e236-4d11-4497-a101-e03c971649fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293995489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.1293995489
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.1340518240
Short name T598
Test name
Test status
Simulation time 1080996004 ps
CPU time 26.46 seconds
Started May 07 12:37:19 PM PDT 24
Finished May 07 12:37:49 PM PDT 24
Peak memory 208540 kb
Host smart-d5a4a25e-a372-4552-bb0f-1a957b2921f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340518240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.1340518240
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.1665955999
Short name T700
Test name
Test status
Simulation time 324857442 ps
CPU time 2.65 seconds
Started May 07 12:37:37 PM PDT 24
Finished May 07 12:37:41 PM PDT 24
Peak memory 206760 kb
Host smart-0a4cc37b-176d-439e-bb1d-f809a5a4b09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665955999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.1665955999
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.260923289
Short name T752
Test name
Test status
Simulation time 36800337 ps
CPU time 2.37 seconds
Started May 07 12:37:45 PM PDT 24
Finished May 07 12:37:49 PM PDT 24
Peak memory 206796 kb
Host smart-e5a91a48-a334-4693-8bde-18acc0d829de
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260923289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.260923289
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.1899977947
Short name T554
Test name
Test status
Simulation time 79037425 ps
CPU time 3.19 seconds
Started May 07 12:37:20 PM PDT 24
Finished May 07 12:37:26 PM PDT 24
Peak memory 206828 kb
Host smart-603e8f97-a64c-4c6d-aef3-67d914143244
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899977947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.1899977947
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.163968439
Short name T573
Test name
Test status
Simulation time 241734670 ps
CPU time 4.58 seconds
Started May 07 12:37:19 PM PDT 24
Finished May 07 12:37:27 PM PDT 24
Peak memory 208392 kb
Host smart-d75c2a42-b032-4732-90c9-6451e3b10bf2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163968439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.163968439
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.2590003062
Short name T770
Test name
Test status
Simulation time 145192675 ps
CPU time 2.53 seconds
Started May 07 12:37:49 PM PDT 24
Finished May 07 12:37:53 PM PDT 24
Peak memory 208656 kb
Host smart-cb6c4f06-e17c-463f-8a1c-81bb06f85a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590003062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.2590003062
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.2452971897
Short name T513
Test name
Test status
Simulation time 20203838 ps
CPU time 1.74 seconds
Started May 07 12:37:25 PM PDT 24
Finished May 07 12:37:29 PM PDT 24
Peak memory 206628 kb
Host smart-633369a1-4727-4d3c-8522-7b8affe080a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452971897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.2452971897
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.3263585247
Short name T375
Test name
Test status
Simulation time 425514680 ps
CPU time 3.47 seconds
Started May 07 12:37:21 PM PDT 24
Finished May 07 12:37:27 PM PDT 24
Peak memory 208580 kb
Host smart-81b8931f-27f0-4de2-bb0d-3ea5bbbd25b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263585247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.3263585247
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.1802727889
Short name T27
Test name
Test status
Simulation time 299301211 ps
CPU time 3.97 seconds
Started May 07 12:37:20 PM PDT 24
Finished May 07 12:37:28 PM PDT 24
Peak memory 214228 kb
Host smart-4957aa23-b073-42f9-97e3-c6952504d7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802727889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.1802727889
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.2245753399
Short name T198
Test name
Test status
Simulation time 72886035 ps
CPU time 3.24 seconds
Started May 07 12:37:41 PM PDT 24
Finished May 07 12:37:46 PM PDT 24
Peak memory 210420 kb
Host smart-3ab144c2-7e3c-43f0-913c-983be8e2c518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245753399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.2245753399
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.3470464811
Short name T882
Test name
Test status
Simulation time 19831775 ps
CPU time 1.01 seconds
Started May 07 12:37:45 PM PDT 24
Finished May 07 12:37:47 PM PDT 24
Peak memory 206060 kb
Host smart-a782deaf-f47f-4c65-86f6-75d18d1ce7ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470464811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.3470464811
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.3261804826
Short name T72
Test name
Test status
Simulation time 36448391 ps
CPU time 1.94 seconds
Started May 07 12:37:26 PM PDT 24
Finished May 07 12:37:29 PM PDT 24
Peak memory 222676 kb
Host smart-23ebd719-4b5b-4d17-bfb4-83d35efc1994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261804826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.3261804826
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.4241371066
Short name T543
Test name
Test status
Simulation time 67924019 ps
CPU time 2.31 seconds
Started May 07 12:37:25 PM PDT 24
Finished May 07 12:37:29 PM PDT 24
Peak memory 207388 kb
Host smart-b2966432-2404-4419-89fc-310f086ca137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241371066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.4241371066
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.2096184398
Short name T273
Test name
Test status
Simulation time 370922833 ps
CPU time 3.38 seconds
Started May 07 12:37:38 PM PDT 24
Finished May 07 12:37:43 PM PDT 24
Peak memory 214260 kb
Host smart-c6d44c31-5026-4951-9f8b-62de3df06921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096184398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.2096184398
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.2101588822
Short name T572
Test name
Test status
Simulation time 63601086 ps
CPU time 3.23 seconds
Started May 07 12:37:27 PM PDT 24
Finished May 07 12:37:32 PM PDT 24
Peak memory 214540 kb
Host smart-9bd7ad39-5470-48f2-a8d0-5ad9c073677b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101588822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.2101588822
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.1923617885
Short name T245
Test name
Test status
Simulation time 175796763 ps
CPU time 2.87 seconds
Started May 07 12:37:28 PM PDT 24
Finished May 07 12:37:32 PM PDT 24
Peak memory 208244 kb
Host smart-e20e71cb-c063-48ef-8b02-5db5d73540e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923617885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.1923617885
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.1687517544
Short name T547
Test name
Test status
Simulation time 576387785 ps
CPU time 5.13 seconds
Started May 07 12:37:35 PM PDT 24
Finished May 07 12:37:41 PM PDT 24
Peak memory 219136 kb
Host smart-30b37a7f-55c5-481b-a766-9e9ed84df904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687517544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.1687517544
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.1067258859
Short name T436
Test name
Test status
Simulation time 202713502 ps
CPU time 7.52 seconds
Started May 07 12:37:42 PM PDT 24
Finished May 07 12:37:51 PM PDT 24
Peak memory 206716 kb
Host smart-11af93f1-56b4-45eb-92b0-2be56604601d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067258859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.1067258859
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.2855930524
Short name T266
Test name
Test status
Simulation time 1470265714 ps
CPU time 5.85 seconds
Started May 07 12:37:33 PM PDT 24
Finished May 07 12:37:40 PM PDT 24
Peak memory 208276 kb
Host smart-ff9b0856-a5c1-4d76-b8cd-35235e64f049
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855930524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.2855930524
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.929876949
Short name T491
Test name
Test status
Simulation time 528598788 ps
CPU time 5.97 seconds
Started May 07 12:37:25 PM PDT 24
Finished May 07 12:37:33 PM PDT 24
Peak memory 208600 kb
Host smart-39799c19-3c5e-488d-bd4c-968a49766f51
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929876949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.929876949
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.83442805
Short name T485
Test name
Test status
Simulation time 180487975 ps
CPU time 6.62 seconds
Started May 07 12:37:31 PM PDT 24
Finished May 07 12:37:39 PM PDT 24
Peak memory 208956 kb
Host smart-05bfa26d-c1fc-4ec3-afd7-d331d8fbcd88
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83442805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.83442805
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.912564424
Short name T262
Test name
Test status
Simulation time 489980425 ps
CPU time 3.79 seconds
Started May 07 12:37:25 PM PDT 24
Finished May 07 12:37:30 PM PDT 24
Peak memory 208760 kb
Host smart-7cb17e08-c14a-4623-9390-c240a1ed4c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912564424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.912564424
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.2369534147
Short name T806
Test name
Test status
Simulation time 240660999 ps
CPU time 2.86 seconds
Started May 07 12:37:32 PM PDT 24
Finished May 07 12:37:37 PM PDT 24
Peak memory 206676 kb
Host smart-152a71c5-8bd4-4e52-aa35-77485fad522f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369534147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.2369534147
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.3601364598
Short name T321
Test name
Test status
Simulation time 921172247 ps
CPU time 31.37 seconds
Started May 07 12:37:29 PM PDT 24
Finished May 07 12:38:02 PM PDT 24
Peak memory 222012 kb
Host smart-e8d9051c-d0dc-4f23-8e89-40fcfb75785b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601364598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.3601364598
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.1539265068
Short name T115
Test name
Test status
Simulation time 997632154 ps
CPU time 20.08 seconds
Started May 07 12:37:21 PM PDT 24
Finished May 07 12:37:44 PM PDT 24
Peak memory 222668 kb
Host smart-27321952-6baf-4c62-963c-dc329a40e3ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539265068 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.1539265068
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.3426425666
Short name T657
Test name
Test status
Simulation time 4503148632 ps
CPU time 9.6 seconds
Started May 07 12:37:34 PM PDT 24
Finished May 07 12:37:45 PM PDT 24
Peak memory 207896 kb
Host smart-92916bab-5362-49ac-bb5c-06e20a512f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426425666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.3426425666
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.286401594
Short name T637
Test name
Test status
Simulation time 55729160 ps
CPU time 1.95 seconds
Started May 07 12:37:35 PM PDT 24
Finished May 07 12:37:38 PM PDT 24
Peak memory 209612 kb
Host smart-64306c95-a153-4d39-9d8b-ebd3da51740d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286401594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.286401594
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.1450080431
Short name T453
Test name
Test status
Simulation time 16638460 ps
CPU time 0.9 seconds
Started May 07 12:36:32 PM PDT 24
Finished May 07 12:36:34 PM PDT 24
Peak memory 206156 kb
Host smart-861fe7bc-9c48-4fdf-ad6f-beda9dc62106
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450080431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.1450080431
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.1215628905
Short name T845
Test name
Test status
Simulation time 32502920 ps
CPU time 2.64 seconds
Started May 07 12:36:21 PM PDT 24
Finished May 07 12:36:27 PM PDT 24
Peak memory 214248 kb
Host smart-9d79cd6c-2648-4aee-86d5-33642b4fc765
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1215628905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.1215628905
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.1566902885
Short name T41
Test name
Test status
Simulation time 290194205 ps
CPU time 3.74 seconds
Started May 07 12:36:23 PM PDT 24
Finished May 07 12:36:29 PM PDT 24
Peak memory 218312 kb
Host smart-9ec41507-5726-4234-ab6e-935c964f81d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566902885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.1566902885
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.2310761769
Short name T840
Test name
Test status
Simulation time 952294217 ps
CPU time 2.7 seconds
Started May 07 12:36:28 PM PDT 24
Finished May 07 12:36:33 PM PDT 24
Peak memory 208696 kb
Host smart-3b1087f7-e379-48f2-a7a3-12bbbf495335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310761769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.2310761769
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.1137059282
Short name T94
Test name
Test status
Simulation time 326613685 ps
CPU time 4.12 seconds
Started May 07 12:36:28 PM PDT 24
Finished May 07 12:36:34 PM PDT 24
Peak memory 208696 kb
Host smart-aa83726e-3bb2-4501-be8f-2a0a9b68dcaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137059282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.1137059282
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.151550612
Short name T556
Test name
Test status
Simulation time 482315552 ps
CPU time 4.35 seconds
Started May 07 12:36:20 PM PDT 24
Finished May 07 12:36:27 PM PDT 24
Peak memory 214304 kb
Host smart-73121863-b9db-4df2-a260-a7fe53fde9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151550612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.151550612
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.1503769813
Short name T450
Test name
Test status
Simulation time 47269864 ps
CPU time 1.39 seconds
Started May 07 12:36:16 PM PDT 24
Finished May 07 12:36:20 PM PDT 24
Peak memory 206824 kb
Host smart-914a805a-a459-43e2-a37b-80674115a9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503769813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.1503769813
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.4273535747
Short name T315
Test name
Test status
Simulation time 1600576371 ps
CPU time 4.28 seconds
Started May 07 12:36:29 PM PDT 24
Finished May 07 12:36:35 PM PDT 24
Peak memory 208872 kb
Host smart-7892f1e8-a8ff-44e9-9c46-7d2138ead38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273535747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.4273535747
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.1626399931
Short name T42
Test name
Test status
Simulation time 554026270 ps
CPU time 11.56 seconds
Started May 07 12:36:22 PM PDT 24
Finished May 07 12:36:36 PM PDT 24
Peak memory 232336 kb
Host smart-9fdc4de9-1064-4d3e-9955-ad000b3e4f90
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626399931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.1626399931
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.3274859944
Short name T544
Test name
Test status
Simulation time 226554635 ps
CPU time 2.9 seconds
Started May 07 12:36:24 PM PDT 24
Finished May 07 12:36:39 PM PDT 24
Peak memory 206768 kb
Host smart-7d6a4256-f670-4f1a-92ab-25cd2b316b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274859944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.3274859944
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.3685480457
Short name T318
Test name
Test status
Simulation time 439292330 ps
CPU time 3.83 seconds
Started May 07 12:36:35 PM PDT 24
Finished May 07 12:36:41 PM PDT 24
Peak memory 206836 kb
Host smart-f6a5560d-66b5-452d-ab27-bb48bca80820
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685480457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.3685480457
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.3869425732
Short name T691
Test name
Test status
Simulation time 58255972 ps
CPU time 3.05 seconds
Started May 07 12:36:24 PM PDT 24
Finished May 07 12:36:29 PM PDT 24
Peak memory 206808 kb
Host smart-f8a3a1d8-51e1-49dd-8788-209ba9ad439f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869425732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.3869425732
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.860145054
Short name T693
Test name
Test status
Simulation time 610676871 ps
CPU time 4.93 seconds
Started May 07 12:36:37 PM PDT 24
Finished May 07 12:36:44 PM PDT 24
Peak memory 208564 kb
Host smart-0fc64d7d-f9a7-40c9-bbca-2e5f2dfb2f89
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860145054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.860145054
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.4099926321
Short name T602
Test name
Test status
Simulation time 87038032 ps
CPU time 2.26 seconds
Started May 07 12:36:29 PM PDT 24
Finished May 07 12:36:33 PM PDT 24
Peak memory 208452 kb
Host smart-0acc568c-5c8d-49f2-b32d-b900f45940c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099926321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.4099926321
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.4185038742
Short name T392
Test name
Test status
Simulation time 877308022 ps
CPU time 4.04 seconds
Started May 07 12:36:26 PM PDT 24
Finished May 07 12:36:32 PM PDT 24
Peak memory 208376 kb
Host smart-d84f1d79-f072-4a4a-a517-d21b92bc9a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185038742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.4185038742
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.683636451
Short name T316
Test name
Test status
Simulation time 8476115407 ps
CPU time 85.69 seconds
Started May 07 12:36:18 PM PDT 24
Finished May 07 12:37:46 PM PDT 24
Peak memory 222752 kb
Host smart-3945ecde-6bc6-467d-9959-734ecd4be8cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683636451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.683636451
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.3000908744
Short name T163
Test name
Test status
Simulation time 389385681 ps
CPU time 9.56 seconds
Started May 07 12:36:25 PM PDT 24
Finished May 07 12:36:37 PM PDT 24
Peak memory 219052 kb
Host smart-3c0d93fa-c3c1-4940-b11e-8dc5fb68cab9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000908744 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.3000908744
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.1350001882
Short name T713
Test name
Test status
Simulation time 826515440 ps
CPU time 8.89 seconds
Started May 07 12:36:25 PM PDT 24
Finished May 07 12:36:37 PM PDT 24
Peak memory 209160 kb
Host smart-148899e7-37f0-4d0d-8bb1-b5dcea0ed45c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350001882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.1350001882
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.2173435321
Short name T182
Test name
Test status
Simulation time 229196403 ps
CPU time 2.11 seconds
Started May 07 12:36:29 PM PDT 24
Finished May 07 12:36:33 PM PDT 24
Peak memory 209812 kb
Host smart-ec3c6f4b-385a-4a14-8bbc-5359458e380b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173435321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.2173435321
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.2487818316
Short name T829
Test name
Test status
Simulation time 35615352 ps
CPU time 0.74 seconds
Started May 07 12:37:35 PM PDT 24
Finished May 07 12:37:36 PM PDT 24
Peak memory 205872 kb
Host smart-9da50d3f-e54f-462d-899b-7248c792bd60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487818316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.2487818316
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.406189066
Short name T32
Test name
Test status
Simulation time 60719115 ps
CPU time 1.83 seconds
Started May 07 12:37:37 PM PDT 24
Finished May 07 12:37:50 PM PDT 24
Peak memory 206024 kb
Host smart-665791c7-1b6e-4ea1-bb6d-53c090f1c14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406189066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.406189066
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.3526815115
Short name T582
Test name
Test status
Simulation time 415389180 ps
CPU time 4 seconds
Started May 07 12:37:21 PM PDT 24
Finished May 07 12:37:28 PM PDT 24
Peak memory 207600 kb
Host smart-f4a86e6b-dfe0-4cd4-a99e-24e568c63eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526815115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.3526815115
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.3960228046
Short name T230
Test name
Test status
Simulation time 32673170 ps
CPU time 1.9 seconds
Started May 07 12:37:20 PM PDT 24
Finished May 07 12:37:25 PM PDT 24
Peak memory 214332 kb
Host smart-03c86f05-75ee-4772-9f5f-535505028652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960228046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.3960228046
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.640968754
Short name T37
Test name
Test status
Simulation time 98608466 ps
CPU time 4.72 seconds
Started May 07 12:37:22 PM PDT 24
Finished May 07 12:37:29 PM PDT 24
Peak memory 222364 kb
Host smart-6d08c9f4-c5a8-4a58-9ba7-465b414b4982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640968754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.640968754
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.2398172427
Short name T43
Test name
Test status
Simulation time 87355920 ps
CPU time 2.93 seconds
Started May 07 12:37:41 PM PDT 24
Finished May 07 12:37:46 PM PDT 24
Peak memory 214336 kb
Host smart-47c391a6-cc56-4206-810e-5d7ad277dd29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398172427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.2398172427
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.2514098568
Short name T665
Test name
Test status
Simulation time 9794960154 ps
CPU time 102.83 seconds
Started May 07 12:37:27 PM PDT 24
Finished May 07 12:39:11 PM PDT 24
Peak memory 213924 kb
Host smart-b3eb199c-e807-431d-b240-5ded0a9636c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514098568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.2514098568
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.4112597102
Short name T82
Test name
Test status
Simulation time 362246488 ps
CPU time 3.64 seconds
Started May 07 12:37:37 PM PDT 24
Finished May 07 12:37:42 PM PDT 24
Peak memory 208220 kb
Host smart-26940be5-0f04-48e3-aef3-b2c00fb8b9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112597102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.4112597102
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.2055825305
Short name T820
Test name
Test status
Simulation time 28523587 ps
CPU time 1.88 seconds
Started May 07 12:37:19 PM PDT 24
Finished May 07 12:37:25 PM PDT 24
Peak memory 207924 kb
Host smart-e1042ba8-7547-413a-a23f-1a6a70db3e52
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055825305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.2055825305
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.854812316
Short name T550
Test name
Test status
Simulation time 868560791 ps
CPU time 6.14 seconds
Started May 07 12:37:19 PM PDT 24
Finished May 07 12:37:29 PM PDT 24
Peak memory 208844 kb
Host smart-a113c6a1-02df-4e62-b51e-6859d02f816a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854812316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.854812316
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.991506529
Short name T552
Test name
Test status
Simulation time 131956446 ps
CPU time 3.5 seconds
Started May 07 12:37:47 PM PDT 24
Finished May 07 12:37:52 PM PDT 24
Peak memory 208256 kb
Host smart-1dc83e07-dadb-470b-957d-80f3ad5fdb10
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991506529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.991506529
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.607117383
Short name T878
Test name
Test status
Simulation time 231804544 ps
CPU time 2.18 seconds
Started May 07 12:37:58 PM PDT 24
Finished May 07 12:38:01 PM PDT 24
Peak memory 210000 kb
Host smart-32989f38-333b-473f-83bc-6775b36256f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607117383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.607117383
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.1553403324
Short name T482
Test name
Test status
Simulation time 6940410237 ps
CPU time 22.81 seconds
Started May 07 12:37:42 PM PDT 24
Finished May 07 12:38:07 PM PDT 24
Peak memory 208152 kb
Host smart-25298906-7ad4-447f-bb77-b52e77f02e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553403324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.1553403324
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.3397426463
Short name T568
Test name
Test status
Simulation time 671756327 ps
CPU time 10.88 seconds
Started May 07 12:37:37 PM PDT 24
Finished May 07 12:37:49 PM PDT 24
Peak memory 214264 kb
Host smart-79cba758-de47-43de-a2fb-6e4132469999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397426463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.3397426463
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.388391502
Short name T651
Test name
Test status
Simulation time 130428204 ps
CPU time 2.19 seconds
Started May 07 12:37:41 PM PDT 24
Finished May 07 12:37:45 PM PDT 24
Peak memory 209968 kb
Host smart-284f1425-1dd3-415e-9c0e-d30b99d7dadc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388391502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.388391502
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.3568431319
Short name T421
Test name
Test status
Simulation time 30094209 ps
CPU time 0.88 seconds
Started May 07 12:37:29 PM PDT 24
Finished May 07 12:37:31 PM PDT 24
Peak memory 205868 kb
Host smart-35eeb3e3-d17a-43f1-8571-d9991738c57f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568431319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.3568431319
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.874832340
Short name T721
Test name
Test status
Simulation time 106616005 ps
CPU time 4.28 seconds
Started May 07 12:37:48 PM PDT 24
Finished May 07 12:37:53 PM PDT 24
Peak memory 214228 kb
Host smart-8bbde89f-4edf-4e0b-be19-7cc35cac1104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874832340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.874832340
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.3186086569
Short name T53
Test name
Test status
Simulation time 97900779 ps
CPU time 2.04 seconds
Started May 07 12:37:50 PM PDT 24
Finished May 07 12:37:53 PM PDT 24
Peak memory 209984 kb
Host smart-1b2aa47c-b2dc-42a5-ba4f-ce8bc825e43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186086569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.3186086569
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.1137393201
Short name T300
Test name
Test status
Simulation time 45297319 ps
CPU time 2.62 seconds
Started May 07 12:37:32 PM PDT 24
Finished May 07 12:37:36 PM PDT 24
Peak memory 222424 kb
Host smart-97671637-c24b-4f09-998b-862ac70590f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137393201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.1137393201
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.1823247934
Short name T435
Test name
Test status
Simulation time 34934863 ps
CPU time 2.02 seconds
Started May 07 12:37:43 PM PDT 24
Finished May 07 12:37:47 PM PDT 24
Peak memory 219604 kb
Host smart-c6125d4f-5f1a-4eb4-9350-1c13f212bef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823247934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.1823247934
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.4232149901
Short name T570
Test name
Test status
Simulation time 105021961 ps
CPU time 4.82 seconds
Started May 07 12:37:23 PM PDT 24
Finished May 07 12:37:30 PM PDT 24
Peak memory 207172 kb
Host smart-48734336-f848-4892-866a-f6ea0296aefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232149901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.4232149901
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.720622988
Short name T725
Test name
Test status
Simulation time 30882311 ps
CPU time 2.15 seconds
Started May 07 12:37:43 PM PDT 24
Finished May 07 12:37:47 PM PDT 24
Peak memory 206708 kb
Host smart-47fb4a25-5a65-416b-9368-8abb828da99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720622988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.720622988
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.1654973014
Short name T694
Test name
Test status
Simulation time 50376172 ps
CPU time 2.53 seconds
Started May 07 12:37:36 PM PDT 24
Finished May 07 12:37:40 PM PDT 24
Peak memory 206720 kb
Host smart-fb3280a7-9f7f-46dc-ad51-173182122e48
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654973014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.1654973014
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.1206535858
Short name T847
Test name
Test status
Simulation time 142396041 ps
CPU time 2.64 seconds
Started May 07 12:37:40 PM PDT 24
Finished May 07 12:37:44 PM PDT 24
Peak memory 208616 kb
Host smart-5bc19cb1-e4c2-4275-9c68-94244dc0be00
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206535858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.1206535858
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.1682004633
Short name T523
Test name
Test status
Simulation time 543730320 ps
CPU time 4.41 seconds
Started May 07 12:37:43 PM PDT 24
Finished May 07 12:37:49 PM PDT 24
Peak memory 208640 kb
Host smart-af87cdf6-845d-49f1-ac18-7110c7cac4a8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682004633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.1682004633
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.2504156860
Short name T347
Test name
Test status
Simulation time 136554594 ps
CPU time 3.97 seconds
Started May 07 12:37:38 PM PDT 24
Finished May 07 12:37:43 PM PDT 24
Peak memory 208168 kb
Host smart-cee4a949-c36d-4c53-b97a-79f6d0624eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504156860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.2504156860
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.2650707624
Short name T861
Test name
Test status
Simulation time 70302039 ps
CPU time 3.29 seconds
Started May 07 12:37:46 PM PDT 24
Finished May 07 12:37:50 PM PDT 24
Peak memory 208340 kb
Host smart-8818b816-921e-43a0-bd7e-b2edaf68a11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650707624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.2650707624
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.3366500810
Short name T244
Test name
Test status
Simulation time 2847830253 ps
CPU time 25.39 seconds
Started May 07 12:37:33 PM PDT 24
Finished May 07 12:38:00 PM PDT 24
Peak memory 216788 kb
Host smart-d93006e3-550a-4b3b-bfb9-32cc70892bc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366500810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.3366500810
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.2722670809
Short name T712
Test name
Test status
Simulation time 898982487 ps
CPU time 3.44 seconds
Started May 07 12:37:40 PM PDT 24
Finished May 07 12:37:44 PM PDT 24
Peak memory 218220 kb
Host smart-0536636a-65a7-42bf-bab3-4e59d5cb5203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722670809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.2722670809
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.1165914479
Short name T627
Test name
Test status
Simulation time 19940008 ps
CPU time 0.69 seconds
Started May 07 12:37:30 PM PDT 24
Finished May 07 12:37:32 PM PDT 24
Peak memory 205808 kb
Host smart-7c41a755-9624-46b9-8102-700376d30901
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165914479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.1165914479
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.3826421112
Short name T406
Test name
Test status
Simulation time 139154614 ps
CPU time 2.87 seconds
Started May 07 12:37:28 PM PDT 24
Finished May 07 12:37:32 PM PDT 24
Peak memory 214280 kb
Host smart-e2ce2098-fbfa-425a-b249-a4e584af9036
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3826421112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.3826421112
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.3271978323
Short name T601
Test name
Test status
Simulation time 70392061 ps
CPU time 2.37 seconds
Started May 07 12:37:40 PM PDT 24
Finished May 07 12:37:43 PM PDT 24
Peak memory 214512 kb
Host smart-94d9a21c-7a73-46e3-91d7-1a06aec58edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271978323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.3271978323
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.1796904193
Short name T75
Test name
Test status
Simulation time 564351494 ps
CPU time 4.02 seconds
Started May 07 12:37:24 PM PDT 24
Finished May 07 12:37:30 PM PDT 24
Peak memory 208936 kb
Host smart-95e0622d-64bf-40fb-9d30-e079cd4245b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796904193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.1796904193
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.2303341248
Short name T93
Test name
Test status
Simulation time 304413119 ps
CPU time 3.62 seconds
Started May 07 12:37:39 PM PDT 24
Finished May 07 12:37:43 PM PDT 24
Peak memory 220204 kb
Host smart-e8cdd47e-72f7-418a-b7e5-2e61f5874885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303341248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.2303341248
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.3972973636
Short name T545
Test name
Test status
Simulation time 145685604 ps
CPU time 3.79 seconds
Started May 07 12:37:58 PM PDT 24
Finished May 07 12:38:03 PM PDT 24
Peak memory 214208 kb
Host smart-16f24e6c-5ded-4a2d-976f-9140c070f689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972973636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.3972973636
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.1324684695
Short name T388
Test name
Test status
Simulation time 172146973 ps
CPU time 2.74 seconds
Started May 07 12:37:33 PM PDT 24
Finished May 07 12:37:37 PM PDT 24
Peak memory 209748 kb
Host smart-9df96593-12c0-44a2-8725-b7520237607f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324684695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.1324684695
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.1735033435
Short name T841
Test name
Test status
Simulation time 108412910 ps
CPU time 5.15 seconds
Started May 07 12:37:49 PM PDT 24
Finished May 07 12:37:55 PM PDT 24
Peak memory 218264 kb
Host smart-3335cc38-67c0-4355-ae72-46959c06dec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735033435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.1735033435
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.4009183311
Short name T226
Test name
Test status
Simulation time 1111959255 ps
CPU time 22.71 seconds
Started May 07 12:37:50 PM PDT 24
Finished May 07 12:38:14 PM PDT 24
Peak memory 208328 kb
Host smart-6dc2ba81-1eed-4c82-9dbe-e9ae0f7572e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009183311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.4009183311
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.2161316607
Short name T531
Test name
Test status
Simulation time 344526221 ps
CPU time 5.42 seconds
Started May 07 12:37:50 PM PDT 24
Finished May 07 12:37:57 PM PDT 24
Peak memory 208908 kb
Host smart-2e4f888c-0c96-4c1d-ace3-21b51566fc2c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161316607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.2161316607
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.2458386789
Short name T579
Test name
Test status
Simulation time 2076664391 ps
CPU time 12.74 seconds
Started May 07 12:37:35 PM PDT 24
Finished May 07 12:37:48 PM PDT 24
Peak memory 207904 kb
Host smart-a60a8cf8-ac33-4ec2-a557-b6d1f08a19d5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458386789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.2458386789
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.1030219996
Short name T753
Test name
Test status
Simulation time 621718188 ps
CPU time 5.51 seconds
Started May 07 12:37:29 PM PDT 24
Finished May 07 12:37:36 PM PDT 24
Peak memory 209008 kb
Host smart-0f65ef09-8d46-4ef6-8528-10cae469da56
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030219996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.1030219996
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.4024131103
Short name T25
Test name
Test status
Simulation time 45956526 ps
CPU time 2.39 seconds
Started May 07 12:37:30 PM PDT 24
Finished May 07 12:37:34 PM PDT 24
Peak memory 208676 kb
Host smart-300e360f-8ec1-4c1d-85c3-f149d401c997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024131103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.4024131103
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.3459198532
Short name T537
Test name
Test status
Simulation time 132431888 ps
CPU time 2.45 seconds
Started May 07 12:37:41 PM PDT 24
Finished May 07 12:37:45 PM PDT 24
Peak memory 208248 kb
Host smart-d96edc1e-afc6-4aa2-9b9d-ebe0ebae37ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459198532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.3459198532
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.1663134829
Short name T297
Test name
Test status
Simulation time 90458051 ps
CPU time 4.32 seconds
Started May 07 12:37:44 PM PDT 24
Finished May 07 12:37:49 PM PDT 24
Peak memory 208856 kb
Host smart-e6eaf789-abc2-48e5-8d5f-de543591c772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663134829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.1663134829
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.2455657659
Short name T677
Test name
Test status
Simulation time 231816404 ps
CPU time 2.66 seconds
Started May 07 12:37:32 PM PDT 24
Finished May 07 12:37:36 PM PDT 24
Peak memory 210320 kb
Host smart-ef6dde75-baa8-4b92-a62c-ada974df6a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455657659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.2455657659
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.116407775
Short name T696
Test name
Test status
Simulation time 24630889 ps
CPU time 0.9 seconds
Started May 07 12:37:49 PM PDT 24
Finished May 07 12:37:51 PM PDT 24
Peak memory 205924 kb
Host smart-11b3dd36-a721-43a5-a439-9b78cb6453d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116407775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.116407775
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.2948301562
Short name T412
Test name
Test status
Simulation time 357362447 ps
CPU time 5.55 seconds
Started May 07 12:37:43 PM PDT 24
Finished May 07 12:37:50 PM PDT 24
Peak memory 214448 kb
Host smart-b4b093ee-bed3-456f-91c1-616ede8f27e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2948301562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.2948301562
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.771929942
Short name T77
Test name
Test status
Simulation time 85183269 ps
CPU time 1.78 seconds
Started May 07 12:37:49 PM PDT 24
Finished May 07 12:37:53 PM PDT 24
Peak memory 208004 kb
Host smart-2a28701c-4e59-4174-ad63-f47804b73356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771929942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.771929942
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.354917375
Short name T269
Test name
Test status
Simulation time 60945094 ps
CPU time 3.26 seconds
Started May 07 12:37:37 PM PDT 24
Finished May 07 12:37:41 PM PDT 24
Peak memory 222500 kb
Host smart-89a5c2e0-2cf5-4242-b59a-283b40dcae7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354917375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.354917375
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.1510719111
Short name T410
Test name
Test status
Simulation time 45370317 ps
CPU time 2.78 seconds
Started May 07 12:37:37 PM PDT 24
Finished May 07 12:37:42 PM PDT 24
Peak memory 222388 kb
Host smart-58628ba7-1a76-495c-b967-63db0623fa4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510719111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.1510719111
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.879418559
Short name T837
Test name
Test status
Simulation time 45517719 ps
CPU time 2.64 seconds
Started May 07 12:37:58 PM PDT 24
Finished May 07 12:38:02 PM PDT 24
Peak memory 208304 kb
Host smart-1df95871-1b30-40a3-b118-6b91f3e959cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879418559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.879418559
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_sideload.3529062355
Short name T441
Test name
Test status
Simulation time 119796642 ps
CPU time 2.85 seconds
Started May 07 12:37:47 PM PDT 24
Finished May 07 12:37:50 PM PDT 24
Peak memory 206852 kb
Host smart-b19be3dc-dea9-4ba5-a047-fb66c9c9f29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529062355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.3529062355
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.841299304
Short name T223
Test name
Test status
Simulation time 76206449 ps
CPU time 3 seconds
Started May 07 12:38:00 PM PDT 24
Finished May 07 12:38:05 PM PDT 24
Peak memory 206820 kb
Host smart-e8ea1bfc-0b2b-4d1e-afab-686d67688893
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841299304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.841299304
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.844368187
Short name T330
Test name
Test status
Simulation time 152727036 ps
CPU time 3.86 seconds
Started May 07 12:37:33 PM PDT 24
Finished May 07 12:37:38 PM PDT 24
Peak memory 208540 kb
Host smart-02e36f28-7c6b-410a-adcc-f84f1c3137b1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844368187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.844368187
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.2563489515
Short name T310
Test name
Test status
Simulation time 35302418 ps
CPU time 1.88 seconds
Started May 07 12:37:40 PM PDT 24
Finished May 07 12:37:43 PM PDT 24
Peak memory 206812 kb
Host smart-211126b5-0cf6-42fd-ab11-80572d777696
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563489515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.2563489515
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.570347416
Short name T856
Test name
Test status
Simulation time 740063239 ps
CPU time 4.71 seconds
Started May 07 12:37:36 PM PDT 24
Finished May 07 12:37:42 PM PDT 24
Peak memory 208628 kb
Host smart-a6d7b2d8-2c1e-460a-8b60-7709ac4335d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570347416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.570347416
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.126428306
Short name T671
Test name
Test status
Simulation time 231240916 ps
CPU time 2.48 seconds
Started May 07 12:37:49 PM PDT 24
Finished May 07 12:37:53 PM PDT 24
Peak memory 207044 kb
Host smart-78ed186e-e7f8-4294-a9c5-20edf57a4bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126428306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.126428306
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.1640576371
Short name T180
Test name
Test status
Simulation time 834589411 ps
CPU time 13.72 seconds
Started May 07 12:37:36 PM PDT 24
Finished May 07 12:37:52 PM PDT 24
Peak memory 216352 kb
Host smart-c5c70463-a4f5-4f8b-bd05-63a96146a725
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640576371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.1640576371
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.1134163818
Short name T650
Test name
Test status
Simulation time 2027898901 ps
CPU time 50.5 seconds
Started May 07 12:37:40 PM PDT 24
Finished May 07 12:38:32 PM PDT 24
Peak memory 218324 kb
Host smart-e2b1937b-4865-4663-88b3-374114d7ac99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134163818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.1134163818
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.1753411941
Short name T535
Test name
Test status
Simulation time 151047840 ps
CPU time 3.14 seconds
Started May 07 12:37:50 PM PDT 24
Finished May 07 12:37:55 PM PDT 24
Peak memory 210368 kb
Host smart-9088f9e6-dd91-4c43-8a47-3f0f77fb1733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753411941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.1753411941
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.538205467
Short name T474
Test name
Test status
Simulation time 11272275 ps
CPU time 0.72 seconds
Started May 07 12:37:58 PM PDT 24
Finished May 07 12:38:00 PM PDT 24
Peak memory 205904 kb
Host smart-340b206a-4a14-47bb-ab14-c14eda4e7831
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538205467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.538205467
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.1262175581
Short name T862
Test name
Test status
Simulation time 349344131 ps
CPU time 18.49 seconds
Started May 07 12:37:48 PM PDT 24
Finished May 07 12:38:08 PM PDT 24
Peak memory 222432 kb
Host smart-a8cdcd5a-3575-429d-8bee-5191913d07b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1262175581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.1262175581
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.3412429278
Short name T31
Test name
Test status
Simulation time 345190852 ps
CPU time 3.06 seconds
Started May 07 12:37:37 PM PDT 24
Finished May 07 12:37:41 PM PDT 24
Peak memory 216720 kb
Host smart-31013840-de58-44d3-ad9b-57746e66283f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412429278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.3412429278
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.2417166082
Short name T497
Test name
Test status
Simulation time 133135423 ps
CPU time 3.39 seconds
Started May 07 12:37:50 PM PDT 24
Finished May 07 12:37:55 PM PDT 24
Peak memory 207436 kb
Host smart-b1c419ac-a36b-42ba-92fd-6070674ffcb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417166082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.2417166082
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.2828393755
Short name T95
Test name
Test status
Simulation time 78034209 ps
CPU time 3.08 seconds
Started May 07 12:37:49 PM PDT 24
Finished May 07 12:37:54 PM PDT 24
Peak memory 220568 kb
Host smart-7b35b046-a8cf-4ad3-89ca-3d92f38345c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828393755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.2828393755
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.2551279005
Short name T218
Test name
Test status
Simulation time 45748310 ps
CPU time 3.04 seconds
Started May 07 12:37:41 PM PDT 24
Finished May 07 12:37:45 PM PDT 24
Peak memory 220560 kb
Host smart-bb0c4bdd-2157-47bb-900a-10ba3ababcf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551279005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.2551279005
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.752001301
Short name T798
Test name
Test status
Simulation time 434032611 ps
CPU time 5.29 seconds
Started May 07 12:37:46 PM PDT 24
Finished May 07 12:37:52 PM PDT 24
Peak memory 218340 kb
Host smart-ba1eac96-56bb-4f33-961b-15e4c0b4747c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752001301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.752001301
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.2670367725
Short name T895
Test name
Test status
Simulation time 89606731 ps
CPU time 4.36 seconds
Started May 07 12:38:01 PM PDT 24
Finished May 07 12:38:08 PM PDT 24
Peak memory 208548 kb
Host smart-e26e93ee-3bd2-49d5-a5fc-f69974420ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670367725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.2670367725
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.3994486183
Short name T314
Test name
Test status
Simulation time 1345754027 ps
CPU time 5.44 seconds
Started May 07 12:37:58 PM PDT 24
Finished May 07 12:38:05 PM PDT 24
Peak memory 208480 kb
Host smart-693ad91a-7393-40de-9b70-b18eee1a4859
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994486183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.3994486183
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.26325524
Short name T448
Test name
Test status
Simulation time 896519985 ps
CPU time 7.72 seconds
Started May 07 12:37:42 PM PDT 24
Finished May 07 12:37:51 PM PDT 24
Peak memory 206932 kb
Host smart-132e76cf-b708-4468-8271-111bb5c750c6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26325524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.26325524
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.4189464789
Short name T623
Test name
Test status
Simulation time 42148984 ps
CPU time 2.34 seconds
Started May 07 12:37:42 PM PDT 24
Finished May 07 12:37:46 PM PDT 24
Peak memory 208112 kb
Host smart-4d38143c-66b2-457d-9e4b-b7d11eb1cd8f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189464789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.4189464789
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.4032491981
Short name T611
Test name
Test status
Simulation time 622992325 ps
CPU time 3.75 seconds
Started May 07 12:37:50 PM PDT 24
Finished May 07 12:37:55 PM PDT 24
Peak memory 206920 kb
Host smart-d71f17e6-b8fd-40ba-8005-94b7d4116928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032491981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.4032491981
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.2808966320
Short name T419
Test name
Test status
Simulation time 410342856 ps
CPU time 2.48 seconds
Started May 07 12:37:52 PM PDT 24
Finished May 07 12:37:56 PM PDT 24
Peak memory 206840 kb
Host smart-67eed94d-fda3-489a-9b5c-0616cab3ad7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808966320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.2808966320
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.1775660187
Short name T765
Test name
Test status
Simulation time 968769279 ps
CPU time 6.45 seconds
Started May 07 12:37:42 PM PDT 24
Finished May 07 12:37:50 PM PDT 24
Peak memory 214280 kb
Host smart-a4f27872-e1b2-4c6f-9020-db09fb83e916
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775660187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.1775660187
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.2895100621
Short name T159
Test name
Test status
Simulation time 335613036 ps
CPU time 11.94 seconds
Started May 07 12:37:48 PM PDT 24
Finished May 07 12:38:02 PM PDT 24
Peak memory 219320 kb
Host smart-d3bbf559-6070-4ce7-8ef7-dd5d4cc752f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895100621 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.2895100621
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.3103796978
Short name T812
Test name
Test status
Simulation time 228315853 ps
CPU time 6.53 seconds
Started May 07 12:37:45 PM PDT 24
Finished May 07 12:37:53 PM PDT 24
Peak memory 209396 kb
Host smart-2afb83cb-31ef-4d19-a640-0b4de1d49b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103796978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.3103796978
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.2014264242
Short name T630
Test name
Test status
Simulation time 232844768 ps
CPU time 2.91 seconds
Started May 07 12:37:41 PM PDT 24
Finished May 07 12:37:46 PM PDT 24
Peak memory 210468 kb
Host smart-3be4013c-7053-4ffc-b072-025df63f2a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014264242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.2014264242
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.1184840378
Short name T501
Test name
Test status
Simulation time 61261823 ps
CPU time 0.77 seconds
Started May 07 12:37:47 PM PDT 24
Finished May 07 12:37:49 PM PDT 24
Peak memory 205880 kb
Host smart-8598cebb-9afa-4590-a726-35b812b50116
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184840378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.1184840378
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.249866420
Short name T252
Test name
Test status
Simulation time 527122159 ps
CPU time 5.33 seconds
Started May 07 12:37:49 PM PDT 24
Finished May 07 12:37:56 PM PDT 24
Peak memory 214496 kb
Host smart-b6cf6909-1cd4-4c13-8653-67954e9352e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249866420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.249866420
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.2074317048
Short name T16
Test name
Test status
Simulation time 61881612 ps
CPU time 2.48 seconds
Started May 07 12:37:43 PM PDT 24
Finished May 07 12:37:47 PM PDT 24
Peak memory 209096 kb
Host smart-b4e4bd5a-f6b6-4724-8f48-75ef9b29d15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074317048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.2074317048
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.1614711878
Short name T814
Test name
Test status
Simulation time 364740453 ps
CPU time 2.81 seconds
Started May 07 12:37:44 PM PDT 24
Finished May 07 12:37:48 PM PDT 24
Peak memory 214244 kb
Host smart-34994a0e-7bae-401e-9f53-9779e14f7d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614711878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.1614711878
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.3291412589
Short name T204
Test name
Test status
Simulation time 60843790 ps
CPU time 3.83 seconds
Started May 07 12:37:45 PM PDT 24
Finished May 07 12:37:50 PM PDT 24
Peak memory 214224 kb
Host smart-98b35230-a276-421b-b649-2ee09966aca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291412589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.3291412589
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.1443032619
Short name T305
Test name
Test status
Simulation time 180902807 ps
CPU time 4.22 seconds
Started May 07 12:37:52 PM PDT 24
Finished May 07 12:37:57 PM PDT 24
Peak memory 218240 kb
Host smart-0edcfafb-3bc4-4404-aea8-f611099b1f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443032619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.1443032619
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.1150323104
Short name T439
Test name
Test status
Simulation time 61577107 ps
CPU time 2.33 seconds
Started May 07 12:38:01 PM PDT 24
Finished May 07 12:38:06 PM PDT 24
Peak memory 206772 kb
Host smart-d94d2079-2006-46ac-9b03-df5f88f2c96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150323104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.1150323104
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.3452935973
Short name T807
Test name
Test status
Simulation time 196040374 ps
CPU time 6.04 seconds
Started May 07 12:37:36 PM PDT 24
Finished May 07 12:37:43 PM PDT 24
Peak memory 209052 kb
Host smart-80ee1be8-cadf-45c9-819a-34ce0e314d27
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452935973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.3452935973
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.3820786882
Short name T492
Test name
Test status
Simulation time 270526912 ps
CPU time 7.35 seconds
Started May 07 12:37:52 PM PDT 24
Finished May 07 12:38:01 PM PDT 24
Peak memory 209076 kb
Host smart-36f57a06-c9e2-459a-a7b9-737e01de71b9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820786882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.3820786882
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.53052759
Short name T518
Test name
Test status
Simulation time 284910507 ps
CPU time 3.26 seconds
Started May 07 12:37:57 PM PDT 24
Finished May 07 12:38:02 PM PDT 24
Peak memory 206908 kb
Host smart-c80886d1-6b9e-461f-a5a9-eab0874ee953
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53052759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.53052759
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.679278070
Short name T541
Test name
Test status
Simulation time 120950921 ps
CPU time 2.77 seconds
Started May 07 12:37:48 PM PDT 24
Finished May 07 12:37:52 PM PDT 24
Peak memory 215740 kb
Host smart-8b6d0bd4-14df-4438-8224-9003be9015dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679278070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.679278070
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.128569680
Short name T641
Test name
Test status
Simulation time 71748262 ps
CPU time 3.06 seconds
Started May 07 12:37:40 PM PDT 24
Finished May 07 12:37:44 PM PDT 24
Peak memory 208656 kb
Host smart-fd5f76b8-4028-49c8-93c4-8d7d78fb971c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128569680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.128569680
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.581999787
Short name T309
Test name
Test status
Simulation time 214749773 ps
CPU time 12.17 seconds
Started May 07 12:38:04 PM PDT 24
Finished May 07 12:38:20 PM PDT 24
Peak memory 222496 kb
Host smart-042e0fd2-3880-4d6b-98e6-d638055ed777
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581999787 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.581999787
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.1410165660
Short name T743
Test name
Test status
Simulation time 205152926 ps
CPU time 3.51 seconds
Started May 07 12:37:52 PM PDT 24
Finished May 07 12:37:56 PM PDT 24
Peak memory 207896 kb
Host smart-1a4b6c3d-a496-475b-9c0c-8ecbdb1317c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410165660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.1410165660
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.2856819984
Short name T811
Test name
Test status
Simulation time 89941233 ps
CPU time 3.03 seconds
Started May 07 12:37:56 PM PDT 24
Finished May 07 12:38:00 PM PDT 24
Peak memory 210160 kb
Host smart-7f88f76c-8fc9-42bf-910a-153650271f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856819984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.2856819984
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.3009530509
Short name T96
Test name
Test status
Simulation time 47802385 ps
CPU time 0.84 seconds
Started May 07 12:38:03 PM PDT 24
Finished May 07 12:38:06 PM PDT 24
Peak memory 205892 kb
Host smart-f40e9757-1ea9-4d04-990a-7a292f26c6ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009530509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.3009530509
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.3489650535
Short name T716
Test name
Test status
Simulation time 41459062 ps
CPU time 2.91 seconds
Started May 07 12:37:58 PM PDT 24
Finished May 07 12:38:02 PM PDT 24
Peak memory 215212 kb
Host smart-30c9414f-9ed4-4f09-b322-74d62ac0c42d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3489650535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.3489650535
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.3441146901
Short name T206
Test name
Test status
Simulation time 107538581 ps
CPU time 4.86 seconds
Started May 07 12:37:59 PM PDT 24
Finished May 07 12:38:06 PM PDT 24
Peak memory 209948 kb
Host smart-b117ad1c-8468-46f7-be3e-094b3f23a0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441146901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.3441146901
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.1380856671
Short name T17
Test name
Test status
Simulation time 273869845 ps
CPU time 2.58 seconds
Started May 07 12:37:53 PM PDT 24
Finished May 07 12:37:57 PM PDT 24
Peak memory 207560 kb
Host smart-6dff9cc9-c0ac-4e6b-9ec6-7adb81f09891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380856671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.1380856671
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.414160037
Short name T394
Test name
Test status
Simulation time 1720500814 ps
CPU time 29.22 seconds
Started May 07 12:37:53 PM PDT 24
Finished May 07 12:38:24 PM PDT 24
Peak memory 209308 kb
Host smart-fa4e958b-4661-49a3-bfd4-526f7ae6626a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414160037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.414160037
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.2846067097
Short name T661
Test name
Test status
Simulation time 385402569 ps
CPU time 3.65 seconds
Started May 07 12:37:52 PM PDT 24
Finished May 07 12:37:56 PM PDT 24
Peak memory 221752 kb
Host smart-2841f26c-9b0c-4d7c-8a9c-a1d361667746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846067097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.2846067097
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.3891270683
Short name T797
Test name
Test status
Simulation time 136598872 ps
CPU time 2.52 seconds
Started May 07 12:37:49 PM PDT 24
Finished May 07 12:37:53 PM PDT 24
Peak memory 209192 kb
Host smart-cb2193f6-923b-4d08-a4db-356c3c9cda81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891270683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.3891270683
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.2188380633
Short name T288
Test name
Test status
Simulation time 739945513 ps
CPU time 6.51 seconds
Started May 07 12:37:55 PM PDT 24
Finished May 07 12:38:02 PM PDT 24
Peak memory 209828 kb
Host smart-67408010-7ff6-4db3-9f0b-fb13665e23a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188380633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.2188380633
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.3598859352
Short name T620
Test name
Test status
Simulation time 62769431 ps
CPU time 2.66 seconds
Started May 07 12:37:41 PM PDT 24
Finished May 07 12:37:45 PM PDT 24
Peak memory 206588 kb
Host smart-910217a4-1143-44c9-b2bd-b7eecfb3c92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598859352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.3598859352
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.3259470238
Short name T724
Test name
Test status
Simulation time 52165649 ps
CPU time 2.79 seconds
Started May 07 12:38:02 PM PDT 24
Finished May 07 12:38:07 PM PDT 24
Peak memory 207952 kb
Host smart-b0e384f4-810c-409c-85b4-17978a9a3ea1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259470238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.3259470238
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.1569922560
Short name T469
Test name
Test status
Simulation time 43979034 ps
CPU time 1.98 seconds
Started May 07 12:38:00 PM PDT 24
Finished May 07 12:38:05 PM PDT 24
Peak memory 208596 kb
Host smart-bed57324-6cdb-41b9-afa3-0eb64767a5b6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569922560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.1569922560
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.3181377038
Short name T885
Test name
Test status
Simulation time 172941982 ps
CPU time 3.1 seconds
Started May 07 12:37:55 PM PDT 24
Finished May 07 12:38:00 PM PDT 24
Peak memory 206920 kb
Host smart-634f2baf-f4cd-4199-bd09-bc36de01f7f9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181377038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.3181377038
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.2994036991
Short name T346
Test name
Test status
Simulation time 70235572 ps
CPU time 2.88 seconds
Started May 07 12:37:55 PM PDT 24
Finished May 07 12:37:59 PM PDT 24
Peak memory 209272 kb
Host smart-5e36e4f3-1d72-4502-b8a5-bfe3670b121e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994036991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.2994036991
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.3561530022
Short name T758
Test name
Test status
Simulation time 4480892694 ps
CPU time 6.88 seconds
Started May 07 12:37:49 PM PDT 24
Finished May 07 12:37:58 PM PDT 24
Peak memory 206936 kb
Host smart-31077fb0-1559-461e-afc2-ffc2ed6b832e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561530022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.3561530022
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.3115720282
Short name T880
Test name
Test status
Simulation time 373896304 ps
CPU time 6.17 seconds
Started May 07 12:37:55 PM PDT 24
Finished May 07 12:38:02 PM PDT 24
Peak memory 220776 kb
Host smart-7010b70f-8364-483d-bbcf-e3b380d89db6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115720282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.3115720282
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.4111923264
Short name T781
Test name
Test status
Simulation time 1986469113 ps
CPU time 15.09 seconds
Started May 07 12:37:58 PM PDT 24
Finished May 07 12:38:14 PM PDT 24
Peak memory 209872 kb
Host smart-99736aa3-9a93-4acb-9cb5-70af06c1815f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111923264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.4111923264
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.3939046336
Short name T868
Test name
Test status
Simulation time 105282092 ps
CPU time 2.52 seconds
Started May 07 12:38:09 PM PDT 24
Finished May 07 12:38:15 PM PDT 24
Peak memory 210092 kb
Host smart-7a51aaa1-74b9-4a45-941f-21d6d3b07da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939046336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.3939046336
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.1982216305
Short name T438
Test name
Test status
Simulation time 9734579 ps
CPU time 0.72 seconds
Started May 07 12:38:09 PM PDT 24
Finished May 07 12:38:14 PM PDT 24
Peak memory 205908 kb
Host smart-9bf43f41-f362-42ad-a9b7-3b26ffa1c4c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982216305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.1982216305
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.518144302
Short name T283
Test name
Test status
Simulation time 363214447 ps
CPU time 5.61 seconds
Started May 07 12:38:03 PM PDT 24
Finished May 07 12:38:11 PM PDT 24
Peak memory 222548 kb
Host smart-7f8b87f6-46c9-434d-aa44-0bdb4a4b2d37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=518144302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.518144302
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.3722492963
Short name T569
Test name
Test status
Simulation time 128698107 ps
CPU time 3.84 seconds
Started May 07 12:38:01 PM PDT 24
Finished May 07 12:38:07 PM PDT 24
Peak memory 209956 kb
Host smart-54d65a3a-a596-4b00-b688-12f8fe8ff324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722492963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.3722492963
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.1925079689
Short name T704
Test name
Test status
Simulation time 31528742 ps
CPU time 2.12 seconds
Started May 07 12:37:47 PM PDT 24
Finished May 07 12:37:50 PM PDT 24
Peak memory 214264 kb
Host smart-b4a76c44-020c-48b3-9f9b-d791605f7db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925079689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.1925079689
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.1865519084
Short name T83
Test name
Test status
Simulation time 261452485 ps
CPU time 3.99 seconds
Started May 07 12:37:55 PM PDT 24
Finished May 07 12:38:00 PM PDT 24
Peak memory 209348 kb
Host smart-06ebf398-ee95-4f8d-b845-30c430808b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865519084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.1865519084
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.3055477397
Short name T55
Test name
Test status
Simulation time 138752490 ps
CPU time 6.19 seconds
Started May 07 12:38:07 PM PDT 24
Finished May 07 12:38:17 PM PDT 24
Peak memory 214272 kb
Host smart-7f09aeb7-812f-4db6-ad93-cfedc5390cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055477397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.3055477397
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.3429092457
Short name T898
Test name
Test status
Simulation time 402688442 ps
CPU time 3.23 seconds
Started May 07 12:38:02 PM PDT 24
Finished May 07 12:38:08 PM PDT 24
Peak memory 214252 kb
Host smart-76e135f5-866b-4e76-9db1-559cd73c0b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429092457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.3429092457
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.1240122078
Short name T267
Test name
Test status
Simulation time 193054892 ps
CPU time 7.25 seconds
Started May 07 12:38:06 PM PDT 24
Finished May 07 12:38:17 PM PDT 24
Peak memory 206736 kb
Host smart-645c659e-e041-4a34-8d87-f5d9f99f0ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240122078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.1240122078
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.3755815612
Short name T263
Test name
Test status
Simulation time 143602280 ps
CPU time 2.52 seconds
Started May 07 12:38:01 PM PDT 24
Finished May 07 12:38:05 PM PDT 24
Peak memory 206872 kb
Host smart-b8b5b2f1-5d7f-4649-923e-66847add9e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755815612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.3755815612
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.1750985569
Short name T311
Test name
Test status
Simulation time 718568860 ps
CPU time 19.24 seconds
Started May 07 12:37:55 PM PDT 24
Finished May 07 12:38:16 PM PDT 24
Peak memory 208120 kb
Host smart-fd5c0935-6d5a-44f5-9c48-c17f624b7f50
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750985569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.1750985569
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.3677447961
Short name T458
Test name
Test status
Simulation time 192690882 ps
CPU time 3.81 seconds
Started May 07 12:37:54 PM PDT 24
Finished May 07 12:37:59 PM PDT 24
Peak memory 208796 kb
Host smart-170623e4-f394-40e8-8f1a-e85ac0981365
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677447961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.3677447961
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.992579023
Short name T669
Test name
Test status
Simulation time 1157569331 ps
CPU time 25.42 seconds
Started May 07 12:38:02 PM PDT 24
Finished May 07 12:38:30 PM PDT 24
Peak memory 208576 kb
Host smart-e8d6e6ad-a703-4e29-a5d6-1db87f2fa7c0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992579023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.992579023
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.2256387299
Short name T332
Test name
Test status
Simulation time 168637828 ps
CPU time 2.74 seconds
Started May 07 12:37:47 PM PDT 24
Finished May 07 12:37:51 PM PDT 24
Peak memory 215404 kb
Host smart-e3ae6469-4e8b-4b3e-836c-86c05112443a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256387299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.2256387299
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.2137700679
Short name T460
Test name
Test status
Simulation time 35478817 ps
CPU time 2.29 seconds
Started May 07 12:37:59 PM PDT 24
Finished May 07 12:38:02 PM PDT 24
Peak memory 206876 kb
Host smart-66de6329-ae70-4cd9-b574-1e79532d1e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137700679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.2137700679
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.1807647782
Short name T763
Test name
Test status
Simulation time 150434676 ps
CPU time 6.92 seconds
Started May 07 12:37:59 PM PDT 24
Finished May 07 12:38:08 PM PDT 24
Peak memory 210644 kb
Host smart-95b3084f-a691-4ab5-b677-47887a081256
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807647782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.1807647782
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.1302631615
Short name T466
Test name
Test status
Simulation time 438501363 ps
CPU time 10.95 seconds
Started May 07 12:38:05 PM PDT 24
Finished May 07 12:38:20 PM PDT 24
Peak memory 219836 kb
Host smart-1c7666d4-3c8a-494a-a4bc-d3ad55d32b40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302631615 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.1302631615
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.3149918724
Short name T631
Test name
Test status
Simulation time 310667091 ps
CPU time 3.87 seconds
Started May 07 12:38:10 PM PDT 24
Finished May 07 12:38:18 PM PDT 24
Peak memory 209900 kb
Host smart-1ba589c4-e89e-40de-b389-f3173d8a12b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149918724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.3149918724
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.3971372563
Short name T618
Test name
Test status
Simulation time 244984706 ps
CPU time 2.11 seconds
Started May 07 12:37:59 PM PDT 24
Finished May 07 12:38:02 PM PDT 24
Peak memory 210664 kb
Host smart-6e12fc68-6324-4824-a7fc-152a8170d574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971372563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.3971372563
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.1344624291
Short name T628
Test name
Test status
Simulation time 22950048 ps
CPU time 0.75 seconds
Started May 07 12:38:11 PM PDT 24
Finished May 07 12:38:16 PM PDT 24
Peak memory 205872 kb
Host smart-9c8fbcb2-b296-4830-bc16-3425c39f6c70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344624291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.1344624291
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.2451052063
Short name T413
Test name
Test status
Simulation time 547121704 ps
CPU time 14.35 seconds
Started May 07 12:37:57 PM PDT 24
Finished May 07 12:38:13 PM PDT 24
Peak memory 215988 kb
Host smart-e6578ed4-b32f-4f34-8a86-836f7c036370
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2451052063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.2451052063
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.359464754
Short name T656
Test name
Test status
Simulation time 475968356 ps
CPU time 2.11 seconds
Started May 07 12:38:06 PM PDT 24
Finished May 07 12:38:11 PM PDT 24
Peak memory 221824 kb
Host smart-170ed38e-e370-4adf-a262-648cdd047949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359464754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.359464754
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.3600711364
Short name T265
Test name
Test status
Simulation time 179479398 ps
CPU time 4.74 seconds
Started May 07 12:38:07 PM PDT 24
Finished May 07 12:38:16 PM PDT 24
Peak memory 218196 kb
Host smart-34f9e2a6-b956-4d5b-8c71-b186243c7d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600711364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.3600711364
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.3466576590
Short name T250
Test name
Test status
Simulation time 121112408 ps
CPU time 3.36 seconds
Started May 07 12:38:10 PM PDT 24
Finished May 07 12:38:17 PM PDT 24
Peak memory 214400 kb
Host smart-5bcc6e06-1016-47ad-901e-ddb5834ba8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466576590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.3466576590
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.2076186684
Short name T749
Test name
Test status
Simulation time 199775964 ps
CPU time 4.7 seconds
Started May 07 12:38:11 PM PDT 24
Finished May 07 12:38:20 PM PDT 24
Peak memory 214208 kb
Host smart-2fc7673c-9db3-4c41-8979-b646950860ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076186684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.2076186684
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.3197240796
Short name T577
Test name
Test status
Simulation time 60969278 ps
CPU time 2.88 seconds
Started May 07 12:37:56 PM PDT 24
Finished May 07 12:38:00 PM PDT 24
Peak memory 209864 kb
Host smart-3600c2bb-c73e-4891-a69d-e2dd5717fcd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197240796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.3197240796
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.11056284
Short name T187
Test name
Test status
Simulation time 385661246 ps
CPU time 4.84 seconds
Started May 07 12:37:55 PM PDT 24
Finished May 07 12:38:01 PM PDT 24
Peak memory 209224 kb
Host smart-134f6494-65f8-459b-be54-47dbf2cd91de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11056284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.11056284
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.957590056
Short name T864
Test name
Test status
Simulation time 181111041 ps
CPU time 2.71 seconds
Started May 07 12:37:52 PM PDT 24
Finished May 07 12:37:55 PM PDT 24
Peak memory 206920 kb
Host smart-fb91ef00-cf07-4d68-9a03-28ba04280dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957590056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.957590056
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.2208710031
Short name T549
Test name
Test status
Simulation time 60271163 ps
CPU time 2.85 seconds
Started May 07 12:38:03 PM PDT 24
Finished May 07 12:38:09 PM PDT 24
Peak memory 208532 kb
Host smart-b66b9e46-af7b-4699-8f91-dc0c41a885a5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208710031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.2208710031
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.3506923250
Short name T805
Test name
Test status
Simulation time 288041058 ps
CPU time 4.83 seconds
Started May 07 12:38:02 PM PDT 24
Finished May 07 12:38:10 PM PDT 24
Peak memory 208100 kb
Host smart-fbc9c531-58fe-40c9-a676-88f0bcaf08cc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506923250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.3506923250
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.1596157179
Short name T869
Test name
Test status
Simulation time 401100422 ps
CPU time 5.28 seconds
Started May 07 12:38:04 PM PDT 24
Finished May 07 12:38:12 PM PDT 24
Peak memory 207464 kb
Host smart-37c1e3f7-6f91-4064-ae20-4769bb39eff0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596157179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.1596157179
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.1237944909
Short name T854
Test name
Test status
Simulation time 324900277 ps
CPU time 3.48 seconds
Started May 07 12:38:05 PM PDT 24
Finished May 07 12:38:12 PM PDT 24
Peak memory 208064 kb
Host smart-2ac5b9f6-6ca5-41c6-a47e-a6db6d9974f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237944909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.1237944909
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.3524197924
Short name T786
Test name
Test status
Simulation time 237889666 ps
CPU time 3.66 seconds
Started May 07 12:38:01 PM PDT 24
Finished May 07 12:38:07 PM PDT 24
Peak memory 206676 kb
Host smart-6ad32411-e92b-4146-b937-d78b4f7613c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524197924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.3524197924
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.178575975
Short name T707
Test name
Test status
Simulation time 8948705820 ps
CPU time 87.29 seconds
Started May 07 12:38:05 PM PDT 24
Finished May 07 12:39:36 PM PDT 24
Peak memory 215532 kb
Host smart-fa1536c8-12c8-4168-811c-c16bbba92c21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178575975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.178575975
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.1750447368
Short name T167
Test name
Test status
Simulation time 258082659 ps
CPU time 8.49 seconds
Started May 07 12:38:08 PM PDT 24
Finished May 07 12:38:20 PM PDT 24
Peak memory 222580 kb
Host smart-ff9665d2-d601-41bf-b35a-5ceb03975dfd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750447368 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.1750447368
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.273766025
Short name T727
Test name
Test status
Simulation time 176091087 ps
CPU time 5.12 seconds
Started May 07 12:38:06 PM PDT 24
Finished May 07 12:38:15 PM PDT 24
Peak memory 218392 kb
Host smart-2d650e68-34f8-480c-a578-a57c62288f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273766025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.273766025
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.2747013870
Short name T510
Test name
Test status
Simulation time 247677818 ps
CPU time 3.29 seconds
Started May 07 12:38:05 PM PDT 24
Finished May 07 12:38:12 PM PDT 24
Peak memory 210968 kb
Host smart-85581950-e27c-4eb1-be6e-0c3de67fedf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747013870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.2747013870
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.2122811075
Short name T486
Test name
Test status
Simulation time 16191281 ps
CPU time 1 seconds
Started May 07 12:37:57 PM PDT 24
Finished May 07 12:38:00 PM PDT 24
Peak memory 206144 kb
Host smart-548062f1-6849-4bc9-a711-2e990665160c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122811075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.2122811075
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.3105297833
Short name T383
Test name
Test status
Simulation time 244294799 ps
CPU time 4.54 seconds
Started May 07 12:37:54 PM PDT 24
Finished May 07 12:38:00 PM PDT 24
Peak memory 215160 kb
Host smart-e2af6339-5cc5-451b-86b6-5d8104e2bddb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3105297833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.3105297833
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.3105524031
Short name T614
Test name
Test status
Simulation time 76057958 ps
CPU time 3.13 seconds
Started May 07 12:38:05 PM PDT 24
Finished May 07 12:38:12 PM PDT 24
Peak memory 209976 kb
Host smart-00d9e0c8-bb22-4e15-91e5-f54e9de373df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105524031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.3105524031
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.936637630
Short name T703
Test name
Test status
Simulation time 87632292 ps
CPU time 2.11 seconds
Started May 07 12:38:00 PM PDT 24
Finished May 07 12:38:04 PM PDT 24
Peak memory 210532 kb
Host smart-84ecc742-0266-496f-89c4-2aebb13a2b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936637630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.936637630
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.980523638
Short name T67
Test name
Test status
Simulation time 49141760 ps
CPU time 2.8 seconds
Started May 07 12:38:05 PM PDT 24
Finished May 07 12:38:11 PM PDT 24
Peak memory 209472 kb
Host smart-88a23250-38d2-405b-b4d5-ec7697bbc408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980523638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.980523638
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.887182748
Short name T796
Test name
Test status
Simulation time 335855797 ps
CPU time 11.11 seconds
Started May 07 12:38:02 PM PDT 24
Finished May 07 12:38:16 PM PDT 24
Peak memory 218316 kb
Host smart-68f1db5c-53f9-436a-9125-257dbf3e20fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887182748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.887182748
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.1401513388
Short name T732
Test name
Test status
Simulation time 10282867729 ps
CPU time 51.09 seconds
Started May 07 12:38:07 PM PDT 24
Finished May 07 12:39:02 PM PDT 24
Peak memory 208040 kb
Host smart-ac5bc4cd-bc66-431c-a499-10a7ddf60d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401513388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.1401513388
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.2127872440
Short name T562
Test name
Test status
Simulation time 224183234 ps
CPU time 3.2 seconds
Started May 07 12:38:08 PM PDT 24
Finished May 07 12:38:15 PM PDT 24
Peak memory 208376 kb
Host smart-377fa7dd-826a-402a-8856-e4e91ef58c66
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127872440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.2127872440
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.517930673
Short name T487
Test name
Test status
Simulation time 138961619 ps
CPU time 2.86 seconds
Started May 07 12:38:03 PM PDT 24
Finished May 07 12:38:09 PM PDT 24
Peak memory 206776 kb
Host smart-80b8d116-21e9-4d52-bf2b-b218b2093381
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517930673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.517930673
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.3972830521
Short name T822
Test name
Test status
Simulation time 278439407 ps
CPU time 7.25 seconds
Started May 07 12:38:05 PM PDT 24
Finished May 07 12:38:16 PM PDT 24
Peak memory 208076 kb
Host smart-009f1e57-7794-4fc0-ad7c-d495b6d48254
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972830521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.3972830521
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.1867477425
Short name T454
Test name
Test status
Simulation time 433509035 ps
CPU time 2.68 seconds
Started May 07 12:38:02 PM PDT 24
Finished May 07 12:38:07 PM PDT 24
Peak memory 217872 kb
Host smart-f1353bf7-3d51-4eb2-a73a-fc044cca3d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867477425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.1867477425
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.4171986613
Short name T817
Test name
Test status
Simulation time 860073351 ps
CPU time 8.16 seconds
Started May 07 12:37:57 PM PDT 24
Finished May 07 12:38:06 PM PDT 24
Peak memory 208104 kb
Host smart-d9c91afe-ffd8-4293-b644-f1c69fa648cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171986613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.4171986613
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.2321553456
Short name T768
Test name
Test status
Simulation time 2321138526 ps
CPU time 30.82 seconds
Started May 07 12:37:57 PM PDT 24
Finished May 07 12:38:29 PM PDT 24
Peak memory 221284 kb
Host smart-042e7ddc-95d9-4676-b3d3-66fe78ff1f16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321553456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.2321553456
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.1836804160
Short name T68
Test name
Test status
Simulation time 461537365 ps
CPU time 8.17 seconds
Started May 07 12:38:04 PM PDT 24
Finished May 07 12:38:15 PM PDT 24
Peak memory 222560 kb
Host smart-75eb57be-990f-4261-baab-c00e7d508371
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836804160 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.1836804160
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.1337814284
Short name T859
Test name
Test status
Simulation time 492813077 ps
CPU time 5.45 seconds
Started May 07 12:38:05 PM PDT 24
Finished May 07 12:38:15 PM PDT 24
Peak memory 209388 kb
Host smart-a7c09963-96db-447a-91f8-3a24d7e831b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337814284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.1337814284
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.3761346735
Short name T367
Test name
Test status
Simulation time 102677238 ps
CPU time 1.67 seconds
Started May 07 12:38:02 PM PDT 24
Finished May 07 12:38:06 PM PDT 24
Peak memory 209840 kb
Host smart-3cc9f444-4b0d-4cf1-8213-815026b421bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761346735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.3761346735
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.4167859509
Short name T901
Test name
Test status
Simulation time 69489099 ps
CPU time 0.84 seconds
Started May 07 12:36:22 PM PDT 24
Finished May 07 12:36:25 PM PDT 24
Peak memory 205896 kb
Host smart-d6dc43a5-d4dc-407e-9dd5-451690bf8b91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167859509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.4167859509
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.1747049243
Short name T278
Test name
Test status
Simulation time 186457661 ps
CPU time 3.67 seconds
Started May 07 12:36:45 PM PDT 24
Finished May 07 12:36:51 PM PDT 24
Peak memory 214292 kb
Host smart-dfbef204-6082-41b0-9213-1e84798975c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1747049243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.1747049243
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.1491095578
Short name T851
Test name
Test status
Simulation time 571280740 ps
CPU time 12.8 seconds
Started May 07 12:36:22 PM PDT 24
Finished May 07 12:36:37 PM PDT 24
Peak memory 208840 kb
Host smart-e6d04bd8-702e-4bb6-8e04-ab496128951e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491095578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.1491095578
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.1961396001
Short name T26
Test name
Test status
Simulation time 183554723 ps
CPU time 2.92 seconds
Started May 07 12:36:22 PM PDT 24
Finished May 07 12:36:28 PM PDT 24
Peak memory 209644 kb
Host smart-1397b1fc-d268-4854-8fbb-fef468394b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961396001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.1961396001
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.2219352719
Short name T857
Test name
Test status
Simulation time 25815437 ps
CPU time 2.18 seconds
Started May 07 12:36:34 PM PDT 24
Finished May 07 12:36:38 PM PDT 24
Peak memory 214208 kb
Host smart-2d843b84-5aee-4b97-848f-f434ee597500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219352719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.2219352719
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.4255228843
Short name T344
Test name
Test status
Simulation time 76093765 ps
CPU time 2.65 seconds
Started May 07 12:36:23 PM PDT 24
Finished May 07 12:36:28 PM PDT 24
Peak memory 214312 kb
Host smart-85aed2e7-f4e3-449a-b63c-a244dd0d9e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255228843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.4255228843
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.2394138710
Short name T44
Test name
Test status
Simulation time 62544641 ps
CPU time 2.7 seconds
Started May 07 12:36:28 PM PDT 24
Finished May 07 12:36:32 PM PDT 24
Peak memory 220128 kb
Host smart-fab154f0-7e2a-4be8-8f3b-7fe78dbe67c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394138710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.2394138710
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.1567889731
Short name T844
Test name
Test status
Simulation time 412700318 ps
CPU time 4.37 seconds
Started May 07 12:36:25 PM PDT 24
Finished May 07 12:36:32 PM PDT 24
Peak memory 208036 kb
Host smart-bd5a2863-72e5-498a-b3bc-a2bd9f45bbf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567889731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.1567889731
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.1489123584
Short name T12
Test name
Test status
Simulation time 1018179649 ps
CPU time 13.99 seconds
Started May 07 12:36:37 PM PDT 24
Finished May 07 12:36:52 PM PDT 24
Peak memory 236200 kb
Host smart-c60a38c7-68a0-4bd7-a2f0-b3d5d1b8b16f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489123584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.1489123584
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.13753338
Short name T595
Test name
Test status
Simulation time 69065150 ps
CPU time 2.11 seconds
Started May 07 12:36:21 PM PDT 24
Finished May 07 12:36:26 PM PDT 24
Peak memory 206544 kb
Host smart-bae0ff9b-389a-45bc-938a-79b219fbc950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13753338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.13753338
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.1212407342
Short name T470
Test name
Test status
Simulation time 72087889 ps
CPU time 3.17 seconds
Started May 07 12:36:36 PM PDT 24
Finished May 07 12:36:41 PM PDT 24
Peak memory 206940 kb
Host smart-cd776cae-029d-4ed3-8bda-4dbd188896cf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212407342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.1212407342
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.941428829
Short name T425
Test name
Test status
Simulation time 47115779 ps
CPU time 2.52 seconds
Started May 07 12:36:23 PM PDT 24
Finished May 07 12:36:28 PM PDT 24
Peak memory 206752 kb
Host smart-02075fcc-339f-42a8-9d0e-c997c9258fe8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941428829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.941428829
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.1122233685
Short name T307
Test name
Test status
Simulation time 76657466 ps
CPU time 3.21 seconds
Started May 07 12:36:32 PM PDT 24
Finished May 07 12:36:36 PM PDT 24
Peak memory 208524 kb
Host smart-c1cf32aa-206c-4bd3-97ee-6b04dab1d48e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122233685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.1122233685
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.3662306255
Short name T264
Test name
Test status
Simulation time 1028135517 ps
CPU time 3.39 seconds
Started May 07 12:36:37 PM PDT 24
Finished May 07 12:36:42 PM PDT 24
Peak memory 209328 kb
Host smart-f86e0441-2ece-4486-aff7-161410d25535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662306255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.3662306255
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.3552243919
Short name T567
Test name
Test status
Simulation time 81006188 ps
CPU time 2.61 seconds
Started May 07 12:36:26 PM PDT 24
Finished May 07 12:36:31 PM PDT 24
Peak memory 206532 kb
Host smart-3203e6e8-5c15-458e-9063-2f5beedfed00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552243919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.3552243919
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.509063673
Short name T212
Test name
Test status
Simulation time 3834464869 ps
CPU time 91.56 seconds
Started May 07 12:36:42 PM PDT 24
Finished May 07 12:38:17 PM PDT 24
Peak memory 222500 kb
Host smart-e3cd268f-a947-432e-b6d6-8e6a460d56bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509063673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.509063673
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.781767426
Short name T629
Test name
Test status
Simulation time 826716256 ps
CPU time 20.93 seconds
Started May 07 12:36:24 PM PDT 24
Finished May 07 12:36:48 PM PDT 24
Peak memory 208420 kb
Host smart-7053fa5b-d889-41d5-a6ff-9b43d001d4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781767426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.781767426
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.4157959071
Short name T387
Test name
Test status
Simulation time 111123874 ps
CPU time 1.63 seconds
Started May 07 12:36:32 PM PDT 24
Finished May 07 12:36:35 PM PDT 24
Peak memory 209928 kb
Host smart-272c7394-84ac-47c4-92a1-5b787d26ea25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157959071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.4157959071
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.2821860809
Short name T494
Test name
Test status
Simulation time 47315050 ps
CPU time 0.8 seconds
Started May 07 12:37:59 PM PDT 24
Finished May 07 12:38:02 PM PDT 24
Peak memory 205864 kb
Host smart-7212568e-443b-420a-b3a4-f1e07976a23b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821860809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.2821860809
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.770854211
Short name T503
Test name
Test status
Simulation time 41187597 ps
CPU time 1.56 seconds
Started May 07 12:38:07 PM PDT 24
Finished May 07 12:38:13 PM PDT 24
Peak memory 207412 kb
Host smart-ddaef391-5578-4213-bef9-9d460992a637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770854211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.770854211
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.600150210
Short name T99
Test name
Test status
Simulation time 499554769 ps
CPU time 4.1 seconds
Started May 07 12:38:05 PM PDT 24
Finished May 07 12:38:12 PM PDT 24
Peak memory 222352 kb
Host smart-de761572-bec7-4f64-8d41-5d22a6559887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600150210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.600150210
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.2713155848
Short name T70
Test name
Test status
Simulation time 103023169 ps
CPU time 2.15 seconds
Started May 07 12:38:10 PM PDT 24
Finished May 07 12:38:16 PM PDT 24
Peak memory 209396 kb
Host smart-c1444ad3-6755-4c84-aed7-82f8dfd8be1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713155848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.2713155848
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.173237985
Short name T287
Test name
Test status
Simulation time 328010225 ps
CPU time 5.57 seconds
Started May 07 12:38:05 PM PDT 24
Finished May 07 12:38:14 PM PDT 24
Peak memory 210080 kb
Host smart-559a5cc5-6146-478e-b3a0-7a48953f8982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173237985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.173237985
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.3707624408
Short name T480
Test name
Test status
Simulation time 175656981 ps
CPU time 3.53 seconds
Started May 07 12:38:08 PM PDT 24
Finished May 07 12:38:15 PM PDT 24
Peak memory 208396 kb
Host smart-3b48e0e7-8fbd-4773-b2a8-54f80bf47f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707624408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.3707624408
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.1882245365
Short name T723
Test name
Test status
Simulation time 136541489 ps
CPU time 2.56 seconds
Started May 07 12:38:02 PM PDT 24
Finished May 07 12:38:07 PM PDT 24
Peak memory 206864 kb
Host smart-6f068155-0f64-43ce-ba01-4bed5f8f4cde
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882245365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.1882245365
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.2555919426
Short name T692
Test name
Test status
Simulation time 7195615197 ps
CPU time 46.75 seconds
Started May 07 12:38:08 PM PDT 24
Finished May 07 12:38:59 PM PDT 24
Peak memory 208712 kb
Host smart-abc90682-86f0-4a5e-a3e8-eae9d5699458
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555919426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.2555919426
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.4190414457
Short name T594
Test name
Test status
Simulation time 6596097655 ps
CPU time 34.14 seconds
Started May 07 12:38:00 PM PDT 24
Finished May 07 12:38:36 PM PDT 24
Peak memory 208968 kb
Host smart-6845cbeb-34d8-4da5-b621-560bde24e4cb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190414457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.4190414457
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.2680259646
Short name T673
Test name
Test status
Simulation time 52893272 ps
CPU time 2.13 seconds
Started May 07 12:37:57 PM PDT 24
Finished May 07 12:38:00 PM PDT 24
Peak memory 207628 kb
Host smart-81a3e85b-2eec-404f-93ca-73e8036bc0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680259646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.2680259646
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.1293765171
Short name T788
Test name
Test status
Simulation time 414848397 ps
CPU time 11.5 seconds
Started May 07 12:38:02 PM PDT 24
Finished May 07 12:38:16 PM PDT 24
Peak memory 208044 kb
Host smart-79eebe31-bbf2-49b6-a211-eb76a70b62e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293765171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.1293765171
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.1947286413
Short name T345
Test name
Test status
Simulation time 1050107327 ps
CPU time 39.41 seconds
Started May 07 12:38:09 PM PDT 24
Finished May 07 12:38:52 PM PDT 24
Peak memory 222356 kb
Host smart-bb593e60-e20b-45c8-bde0-3a7f19fc4d8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947286413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.1947286413
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.3813594064
Short name T616
Test name
Test status
Simulation time 166417219 ps
CPU time 2.85 seconds
Started May 07 12:38:08 PM PDT 24
Finished May 07 12:38:14 PM PDT 24
Peak memory 208132 kb
Host smart-7df20903-9a62-4823-965b-d1207c394ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813594064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.3813594064
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.3317762916
Short name T371
Test name
Test status
Simulation time 139496507 ps
CPU time 2.23 seconds
Started May 07 12:37:58 PM PDT 24
Finished May 07 12:38:02 PM PDT 24
Peak memory 209912 kb
Host smart-fcc98ee1-577d-4d82-8cce-7c624b44e596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317762916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.3317762916
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.3382765054
Short name T427
Test name
Test status
Simulation time 14749043 ps
CPU time 0.89 seconds
Started May 07 12:38:05 PM PDT 24
Finished May 07 12:38:10 PM PDT 24
Peak memory 206096 kb
Host smart-cc0bb91c-13e4-4d6f-9a0b-9105cef88fd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382765054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.3382765054
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.57554104
Short name T742
Test name
Test status
Simulation time 664667790 ps
CPU time 1.71 seconds
Started May 07 12:38:12 PM PDT 24
Finished May 07 12:38:18 PM PDT 24
Peak memory 207768 kb
Host smart-0afa2856-5e79-4f45-8698-04ab1d482f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57554104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.57554104
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.4264549736
Short name T777
Test name
Test status
Simulation time 527700543 ps
CPU time 9.79 seconds
Started May 07 12:38:01 PM PDT 24
Finished May 07 12:38:14 PM PDT 24
Peak memory 208304 kb
Host smart-145cd920-f91b-4e83-9729-02aa5c34fec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264549736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.4264549736
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.1528385554
Short name T780
Test name
Test status
Simulation time 48306086 ps
CPU time 1.94 seconds
Started May 07 12:38:10 PM PDT 24
Finished May 07 12:38:16 PM PDT 24
Peak memory 214268 kb
Host smart-5aff67d0-c272-4c47-852e-6eabe3428459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528385554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.1528385554
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.1715328356
Short name T506
Test name
Test status
Simulation time 119371192 ps
CPU time 2.73 seconds
Started May 07 12:38:05 PM PDT 24
Finished May 07 12:38:12 PM PDT 24
Peak memory 220768 kb
Host smart-cca76584-8226-4d22-af61-674aeeaa2762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715328356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.1715328356
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.3572108616
Short name T225
Test name
Test status
Simulation time 41385936 ps
CPU time 2.59 seconds
Started May 07 12:38:06 PM PDT 24
Finished May 07 12:38:12 PM PDT 24
Peak memory 208184 kb
Host smart-80242192-8da5-474f-abdf-6faba5a89155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572108616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.3572108616
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.3862960984
Short name T171
Test name
Test status
Simulation time 62580934 ps
CPU time 3.03 seconds
Started May 07 12:38:10 PM PDT 24
Finished May 07 12:38:18 PM PDT 24
Peak memory 208068 kb
Host smart-8f641169-f689-4e17-be43-26fcb136a665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862960984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.3862960984
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.1304688105
Short name T782
Test name
Test status
Simulation time 318738887 ps
CPU time 3.88 seconds
Started May 07 12:38:00 PM PDT 24
Finished May 07 12:38:07 PM PDT 24
Peak memory 206828 kb
Host smart-6071e755-439b-45ad-834b-4061fbab1bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304688105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.1304688105
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.3616355872
Short name T475
Test name
Test status
Simulation time 45037353 ps
CPU time 1.98 seconds
Started May 07 12:38:02 PM PDT 24
Finished May 07 12:38:07 PM PDT 24
Peak memory 208688 kb
Host smart-66d5dcf5-bbdb-4d82-ad26-ace420e7fd84
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616355872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.3616355872
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.1682767513
Short name T442
Test name
Test status
Simulation time 40058634 ps
CPU time 2.35 seconds
Started May 07 12:38:07 PM PDT 24
Finished May 07 12:38:13 PM PDT 24
Peak memory 208100 kb
Host smart-50f55622-2444-40d5-8f54-7cd3eecd67fd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682767513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.1682767513
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.2877892837
Short name T612
Test name
Test status
Simulation time 4551497398 ps
CPU time 28.47 seconds
Started May 07 12:38:11 PM PDT 24
Finished May 07 12:38:43 PM PDT 24
Peak memory 208140 kb
Host smart-b4f267f9-0488-48d7-a966-fd2ce4b92acd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877892837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.2877892837
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.1207429626
Short name T773
Test name
Test status
Simulation time 469136685 ps
CPU time 4.13 seconds
Started May 07 12:38:03 PM PDT 24
Finished May 07 12:38:10 PM PDT 24
Peak memory 209456 kb
Host smart-6c21bcbf-c8b7-4d6d-bca9-a123314cf13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207429626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.1207429626
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.1913215824
Short name T808
Test name
Test status
Simulation time 391873665 ps
CPU time 4.69 seconds
Started May 07 12:37:55 PM PDT 24
Finished May 07 12:38:01 PM PDT 24
Peak memory 208216 kb
Host smart-1764ec46-11df-44df-911d-6c81d47e4b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913215824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.1913215824
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.24334106
Short name T162
Test name
Test status
Simulation time 264289066 ps
CPU time 7.55 seconds
Started May 07 12:37:55 PM PDT 24
Finished May 07 12:38:03 PM PDT 24
Peak memory 218048 kb
Host smart-87a8ce7c-5611-4eab-b7b0-818f3eb547d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24334106 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.24334106
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.808784649
Short name T242
Test name
Test status
Simulation time 100269254 ps
CPU time 5.1 seconds
Started May 07 12:38:09 PM PDT 24
Finished May 07 12:38:18 PM PDT 24
Peak memory 208960 kb
Host smart-05082678-da43-470d-a725-9172bd437a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808784649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.808784649
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.456853675
Short name T881
Test name
Test status
Simulation time 80223458 ps
CPU time 1.41 seconds
Started May 07 12:38:04 PM PDT 24
Finished May 07 12:38:08 PM PDT 24
Peak memory 209428 kb
Host smart-c1e59e80-f332-4269-a728-4d4e637af641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456853675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.456853675
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.2845313290
Short name T449
Test name
Test status
Simulation time 31686921 ps
CPU time 0.77 seconds
Started May 07 12:38:07 PM PDT 24
Finished May 07 12:38:12 PM PDT 24
Peak memory 205880 kb
Host smart-04315bef-b3d1-4a65-8223-3aed5ceacf3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845313290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.2845313290
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.3436404096
Short name T73
Test name
Test status
Simulation time 397333862 ps
CPU time 4.14 seconds
Started May 07 12:38:11 PM PDT 24
Finished May 07 12:38:19 PM PDT 24
Peak memory 209164 kb
Host smart-65527abb-cfd6-44f8-b124-4b1b32046d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436404096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.3436404096
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.4073396598
Short name T359
Test name
Test status
Simulation time 119404451 ps
CPU time 2.47 seconds
Started May 07 12:38:07 PM PDT 24
Finished May 07 12:38:19 PM PDT 24
Peak memory 208488 kb
Host smart-3ebc2e23-7dd0-4fec-b2d5-f39f39c7a0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073396598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.4073396598
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.1063422624
Short name T688
Test name
Test status
Simulation time 45408551 ps
CPU time 3.14 seconds
Started May 07 12:38:13 PM PDT 24
Finished May 07 12:38:20 PM PDT 24
Peak memory 215020 kb
Host smart-6e2bd725-586e-41c0-b30e-04b69cfa9abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063422624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.1063422624
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.3551465041
Short name T855
Test name
Test status
Simulation time 154241479 ps
CPU time 2.67 seconds
Started May 07 12:38:04 PM PDT 24
Finished May 07 12:38:10 PM PDT 24
Peak memory 216528 kb
Host smart-5fcb7566-849e-4a24-a339-e4a7f36dc1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551465041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.3551465041
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.3433214500
Short name T525
Test name
Test status
Simulation time 550487905 ps
CPU time 6.5 seconds
Started May 07 12:37:59 PM PDT 24
Finished May 07 12:38:07 PM PDT 24
Peak memory 207284 kb
Host smart-3dc51bd5-2600-434b-af91-58b239553afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433214500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.3433214500
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.851856976
Short name T424
Test name
Test status
Simulation time 1082344170 ps
CPU time 27.45 seconds
Started May 07 12:38:05 PM PDT 24
Finished May 07 12:38:35 PM PDT 24
Peak memory 209044 kb
Host smart-2e08821e-ac73-4600-a9ca-1b63c43aa14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851856976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.851856976
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.3369130192
Short name T13
Test name
Test status
Simulation time 78141124 ps
CPU time 2.46 seconds
Started May 07 12:38:05 PM PDT 24
Finished May 07 12:38:10 PM PDT 24
Peak memory 206884 kb
Host smart-181b030c-2271-4b11-88fc-763694c39161
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369130192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.3369130192
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.2962796339
Short name T899
Test name
Test status
Simulation time 174524245 ps
CPU time 2.5 seconds
Started May 07 12:38:00 PM PDT 24
Finished May 07 12:38:04 PM PDT 24
Peak memory 206932 kb
Host smart-9ca3dc21-fe3a-4c5d-8256-133b63591478
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962796339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.2962796339
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.3692469851
Short name T502
Test name
Test status
Simulation time 36618496 ps
CPU time 2.05 seconds
Started May 07 12:38:06 PM PDT 24
Finished May 07 12:38:12 PM PDT 24
Peak memory 208804 kb
Host smart-b29edaf8-518d-4995-b76e-fd8f77262bba
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692469851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.3692469851
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.173944187
Short name T294
Test name
Test status
Simulation time 32024479 ps
CPU time 2.49 seconds
Started May 07 12:38:03 PM PDT 24
Finished May 07 12:38:08 PM PDT 24
Peak memory 218084 kb
Host smart-7a001ab4-81c0-4fb2-adbc-70e1fa8911f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173944187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.173944187
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.266563648
Short name T684
Test name
Test status
Simulation time 196967450 ps
CPU time 3.07 seconds
Started May 07 12:38:01 PM PDT 24
Finished May 07 12:38:07 PM PDT 24
Peak memory 206624 kb
Host smart-87143bb6-1775-4a33-824e-3c5ad28499b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266563648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.266563648
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.892915362
Short name T730
Test name
Test status
Simulation time 184006584 ps
CPU time 3.55 seconds
Started May 07 12:38:06 PM PDT 24
Finished May 07 12:38:14 PM PDT 24
Peak memory 207476 kb
Host smart-5126b2d8-b042-48f2-972b-e7a4d43bf549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892915362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.892915362
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.2897423509
Short name T838
Test name
Test status
Simulation time 76508525 ps
CPU time 2.34 seconds
Started May 07 12:38:09 PM PDT 24
Finished May 07 12:38:15 PM PDT 24
Peak memory 210200 kb
Host smart-b17d6123-c2a7-4273-82b8-32e76e36f47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897423509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.2897423509
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.3980753239
Short name T445
Test name
Test status
Simulation time 28083888 ps
CPU time 0.95 seconds
Started May 07 12:38:26 PM PDT 24
Finished May 07 12:38:29 PM PDT 24
Peak memory 206188 kb
Host smart-48852547-6311-4eeb-9f89-3dffd1f168dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980753239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.3980753239
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.509026847
Short name T414
Test name
Test status
Simulation time 37096923 ps
CPU time 2.59 seconds
Started May 07 12:38:06 PM PDT 24
Finished May 07 12:38:12 PM PDT 24
Peak memory 214312 kb
Host smart-06fffeb0-60ff-4406-8d74-6ed3a7428bfa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=509026847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.509026847
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.3244923828
Short name T339
Test name
Test status
Simulation time 1644081851 ps
CPU time 14.75 seconds
Started May 07 12:38:05 PM PDT 24
Finished May 07 12:38:24 PM PDT 24
Peak memory 218216 kb
Host smart-367fb802-35ab-4f78-ba1a-97e4bd535e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244923828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.3244923828
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.443401143
Short name T229
Test name
Test status
Simulation time 100586785 ps
CPU time 3 seconds
Started May 07 12:38:02 PM PDT 24
Finished May 07 12:38:07 PM PDT 24
Peak memory 206016 kb
Host smart-0ffa4cb4-8da2-49bf-9f4e-834d58b5f068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443401143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.443401143
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.3906239329
Short name T213
Test name
Test status
Simulation time 71508513 ps
CPU time 2.44 seconds
Started May 07 12:38:08 PM PDT 24
Finished May 07 12:38:15 PM PDT 24
Peak memory 214300 kb
Host smart-78b8b692-85a8-4611-b508-c09f10ce8af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906239329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.3906239329
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.2400796416
Short name T802
Test name
Test status
Simulation time 227279425 ps
CPU time 4.92 seconds
Started May 07 12:38:11 PM PDT 24
Finished May 07 12:38:24 PM PDT 24
Peak memory 207128 kb
Host smart-78366bf4-617e-4bd2-9bbe-a301256ce5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400796416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.2400796416
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.739318679
Short name T836
Test name
Test status
Simulation time 1259330244 ps
CPU time 5.02 seconds
Started May 07 12:38:10 PM PDT 24
Finished May 07 12:38:19 PM PDT 24
Peak memory 208900 kb
Host smart-2d439cbd-a974-4dd5-bc0f-2310494dc976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739318679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.739318679
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.3415678507
Short name T578
Test name
Test status
Simulation time 217316725 ps
CPU time 3.18 seconds
Started May 07 12:38:07 PM PDT 24
Finished May 07 12:38:15 PM PDT 24
Peak memory 206924 kb
Host smart-022d6289-70a0-4678-88ca-fef7f2bf886d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415678507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.3415678507
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.816748054
Short name T580
Test name
Test status
Simulation time 35350630 ps
CPU time 2.44 seconds
Started May 07 12:38:06 PM PDT 24
Finished May 07 12:38:12 PM PDT 24
Peak memory 206888 kb
Host smart-0c426972-46e2-44a5-a9ee-c36779fb3b95
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816748054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.816748054
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.728065410
Short name T496
Test name
Test status
Simulation time 969286792 ps
CPU time 6.76 seconds
Started May 07 12:38:04 PM PDT 24
Finished May 07 12:38:14 PM PDT 24
Peak memory 208092 kb
Host smart-23579b54-dc33-46e9-b6f5-706d716c0a42
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728065410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.728065410
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.3518901554
Short name T717
Test name
Test status
Simulation time 538210530 ps
CPU time 11.5 seconds
Started May 07 12:38:11 PM PDT 24
Finished May 07 12:38:26 PM PDT 24
Peak memory 209632 kb
Host smart-b5823c26-da06-4895-8f37-af62475552ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518901554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.3518901554
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.2199233429
Short name T835
Test name
Test status
Simulation time 245039600 ps
CPU time 3.74 seconds
Started May 07 12:38:03 PM PDT 24
Finished May 07 12:38:09 PM PDT 24
Peak memory 206588 kb
Host smart-773112f2-b211-438a-9cbf-5c4a7fb9571f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199233429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.2199233429
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.2435165839
Short name T894
Test name
Test status
Simulation time 282804297 ps
CPU time 10.19 seconds
Started May 07 12:38:00 PM PDT 24
Finished May 07 12:38:12 PM PDT 24
Peak memory 216968 kb
Host smart-c3feb6e8-5dea-4b9b-bfb0-04df68056970
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435165839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.2435165839
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.862016124
Short name T227
Test name
Test status
Simulation time 123916196 ps
CPU time 2.82 seconds
Started May 07 12:38:16 PM PDT 24
Finished May 07 12:38:21 PM PDT 24
Peak memory 208068 kb
Host smart-d0d3f48a-123e-42b6-a24d-4ad63b58c6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862016124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.862016124
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.2878016776
Short name T374
Test name
Test status
Simulation time 100507432 ps
CPU time 1.94 seconds
Started May 07 12:38:11 PM PDT 24
Finished May 07 12:38:18 PM PDT 24
Peak memory 210128 kb
Host smart-00906710-724f-46a9-9c0b-7d5f1ce690b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878016776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.2878016776
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.281543233
Short name T420
Test name
Test status
Simulation time 72380174 ps
CPU time 0.81 seconds
Started May 07 12:38:11 PM PDT 24
Finished May 07 12:38:16 PM PDT 24
Peak memory 205892 kb
Host smart-43aa4da0-fc60-4ea7-8b15-8ee036ef4fec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281543233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.281543233
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.264443485
Short name T378
Test name
Test status
Simulation time 135029834 ps
CPU time 4.71 seconds
Started May 07 12:38:02 PM PDT 24
Finished May 07 12:38:09 PM PDT 24
Peak memory 215320 kb
Host smart-e68d475e-8d02-4a5c-8278-ab7be4c70227
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=264443485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.264443485
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.814742976
Short name T303
Test name
Test status
Simulation time 502045060 ps
CPU time 4.91 seconds
Started May 07 12:38:03 PM PDT 24
Finished May 07 12:38:10 PM PDT 24
Peak memory 214516 kb
Host smart-0b383ae9-b3ed-4d4b-b53a-79092469d335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814742976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.814742976
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.2750515945
Short name T173
Test name
Test status
Simulation time 376495410 ps
CPU time 4.29 seconds
Started May 07 12:38:03 PM PDT 24
Finished May 07 12:38:10 PM PDT 24
Peak memory 207848 kb
Host smart-7a6d1349-142d-45d1-a4c9-29dc72effb10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750515945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.2750515945
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.3837085156
Short name T907
Test name
Test status
Simulation time 100278589 ps
CPU time 4.14 seconds
Started May 07 12:38:00 PM PDT 24
Finished May 07 12:38:07 PM PDT 24
Peak memory 209156 kb
Host smart-391ca376-ac10-4c25-93ed-e0267f32ebbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837085156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.3837085156
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.3135678387
Short name T322
Test name
Test status
Simulation time 94026890 ps
CPU time 2.93 seconds
Started May 07 12:38:02 PM PDT 24
Finished May 07 12:38:07 PM PDT 24
Peak memory 214232 kb
Host smart-e85e2278-cbce-4c29-bc97-211a38f4771c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135678387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.3135678387
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.3127210251
Short name T667
Test name
Test status
Simulation time 137250264 ps
CPU time 2.94 seconds
Started May 07 12:38:03 PM PDT 24
Finished May 07 12:38:08 PM PDT 24
Peak memory 219992 kb
Host smart-8e6cacad-3f50-469f-b6d9-7b72e2d336f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127210251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.3127210251
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.2448703938
Short name T910
Test name
Test status
Simulation time 36799155 ps
CPU time 2.49 seconds
Started May 07 12:38:02 PM PDT 24
Finished May 07 12:38:07 PM PDT 24
Peak memory 208044 kb
Host smart-66b6b221-9e65-4030-9412-5da0b36999ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448703938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.2448703938
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.1303308175
Short name T422
Test name
Test status
Simulation time 84983892 ps
CPU time 3.68 seconds
Started May 07 12:38:08 PM PDT 24
Finished May 07 12:38:16 PM PDT 24
Peak memory 208400 kb
Host smart-9f0eddcb-f672-4709-91ba-cb41d0814b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303308175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.1303308175
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.2769405764
Short name T779
Test name
Test status
Simulation time 223467420 ps
CPU time 2.15 seconds
Started May 07 12:38:03 PM PDT 24
Finished May 07 12:38:08 PM PDT 24
Peak memory 208900 kb
Host smart-d3900d40-20bb-4cea-9384-676f721095d4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769405764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.2769405764
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.3550259507
Short name T515
Test name
Test status
Simulation time 2382313639 ps
CPU time 16.38 seconds
Started May 07 12:38:01 PM PDT 24
Finished May 07 12:38:26 PM PDT 24
Peak memory 208120 kb
Host smart-0fadd4ec-cabc-434c-b254-a05beadd6d9d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550259507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.3550259507
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.1468787108
Short name T440
Test name
Test status
Simulation time 65340947 ps
CPU time 2.76 seconds
Started May 07 12:38:10 PM PDT 24
Finished May 07 12:38:17 PM PDT 24
Peak memory 214240 kb
Host smart-e21e9fda-2e3f-4d0b-a748-ee8c6f1bb6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468787108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.1468787108
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.2705323158
Short name T495
Test name
Test status
Simulation time 354005879 ps
CPU time 4.88 seconds
Started May 07 12:38:11 PM PDT 24
Finished May 07 12:38:20 PM PDT 24
Peak memory 206744 kb
Host smart-2a738d5a-b10f-4cb4-8fd2-5b5cf523947b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705323158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.2705323158
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.3683980607
Short name T738
Test name
Test status
Simulation time 2155293698 ps
CPU time 53.9 seconds
Started May 07 12:38:08 PM PDT 24
Finished May 07 12:39:06 PM PDT 24
Peak memory 222460 kb
Host smart-dbdb6292-8ef4-4b1b-883a-16a955222347
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683980607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.3683980607
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.1762690022
Short name T804
Test name
Test status
Simulation time 318421837 ps
CPU time 3.89 seconds
Started May 07 12:38:01 PM PDT 24
Finished May 07 12:38:08 PM PDT 24
Peak memory 207692 kb
Host smart-74ac1dc8-49f6-40df-82a4-caf65ba9b7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762690022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.1762690022
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.2912116844
Short name T174
Test name
Test status
Simulation time 329862718 ps
CPU time 3.14 seconds
Started May 07 12:37:59 PM PDT 24
Finished May 07 12:38:04 PM PDT 24
Peak memory 210172 kb
Host smart-cdedb10c-1f84-419b-a683-a45fa5280b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912116844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.2912116844
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.702832248
Short name T776
Test name
Test status
Simulation time 9234238 ps
CPU time 0.83 seconds
Started May 07 12:38:15 PM PDT 24
Finished May 07 12:38:19 PM PDT 24
Peak memory 205912 kb
Host smart-72a675ce-cdf6-472f-8981-44f18f2952b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702832248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.702832248
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.2104498480
Short name T755
Test name
Test status
Simulation time 125323019 ps
CPU time 6.85 seconds
Started May 07 12:38:36 PM PDT 24
Finished May 07 12:38:44 PM PDT 24
Peak memory 214456 kb
Host smart-631db2db-9e5b-4018-a841-b6ead715ff10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2104498480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.2104498480
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.2572407665
Short name T34
Test name
Test status
Simulation time 506266479 ps
CPU time 4.28 seconds
Started May 07 12:38:08 PM PDT 24
Finished May 07 12:38:16 PM PDT 24
Peak memory 222504 kb
Host smart-3bd054fd-c3b0-4656-bac5-80d242f5e43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572407665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.2572407665
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.3694686525
Short name T79
Test name
Test status
Simulation time 221465287 ps
CPU time 2.12 seconds
Started May 07 12:37:55 PM PDT 24
Finished May 07 12:37:58 PM PDT 24
Peak memory 214256 kb
Host smart-85120de2-669f-4ca7-8ef0-33a6fbd1ffa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694686525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.3694686525
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.3672297691
Short name T251
Test name
Test status
Simulation time 431920009 ps
CPU time 4.8 seconds
Started May 07 12:38:21 PM PDT 24
Finished May 07 12:38:27 PM PDT 24
Peak memory 222296 kb
Host smart-e38c079e-eaac-41f6-960f-18a9da4b7778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672297691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.3672297691
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.2744044096
Short name T342
Test name
Test status
Simulation time 618972489 ps
CPU time 4.58 seconds
Started May 07 12:38:04 PM PDT 24
Finished May 07 12:38:11 PM PDT 24
Peak memory 222304 kb
Host smart-7dbe9efc-21dc-4a34-b5b3-14394a2a2292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744044096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.2744044096
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.1975351526
Short name T201
Test name
Test status
Simulation time 59258371 ps
CPU time 2.06 seconds
Started May 07 12:38:05 PM PDT 24
Finished May 07 12:38:11 PM PDT 24
Peak memory 214288 kb
Host smart-73a7371c-82e2-4300-a68d-33e6983ab5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975351526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.1975351526
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.3921489470
Short name T188
Test name
Test status
Simulation time 549885094 ps
CPU time 3.12 seconds
Started May 07 12:38:09 PM PDT 24
Finished May 07 12:38:16 PM PDT 24
Peak memory 207784 kb
Host smart-b32fe9f2-e2dc-4e6f-adac-b0a6647feee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921489470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.3921489470
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.3982176873
Short name T317
Test name
Test status
Simulation time 2967293368 ps
CPU time 20.01 seconds
Started May 07 12:38:02 PM PDT 24
Finished May 07 12:38:24 PM PDT 24
Peak memory 208888 kb
Host smart-dc55809a-9d2e-487e-84b7-a0a03d7355d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982176873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.3982176873
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.2562217726
Short name T499
Test name
Test status
Simulation time 1624203194 ps
CPU time 19.34 seconds
Started May 07 12:38:03 PM PDT 24
Finished May 07 12:38:25 PM PDT 24
Peak memory 208748 kb
Host smart-d184ab07-5d4d-47e1-a718-6789b7de38bf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562217726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.2562217726
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.3971349563
Short name T260
Test name
Test status
Simulation time 308128534 ps
CPU time 3 seconds
Started May 07 12:38:21 PM PDT 24
Finished May 07 12:38:25 PM PDT 24
Peak memory 206884 kb
Host smart-69715d18-a194-4a3c-a59b-c87972b270c6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971349563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.3971349563
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.176611512
Short name T610
Test name
Test status
Simulation time 644516069 ps
CPU time 7.39 seconds
Started May 07 12:38:31 PM PDT 24
Finished May 07 12:38:40 PM PDT 24
Peak memory 206868 kb
Host smart-81413e68-7e3a-4915-ad83-d76f7aa3a076
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176611512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.176611512
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.3873624042
Short name T824
Test name
Test status
Simulation time 137281660 ps
CPU time 2.6 seconds
Started May 07 12:38:26 PM PDT 24
Finished May 07 12:38:30 PM PDT 24
Peak memory 215952 kb
Host smart-0aaa8a44-618d-4d52-b563-810099dccb1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873624042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.3873624042
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.3916734432
Short name T396
Test name
Test status
Simulation time 389672774 ps
CPU time 3.18 seconds
Started May 07 12:38:12 PM PDT 24
Finished May 07 12:38:20 PM PDT 24
Peak memory 206740 kb
Host smart-b81ec8be-4e22-46f4-93e5-5131a04f3ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916734432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.3916734432
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.29569617
Short name T279
Test name
Test status
Simulation time 3328945127 ps
CPU time 36.08 seconds
Started May 07 12:38:13 PM PDT 24
Finished May 07 12:38:53 PM PDT 24
Peak memory 216560 kb
Host smart-c6d933fd-0976-4c92-92f0-7229484bb6a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29569617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.29569617
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.11780239
Short name T532
Test name
Test status
Simulation time 210986513 ps
CPU time 10.04 seconds
Started May 07 12:38:09 PM PDT 24
Finished May 07 12:38:23 PM PDT 24
Peak memory 222504 kb
Host smart-14a626f1-6b79-4b54-b3f8-2e62429eef17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11780239 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.11780239
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.2297425573
Short name T237
Test name
Test status
Simulation time 227791585 ps
CPU time 4.57 seconds
Started May 07 12:38:31 PM PDT 24
Finished May 07 12:38:37 PM PDT 24
Peak memory 218212 kb
Host smart-a187048a-9ef6-46ac-a2b8-081bbdbe7cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297425573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.2297425573
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.2297148723
Short name T858
Test name
Test status
Simulation time 660695096 ps
CPU time 3.83 seconds
Started May 07 12:38:20 PM PDT 24
Finished May 07 12:38:25 PM PDT 24
Peak memory 210428 kb
Host smart-6ae649c0-0df1-4ed8-8f54-7349c6cb2148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297148723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.2297148723
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.2621600338
Short name T747
Test name
Test status
Simulation time 22865369 ps
CPU time 0.81 seconds
Started May 07 12:38:12 PM PDT 24
Finished May 07 12:38:18 PM PDT 24
Peak memory 205900 kb
Host smart-b1a8d024-4da6-41bb-be39-7e4048dcb19e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621600338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.2621600338
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.536554272
Short name T118
Test name
Test status
Simulation time 58706711 ps
CPU time 4.07 seconds
Started May 07 12:38:11 PM PDT 24
Finished May 07 12:38:19 PM PDT 24
Peak memory 214248 kb
Host smart-380b3312-d9fe-4168-b328-084ca9626424
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=536554272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.536554272
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.3548968876
Short name T8
Test name
Test status
Simulation time 77058381 ps
CPU time 3.55 seconds
Started May 07 12:38:02 PM PDT 24
Finished May 07 12:38:08 PM PDT 24
Peak memory 221444 kb
Host smart-dd26f63f-e413-4fd6-8754-331c407dbe54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548968876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.3548968876
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.2986472284
Short name T340
Test name
Test status
Simulation time 823639284 ps
CPU time 18.53 seconds
Started May 07 12:38:04 PM PDT 24
Finished May 07 12:38:26 PM PDT 24
Peak memory 207712 kb
Host smart-ad40ca89-680f-43de-b76e-d387266134dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986472284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.2986472284
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.1421492036
Short name T355
Test name
Test status
Simulation time 585884711 ps
CPU time 4.27 seconds
Started May 07 12:38:21 PM PDT 24
Finished May 07 12:38:27 PM PDT 24
Peak memory 221404 kb
Host smart-c8407ddf-d473-40d2-8532-b44770d743e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421492036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.1421492036
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.3563707656
Short name T687
Test name
Test status
Simulation time 109069877 ps
CPU time 4.83 seconds
Started May 07 12:38:05 PM PDT 24
Finished May 07 12:38:13 PM PDT 24
Peak memory 214160 kb
Host smart-2037d832-7bd7-42bb-8c49-add32851cc6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563707656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.3563707656
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.2359348685
Short name T241
Test name
Test status
Simulation time 217379715 ps
CPU time 4.97 seconds
Started May 07 12:38:05 PM PDT 24
Finished May 07 12:38:14 PM PDT 24
Peak memory 210524 kb
Host smart-b4987c4d-6a27-4294-bd32-1670aadfa150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359348685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.2359348685
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.2178510979
Short name T900
Test name
Test status
Simulation time 171655079 ps
CPU time 2.99 seconds
Started May 07 12:38:27 PM PDT 24
Finished May 07 12:38:31 PM PDT 24
Peak memory 209588 kb
Host smart-3cf605df-a587-4ef7-93c5-6b85a410cdf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178510979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.2178510979
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.319248822
Short name T479
Test name
Test status
Simulation time 639243425 ps
CPU time 13.4 seconds
Started May 07 12:38:11 PM PDT 24
Finished May 07 12:38:29 PM PDT 24
Peak memory 208044 kb
Host smart-3220171b-f5c0-48bd-9c81-037e8d85e726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319248822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.319248822
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.1358415180
Short name T843
Test name
Test status
Simulation time 105085158 ps
CPU time 2.92 seconds
Started May 07 12:38:10 PM PDT 24
Finished May 07 12:38:16 PM PDT 24
Peak memory 208644 kb
Host smart-64b1a3da-d8fc-4a44-bc34-75fd95d981a9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358415180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.1358415180
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.2206668241
Short name T461
Test name
Test status
Simulation time 118688470 ps
CPU time 3.08 seconds
Started May 07 12:38:15 PM PDT 24
Finished May 07 12:38:21 PM PDT 24
Peak memory 206704 kb
Host smart-2de05764-bbf6-42a3-a327-81eb64f5613b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206668241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.2206668241
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.1711962420
Short name T689
Test name
Test status
Simulation time 32204132 ps
CPU time 2.37 seconds
Started May 07 12:38:07 PM PDT 24
Finished May 07 12:38:13 PM PDT 24
Peak memory 206752 kb
Host smart-ca064c9a-59bf-4d24-b45c-3b7c598b5cbc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711962420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.1711962420
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.1392563854
Short name T192
Test name
Test status
Simulation time 133005720 ps
CPU time 2.06 seconds
Started May 07 12:38:09 PM PDT 24
Finished May 07 12:38:15 PM PDT 24
Peak memory 209064 kb
Host smart-a0f13171-2413-4fdb-9606-1cd6ffa1ded5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392563854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.1392563854
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.3679168747
Short name T772
Test name
Test status
Simulation time 1577518666 ps
CPU time 32.56 seconds
Started May 07 12:38:21 PM PDT 24
Finished May 07 12:38:55 PM PDT 24
Peak memory 208216 kb
Host smart-2443cb3d-2729-455b-a950-90bd9a2e1cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679168747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.3679168747
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.722578878
Short name T258
Test name
Test status
Simulation time 413575677 ps
CPU time 14.34 seconds
Started May 07 12:38:27 PM PDT 24
Finished May 07 12:38:43 PM PDT 24
Peak memory 219584 kb
Host smart-2c98aac9-4cb2-4f32-bf76-eb047e8cbb83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722578878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.722578878
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.325856496
Short name T111
Test name
Test status
Simulation time 415017830 ps
CPU time 10.88 seconds
Started May 07 12:38:15 PM PDT 24
Finished May 07 12:38:29 PM PDT 24
Peak memory 218640 kb
Host smart-4bd5b80f-7042-4475-9f24-c226a55a696e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325856496 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.325856496
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.2010649247
Short name T234
Test name
Test status
Simulation time 6721841461 ps
CPU time 42.86 seconds
Started May 07 12:38:14 PM PDT 24
Finished May 07 12:39:01 PM PDT 24
Peak memory 214316 kb
Host smart-a319d8e0-6a2b-4e9e-b798-dcde2012ec92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010649247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.2010649247
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.1897568056
Short name T365
Test name
Test status
Simulation time 49416647 ps
CPU time 2.36 seconds
Started May 07 12:38:06 PM PDT 24
Finished May 07 12:38:13 PM PDT 24
Peak memory 209928 kb
Host smart-6818d691-5943-4cd8-b676-473c1686b2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897568056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.1897568056
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.1788082514
Short name T825
Test name
Test status
Simulation time 12235789 ps
CPU time 0.88 seconds
Started May 07 12:38:08 PM PDT 24
Finished May 07 12:38:13 PM PDT 24
Peak memory 205864 kb
Host smart-eb92e4f4-a6d5-4bf9-8b4e-e57367a40273
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788082514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.1788082514
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.3589977423
Short name T134
Test name
Test status
Simulation time 307684889 ps
CPU time 4.29 seconds
Started May 07 12:38:10 PM PDT 24
Finished May 07 12:38:18 PM PDT 24
Peak memory 214252 kb
Host smart-c06c6077-33e9-434f-8a95-2bedd7d983c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3589977423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.3589977423
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.1872060683
Short name T659
Test name
Test status
Simulation time 40405360 ps
CPU time 1.58 seconds
Started May 07 12:38:19 PM PDT 24
Finished May 07 12:38:22 PM PDT 24
Peak memory 214272 kb
Host smart-ee23b755-faf1-40b6-a01e-2d7e03775df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872060683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.1872060683
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.3017179339
Short name T714
Test name
Test status
Simulation time 126478874 ps
CPU time 3.59 seconds
Started May 07 12:38:06 PM PDT 24
Finished May 07 12:38:13 PM PDT 24
Peak memory 214200 kb
Host smart-e25c08e6-4bb4-4c65-bbc2-7336ce34da0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017179339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.3017179339
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.1709587722
Short name T571
Test name
Test status
Simulation time 59919709 ps
CPU time 2.59 seconds
Started May 07 12:38:04 PM PDT 24
Finished May 07 12:38:09 PM PDT 24
Peak memory 222344 kb
Host smart-a0fbee6f-bcf5-4811-a829-bb97d7fe8d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709587722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.1709587722
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.951552524
Short name T701
Test name
Test status
Simulation time 148890478 ps
CPU time 2.48 seconds
Started May 07 12:38:08 PM PDT 24
Finished May 07 12:38:14 PM PDT 24
Peak memory 215180 kb
Host smart-b258a196-46af-49e3-b2b2-0d2ad208416a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951552524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.951552524
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.3350531168
Short name T177
Test name
Test status
Simulation time 507456328 ps
CPU time 9.73 seconds
Started May 07 12:38:18 PM PDT 24
Finished May 07 12:38:30 PM PDT 24
Peak memory 218504 kb
Host smart-7d86808e-104a-4ed1-9354-941522a2bbfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350531168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.3350531168
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.1127839991
Short name T906
Test name
Test status
Simulation time 125182904 ps
CPU time 2.76 seconds
Started May 07 12:38:21 PM PDT 24
Finished May 07 12:38:25 PM PDT 24
Peak memory 206740 kb
Host smart-9912cf1a-56db-4190-b1ab-ba182732e6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127839991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.1127839991
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.2049792604
Short name T336
Test name
Test status
Simulation time 130762428 ps
CPU time 2.57 seconds
Started May 07 12:38:07 PM PDT 24
Finished May 07 12:38:19 PM PDT 24
Peak memory 206920 kb
Host smart-12bb5b91-85ce-431f-a837-b53f006b80d2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049792604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.2049792604
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.3122332566
Short name T600
Test name
Test status
Simulation time 433388077 ps
CPU time 6.07 seconds
Started May 07 12:38:12 PM PDT 24
Finished May 07 12:38:22 PM PDT 24
Peak memory 208356 kb
Host smart-64666fdb-1afa-49f5-aefd-5661f3e321cf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122332566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.3122332566
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.3412010012
Short name T522
Test name
Test status
Simulation time 146783876 ps
CPU time 2.55 seconds
Started May 07 12:38:34 PM PDT 24
Finished May 07 12:38:38 PM PDT 24
Peak memory 206612 kb
Host smart-906779ce-c31d-412b-8ea6-ecf8344347c8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412010012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.3412010012
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.291141234
Short name T826
Test name
Test status
Simulation time 23143645 ps
CPU time 1.65 seconds
Started May 07 12:38:03 PM PDT 24
Finished May 07 12:38:08 PM PDT 24
Peak memory 208304 kb
Host smart-6e4c7e08-f24f-44a1-bff2-04c1abd58ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291141234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.291141234
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.1410053502
Short name T462
Test name
Test status
Simulation time 78269344 ps
CPU time 2.66 seconds
Started May 07 12:38:07 PM PDT 24
Finished May 07 12:38:13 PM PDT 24
Peak memory 206776 kb
Host smart-be94f268-5506-41a9-a1f4-a37002d3d3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410053502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.1410053502
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.2296858274
Short name T674
Test name
Test status
Simulation time 485819438 ps
CPU time 5.35 seconds
Started May 07 12:38:12 PM PDT 24
Finished May 07 12:38:22 PM PDT 24
Peak memory 210496 kb
Host smart-4e8a279c-f525-43d2-8dd1-bf1acee82f19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296858274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.2296858274
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.924455185
Short name T830
Test name
Test status
Simulation time 159336067 ps
CPU time 8.4 seconds
Started May 07 12:38:11 PM PDT 24
Finished May 07 12:38:28 PM PDT 24
Peak memory 220268 kb
Host smart-bc2143cc-17d1-41fd-baf9-0f69eb5df5ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924455185 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.924455185
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.2351354622
Short name T338
Test name
Test status
Simulation time 616979707 ps
CPU time 4.92 seconds
Started May 07 12:38:27 PM PDT 24
Finished May 07 12:38:33 PM PDT 24
Peak memory 208068 kb
Host smart-81d87915-c461-4c5a-a5f8-c5afa2610fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351354622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.2351354622
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.1847513809
Short name T368
Test name
Test status
Simulation time 96863177 ps
CPU time 3.53 seconds
Started May 07 12:38:08 PM PDT 24
Finished May 07 12:38:15 PM PDT 24
Peak memory 210036 kb
Host smart-9c883989-1bd4-4035-8296-be947f0bd328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847513809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.1847513809
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.2404036219
Short name T731
Test name
Test status
Simulation time 12351309 ps
CPU time 0.74 seconds
Started May 07 12:38:04 PM PDT 24
Finished May 07 12:38:08 PM PDT 24
Peak memory 205900 kb
Host smart-959c3b36-ac5f-49d6-822b-dfc2576b46f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404036219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.2404036219
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.39557857
Short name T20
Test name
Test status
Simulation time 67940766 ps
CPU time 1.79 seconds
Started May 07 12:38:09 PM PDT 24
Finished May 07 12:38:15 PM PDT 24
Peak memory 216056 kb
Host smart-bf3067d1-7701-437c-ac2a-c77fa554b8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39557857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.39557857
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.623632978
Short name T232
Test name
Test status
Simulation time 93049373 ps
CPU time 2.64 seconds
Started May 07 12:38:05 PM PDT 24
Finished May 07 12:38:11 PM PDT 24
Peak memory 218420 kb
Host smart-e54d25d7-55bf-4b17-9adb-16931b2e6dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623632978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.623632978
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.1183077896
Short name T360
Test name
Test status
Simulation time 199325925 ps
CPU time 3.51 seconds
Started May 07 12:38:11 PM PDT 24
Finished May 07 12:38:19 PM PDT 24
Peak memory 209092 kb
Host smart-430aa975-b973-424f-924d-c449a8b5dfe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183077896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.1183077896
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.4284156522
Short name T356
Test name
Test status
Simulation time 616446859 ps
CPU time 3.31 seconds
Started May 07 12:38:08 PM PDT 24
Finished May 07 12:38:16 PM PDT 24
Peak memory 214180 kb
Host smart-d4d6d302-2feb-4e5e-b913-fd3c0704142f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284156522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.4284156522
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_random.962628862
Short name T587
Test name
Test status
Simulation time 503445469 ps
CPU time 4.26 seconds
Started May 07 12:38:10 PM PDT 24
Finished May 07 12:38:18 PM PDT 24
Peak memory 208388 kb
Host smart-1b4a6474-2ae5-415b-b870-fb40b882db14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962628862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.962628862
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.1701608114
Short name T1
Test name
Test status
Simulation time 252716305 ps
CPU time 5.72 seconds
Started May 07 12:38:09 PM PDT 24
Finished May 07 12:38:18 PM PDT 24
Peak memory 208844 kb
Host smart-3f02ebee-e069-4a82-8577-7e12f7808c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701608114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.1701608114
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.9639803
Short name T565
Test name
Test status
Simulation time 176385654 ps
CPU time 3.2 seconds
Started May 07 12:38:12 PM PDT 24
Finished May 07 12:38:19 PM PDT 24
Peak memory 208608 kb
Host smart-106eb708-a6a1-4726-8719-003f731906fd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9639803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.9639803
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.4141578531
Short name T586
Test name
Test status
Simulation time 94089260 ps
CPU time 2.89 seconds
Started May 07 12:38:03 PM PDT 24
Finished May 07 12:38:09 PM PDT 24
Peak memory 206940 kb
Host smart-fe6fe5ae-6c33-4a5f-8252-82e1a7ad9176
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141578531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.4141578531
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.578777214
Short name T348
Test name
Test status
Simulation time 219373925 ps
CPU time 5.88 seconds
Started May 07 12:38:13 PM PDT 24
Finished May 07 12:38:23 PM PDT 24
Peak memory 207964 kb
Host smart-2e7b5a32-4102-4115-acb6-30551a8454f8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578777214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.578777214
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.3688303741
Short name T559
Test name
Test status
Simulation time 171653384 ps
CPU time 2.93 seconds
Started May 07 12:38:06 PM PDT 24
Finished May 07 12:38:12 PM PDT 24
Peak memory 214292 kb
Host smart-d26d0dcf-a261-4659-9a40-ae34dcfbe3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688303741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.3688303741
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.409559552
Short name T520
Test name
Test status
Simulation time 114502700 ps
CPU time 2.32 seconds
Started May 07 12:38:04 PM PDT 24
Finished May 07 12:38:10 PM PDT 24
Peak memory 206668 kb
Host smart-aa0d341f-6b73-4cee-94af-405a8ea695c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409559552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.409559552
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.1230287272
Short name T624
Test name
Test status
Simulation time 226128285 ps
CPU time 5.9 seconds
Started May 07 12:38:06 PM PDT 24
Finished May 07 12:38:15 PM PDT 24
Peak memory 210452 kb
Host smart-b1517a31-c4e1-4418-a2ea-3327382efbee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230287272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.1230287272
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.2863657601
Short name T38
Test name
Test status
Simulation time 41550839 ps
CPU time 1.52 seconds
Started May 07 12:38:12 PM PDT 24
Finished May 07 12:38:22 PM PDT 24
Peak memory 209652 kb
Host smart-f6ca3890-f171-4ab8-be9d-0f1b29fb7c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863657601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.2863657601
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.1693803042
Short name T737
Test name
Test status
Simulation time 15044199 ps
CPU time 0.78 seconds
Started May 07 12:38:21 PM PDT 24
Finished May 07 12:38:24 PM PDT 24
Peak memory 205912 kb
Host smart-46db82c5-28ec-41af-a5ce-3057bd92a63e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693803042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.1693803042
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.3514185812
Short name T210
Test name
Test status
Simulation time 271091793 ps
CPU time 8.07 seconds
Started May 07 12:38:21 PM PDT 24
Finished May 07 12:38:30 PM PDT 24
Peak memory 221668 kb
Host smart-48e34748-2564-4374-a0b8-bb6f1e40d66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514185812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.3514185812
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.3803405659
Short name T733
Test name
Test status
Simulation time 45026555 ps
CPU time 2.3 seconds
Started May 07 12:38:12 PM PDT 24
Finished May 07 12:38:18 PM PDT 24
Peak memory 214352 kb
Host smart-464d1f38-3f09-4cff-abe3-9cb180abd084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803405659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.3803405659
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.2558597066
Short name T46
Test name
Test status
Simulation time 588629741 ps
CPU time 3.34 seconds
Started May 07 12:38:12 PM PDT 24
Finished May 07 12:38:20 PM PDT 24
Peak memory 214408 kb
Host smart-9824a544-adb9-4827-889f-1e7bcb5b8345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558597066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.2558597066
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.156365818
Short name T771
Test name
Test status
Simulation time 87473832 ps
CPU time 2.94 seconds
Started May 07 12:38:19 PM PDT 24
Finished May 07 12:38:23 PM PDT 24
Peak memory 214216 kb
Host smart-bf7fa400-8350-491d-9085-c36eb1ad7bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156365818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.156365818
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.1138234354
Short name T66
Test name
Test status
Simulation time 76145866 ps
CPU time 2.95 seconds
Started May 07 12:38:21 PM PDT 24
Finished May 07 12:38:26 PM PDT 24
Peak memory 222404 kb
Host smart-a0f47984-8e30-4a69-83a5-bb6f5ec71991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138234354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.1138234354
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.943880250
Short name T505
Test name
Test status
Simulation time 140003559 ps
CPU time 4.34 seconds
Started May 07 12:38:37 PM PDT 24
Finished May 07 12:38:43 PM PDT 24
Peak memory 208068 kb
Host smart-1d24a081-c203-4f7b-b2b5-b7ed311b0378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943880250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.943880250
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.944828195
Short name T500
Test name
Test status
Simulation time 165217485 ps
CPU time 3.68 seconds
Started May 07 12:38:55 PM PDT 24
Finished May 07 12:39:01 PM PDT 24
Peak memory 208056 kb
Host smart-cbad467c-dfef-4a6f-8991-accb44583555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944828195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.944828195
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.3213383022
Short name T81
Test name
Test status
Simulation time 32865662 ps
CPU time 2.37 seconds
Started May 07 12:38:05 PM PDT 24
Finished May 07 12:38:10 PM PDT 24
Peak memory 206896 kb
Host smart-d97081d4-6e34-4894-8cd5-fca5c10539b0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213383022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.3213383022
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.3360723011
Short name T622
Test name
Test status
Simulation time 222053978 ps
CPU time 7.82 seconds
Started May 07 12:38:25 PM PDT 24
Finished May 07 12:38:34 PM PDT 24
Peak memory 208812 kb
Host smart-9ea2ed15-9ca0-4e4f-8d8b-eb089b97149b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360723011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.3360723011
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.2359791677
Short name T685
Test name
Test status
Simulation time 720324448 ps
CPU time 5.8 seconds
Started May 07 12:38:05 PM PDT 24
Finished May 07 12:38:15 PM PDT 24
Peak memory 208916 kb
Host smart-b98fba96-21d6-4287-b4b8-07d620a0b4d8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359791677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.2359791677
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.1489997949
Short name T615
Test name
Test status
Simulation time 810810462 ps
CPU time 8.44 seconds
Started May 07 12:38:05 PM PDT 24
Finished May 07 12:38:17 PM PDT 24
Peak memory 208224 kb
Host smart-15b7e8a9-a8e2-45b9-a103-32b42fc0e07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489997949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.1489997949
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.1683971289
Short name T397
Test name
Test status
Simulation time 1097242696 ps
CPU time 5.93 seconds
Started May 07 12:38:10 PM PDT 24
Finished May 07 12:38:24 PM PDT 24
Peak memory 207152 kb
Host smart-b0fd5c5b-7dc5-4530-9c5c-0699fda9f69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683971289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.1683971289
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.1551353721
Short name T285
Test name
Test status
Simulation time 20830484685 ps
CPU time 68.47 seconds
Started May 07 12:38:11 PM PDT 24
Finished May 07 12:39:24 PM PDT 24
Peak memory 222500 kb
Host smart-8682597c-e258-4386-9415-21c79fb392b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551353721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.1551353721
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.3394676582
Short name T409
Test name
Test status
Simulation time 1852796065 ps
CPU time 6.27 seconds
Started May 07 12:38:13 PM PDT 24
Finished May 07 12:38:23 PM PDT 24
Peak memory 207692 kb
Host smart-3280a681-8bc8-4c0e-8d31-d85ef64199e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394676582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.3394676582
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.421142197
Short name T794
Test name
Test status
Simulation time 156584413 ps
CPU time 3.21 seconds
Started May 07 12:38:12 PM PDT 24
Finished May 07 12:38:19 PM PDT 24
Peak memory 210360 kb
Host smart-91da095b-7a5f-4e66-9f92-52aef818e623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421142197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.421142197
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.11645008
Short name T790
Test name
Test status
Simulation time 15744774 ps
CPU time 0.99 seconds
Started May 07 12:36:41 PM PDT 24
Finished May 07 12:36:44 PM PDT 24
Peak memory 206100 kb
Host smart-50275d6f-cb1d-41af-867e-cd5d8ab34d17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11645008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.11645008
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.2226265480
Short name T400
Test name
Test status
Simulation time 53948964 ps
CPU time 3.77 seconds
Started May 07 12:36:39 PM PDT 24
Finished May 07 12:36:44 PM PDT 24
Peak memory 214268 kb
Host smart-a66247f6-2cc9-415a-872d-1de0b1e14915
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2226265480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.2226265480
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.1905726699
Short name T589
Test name
Test status
Simulation time 2858477187 ps
CPU time 19.83 seconds
Started May 07 12:36:29 PM PDT 24
Finished May 07 12:36:51 PM PDT 24
Peak memory 214732 kb
Host smart-269b804a-a8c8-4668-9bac-11b8e12f0d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905726699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.1905726699
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.2950141347
Short name T298
Test name
Test status
Simulation time 163239936 ps
CPU time 4.22 seconds
Started May 07 12:36:41 PM PDT 24
Finished May 07 12:36:47 PM PDT 24
Peak memory 207304 kb
Host smart-4e73a502-de53-4af9-9ab3-b2482306e4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950141347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.2950141347
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.3016083806
Short name T739
Test name
Test status
Simulation time 356599685 ps
CPU time 7.69 seconds
Started May 07 12:36:29 PM PDT 24
Finished May 07 12:36:39 PM PDT 24
Peak memory 220884 kb
Host smart-9c6c7925-053e-4b61-b985-8a01927e088a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016083806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.3016083806
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.1853594670
Short name T272
Test name
Test status
Simulation time 341448178 ps
CPU time 3.92 seconds
Started May 07 12:36:24 PM PDT 24
Finished May 07 12:36:31 PM PDT 24
Peak memory 219744 kb
Host smart-2b2f3dd8-80b2-4fa3-8a82-9e0bcf88cdd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853594670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.1853594670
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.3756060012
Short name T583
Test name
Test status
Simulation time 180960114 ps
CPU time 3.95 seconds
Started May 07 12:36:34 PM PDT 24
Finished May 07 12:36:40 PM PDT 24
Peak memory 216148 kb
Host smart-41087758-d36a-4ae8-ab5e-e47073714d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756060012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.3756060012
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.52263700
Short name T477
Test name
Test status
Simulation time 1061713191 ps
CPU time 3.96 seconds
Started May 07 12:36:25 PM PDT 24
Finished May 07 12:36:32 PM PDT 24
Peak memory 207140 kb
Host smart-7beec9c1-89b0-4884-93c4-07b1dfd1ecd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52263700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.52263700
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.1253986505
Short name T819
Test name
Test status
Simulation time 62605459 ps
CPU time 2.33 seconds
Started May 07 12:36:27 PM PDT 24
Finished May 07 12:36:32 PM PDT 24
Peak memory 206768 kb
Host smart-39c654b7-a280-4475-b4a4-13541e40a28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253986505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.1253986505
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.4077093201
Short name T655
Test name
Test status
Simulation time 123547705 ps
CPU time 2.49 seconds
Started May 07 12:36:33 PM PDT 24
Finished May 07 12:36:37 PM PDT 24
Peak memory 206900 kb
Host smart-8e27e988-b7f0-4f7c-86aa-07b05d506e32
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077093201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.4077093201
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.3023645383
Short name T603
Test name
Test status
Simulation time 382675992 ps
CPU time 8.22 seconds
Started May 07 12:36:24 PM PDT 24
Finished May 07 12:36:35 PM PDT 24
Peak memory 208768 kb
Host smart-e0eb9533-eab1-4538-9170-00b6d5dce514
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023645383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.3023645383
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.2390023075
Short name T914
Test name
Test status
Simulation time 147655182 ps
CPU time 3.51 seconds
Started May 07 12:36:37 PM PDT 24
Finished May 07 12:36:42 PM PDT 24
Peak memory 206796 kb
Host smart-54c67c85-c4ac-4be2-babe-cede3a0bab5c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390023075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.2390023075
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.2229820256
Short name T350
Test name
Test status
Simulation time 94901456 ps
CPU time 3.95 seconds
Started May 07 12:36:44 PM PDT 24
Finished May 07 12:36:50 PM PDT 24
Peak memory 215748 kb
Host smart-142c0711-e2bd-4bfc-82da-140186dbaee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229820256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.2229820256
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.2224584821
Short name T769
Test name
Test status
Simulation time 322254874 ps
CPU time 4.41 seconds
Started May 07 12:36:30 PM PDT 24
Finished May 07 12:36:42 PM PDT 24
Peak memory 207844 kb
Host smart-a8c0cfcd-d8fa-4006-acec-90b500e62ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224584821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.2224584821
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.1561972620
Short name T215
Test name
Test status
Simulation time 675369100 ps
CPU time 13.18 seconds
Started May 07 12:36:26 PM PDT 24
Finished May 07 12:36:41 PM PDT 24
Peak memory 220564 kb
Host smart-19d66348-3a52-4be6-8c91-3fc008c573c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561972620 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.1561972620
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.299321069
Short name T751
Test name
Test status
Simulation time 186812884 ps
CPU time 5.05 seconds
Started May 07 12:36:44 PM PDT 24
Finished May 07 12:36:52 PM PDT 24
Peak memory 209104 kb
Host smart-f74732e3-9775-4430-836d-cd1438e193da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299321069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.299321069
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.1640336083
Short name T364
Test name
Test status
Simulation time 182324191 ps
CPU time 2.22 seconds
Started May 07 12:36:25 PM PDT 24
Finished May 07 12:36:30 PM PDT 24
Peak memory 210116 kb
Host smart-bbdf7049-77ac-4f8c-8e1d-6aff9c6feb73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640336083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.1640336083
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.2750640258
Short name T664
Test name
Test status
Simulation time 25232147 ps
CPU time 0.89 seconds
Started May 07 12:36:49 PM PDT 24
Finished May 07 12:36:53 PM PDT 24
Peak memory 205892 kb
Host smart-d8eeecfe-1850-4d02-8e96-d9153a8ef81f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750640258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.2750640258
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.1325403309
Short name T744
Test name
Test status
Simulation time 431131834 ps
CPU time 4.36 seconds
Started May 07 12:36:33 PM PDT 24
Finished May 07 12:36:39 PM PDT 24
Peak memory 215512 kb
Host smart-50db156e-1b57-49a6-b1f7-d8ab178e080f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1325403309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.1325403309
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.2458048408
Short name T33
Test name
Test status
Simulation time 128637306 ps
CPU time 3.66 seconds
Started May 07 12:36:27 PM PDT 24
Finished May 07 12:36:38 PM PDT 24
Peak memory 214208 kb
Host smart-14616477-7b29-432e-8c3e-1bc5cfef1bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458048408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.2458048408
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.1120011546
Short name T877
Test name
Test status
Simulation time 94568964 ps
CPU time 2.7 seconds
Started May 07 12:36:51 PM PDT 24
Finished May 07 12:36:57 PM PDT 24
Peak memory 207760 kb
Host smart-4674ba6f-2bc6-4f05-8a7d-3207ad46f39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120011546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.1120011546
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.3886340907
Short name T87
Test name
Test status
Simulation time 96963301 ps
CPU time 2.98 seconds
Started May 07 12:36:46 PM PDT 24
Finished May 07 12:36:52 PM PDT 24
Peak memory 214284 kb
Host smart-33f009d2-f9ae-4ba9-80a7-f8cfeb83ff3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886340907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.3886340907
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.1116069227
Short name T353
Test name
Test status
Simulation time 213632882 ps
CPU time 3.52 seconds
Started May 07 12:36:33 PM PDT 24
Finished May 07 12:36:38 PM PDT 24
Peak memory 220332 kb
Host smart-b4ecde16-30b3-44c5-956e-85dc43ef73ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116069227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.1116069227
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.3525221214
Short name T892
Test name
Test status
Simulation time 125491395 ps
CPU time 1.81 seconds
Started May 07 12:36:19 PM PDT 24
Finished May 07 12:36:24 PM PDT 24
Peak memory 215748 kb
Host smart-d6563ba9-2253-42be-a332-7a2cdb3c6b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525221214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.3525221214
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.1880878231
Short name T293
Test name
Test status
Simulation time 680772914 ps
CPU time 5.24 seconds
Started May 07 12:36:26 PM PDT 24
Finished May 07 12:36:34 PM PDT 24
Peak memory 208628 kb
Host smart-560676e9-5b30-468f-abc0-f479fce1b95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880878231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.1880878231
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.405658274
Short name T478
Test name
Test status
Simulation time 141785010 ps
CPU time 4.81 seconds
Started May 07 12:36:37 PM PDT 24
Finished May 07 12:36:44 PM PDT 24
Peak memory 206644 kb
Host smart-124922a0-61c2-4ac4-b16a-ee350f8cbe88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405658274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.405658274
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.4249786241
Short name T176
Test name
Test status
Simulation time 235975604 ps
CPU time 8.68 seconds
Started May 07 12:36:49 PM PDT 24
Finished May 07 12:37:00 PM PDT 24
Peak memory 206840 kb
Host smart-97e6d783-850f-4825-b4dd-2d4d200a1a67
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249786241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.4249786241
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.1997092179
Short name T588
Test name
Test status
Simulation time 73139964 ps
CPU time 3.75 seconds
Started May 07 12:36:25 PM PDT 24
Finished May 07 12:36:31 PM PDT 24
Peak memory 208876 kb
Host smart-609af237-4951-4c6e-989a-a0d3b3ccde00
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997092179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.1997092179
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.479695561
Short name T195
Test name
Test status
Simulation time 468453851 ps
CPU time 7.19 seconds
Started May 07 12:36:34 PM PDT 24
Finished May 07 12:36:43 PM PDT 24
Peak memory 208004 kb
Host smart-e2dec4e5-5c9b-4e8d-8add-4fa33fb50b60
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479695561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.479695561
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.2894867660
Short name T609
Test name
Test status
Simulation time 280041278 ps
CPU time 4.47 seconds
Started May 07 12:36:32 PM PDT 24
Finished May 07 12:36:38 PM PDT 24
Peak memory 218060 kb
Host smart-26b40ab4-2599-42af-843b-203b726a657d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894867660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.2894867660
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.2150695859
Short name T887
Test name
Test status
Simulation time 3040933849 ps
CPU time 31.85 seconds
Started May 07 12:36:44 PM PDT 24
Finished May 07 12:37:18 PM PDT 24
Peak memory 208192 kb
Host smart-e778b93e-655e-453b-b0fd-992ab323bfb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150695859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.2150695859
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.786185328
Short name T789
Test name
Test status
Simulation time 3444334660 ps
CPU time 12.76 seconds
Started May 07 12:36:23 PM PDT 24
Finished May 07 12:36:38 PM PDT 24
Peak memory 218608 kb
Host smart-cd5ff15e-db49-4c42-9e76-08e4db250aea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786185328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.786185328
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.2265587811
Short name T161
Test name
Test status
Simulation time 479760055 ps
CPU time 18.04 seconds
Started May 07 12:36:28 PM PDT 24
Finished May 07 12:36:49 PM PDT 24
Peak memory 222608 kb
Host smart-0f8ad75a-eb35-485f-8846-276c74d4945b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265587811 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.2265587811
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.958108699
Short name T275
Test name
Test status
Simulation time 671359659 ps
CPU time 5.5 seconds
Started May 07 12:36:18 PM PDT 24
Finished May 07 12:36:26 PM PDT 24
Peak memory 207024 kb
Host smart-c6755144-5206-4e5d-b753-87b8ef94cfee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958108699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.958108699
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.697227518
Short name T745
Test name
Test status
Simulation time 168093706 ps
CPU time 4.41 seconds
Started May 07 12:36:20 PM PDT 24
Finished May 07 12:36:27 PM PDT 24
Peak memory 210576 kb
Host smart-c7c2b05f-8754-4dc1-a8e8-6ea537e1562c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697227518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.697227518
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.2116940768
Short name T870
Test name
Test status
Simulation time 155058999 ps
CPU time 0.8 seconds
Started May 07 12:37:00 PM PDT 24
Finished May 07 12:37:04 PM PDT 24
Peak memory 205880 kb
Host smart-689e59bb-7037-49a7-9700-6cdaf42cb35d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116940768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.2116940768
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.4291487460
Short name T402
Test name
Test status
Simulation time 103647926 ps
CPU time 2.3 seconds
Started May 07 12:36:44 PM PDT 24
Finished May 07 12:36:49 PM PDT 24
Peak memory 215216 kb
Host smart-d82f228e-1785-4f5f-81b6-b469c6770f70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4291487460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.4291487460
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.660942529
Short name T783
Test name
Test status
Simulation time 718515840 ps
CPU time 6.35 seconds
Started May 07 12:36:29 PM PDT 24
Finished May 07 12:36:37 PM PDT 24
Peak memory 208620 kb
Host smart-2e73c114-d448-4cb3-ba5f-2983e1a3d1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660942529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.660942529
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.2142347077
Short name T170
Test name
Test status
Simulation time 438530560 ps
CPU time 3.8 seconds
Started May 07 12:36:34 PM PDT 24
Finished May 07 12:36:39 PM PDT 24
Peak memory 214248 kb
Host smart-1871b1f0-e5ab-46b8-b18d-576b389ee458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142347077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.2142347077
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.742958551
Short name T834
Test name
Test status
Simulation time 85374655 ps
CPU time 2.52 seconds
Started May 07 12:36:43 PM PDT 24
Finished May 07 12:36:53 PM PDT 24
Peak memory 214264 kb
Host smart-388eb297-4a0d-4edc-bce3-a04b77354cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742958551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.742958551
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.162628034
Short name T323
Test name
Test status
Simulation time 166060296 ps
CPU time 3.07 seconds
Started May 07 12:36:47 PM PDT 24
Finished May 07 12:36:53 PM PDT 24
Peak memory 214260 kb
Host smart-95e84e48-7d6c-47b4-97a0-e26d0fa94816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162628034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.162628034
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.3534654356
Short name T668
Test name
Test status
Simulation time 134946948 ps
CPU time 2.43 seconds
Started May 07 12:36:47 PM PDT 24
Finished May 07 12:36:53 PM PDT 24
Peak memory 220124 kb
Host smart-bb3dd92d-51e6-4b98-81ba-344369c54f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534654356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.3534654356
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.1336844074
Short name T80
Test name
Test status
Simulation time 5629615069 ps
CPU time 38.41 seconds
Started May 07 12:36:24 PM PDT 24
Finished May 07 12:37:05 PM PDT 24
Peak memory 209256 kb
Host smart-d034285d-e722-42b4-9cc6-ed4b88875f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336844074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.1336844074
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.1534542942
Short name T654
Test name
Test status
Simulation time 1028105674 ps
CPU time 11.4 seconds
Started May 07 12:36:40 PM PDT 24
Finished May 07 12:36:52 PM PDT 24
Peak memory 208352 kb
Host smart-8426f205-b84c-4824-a19a-ad333f986001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534542942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.1534542942
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.3823924192
Short name T593
Test name
Test status
Simulation time 6264685666 ps
CPU time 59.01 seconds
Started May 07 12:36:38 PM PDT 24
Finished May 07 12:37:38 PM PDT 24
Peak memory 208824 kb
Host smart-f790d7f8-d5dc-4b27-9581-c931fda14715
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823924192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.3823924192
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.773588291
Short name T529
Test name
Test status
Simulation time 705110775 ps
CPU time 4.9 seconds
Started May 07 12:36:27 PM PDT 24
Finished May 07 12:36:34 PM PDT 24
Peak memory 207972 kb
Host smart-b47257f4-d1d6-4554-94c0-63e67e1accb8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773588291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.773588291
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.885621409
Short name T613
Test name
Test status
Simulation time 2275342020 ps
CPU time 15.22 seconds
Started May 07 12:36:29 PM PDT 24
Finished May 07 12:36:47 PM PDT 24
Peak memory 208856 kb
Host smart-78fe697e-87e4-4fcf-bc60-400eb929674e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885621409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.885621409
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.3181846387
Short name T576
Test name
Test status
Simulation time 1762879816 ps
CPU time 5.61 seconds
Started May 07 12:36:36 PM PDT 24
Finished May 07 12:36:43 PM PDT 24
Peak memory 207508 kb
Host smart-50f3f104-9b44-4b9c-930f-5f3691623d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181846387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.3181846387
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.2533031662
Short name T816
Test name
Test status
Simulation time 9971463704 ps
CPU time 33.06 seconds
Started May 07 12:36:26 PM PDT 24
Finished May 07 12:37:01 PM PDT 24
Peak memory 216176 kb
Host smart-7ff07b4e-6e86-4d14-863f-6b7cbb7bbed7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533031662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.2533031662
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.415265714
Short name T444
Test name
Test status
Simulation time 111583494 ps
CPU time 2.14 seconds
Started May 07 12:36:45 PM PDT 24
Finished May 07 12:36:50 PM PDT 24
Peak memory 207696 kb
Host smart-761a4a8d-3717-436f-b9b1-2e71adc86d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415265714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.415265714
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.2755155033
Short name T154
Test name
Test status
Simulation time 229684202 ps
CPU time 1.78 seconds
Started May 07 12:36:29 PM PDT 24
Finished May 07 12:36:33 PM PDT 24
Peak memory 209844 kb
Host smart-e05193f9-8762-45f2-95f2-7cb3033191c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755155033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.2755155033
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.4059688568
Short name T169
Test name
Test status
Simulation time 65612068 ps
CPU time 0.83 seconds
Started May 07 12:36:41 PM PDT 24
Finished May 07 12:36:44 PM PDT 24
Peak memory 205876 kb
Host smart-f496ae77-9a22-4d58-8190-32b6d753100d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059688568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.4059688568
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.2914685494
Short name T645
Test name
Test status
Simulation time 589657106 ps
CPU time 11.26 seconds
Started May 07 12:36:40 PM PDT 24
Finished May 07 12:36:52 PM PDT 24
Peak memory 210756 kb
Host smart-dfca1851-1daf-4195-b183-2eb3c8a31c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914685494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.2914685494
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.568076028
Short name T792
Test name
Test status
Simulation time 557513649 ps
CPU time 4.76 seconds
Started May 07 12:36:53 PM PDT 24
Finished May 07 12:37:00 PM PDT 24
Peak memory 218296 kb
Host smart-5dd5b21e-cfae-4df0-bc2d-4ffeb8fb7ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568076028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.568076028
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.568369597
Short name T247
Test name
Test status
Simulation time 164213957 ps
CPU time 3.64 seconds
Started May 07 12:36:39 PM PDT 24
Finished May 07 12:36:44 PM PDT 24
Peak memory 214316 kb
Host smart-f1d17bcd-8b37-4e2f-93b5-e0243b749463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568369597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.568369597
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.4087324876
Short name T860
Test name
Test status
Simulation time 47272180 ps
CPU time 1.94 seconds
Started May 07 12:36:44 PM PDT 24
Finished May 07 12:36:48 PM PDT 24
Peak memory 220204 kb
Host smart-585422df-46ca-41ac-b5de-6b6d5f71ea36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087324876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.4087324876
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.2085913988
Short name T762
Test name
Test status
Simulation time 123188324 ps
CPU time 5.5 seconds
Started May 07 12:36:46 PM PDT 24
Finished May 07 12:36:55 PM PDT 24
Peak memory 210100 kb
Host smart-c7af8614-190a-43d0-9f30-0f3c79da367a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085913988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.2085913988
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.1780531118
Short name T196
Test name
Test status
Simulation time 208435921 ps
CPU time 3.59 seconds
Started May 07 12:37:05 PM PDT 24
Finished May 07 12:37:10 PM PDT 24
Peak memory 214212 kb
Host smart-9d498b57-18c0-44c6-b3b0-f5512e58c81e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780531118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.1780531118
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.1901353065
Short name T313
Test name
Test status
Simulation time 64125283 ps
CPU time 3.15 seconds
Started May 07 12:36:52 PM PDT 24
Finished May 07 12:36:58 PM PDT 24
Peak memory 208480 kb
Host smart-4fc4a46f-075c-4465-ab45-89c43125c91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901353065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.1901353065
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.2749009061
Short name T386
Test name
Test status
Simulation time 568907985 ps
CPU time 14.57 seconds
Started May 07 12:36:32 PM PDT 24
Finished May 07 12:36:47 PM PDT 24
Peak memory 208876 kb
Host smart-a31cdfa9-b6d9-409b-b8f4-2af00f072751
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749009061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.2749009061
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.3292276275
Short name T726
Test name
Test status
Simulation time 171942289 ps
CPU time 2.69 seconds
Started May 07 12:36:36 PM PDT 24
Finished May 07 12:36:40 PM PDT 24
Peak memory 208764 kb
Host smart-cc4e382b-ea1c-43c6-be96-92c0f7715649
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292276275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.3292276275
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.3530697831
Short name T564
Test name
Test status
Simulation time 22269527 ps
CPU time 1.76 seconds
Started May 07 12:36:44 PM PDT 24
Finished May 07 12:36:49 PM PDT 24
Peak memory 206928 kb
Host smart-c5e8bec4-59e5-42e2-ba98-e53377c32b28
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530697831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.3530697831
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.2497306567
Short name T827
Test name
Test status
Simulation time 50939574 ps
CPU time 2.38 seconds
Started May 07 12:36:44 PM PDT 24
Finished May 07 12:36:50 PM PDT 24
Peak memory 218324 kb
Host smart-4e1f2e29-b10b-4794-94a1-4d2b35928643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497306567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.2497306567
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.1810316666
Short name T606
Test name
Test status
Simulation time 36046490545 ps
CPU time 42.83 seconds
Started May 07 12:37:02 PM PDT 24
Finished May 07 12:37:46 PM PDT 24
Peak memory 208896 kb
Host smart-88028dc3-f4a2-4c0e-8e5d-ce4365141328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810316666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.1810316666
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.2699435748
Short name T261
Test name
Test status
Simulation time 905403575 ps
CPU time 30.7 seconds
Started May 07 12:36:39 PM PDT 24
Finished May 07 12:37:11 PM PDT 24
Peak memory 218600 kb
Host smart-2ccc5d1a-f287-40b0-8e03-096b49416c7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699435748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.2699435748
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.237970176
Short name T186
Test name
Test status
Simulation time 107093255 ps
CPU time 2.88 seconds
Started May 07 12:36:51 PM PDT 24
Finished May 07 12:36:57 PM PDT 24
Peak memory 207840 kb
Host smart-60691220-1e5a-44d8-99e9-154e474827c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237970176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.237970176
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.3197564974
Short name T471
Test name
Test status
Simulation time 43091637 ps
CPU time 0.89 seconds
Started May 07 12:36:43 PM PDT 24
Finished May 07 12:36:47 PM PDT 24
Peak memory 205896 kb
Host smart-7a2427f5-101a-4984-ab77-b6d8e65d9eb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197564974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.3197564974
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.2609644309
Short name T220
Test name
Test status
Simulation time 138444861 ps
CPU time 4.19 seconds
Started May 07 12:36:43 PM PDT 24
Finished May 07 12:36:50 PM PDT 24
Peak memory 214240 kb
Host smart-cabe57e8-03e0-4570-8747-28a64c6057d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2609644309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.2609644309
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.2545983553
Short name T30
Test name
Test status
Simulation time 61433067 ps
CPU time 3.12 seconds
Started May 07 12:36:46 PM PDT 24
Finished May 07 12:36:52 PM PDT 24
Peak memory 219128 kb
Host smart-aa85633e-d2d2-4182-8f72-54dd10dd2bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545983553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.2545983553
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.2668314751
Short name T228
Test name
Test status
Simulation time 95140787 ps
CPU time 2.01 seconds
Started May 07 12:36:54 PM PDT 24
Finished May 07 12:36:58 PM PDT 24
Peak memory 214276 kb
Host smart-4b128483-dc39-465f-a573-d15e5535bbd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668314751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.2668314751
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.2289072388
Short name T876
Test name
Test status
Simulation time 58515845 ps
CPU time 3.12 seconds
Started May 07 12:36:46 PM PDT 24
Finished May 07 12:36:57 PM PDT 24
Peak memory 214204 kb
Host smart-4af69d3d-6ea0-4baa-b96c-114c44201885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289072388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.2289072388
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.1146906158
Short name T282
Test name
Test status
Simulation time 182517529 ps
CPU time 4.43 seconds
Started May 07 12:36:56 PM PDT 24
Finished May 07 12:37:02 PM PDT 24
Peak memory 214128 kb
Host smart-1b7da039-b65c-4c4e-af6d-2d27cc3b51d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146906158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.1146906158
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_random.2157539398
Short name T735
Test name
Test status
Simulation time 1042893186 ps
CPU time 7.79 seconds
Started May 07 12:36:44 PM PDT 24
Finished May 07 12:36:54 PM PDT 24
Peak memory 209108 kb
Host smart-1c928433-d48e-481c-8596-3135244cac8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157539398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.2157539398
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.4001395634
Short name T760
Test name
Test status
Simulation time 55044158 ps
CPU time 2.23 seconds
Started May 07 12:36:37 PM PDT 24
Finished May 07 12:36:40 PM PDT 24
Peak memory 206836 kb
Host smart-43213b0e-9c13-4986-8515-e3eac4b736d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001395634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.4001395634
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.1961283576
Short name T889
Test name
Test status
Simulation time 1367004112 ps
CPU time 11.97 seconds
Started May 07 12:36:26 PM PDT 24
Finished May 07 12:36:41 PM PDT 24
Peak memory 209076 kb
Host smart-2075b6d9-0ccc-45e8-9950-c87c186ec2a6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961283576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.1961283576
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.3766335771
Short name T429
Test name
Test status
Simulation time 188020751 ps
CPU time 3.31 seconds
Started May 07 12:36:37 PM PDT 24
Finished May 07 12:36:42 PM PDT 24
Peak memory 206880 kb
Host smart-2c3249b6-6694-4bf7-82db-7f9cd2a0a065
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766335771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.3766335771
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.1282105769
Short name T465
Test name
Test status
Simulation time 663392118 ps
CPU time 3.41 seconds
Started May 07 12:36:49 PM PDT 24
Finished May 07 12:36:55 PM PDT 24
Peak memory 208776 kb
Host smart-e2433a25-07cd-422c-915a-9de3518ab7a1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282105769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.1282105769
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.3189177756
Short name T839
Test name
Test status
Simulation time 111312242 ps
CPU time 2.31 seconds
Started May 07 12:36:51 PM PDT 24
Finished May 07 12:36:56 PM PDT 24
Peak memory 207532 kb
Host smart-35e3168e-0aec-4de5-b32b-852d39aaa06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189177756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.3189177756
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.1553339669
Short name T875
Test name
Test status
Simulation time 872535917 ps
CPU time 9.05 seconds
Started May 07 12:36:53 PM PDT 24
Finished May 07 12:37:04 PM PDT 24
Peak memory 208484 kb
Host smart-f5d76878-dba6-49e1-8d23-42a31f4398b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553339669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.1553339669
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.2956541277
Short name T286
Test name
Test status
Simulation time 1853582518 ps
CPU time 7.37 seconds
Started May 07 12:36:45 PM PDT 24
Finished May 07 12:36:55 PM PDT 24
Peak memory 209988 kb
Host smart-d75a1385-357a-47fd-b929-77bad3926e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956541277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.2956541277
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.826335424
Short name T617
Test name
Test status
Simulation time 53268066 ps
CPU time 1.86 seconds
Started May 07 12:36:42 PM PDT 24
Finished May 07 12:36:45 PM PDT 24
Peak memory 209852 kb
Host smart-cf5fcfce-d286-4fc5-81f1-b93104fb8a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826335424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.826335424
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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