Summary for Variable op_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
5 |
1 |
4 |
80.00 |
Automatically Generated Bins for op_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
auto[OpDisable] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[OpAdvance] |
47 |
1 |
|
|
T14 |
2 |
|
T27 |
1 |
|
T20 |
1 |
auto[OpGenId] |
10 |
1 |
|
|
T36 |
1 |
|
T4 |
1 |
|
T8 |
1 |
auto[OpGenSwOut] |
17 |
1 |
|
|
T4 |
1 |
|
T49 |
1 |
|
T127 |
1 |
auto[OpGenHwOut] |
15 |
1 |
|
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable state_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
7 |
0 |
7 |
100.00 |
Automatically Generated Bins for state_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[StReset] |
1797 |
1 |
|
|
T14 |
2 |
|
T36 |
1 |
|
T46 |
2 |
auto[StInit] |
80 |
1 |
|
|
T14 |
1 |
|
T19 |
1 |
|
T27 |
1 |
auto[StCreatorRootKey] |
53 |
1 |
|
|
T37 |
1 |
|
T7 |
1 |
|
T38 |
1 |
auto[StOwnerIntKey] |
39 |
1 |
|
|
T13 |
1 |
|
T52 |
1 |
|
T56 |
1 |
auto[StOwnerKey] |
35 |
1 |
|
|
T1 |
1 |
|
T46 |
1 |
|
T39 |
1 |
auto[StDisabled] |
508 |
1 |
|
|
T14 |
9 |
|
T27 |
8 |
|
T46 |
6 |
auto[StInvalid] |
50 |
1 |
|
|
T41 |
1 |
|
T47 |
1 |
|
T43 |
1 |
Summary for Variable wip_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wip_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
3557 |
1 |
|
|
T1 |
2 |
|
T2 |
1 |
|
T3 |
1 |
auto[1] |
89 |
1 |
|
|
T14 |
2 |
|
T27 |
1 |
|
T20 |
1 |
Summary for Cross state_x_wip_cross
Samples crossed: state_cp wip_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
14 |
1 |
13 |
92.86 |
1 |
Automatically Generated Cross Bins for state_x_wip_cross
Uncovered bins
state_cp | wip_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[StInvalid]] |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
state_cp | wip_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[StReset] |
auto[0] |
1790 |
1 |
|
|
T14 |
1 |
|
T46 |
2 |
|
T63 |
5 |
auto[StReset] |
auto[1] |
7 |
1 |
|
|
T14 |
1 |
|
T36 |
1 |
|
T60 |
1 |
auto[StInit] |
auto[0] |
38 |
1 |
|
|
T19 |
1 |
|
T102 |
1 |
|
T29 |
1 |
auto[StInit] |
auto[1] |
42 |
1 |
|
|
T14 |
1 |
|
T27 |
1 |
|
T20 |
1 |
auto[StCreatorRootKey] |
auto[0] |
41 |
1 |
|
|
T37 |
1 |
|
T38 |
1 |
|
T35 |
1 |
auto[StCreatorRootKey] |
auto[1] |
12 |
1 |
|
|
T7 |
1 |
|
T49 |
1 |
|
T208 |
1 |
auto[StOwnerIntKey] |
auto[0] |
32 |
1 |
|
|
T13 |
1 |
|
T52 |
1 |
|
T56 |
1 |
auto[StOwnerIntKey] |
auto[1] |
7 |
1 |
|
|
T57 |
1 |
|
T209 |
1 |
|
T71 |
1 |
auto[StOwnerKey] |
auto[0] |
25 |
1 |
|
|
T1 |
1 |
|
T46 |
1 |
|
T39 |
1 |
auto[StOwnerKey] |
auto[1] |
10 |
1 |
|
|
T4 |
1 |
|
T49 |
1 |
|
T59 |
1 |
auto[StDisabled] |
auto[0] |
497 |
1 |
|
|
T14 |
9 |
|
T27 |
8 |
|
T46 |
6 |
auto[StDisabled] |
auto[1] |
11 |
1 |
|
|
T4 |
1 |
|
T42 |
1 |
|
T127 |
1 |
auto[StInvalid] |
auto[0] |
50 |
1 |
|
|
T41 |
1 |
|
T47 |
1 |
|
T43 |
1 |
Summary for Cross state_x_op_cross
Samples crossed: state_cp op_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
35 |
13 |
22 |
62.86 |
13 |
Automatically Generated Cross Bins for state_x_op_cross
Element holes
state_cp | op_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[StInvalid]] |
* |
-- |
-- |
5 |
|
Uncovered bins
state_cp | op_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[StReset] , auto[StInit]] |
[auto[OpDisable]] |
-- |
-- |
2 |
|
[auto[StCreatorRootKey]] |
[auto[OpGenId]] |
0 |
1 |
1 |
|
[auto[StCreatorRootKey]] |
[auto[OpDisable]] |
0 |
1 |
1 |
|
[auto[StOwnerIntKey]] |
[auto[OpDisable]] |
0 |
1 |
1 |
|
[auto[StOwnerKey]] |
[auto[OpGenHwOut] , auto[OpDisable]] |
-- |
-- |
2 |
|
[auto[StDisabled]] |
[auto[OpDisable]] |
0 |
1 |
1 |
|
Covered bins
state_cp | op_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[StReset] |
auto[OpAdvance] |
4 |
1 |
|
|
T14 |
1 |
|
T44 |
1 |
|
T210 |
1 |
auto[StReset] |
auto[OpGenId] |
1 |
1 |
|
|
T36 |
1 |
|
- |
- |
|
- |
- |
auto[StReset] |
auto[OpGenSwOut] |
1 |
1 |
|
|
T60 |
1 |
|
- |
- |
|
- |
- |
auto[StReset] |
auto[OpGenHwOut] |
1 |
1 |
|
|
T33 |
1 |
|
- |
- |
|
- |
- |
auto[StInit] |
auto[OpAdvance] |
22 |
1 |
|
|
T14 |
1 |
|
T27 |
1 |
|
T20 |
1 |
auto[StInit] |
auto[OpGenId] |
4 |
1 |
|
|
T8 |
1 |
|
T211 |
1 |
|
T212 |
1 |
auto[StInit] |
auto[OpGenSwOut] |
6 |
1 |
|
|
T213 |
1 |
|
T214 |
1 |
|
T51 |
1 |
auto[StInit] |
auto[OpGenHwOut] |
10 |
1 |
|
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
1 |
auto[StCreatorRootKey] |
auto[OpAdvance] |
7 |
1 |
|
|
T7 |
1 |
|
T208 |
1 |
|
T71 |
1 |
auto[StCreatorRootKey] |
auto[OpGenSwOut] |
4 |
1 |
|
|
T49 |
1 |
|
T215 |
1 |
|
T216 |
1 |
auto[StCreatorRootKey] |
auto[OpGenHwOut] |
1 |
1 |
|
|
T217 |
1 |
|
- |
- |
|
- |
- |
auto[StOwnerIntKey] |
auto[OpAdvance] |
4 |
1 |
|
|
T57 |
1 |
|
T71 |
1 |
|
T190 |
1 |
auto[StOwnerIntKey] |
auto[OpGenId] |
1 |
1 |
|
|
T218 |
1 |
|
- |
- |
|
- |
- |
auto[StOwnerIntKey] |
auto[OpGenSwOut] |
1 |
1 |
|
|
T209 |
1 |
|
- |
- |
|
- |
- |
auto[StOwnerIntKey] |
auto[OpGenHwOut] |
1 |
1 |
|
|
T219 |
1 |
|
- |
- |
|
- |
- |
auto[StOwnerKey] |
auto[OpAdvance] |
6 |
1 |
|
|
T49 |
1 |
|
T59 |
1 |
|
T220 |
1 |
auto[StOwnerKey] |
auto[OpGenId] |
2 |
1 |
|
|
T4 |
1 |
|
T221 |
1 |
|
- |
- |
auto[StOwnerKey] |
auto[OpGenSwOut] |
2 |
1 |
|
|
T222 |
1 |
|
T189 |
1 |
|
- |
- |
auto[StDisabled] |
auto[OpAdvance] |
4 |
1 |
|
|
T42 |
1 |
|
T223 |
1 |
|
T124 |
1 |
auto[StDisabled] |
auto[OpGenId] |
2 |
1 |
|
|
T222 |
1 |
|
T221 |
1 |
|
- |
- |
auto[StDisabled] |
auto[OpGenSwOut] |
3 |
1 |
|
|
T4 |
1 |
|
T127 |
1 |
|
T135 |
1 |
auto[StDisabled] |
auto[OpGenHwOut] |
2 |
1 |
|
|
T224 |
1 |
|
T225 |
1 |
|
- |
- |