Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11158

1

T1

4

T2

14

T3

9

auto[Attestation]

8200

1

T1

5

T2

10

T3

5

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2840	1			T1	3		T2	2		T3	2
auto[Aes]	3361	1			T2	7		T3	1		T13	1
auto[Kmac]	3541	1			T1	3		T2	5		T3	3
auto[Otbn]	3423	1			T2	4		T3	1		T14	26

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	8006	1			T1	4		T2	8		T3	8
auto[OpGenId]	6193	1			T1	3		T2	6		T3	7
auto[OpGenSwOut]	6064	1			T1	3		T2	12		T3	5
auto[OpGenHwOut]	7101	1			T1	3		T2	6		T3	2
auto[OpDisable]	147	1			T14	1		T34	1		T27	2

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

11072

1

T1

10

T2

13

T3

8

auto[OpDoneFail]

16439

1

T1

3

T2

19

T3

14

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6284	1			T1	1		T2	1		T3	7
auto[StInit]	3823	1			T1	4		T2	5		T3	2
auto[StCreatorRootKey]	3253	1			T1	4		T2	6		T3	2
auto[StOwnerIntKey]	2932	1			T1	4		T2	3		T3	2
auto[StOwnerKey]	2617	1			T2	3		T3	2		T14	33
auto[StDisabled]	8602	1			T2	14		T3	7		T14	106

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	300	1			T14	3		T19	1		T27	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	102	1			T1	1		T13	1		T14	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	91	1			T46	3		T37	1		T196	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	67	1			T14	1		T15	1		T81	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	74	1			T27	1		T197	1		T48	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	245	1			T14	1		T15	2		T27	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	293	1			T14	1		T19	1		T27	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	109	1			T27	2		T79	1		T81	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	87	1			T14	1		T46	1		T35	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	77	1			T14	2		T15	1		T63	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	63	1			T14	2		T27	1		T110	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	233	1			T2	1		T14	2		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	304	1			T3	2		T14	3		T16	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	106	1			T2	1		T3	1		T34	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	94	1			T2	2		T14	1		T27	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	73	1			T14	1		T46	1		T198	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	70	1			T14	2		T27	1		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	225	1			T2	2		T14	4		T27	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	274	1			T14	2		T19	1		T27	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	110	1			T2	1		T14	1		T27	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	88	1			T63	1		T49	2		T100	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	82	1			T14	3		T46	1		T199	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	55	1			T2	1		T46	1		T110	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	237	1			T14	3		T27	2		T81	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	87	1			T46	2		T48	4		T4	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	92	1			T46	1		T24	1		T75	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	67	1			T197	1		T200	1		T7	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	86	1			T1	1		T27	1		T63	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	65	1			T14	2		T81	1		T120	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	249	1			T2	1		T3	1		T14	5
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	80	1			T14	1		T46	1		T63	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	108	1			T13	1		T14	1		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	80	1			T14	1		T27	4		T38	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	68	1			T14	1		T34	1		T63	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	74	1			T2	1		T63	1		T61	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	226	1			T2	2		T3	1		T14	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	85	1			T14	1		T46	4		T4	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	119	1			T1	1		T27	1		T46	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	80	1			T14	2		T48	3		T100	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	74	1			T14	1		T46	1		T48	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	74	1			T14	1		T110	1		T4	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	252	1			T14	2		T15	1		T27	4
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	111	1			T46	1		T58	1		T49	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	110	1			T19	1		T27	1		T46	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	78	1			T14	1		T134	1		T79	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	70	1			T14	2		T48	1		T4	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	61	1			T79	1		T48	1		T201	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	209	1			T14	5		T27	2		T200	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	254	1			T3	1		T14	1		T27	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	115	1			T14	1		T202	1		T63	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	52	1			T14	4		T27	1		T134	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	72	1			T1	1		T14	1		T46	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	63	1			T14	1		T15	1		T27	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	219	1			T14	2		T34	1		T27	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	402	1			T16	1		T27	3		T46	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	111	1			T63	1		T61	1		T48	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	104	1			T34	1		T27	2		T134	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	100	1			T2	1		T79	1		T46	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	105	1			T14	2		T27	1		T63	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	302	1			T2	1		T14	4		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	391	1			T14	1		T16	1		T17	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	116	1			T14	6		T17	1		T80	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	143	1			T17	1		T27	1		T134	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	95	1			T1	1		T17	1		T34	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	95	1			T14	1		T17	1		T27	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	334	1			T14	7		T15	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	456	1			T16	1		T19	1		T27	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	115	1			T27	1		T46	1		T63	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	120	1			T27	1		T7	1		T39	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	110	1			T81	1		T198	1		T199	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	74	1			T14	1		T81	1		T63	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	283	1			T2	1		T14	1		T15	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	73	1			T14	1		T63	1		T48	4
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	80	1			T14	1		T27	1		T199	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	94	1			T14	1		T196	1		T199	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	63	1			T27	2		T79	1		T199	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	51	1			T14	1		T202	1		T4	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	179	1			T2	1		T14	3		T34	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	64	1			T14	2		T63	2		T49	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	104	1			T14	1		T134	1		T198	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	107	1			T2	1		T134	1		T46	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	102	1			T79	1		T197	1		T48	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	83	1			T14	3		T48	1		T77	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	279	1			T14	8		T15	1		T27	4
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	80	1			T27	4		T48	2		T4	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	114	1			T1	1		T14	1		T203	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	117	1			T13	1		T27	1		T134	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	109	1			T14	1		T27	1		T80	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	108	1			T14	2		T46	1		T204	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	283	1			T14	5		T17	3		T27	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	81	1			T14	3		T27	1		T63	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	124	1			T2	1		T14	1		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	101	1			T14	1		T15	1		T134	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	95	1			T3	1		T27	1		T202	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	90	1			T14	1		T27	1		T79	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	289	1			T14	1		T27	3		T81	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	219	1			T14	1		T15	1		T27	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	660	1			T1	1		T13	1		T14	5
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	209	1			T14	4		T15	1		T27	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	653	1			T2	1		T14	4		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	216	1			T2	2		T14	3		T27	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	656	1			T2	3		T3	3		T14	8
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	207	1			T2	1		T14	3		T46	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	639	1			T2	1		T14	6		T19	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	197	1			T1	1		T14	2		T27	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	449	1			T2	1		T3	1		T14	5
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	203	1			T2	1		T14	1		T34	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	433	1			T2	2		T3	1		T13	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	207	1			T14	1		T46	1		T110	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	477	1			T1	1		T14	6		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	195	1			T14	3		T134	1		T79	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	444	1			T14	5		T19	1		T27	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	173	1			T1	1		T14	5		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	602	1			T3	1		T14	5		T34	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	291	1			T2	1		T14	1		T34	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	833	1			T2	1		T14	5		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	322	1			T1	1		T14	1		T17	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	852	1			T14	14		T15	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	287	1			T14	1		T27	1		T81	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	871	1			T2	1		T14	1		T15	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	191	1			T14	2		T27	1		T79	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	349	1			T2	1		T14	5		T34	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	276	1			T14	3		T134	1		T79	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	463	1			T2	1		T14	11		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	318	1			T13	1		T14	3		T27	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	493	1			T1	1		T14	6		T17	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	266	1			T3	1		T14	2		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	514	1			T2	1		T14	5		T15	1