Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33711

1

T1

13

T2

37

T3

27

auto[1]

231

1

T81

3

T110

3

T263

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	33716	1			T1	13		T2	37		T3	27
auto[134217728:268435455]	10	1			T226	1		T355	1		T271	1
auto[268435456:402653183]	4	1			T81	1		T271	1		T356	1
auto[402653184:536870911]	10	1			T81	1		T226	1		T251	1
auto[536870912:671088639]	8	1			T277	1		T251	1		T380	1
auto[671088640:805306367]	5	1			T369	1		T381	1		T321	1
auto[805306368:939524095]	5	1			T226	1		T137	1		T382	1
auto[939524096:1073741823]	9	1			T367	1		T273	1		T276	1
auto[1073741824:1207959551]	10	1			T226	1		T356	1		T370	1
auto[1207959552:1342177279]	3	1			T383	1		T384	1		T385	1
auto[1342177280:1476395007]	7	1			T226	1		T386	1		T368	1
auto[1476395008:1610612735]	8	1			T138	1		T355	1		T319	1
auto[1610612736:1744830463]	8	1			T138	1		T251	2		T276	1
auto[1744830464:1879048191]	4	1			T367	1		T251	1		T356	1
auto[1879048192:2013265919]	7	1			T277	1		T271	1		T369	1
auto[2013265920:2147483647]	8	1			T367	1		T271	1		T321	1
auto[2147483648:2281701375]	11	1			T110	1		T263	1		T251	1
auto[2281701376:2415919103]	5	1			T251	1		T355	2		T387	1
auto[2415919104:2550136831]	7	1			T110	1		T226	2		T242	2
auto[2550136832:2684354559]	9	1			T137	1		T138	1		T251	1
auto[2684354560:2818572287]	13	1			T81	1		T110	1		T277	1
auto[2818572288:2952790015]	11	1			T226	1		T355	1		T370	1
auto[2952790016:3087007743]	9	1			T260	1		T371	1		T369	1
auto[3087007744:3221225471]	9	1			T226	1		T138	1		T356	1
auto[3221225472:3355443199]	1	1			T137	1		-	-		-	-
auto[3355443200:3489660927]	4	1			T273	1		T319	1		T381	1
auto[3489660928:3623878655]	7	1			T276	1		T334	1		T388	3
auto[3623878656:3758096383]	3	1			T367	1		T371	1		T384	1
auto[3758096384:3892314111]	8	1			T263	1		T356	1		T260	1
auto[3892314112:4026531839]	7	1			T355	1		T370	1		T285	1
auto[4026531840:4160749567]	7	1			T226	1		T355	1		T370	1
auto[4160749568:4294967295]	9	1			T355	1		T276	1		T271	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	33711	1			T1	13		T2	37		T3	27
auto[0:134217727]	auto[1]	5	1			T137	1		T355	1		T271	1
auto[134217728:268435455]	auto[1]	10	1			T226	1		T355	1		T271	1
auto[268435456:402653183]	auto[1]	4	1			T81	1		T271	1		T356	1
auto[402653184:536870911]	auto[1]	10	1			T81	1		T226	1		T251	1
auto[536870912:671088639]	auto[1]	8	1			T277	1		T251	1		T380	1
auto[671088640:805306367]	auto[1]	5	1			T369	1		T381	1		T321	1
auto[805306368:939524095]	auto[1]	5	1			T226	1		T137	1		T382	1
auto[939524096:1073741823]	auto[1]	9	1			T367	1		T273	1		T276	1
auto[1073741824:1207959551]	auto[1]	10	1			T226	1		T356	1		T370	1
auto[1207959552:1342177279]	auto[1]	3	1			T383	1		T384	1		T385	1
auto[1342177280:1476395007]	auto[1]	7	1			T226	1		T386	1		T368	1
auto[1476395008:1610612735]	auto[1]	8	1			T138	1		T355	1		T319	1
auto[1610612736:1744830463]	auto[1]	8	1			T138	1		T251	2		T276	1
auto[1744830464:1879048191]	auto[1]	4	1			T367	1		T251	1		T356	1
auto[1879048192:2013265919]	auto[1]	7	1			T277	1		T271	1		T369	1
auto[2013265920:2147483647]	auto[1]	8	1			T367	1		T271	1		T321	1
auto[2147483648:2281701375]	auto[1]	11	1			T110	1		T263	1		T251	1
auto[2281701376:2415919103]	auto[1]	5	1			T251	1		T355	2		T387	1
auto[2415919104:2550136831]	auto[1]	7	1			T110	1		T226	2		T242	2
auto[2550136832:2684354559]	auto[1]	9	1			T137	1		T138	1		T251	1
auto[2684354560:2818572287]	auto[1]	13	1			T81	1		T110	1		T277	1
auto[2818572288:2952790015]	auto[1]	11	1			T226	1		T355	1		T370	1
auto[2952790016:3087007743]	auto[1]	9	1			T260	1		T371	1		T369	1
auto[3087007744:3221225471]	auto[1]	9	1			T226	1		T138	1		T356	1
auto[3221225472:3355443199]	auto[1]	1	1			T137	1		-	-		-	-
auto[3355443200:3489660927]	auto[1]	4	1			T273	1		T319	1		T381	1
auto[3489660928:3623878655]	auto[1]	7	1			T276	1		T334	1		T388	3
auto[3623878656:3758096383]	auto[1]	3	1			T367	1		T371	1		T384	1
auto[3758096384:3892314111]	auto[1]	8	1			T263	1		T356	1		T260	1
auto[3892314112:4026531839]	auto[1]	7	1			T355	1		T370	1		T285	1
auto[4026531840:4160749567]	auto[1]	7	1			T226	1		T355	1		T370	1
auto[4160749568:4294967295]	auto[1]	9	1			T355	1		T276	1		T271	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1658

1

T1

1

T2

1

T14

22

auto[1]

1817

1

T1

3

T2

4

T14

21

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	114	1			T14	1		T27	2		T20	1
auto[134217728:268435455]	108	1			T14	1		T27	3		T81	1
auto[268435456:402653183]	118	1			T2	1		T14	1		T16	1
auto[402653184:536870911]	108	1			T14	1		T27	1		T120	1
auto[536870912:671088639]	92	1			T1	1		T63	1		T47	1
auto[671088640:805306367]	134	1			T14	4		T81	1		T46	1
auto[805306368:939524095]	110	1			T27	2		T79	2		T198	1
auto[939524096:1073741823]	131	1			T14	3		T15	1		T34	1
auto[1073741824:1207959551]	113	1			T2	1		T14	2		T15	1
auto[1207959552:1342177279]	113	1			T14	3		T27	2		T46	2
auto[1342177280:1476395007]	101	1			T14	2		T81	1		T46	1
auto[1476395008:1610612735]	107	1			T14	1		T41	1		T27	1
auto[1610612736:1744830463]	109	1			T14	1		T16	1		T27	1
auto[1744830464:1879048191]	110	1			T14	2		T15	1		T37	1
auto[1879048192:2013265919]	105	1			T14	1		T16	1		T81	1
auto[2013265920:2147483647]	111	1			T1	2		T16	1		T41	2
auto[2147483648:2281701375]	105	1			T14	1		T27	2		T20	1
auto[2281701376:2415919103]	110	1			T14	1		T15	1		T27	1
auto[2415919104:2550136831]	100	1			T14	1		T79	1		T36	1
auto[2550136832:2684354559]	115	1			T14	1		T16	1		T27	3
auto[2684354560:2818572287]	103	1			T14	2		T34	1		T81	1
auto[2818572288:2952790015]	96	1			T2	2		T14	1		T27	1
auto[2952790016:3087007743]	82	1			T14	3		T27	2		T36	1
auto[3087007744:3221225471]	102	1			T2	1		T14	1		T197	1
auto[3221225472:3355443199]	96	1			T15	1		T37	1		T63	2
auto[3355443200:3489660927]	115	1			T14	1		T198	1		T120	1
auto[3489660928:3623878655]	107	1			T27	1		T46	2		T198	1
auto[3623878656:3758096383]	111	1			T14	1		T27	1		T52	1
auto[3758096384:3892314111]	116	1			T1	1		T14	4		T27	1
auto[3892314112:4026531839]	105	1			T7	1		T199	1		T110	1
auto[4026531840:4160749567]	111	1			T14	1		T46	2		T63	2
auto[4160749568:4294967295]	117	1			T14	2		T15	1		T27	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	48	1			T14	1		T27	1		T20	1
auto[0:134217727]	auto[1]	66	1			T27	1		T81	1		T46	1
auto[134217728:268435455]	auto[0]	56	1			T27	2		T81	1		T46	1
auto[134217728:268435455]	auto[1]	52	1			T14	1		T27	1		T46	1
auto[268435456:402653183]	auto[0]	56	1			T16	1		T53	1		T120	1
auto[268435456:402653183]	auto[1]	62	1			T2	1		T14	1		T27	1
auto[402653184:536870911]	auto[0]	48	1			T27	1		T63	1		T61	1
auto[402653184:536870911]	auto[1]	60	1			T14	1		T120	1		T58	1
auto[536870912:671088639]	auto[0]	41	1			T63	1		T47	1		T100	1
auto[536870912:671088639]	auto[1]	51	1			T1	1		T49	1		T228	1
auto[671088640:805306367]	auto[0]	57	1			T63	1		T47	1		T49	1
auto[671088640:805306367]	auto[1]	77	1			T14	4		T81	1		T46	1
auto[805306368:939524095]	auto[0]	53	1			T27	1		T48	1		T353	1
auto[805306368:939524095]	auto[1]	57	1			T27	1		T79	2		T198	1
auto[939524096:1073741823]	auto[0]	69	1			T14	2		T27	1		T46	1
auto[939524096:1073741823]	auto[1]	62	1			T14	1		T15	1		T34	1
auto[1073741824:1207959551]	auto[0]	48	1			T14	2		T15	1		T81	1
auto[1073741824:1207959551]	auto[1]	65	1			T2	1		T48	1		T122	1
auto[1207959552:1342177279]	auto[0]	55	1			T14	2		T46	1		T48	1
auto[1207959552:1342177279]	auto[1]	58	1			T14	1		T27	2		T46	1
auto[1342177280:1476395007]	auto[0]	46	1			T14	2		T52	1		T110	1
auto[1342177280:1476395007]	auto[1]	55	1			T81	1		T46	1		T48	2
auto[1476395008:1610612735]	auto[0]	60	1			T14	1		T41	1		T79	1
auto[1476395008:1610612735]	auto[1]	47	1			T27	1		T46	1		T61	1
auto[1610612736:1744830463]	auto[0]	56	1			T14	1		T16	1		T27	1
auto[1610612736:1744830463]	auto[1]	53	1			T46	1		T7	1		T61	1
auto[1744830464:1879048191]	auto[0]	52	1			T14	2		T15	1		T37	1
auto[1744830464:1879048191]	auto[1]	58	1			T63	1		T48	2		T4	1
auto[1879048192:2013265919]	auto[0]	51	1			T14	1		T16	1		T66	1
auto[1879048192:2013265919]	auto[1]	54	1			T81	1		T46	2		T110	1
auto[2013265920:2147483647]	auto[0]	54	1			T16	1		T41	1		T49	1
auto[2013265920:2147483647]	auto[1]	57	1			T1	2		T41	1		T199	1
auto[2147483648:2281701375]	auto[0]	47	1			T14	1		T197	1		T63	1
auto[2147483648:2281701375]	auto[1]	58	1			T27	2		T20	1		T46	1
auto[2281701376:2415919103]	auto[0]	53	1			T14	1		T4	1		T236	1
auto[2281701376:2415919103]	auto[1]	57	1			T15	1		T27	1		T110	1
auto[2415919104:2550136831]	auto[0]	45	1			T79	1		T24	1		T4	1
auto[2415919104:2550136831]	auto[1]	55	1			T14	1		T36	1		T46	1
auto[2550136832:2684354559]	auto[0]	49	1			T16	1		T27	1		T53	1
auto[2550136832:2684354559]	auto[1]	66	1			T14	1		T27	2		T46	1
auto[2684354560:2818572287]	auto[0]	44	1			T81	1		T46	1		T63	1
auto[2684354560:2818572287]	auto[1]	59	1			T14	2		T34	1		T198	1
auto[2818572288:2952790015]	auto[0]	40	1			T2	1		T48	2		T49	1
auto[2818572288:2952790015]	auto[1]	56	1			T2	1		T14	1		T27	1
auto[2952790016:3087007743]	auto[0]	44	1			T14	1		T27	1		T36	1
auto[2952790016:3087007743]	auto[1]	38	1			T14	2		T27	1		T46	1
auto[3087007744:3221225471]	auto[0]	50	1			T14	1		T197	1		T58	1
auto[3087007744:3221225471]	auto[1]	52	1			T2	1		T61	1		T4	2
auto[3221225472:3355443199]	auto[0]	53	1			T75	1		T49	1		T172	1
auto[3221225472:3355443199]	auto[1]	43	1			T15	1		T37	1		T63	2
auto[3355443200:3489660927]	auto[0]	64	1			T14	1		T120	1		T63	2
auto[3355443200:3489660927]	auto[1]	51	1			T198	1		T48	1		T4	2
auto[3489660928:3623878655]	auto[0]	54	1			T46	1		T198	1		T197	1
auto[3489660928:3623878655]	auto[1]	53	1			T27	1		T46	1		T49	1
auto[3623878656:3758096383]	auto[0]	51	1			T27	1		T49	1		T236	1
auto[3623878656:3758096383]	auto[1]	60	1			T14	1		T52	1		T4	1
auto[3758096384:3892314111]	auto[0]	57	1			T1	1		T14	2		T27	1
auto[3758096384:3892314111]	auto[1]	59	1			T14	2		T63	2		T48	1
auto[3892314112:4026531839]	auto[0]	50	1			T199	1		T110	1		T63	1
auto[3892314112:4026531839]	auto[1]	55	1			T7	1		T49	2		T127	1
auto[4026531840:4160749567]	auto[0]	48	1			T46	1		T63	1		T43	2
auto[4026531840:4160749567]	auto[1]	63	1			T14	1		T46	1		T63	1
auto[4160749568:4294967295]	auto[0]	59	1			T14	1		T27	1		T53	1
auto[4160749568:4294967295]	auto[1]	58	1			T14	1		T15	1		T197	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1662

1

T2

1

T14

15

T15

2

auto[1]

1813

1

T1

4

T2

4

T14

28

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	120	1			T14	2		T27	1		T46	2
auto[134217728:268435455]	109	1			T14	1		T16	1		T41	1
auto[268435456:402653183]	128	1			T14	1		T41	1		T27	2
auto[402653184:536870911]	110	1			T14	3		T197	2		T53	1
auto[536870912:671088639]	116	1			T14	1		T36	1		T46	2
auto[671088640:805306367]	105	1			T27	1		T7	1		T63	1
auto[805306368:939524095]	126	1			T14	4		T46	2		T198	1
auto[939524096:1073741823]	102	1			T15	1		T27	1		T110	1
auto[1073741824:1207959551]	114	1			T1	1		T14	2		T15	1
auto[1207959552:1342177279]	128	1			T1	1		T14	1		T16	1
auto[1342177280:1476395007]	105	1			T27	1		T46	3		T61	1
auto[1476395008:1610612735]	105	1			T14	1		T27	3		T46	3
auto[1610612736:1744830463]	89	1			T34	1		T36	1		T46	1
auto[1744830464:1879048191]	107	1			T14	1		T20	1		T63	1
auto[1879048192:2013265919]	94	1			T14	1		T81	1		T46	1
auto[2013265920:2147483647]	88	1			T14	1		T34	1		T81	1
auto[2147483648:2281701375]	99	1			T14	1		T15	2		T27	1
auto[2281701376:2415919103]	105	1			T14	2		T79	1		T197	1
auto[2415919104:2550136831]	114	1			T14	2		T79	2		T81	1
auto[2550136832:2684354559]	105	1			T1	1		T27	2		T7	1
auto[2684354560:2818572287]	104	1			T14	1		T122	2		T49	2
auto[2818572288:2952790015]	111	1			T14	4		T63	1		T24	2
auto[2952790016:3087007743]	103	1			T14	2		T27	3		T46	1
auto[3087007744:3221225471]	126	1			T1	1		T2	1		T46	1
auto[3221225472:3355443199]	121	1			T14	1		T81	1		T198	1
auto[3355443200:3489660927]	117	1			T2	1		T14	2		T27	1
auto[3489660928:3623878655]	85	1			T14	1		T27	2		T20	1
auto[3623878656:3758096383]	111	1			T15	1		T27	1		T81	1
auto[3758096384:3892314111]	105	1			T2	2		T14	2		T16	1
auto[3892314112:4026531839]	111	1			T2	1		T14	1		T52	1
auto[4026531840:4160749567]	119	1			T14	5		T15	1		T16	1
auto[4160749568:4294967295]	93	1			T27	1		T198	1		T63	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	56	1			T14	1		T27	1		T46	1
auto[0:134217727]	auto[1]	64	1			T14	1		T46	1		T48	1
auto[134217728:268435455]	auto[0]	51	1			T16	1		T41	1		T48	1
auto[134217728:268435455]	auto[1]	58	1			T14	1		T27	1		T4	2
auto[268435456:402653183]	auto[0]	61	1			T41	1		T46	1		T199	1
auto[268435456:402653183]	auto[1]	67	1			T14	1		T27	2		T79	1
auto[402653184:536870911]	auto[0]	54	1			T14	1		T197	2		T53	1
auto[402653184:536870911]	auto[1]	56	1			T14	2		T63	1		T61	1
auto[536870912:671088639]	auto[0]	55	1			T36	1		T53	1		T42	1
auto[536870912:671088639]	auto[1]	61	1			T14	1		T46	2		T48	2
auto[671088640:805306367]	auto[0]	48	1			T27	1		T63	1		T24	1
auto[671088640:805306367]	auto[1]	57	1			T7	1		T4	2		T58	1
auto[805306368:939524095]	auto[0]	49	1			T46	1		T120	1		T48	2
auto[805306368:939524095]	auto[1]	77	1			T14	4		T46	1		T198	1
auto[939524096:1073741823]	auto[0]	38	1			T27	1		T49	1		T100	1
auto[939524096:1073741823]	auto[1]	64	1			T15	1		T110	1		T4	1
auto[1073741824:1207959551]	auto[0]	56	1			T14	1		T16	1		T27	1
auto[1073741824:1207959551]	auto[1]	58	1			T1	1		T14	1		T15	1
auto[1207959552:1342177279]	auto[0]	67	1			T14	1		T16	1		T41	1
auto[1207959552:1342177279]	auto[1]	61	1			T1	1		T52	1		T63	3
auto[1342177280:1476395007]	auto[0]	58	1			T46	1		T61	1		T58	1
auto[1342177280:1476395007]	auto[1]	47	1			T27	1		T46	2		T48	1
auto[1476395008:1610612735]	auto[0]	52	1			T14	1		T46	1		T197	1
auto[1476395008:1610612735]	auto[1]	53	1			T27	3		T46	2		T63	2
auto[1610612736:1744830463]	auto[0]	39	1			T46	1		T110	1		T120	1
auto[1610612736:1744830463]	auto[1]	50	1			T34	1		T36	1		T198	1
auto[1744830464:1879048191]	auto[0]	53	1			T48	1		T4	2		T49	1
auto[1744830464:1879048191]	auto[1]	54	1			T14	1		T20	1		T63	1
auto[1879048192:2013265919]	auto[0]	39	1			T63	1		T48	2		T47	1
auto[1879048192:2013265919]	auto[1]	55	1			T14	1		T81	1		T46	1
auto[2013265920:2147483647]	auto[0]	44	1			T14	1		T48	2		T49	1
auto[2013265920:2147483647]	auto[1]	44	1			T34	1		T81	1		T110	1
auto[2147483648:2281701375]	auto[0]	45	1			T15	1		T27	1		T46	1
auto[2147483648:2281701375]	auto[1]	54	1			T14	1		T15	1		T120	1
auto[2281701376:2415919103]	auto[0]	55	1			T14	1		T197	1		T4	1
auto[2281701376:2415919103]	auto[1]	50	1			T14	1		T79	1		T63	1
auto[2415919104:2550136831]	auto[0]	57	1			T79	1		T81	1		T53	1
auto[2415919104:2550136831]	auto[1]	57	1			T14	2		T79	1		T53	1
auto[2550136832:2684354559]	auto[0]	45	1			T63	2		T48	1		T49	1
auto[2550136832:2684354559]	auto[1]	60	1			T1	1		T27	2		T7	1
auto[2684354560:2818572287]	auto[0]	60	1			T49	1		T228	1		T57	2
auto[2684354560:2818572287]	auto[1]	44	1			T14	1		T122	2		T49	1
auto[2818572288:2952790015]	auto[0]	51	1			T14	3		T24	1		T49	1
auto[2818572288:2952790015]	auto[1]	60	1			T14	1		T63	1		T24	1
auto[2952790016:3087007743]	auto[0]	59	1			T27	1		T198	1		T53	1
auto[2952790016:3087007743]	auto[1]	44	1			T14	2		T27	2		T46	1
auto[3087007744:3221225471]	auto[0]	63	1			T199	1		T48	1		T47	1
auto[3087007744:3221225471]	auto[1]	63	1			T1	1		T2	1		T46	1
auto[3221225472:3355443199]	auto[0]	64	1			T81	1		T110	1		T48	2
auto[3221225472:3355443199]	auto[1]	57	1			T14	1		T198	1		T127	1
auto[3355443200:3489660927]	auto[0]	50	1			T14	1		T27	1		T46	1
auto[3355443200:3489660927]	auto[1]	67	1			T2	1		T14	1		T63	2
auto[3489660928:3623878655]	auto[0]	45	1			T14	1		T27	1		T20	1
auto[3489660928:3623878655]	auto[1]	40	1			T27	1		T172	1		T100	1
auto[3623878656:3758096383]	auto[0]	52	1			T15	1		T27	1		T81	1
auto[3623878656:3758096383]	auto[1]	59	1			T46	1		T198	1		T110	1
auto[3758096384:3892314111]	auto[0]	41	1			T16	1		T198	1		T42	1
auto[3758096384:3892314111]	auto[1]	64	1			T2	2		T14	2		T27	1
auto[3892314112:4026531839]	auto[0]	53	1			T2	1		T14	1		T48	3
auto[3892314112:4026531839]	auto[1]	58	1			T52	1		T4	1		T172	1
auto[4026531840:4160749567]	auto[0]	59	1			T14	2		T16	1		T27	2
auto[4026531840:4160749567]	auto[1]	60	1			T14	3		T15	1		T46	1
auto[4160749568:4294967295]	auto[0]	43	1			T27	1		T63	1		T48	1
auto[4160749568:4294967295]	auto[1]	50	1			T198	1		T61	1		T49	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1646

1

T2

2

T14

19

T15

1

auto[1]

1828

1

T1

4

T2

3

T14

24

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	114	1			T14	1		T27	2		T36	1
auto[134217728:268435455]	126	1			T14	1		T34	1		T27	3
auto[268435456:402653183]	103	1			T2	1		T27	1		T198	2
auto[402653184:536870911]	104	1			T14	3		T16	1		T27	1
auto[536870912:671088639]	108	1			T2	1		T14	1		T16	1
auto[671088640:805306367]	106	1			T14	1		T15	2		T27	1
auto[805306368:939524095]	117	1			T46	1		T63	3		T48	3
auto[939524096:1073741823]	84	1			T27	1		T81	1		T46	1
auto[1073741824:1207959551]	112	1			T14	1		T27	1		T198	1
auto[1207959552:1342177279]	106	1			T1	1		T14	1		T16	1
auto[1342177280:1476395007]	108	1			T2	2		T14	1		T79	2
auto[1476395008:1610612735]	103	1			T15	2		T46	1		T198	1
auto[1610612736:1744830463]	96	1			T14	2		T27	2		T63	1
auto[1744830464:1879048191]	114	1			T1	1		T14	1		T41	1
auto[1879048192:2013265919]	95	1			T14	2		T27	2		T46	1
auto[2013265920:2147483647]	107	1			T14	1		T16	1		T27	1
auto[2147483648:2281701375]	103	1			T14	1		T41	1		T79	1
auto[2281701376:2415919103]	118	1			T27	1		T20	1		T46	1
auto[2415919104:2550136831]	117	1			T14	2		T16	1		T27	1
auto[2550136832:2684354559]	103	1			T14	3		T27	1		T46	1
auto[2684354560:2818572287]	95	1			T14	1		T15	1		T63	1
auto[2818572288:2952790015]	102	1			T14	1		T41	1		T27	2
auto[2952790016:3087007743]	117	1			T14	2		T15	1		T46	2
auto[3087007744:3221225471]	135	1			T2	1		T27	2		T81	1
auto[3221225472:3355443199]	101	1			T1	1		T14	1		T27	1
auto[3355443200:3489660927]	130	1			T36	1		T81	1		T46	2
auto[3489660928:3623878655]	116	1			T14	1		T27	1		T199	1
auto[3623878656:3758096383]	98	1			T14	5		T198	1		T120	1
auto[3758096384:3892314111]	108	1			T14	2		T34	1		T81	1
auto[3892314112:4026531839]	107	1			T14	2		T20	1		T46	2
auto[4026531840:4160749567]	105	1			T14	2		T46	2		T198	1
auto[4160749568:4294967295]	116	1			T1	1		T14	4		T27	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	56	1			T14	1		T27	1		T81	1
auto[0:134217727]	auto[1]	58	1			T27	1		T36	1		T46	1
auto[134217728:268435455]	auto[0]	69	1			T14	1		T27	2		T53	1
auto[134217728:268435455]	auto[1]	57	1			T34	1		T27	1		T63	1
auto[268435456:402653183]	auto[0]	46	1			T198	1		T53	1		T49	1
auto[268435456:402653183]	auto[1]	57	1			T2	1		T27	1		T198	1
auto[402653184:536870911]	auto[0]	52	1			T16	1		T27	1		T43	1
auto[402653184:536870911]	auto[1]	52	1			T14	3		T4	1		T32	1
auto[536870912:671088639]	auto[0]	54	1			T16	1		T63	1		T24	1
auto[536870912:671088639]	auto[1]	54	1			T2	1		T14	1		T198	1
auto[671088640:805306367]	auto[0]	54	1			T4	1		T58	1		T293	1
auto[671088640:805306367]	auto[1]	52	1			T14	1		T15	2		T27	1
auto[805306368:939524095]	auto[0]	56	1			T46	1		T63	1		T48	1
auto[805306368:939524095]	auto[1]	61	1			T63	2		T48	2		T4	1
auto[939524096:1073741823]	auto[0]	32	1			T48	1		T49	2		T127	1
auto[939524096:1073741823]	auto[1]	52	1			T27	1		T81	1		T46	1
auto[1073741824:1207959551]	auto[0]	48	1			T14	1		T27	1		T197	1
auto[1073741824:1207959551]	auto[1]	64	1			T198	1		T63	1		T48	1
auto[1207959552:1342177279]	auto[0]	49	1			T16	1		T197	2		T236	1
auto[1207959552:1342177279]	auto[1]	57	1			T1	1		T14	1		T27	2
auto[1342177280:1476395007]	auto[0]	48	1			T2	1		T46	1		T37	1
auto[1342177280:1476395007]	auto[1]	60	1			T2	1		T14	1		T79	2
auto[1476395008:1610612735]	auto[0]	52	1			T15	1		T46	1		T198	1
auto[1476395008:1610612735]	auto[1]	51	1			T15	1		T49	2		T127	1
auto[1610612736:1744830463]	auto[0]	42	1			T14	2		T27	2		T49	1
auto[1610612736:1744830463]	auto[1]	54	1			T63	1		T48	1		T4	1
auto[1744830464:1879048191]	auto[0]	54	1			T41	1		T81	1		T48	1
auto[1744830464:1879048191]	auto[1]	60	1			T1	1		T14	1		T36	1
auto[1879048192:2013265919]	auto[0]	51	1			T14	1		T27	1		T46	1
auto[1879048192:2013265919]	auto[1]	44	1			T14	1		T27	1		T48	1
auto[2013265920:2147483647]	auto[0]	45	1			T16	1		T27	1		T48	1
auto[2013265920:2147483647]	auto[1]	62	1			T14	1		T79	1		T63	1
auto[2147483648:2281701375]	auto[0]	50	1			T14	1		T79	1		T48	1
auto[2147483648:2281701375]	auto[1]	53	1			T41	1		T52	1		T38	1
auto[2281701376:2415919103]	auto[0]	57	1			T20	1		T197	1		T110	1
auto[2281701376:2415919103]	auto[1]	61	1			T27	1		T46	1		T48	1
auto[2415919104:2550136831]	auto[0]	56	1			T16	1		T63	2		T49	1
auto[2415919104:2550136831]	auto[1]	61	1			T14	2		T27	1		T81	1
auto[2550136832:2684354559]	auto[0]	48	1			T14	1		T46	1		T199	1
auto[2550136832:2684354559]	auto[1]	55	1			T14	2		T27	1		T63	1
auto[2684354560:2818572287]	auto[0]	52	1			T63	1		T61	1		T49	2
auto[2684354560:2818572287]	auto[1]	43	1			T14	1		T15	1		T61	1
auto[2818572288:2952790015]	auto[0]	43	1			T41	1		T27	2		T46	1
auto[2818572288:2952790015]	auto[1]	59	1			T14	1		T63	2		T48	3
auto[2952790016:3087007743]	auto[0]	51	1			T14	1		T46	1		T49	1
auto[2952790016:3087007743]	auto[1]	66	1			T14	1		T15	1		T46	1
auto[3087007744:3221225471]	auto[0]	54	1			T2	1		T46	1		T37	1
auto[3087007744:3221225471]	auto[1]	81	1			T27	2		T81	1		T46	1
auto[3221225472:3355443199]	auto[0]	60	1			T53	1		T120	1		T63	2
auto[3221225472:3355443199]	auto[1]	41	1			T1	1		T14	1		T27	1
auto[3355443200:3489660927]	auto[0]	64	1			T36	1		T81	1		T58	1
auto[3355443200:3489660927]	auto[1]	66	1			T46	2		T52	1		T120	1
auto[3489660928:3623878655]	auto[0]	55	1			T14	1		T110	1		T120	1
auto[3489660928:3623878655]	auto[1]	61	1			T27	1		T199	1		T48	2
auto[3623878656:3758096383]	auto[0]	45	1			T14	2		T61	1		T48	1
auto[3623878656:3758096383]	auto[1]	53	1			T14	3		T198	1		T120	1
auto[3758096384:3892314111]	auto[0]	53	1			T14	2		T81	1		T48	1
auto[3758096384:3892314111]	auto[1]	55	1			T34	1		T46	2		T110	1
auto[3892314112:4026531839]	auto[0]	50	1			T14	2		T120	1		T63	2
auto[3892314112:4026531839]	auto[1]	57	1			T20	1		T46	2		T49	2
auto[4026531840:4160749567]	auto[0]	41	1			T110	1		T120	1		T48	2
auto[4026531840:4160749567]	auto[1]	64	1			T14	2		T46	2		T198	1
auto[4160749568:4294967295]	auto[0]	59	1			T14	3		T27	1		T4	1
auto[4160749568:4294967295]	auto[1]	57	1			T1	1		T14	1		T7	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1658

1

T1

1

T2

1

T14

16

auto[1]

1816

1

T1

3

T2

4

T14

27

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	120	1			T27	3		T46	2		T53	1
auto[134217728:268435455]	103	1			T110	2		T48	2		T42	1
auto[268435456:402653183]	106	1			T2	1		T46	1		T199	1
auto[402653184:536870911]	129	1			T14	3		T15	1		T27	1
auto[536870912:671088639]	112	1			T14	1		T27	2		T36	1
auto[671088640:805306367]	103	1			T14	1		T36	1		T46	1
auto[805306368:939524095]	106	1			T14	1		T46	1		T63	1
auto[939524096:1073741823]	126	1			T14	2		T81	1		T46	2
auto[1073741824:1207959551]	107	1			T14	1		T34	1		T46	1
auto[1207959552:1342177279]	87	1			T1	1		T63	3		T48	1
auto[1342177280:1476395007]	107	1			T15	1		T27	3		T81	1
auto[1476395008:1610612735]	101	1			T2	1		T27	2		T110	1
auto[1610612736:1744830463]	113	1			T14	2		T15	1		T16	1
auto[1744830464:1879048191]	112	1			T14	5		T63	1		T48	4
auto[1879048192:2013265919]	113	1			T14	2		T198	1		T37	1
auto[2013265920:2147483647]	113	1			T14	1		T27	2		T198	3
auto[2147483648:2281701375]	101	1			T1	1		T14	1		T63	2
auto[2281701376:2415919103]	109	1			T14	1		T7	1		T110	1
auto[2415919104:2550136831]	109	1			T2	1		T14	1		T41	1
auto[2550136832:2684354559]	112	1			T14	2		T81	1		T46	1
auto[2684354560:2818572287]	111	1			T1	1		T2	1		T15	1
auto[2818572288:2952790015]	109	1			T14	1		T16	1		T41	1
auto[2952790016:3087007743]	110	1			T14	2		T79	2		T81	1
auto[3087007744:3221225471]	104	1			T14	1		T46	2		T52	1
auto[3221225472:3355443199]	106	1			T1	1		T16	1		T27	2
auto[3355443200:3489660927]	108	1			T27	2		T61	1		T48	2
auto[3489660928:3623878655]	105	1			T14	3		T34	1		T46	1
auto[3623878656:3758096383]	93	1			T15	1		T27	2		T46	2
auto[3758096384:3892314111]	124	1			T14	2		T27	1		T79	1
auto[3892314112:4026531839]	95	1			T14	2		T15	1		T16	1
auto[4026531840:4160749567]	105	1			T14	5		T16	1		T27	1
auto[4160749568:4294967295]	115	1			T2	1		T14	3		T27	1