Unified Coverage Report :: Group Instance : attest_sw_binding_4

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1651

1

T1

1

T2

1

T14

18

auto[1]

1823

1

T1

3

T2

4

T14

25

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	104	1			T14	1		T27	1		T46	1
auto[134217728:268435455]	116	1			T14	1		T27	1		T52	1
auto[268435456:402653183]	120	1			T14	1		T81	1		T52	1
auto[402653184:536870911]	96	1			T197	1		T110	1		T48	4
auto[536870912:671088639]	106	1			T15	1		T27	1		T197	1
auto[671088640:805306367]	110	1			T27	1		T46	1		T7	1
auto[805306368:939524095]	145	1			T2	1		T14	3		T27	1
auto[939524096:1073741823]	119	1			T27	2		T79	1		T120	1
auto[1073741824:1207959551]	121	1			T1	1		T14	2		T16	1
auto[1207959552:1342177279]	92	1			T14	1		T27	1		T46	1
auto[1342177280:1476395007]	97	1			T14	4		T36	1		T46	1
auto[1476395008:1610612735]	108	1			T14	1		T16	1		T36	1
auto[1610612736:1744830463]	100	1			T198	1		T53	1		T48	2
auto[1744830464:1879048191]	99	1			T1	1		T2	1		T41	1
auto[1879048192:2013265919]	98	1			T1	1		T14	4		T27	1
auto[2013265920:2147483647]	122	1			T14	2		T34	1		T46	4
auto[2147483648:2281701375]	96	1			T14	1		T81	1		T46	1
auto[2281701376:2415919103]	111	1			T14	3		T27	1		T48	1
auto[2415919104:2550136831]	108	1			T14	1		T16	1		T27	2
auto[2550136832:2684354559]	126	1			T27	1		T199	1		T110	1
auto[2684354560:2818572287]	134	1			T2	1		T14	1		T34	1
auto[2818572288:2952790015]	123	1			T14	2		T27	2		T79	1
auto[2952790016:3087007743]	101	1			T1	1		T14	2		T41	1
auto[3087007744:3221225471]	106	1			T2	1		T14	2		T197	1
auto[3221225472:3355443199]	96	1			T2	1		T14	1		T81	1
auto[3355443200:3489660927]	96	1			T14	3		T15	2		T46	1
auto[3489660928:3623878655]	94	1			T14	1		T16	1		T27	2
auto[3623878656:3758096383]	104	1			T14	1		T16	1		T63	1
auto[3758096384:3892314111]	116	1			T14	1		T46	1		T63	1
auto[3892314112:4026531839]	109	1			T14	1		T199	1		T48	3
auto[4026531840:4160749567]	110	1			T14	2		T15	3		T27	2
auto[4160749568:4294967295]	91	1			T14	1		T41	1		T27	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	49	1			T46	1		T43	1		T127	1
auto[0:134217727]	auto[1]	55	1			T14	1		T27	1		T197	1
auto[134217728:268435455]	auto[0]	61	1			T63	1		T4	1		T47	1
auto[134217728:268435455]	auto[1]	55	1			T14	1		T27	1		T52	1
auto[268435456:402653183]	auto[0]	57	1			T81	1		T52	1		T120	1
auto[268435456:402653183]	auto[1]	63	1			T14	1		T48	2		T49	2
auto[402653184:536870911]	auto[0]	46	1			T110	1		T48	1		T4	1
auto[402653184:536870911]	auto[1]	50	1			T197	1		T48	3		T4	1
auto[536870912:671088639]	auto[0]	49	1			T27	1		T197	1		T63	1
auto[536870912:671088639]	auto[1]	57	1			T15	1		T48	3		T127	1
auto[671088640:805306367]	auto[0]	51	1			T27	1		T63	1		T48	1
auto[671088640:805306367]	auto[1]	59	1			T46	1		T7	1		T199	1
auto[805306368:939524095]	auto[0]	69	1			T14	2		T27	1		T127	1
auto[805306368:939524095]	auto[1]	76	1			T2	1		T14	1		T46	2
auto[939524096:1073741823]	auto[0]	64	1			T27	2		T120	1		T63	1
auto[939524096:1073741823]	auto[1]	55	1			T79	1		T63	1		T49	1
auto[1073741824:1207959551]	auto[0]	64	1			T16	1		T27	1		T46	2
auto[1073741824:1207959551]	auto[1]	57	1			T1	1		T14	2		T27	1
auto[1207959552:1342177279]	auto[0]	43	1			T48	1		T49	3		T226	1
auto[1207959552:1342177279]	auto[1]	49	1			T14	1		T27	1		T46	1
auto[1342177280:1476395007]	auto[0]	52	1			T14	2		T36	1		T63	1
auto[1342177280:1476395007]	auto[1]	45	1			T14	2		T46	1		T48	1
auto[1476395008:1610612735]	auto[0]	58	1			T16	1		T36	1		T198	1
auto[1476395008:1610612735]	auto[1]	50	1			T14	1		T63	3		T61	1
auto[1610612736:1744830463]	auto[0]	44	1			T53	1		T48	1		T4	1
auto[1610612736:1744830463]	auto[1]	56	1			T198	1		T48	1		T24	1
auto[1744830464:1879048191]	auto[0]	45	1			T1	1		T2	1		T41	1
auto[1744830464:1879048191]	auto[1]	54	1			T27	2		T81	1		T110	1
auto[1879048192:2013265919]	auto[0]	44	1			T14	1		T198	1		T100	1
auto[1879048192:2013265919]	auto[1]	54	1			T1	1		T14	3		T27	1
auto[2013265920:2147483647]	auto[0]	63	1			T14	1		T46	2		T197	1
auto[2013265920:2147483647]	auto[1]	59	1			T14	1		T34	1		T46	2
auto[2147483648:2281701375]	auto[0]	42	1			T14	1		T46	1		T53	1
auto[2147483648:2281701375]	auto[1]	54	1			T81	1		T48	3		T100	2
auto[2281701376:2415919103]	auto[0]	43	1			T14	2		T24	1		T49	1
auto[2281701376:2415919103]	auto[1]	68	1			T14	1		T27	1		T48	1
auto[2415919104:2550136831]	auto[0]	56	1			T16	1		T27	1		T120	1
auto[2415919104:2550136831]	auto[1]	52	1			T14	1		T27	1		T81	1
auto[2550136832:2684354559]	auto[0]	53	1			T27	1		T199	1		T110	1
auto[2550136832:2684354559]	auto[1]	73	1			T63	1		T48	2		T42	1
auto[2684354560:2818572287]	auto[0]	71	1			T14	1		T110	1		T127	3
auto[2684354560:2818572287]	auto[1]	63	1			T2	1		T34	1		T27	1
auto[2818572288:2952790015]	auto[0]	62	1			T14	2		T27	1		T79	1
auto[2818572288:2952790015]	auto[1]	61	1			T27	1		T46	1		T110	1
auto[2952790016:3087007743]	auto[0]	44	1			T14	1		T27	1		T46	1
auto[2952790016:3087007743]	auto[1]	57	1			T1	1		T14	1		T41	1
auto[3087007744:3221225471]	auto[0]	51	1			T197	1		T63	1		T61	1
auto[3087007744:3221225471]	auto[1]	55	1			T2	1		T14	2		T48	2
auto[3221225472:3355443199]	auto[0]	44	1			T81	1		T49	1		T43	1
auto[3221225472:3355443199]	auto[1]	52	1			T2	1		T14	1		T37	1
auto[3355443200:3489660927]	auto[0]	44	1			T14	2		T15	1		T53	1
auto[3355443200:3489660927]	auto[1]	52	1			T14	1		T15	1		T46	1
auto[3489660928:3623878655]	auto[0]	47	1			T27	1		T20	1		T63	1
auto[3489660928:3623878655]	auto[1]	47	1			T14	1		T16	1		T27	1
auto[3623878656:3758096383]	auto[0]	44	1			T16	1		T63	1		T4	1
auto[3623878656:3758096383]	auto[1]	60	1			T14	1		T4	1		T58	1
auto[3758096384:3892314111]	auto[0]	54	1			T14	1		T46	1		T63	1
auto[3758096384:3892314111]	auto[1]	62	1			T48	1		T4	1		T49	1
auto[3892314112:4026531839]	auto[0]	50	1			T48	1		T4	2		T49	1
auto[3892314112:4026531839]	auto[1]	59	1			T14	1		T199	1		T48	2
auto[4026531840:4160749567]	auto[0]	46	1			T14	1		T15	1		T27	1
auto[4026531840:4160749567]	auto[1]	64	1			T14	1		T15	2		T27	1
auto[4160749568:4294967295]	auto[0]	41	1			T14	1		T41	1		T27	1
auto[4160749568:4294967295]	auto[1]	50	1			T46	1		T198	2		T38	1