Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.72 99.03 98.15 98.26 100.00 99.02 98.41 91.19


Total test records in report: 1084
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T1006 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.3441066016 May 09 01:08:05 PM PDT 24 May 09 01:08:15 PM PDT 24 251104365 ps
T1007 /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1675411367 May 09 01:07:36 PM PDT 24 May 09 01:07:39 PM PDT 24 20465898 ps
T1008 /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2798095514 May 09 01:07:24 PM PDT 24 May 09 01:07:29 PM PDT 24 129652978 ps
T1009 /workspace/coverage/cover_reg_top/24.keymgr_intr_test.3369446059 May 09 01:08:01 PM PDT 24 May 09 01:08:04 PM PDT 24 19098718 ps
T1010 /workspace/coverage/cover_reg_top/42.keymgr_intr_test.2956837321 May 09 01:08:01 PM PDT 24 May 09 01:08:04 PM PDT 24 58048939 ps
T1011 /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.2948320422 May 09 01:07:23 PM PDT 24 May 09 01:07:29 PM PDT 24 1316807628 ps
T1012 /workspace/coverage/cover_reg_top/23.keymgr_intr_test.1726699612 May 09 01:08:05 PM PDT 24 May 09 01:08:08 PM PDT 24 18128468 ps
T1013 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2761580952 May 09 01:07:55 PM PDT 24 May 09 01:08:01 PM PDT 24 360811009 ps
T1014 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.679160047 May 09 01:07:24 PM PDT 24 May 09 01:07:36 PM PDT 24 715631909 ps
T1015 /workspace/coverage/cover_reg_top/36.keymgr_intr_test.4044852328 May 09 01:08:05 PM PDT 24 May 09 01:08:08 PM PDT 24 26942139 ps
T1016 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.582606783 May 09 01:08:01 PM PDT 24 May 09 01:08:05 PM PDT 24 310328828 ps
T1017 /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.3012290101 May 09 01:07:24 PM PDT 24 May 09 01:07:30 PM PDT 24 116303958 ps
T1018 /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.3626210174 May 09 01:07:55 PM PDT 24 May 09 01:07:57 PM PDT 24 17482903 ps
T1019 /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.2685846197 May 09 01:07:21 PM PDT 24 May 09 01:07:22 PM PDT 24 39234647 ps
T1020 /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3088901260 May 09 01:07:46 PM PDT 24 May 09 01:07:48 PM PDT 24 112061226 ps
T1021 /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.2014998586 May 09 01:08:02 PM PDT 24 May 09 01:08:07 PM PDT 24 276494192 ps
T171 /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.200183497 May 09 01:07:41 PM PDT 24 May 09 01:07:50 PM PDT 24 212796364 ps
T1022 /workspace/coverage/cover_reg_top/17.keymgr_intr_test.3590170739 May 09 01:07:55 PM PDT 24 May 09 01:07:57 PM PDT 24 213163685 ps
T1023 /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.3898072276 May 09 01:07:22 PM PDT 24 May 09 01:07:25 PM PDT 24 124875995 ps
T1024 /workspace/coverage/cover_reg_top/41.keymgr_intr_test.83084132 May 09 01:08:03 PM PDT 24 May 09 01:08:06 PM PDT 24 52960212 ps
T1025 /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.1620739277 May 09 01:07:39 PM PDT 24 May 09 01:07:42 PM PDT 24 14254820 ps
T1026 /workspace/coverage/cover_reg_top/12.keymgr_intr_test.3135693676 May 09 01:07:52 PM PDT 24 May 09 01:07:53 PM PDT 24 38490499 ps
T1027 /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.3775692676 May 09 01:07:40 PM PDT 24 May 09 01:07:44 PM PDT 24 61229961 ps
T1028 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.2760531358 May 09 01:07:25 PM PDT 24 May 09 01:07:31 PM PDT 24 514789448 ps
T1029 /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2206782463 May 09 01:07:25 PM PDT 24 May 09 01:07:37 PM PDT 24 2592268749 ps
T1030 /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3158744983 May 09 01:07:49 PM PDT 24 May 09 01:07:52 PM PDT 24 31936095 ps
T1031 /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1963856510 May 09 01:07:24 PM PDT 24 May 09 01:07:30 PM PDT 24 50399380 ps
T1032 /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.2719028973 May 09 01:07:21 PM PDT 24 May 09 01:07:35 PM PDT 24 1936399631 ps
T1033 /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1598879586 May 09 01:07:36 PM PDT 24 May 09 01:07:40 PM PDT 24 107389944 ps
T1034 /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.2189178640 May 09 01:07:24 PM PDT 24 May 09 01:07:41 PM PDT 24 1408314013 ps
T1035 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3153595271 May 09 01:07:35 PM PDT 24 May 09 01:07:45 PM PDT 24 582067117 ps
T1036 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2739643345 May 09 01:07:54 PM PDT 24 May 09 01:07:59 PM PDT 24 289928412 ps
T1037 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.3835701775 May 09 01:07:38 PM PDT 24 May 09 01:07:45 PM PDT 24 205934999 ps
T1038 /workspace/coverage/cover_reg_top/22.keymgr_intr_test.1574068141 May 09 01:08:02 PM PDT 24 May 09 01:08:06 PM PDT 24 26719723 ps
T1039 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.2631505601 May 09 01:07:22 PM PDT 24 May 09 01:07:26 PM PDT 24 265074929 ps
T1040 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.3813491295 May 09 01:07:21 PM PDT 24 May 09 01:07:25 PM PDT 24 691659577 ps
T1041 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.961081631 May 09 01:07:36 PM PDT 24 May 09 01:07:40 PM PDT 24 86729974 ps
T1042 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.2265234517 May 09 01:08:02 PM PDT 24 May 09 01:08:06 PM PDT 24 58609231 ps
T1043 /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1814095590 May 09 01:07:24 PM PDT 24 May 09 01:07:28 PM PDT 24 86531654 ps
T159 /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.1648344854 May 09 01:07:54 PM PDT 24 May 09 01:08:06 PM PDT 24 248670853 ps
T160 /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.57112159 May 09 01:07:24 PM PDT 24 May 09 01:07:32 PM PDT 24 353118785 ps
T1044 /workspace/coverage/cover_reg_top/27.keymgr_intr_test.3974271771 May 09 01:08:01 PM PDT 24 May 09 01:08:03 PM PDT 24 38517422 ps
T1045 /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1159273439 May 09 01:07:23 PM PDT 24 May 09 01:07:26 PM PDT 24 138276306 ps
T1046 /workspace/coverage/cover_reg_top/45.keymgr_intr_test.2100829742 May 09 01:08:01 PM PDT 24 May 09 01:08:04 PM PDT 24 48526539 ps
T1047 /workspace/coverage/cover_reg_top/48.keymgr_intr_test.3933396876 May 09 01:08:01 PM PDT 24 May 09 01:08:04 PM PDT 24 27933993 ps
T1048 /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.3928363427 May 09 01:07:23 PM PDT 24 May 09 01:07:26 PM PDT 24 75488089 ps
T1049 /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2053854088 May 09 01:07:24 PM PDT 24 May 09 01:07:34 PM PDT 24 914855934 ps
T1050 /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.3270915498 May 09 01:07:49 PM PDT 24 May 09 01:07:54 PM PDT 24 46229700 ps
T1051 /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.2002180051 May 09 01:07:54 PM PDT 24 May 09 01:07:57 PM PDT 24 26148094 ps
T1052 /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.511449020 May 09 01:08:00 PM PDT 24 May 09 01:08:06 PM PDT 24 480946890 ps
T1053 /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1653291364 May 09 01:07:38 PM PDT 24 May 09 01:07:41 PM PDT 24 87325848 ps
T1054 /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.653735547 May 09 01:07:45 PM PDT 24 May 09 01:07:50 PM PDT 24 624704163 ps
T1055 /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.295079821 May 09 01:07:23 PM PDT 24 May 09 01:07:29 PM PDT 24 116496319 ps
T1056 /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.2749739833 May 09 01:08:02 PM PDT 24 May 09 01:08:11 PM PDT 24 593833796 ps
T1057 /workspace/coverage/cover_reg_top/11.keymgr_intr_test.3550039547 May 09 01:07:46 PM PDT 24 May 09 01:07:48 PM PDT 24 149146780 ps
T156 /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.1497555176 May 09 01:07:55 PM PDT 24 May 09 01:08:01 PM PDT 24 205748689 ps
T1058 /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.1818812872 May 09 01:07:25 PM PDT 24 May 09 01:07:40 PM PDT 24 1385724864 ps
T1059 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.4039204991 May 09 01:07:39 PM PDT 24 May 09 01:07:44 PM PDT 24 120387963 ps
T1060 /workspace/coverage/cover_reg_top/20.keymgr_intr_test.2723023886 May 09 01:08:03 PM PDT 24 May 09 01:08:06 PM PDT 24 11613696 ps
T1061 /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2421246156 May 09 01:07:25 PM PDT 24 May 09 01:07:30 PM PDT 24 105231556 ps
T1062 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.2211261756 May 09 01:07:35 PM PDT 24 May 09 01:07:38 PM PDT 24 163695638 ps
T1063 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.2927237640 May 09 01:07:23 PM PDT 24 May 09 01:07:31 PM PDT 24 652689115 ps
T1064 /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.2574859541 May 09 01:07:26 PM PDT 24 May 09 01:07:30 PM PDT 24 27581828 ps
T1065 /workspace/coverage/cover_reg_top/25.keymgr_intr_test.85170569 May 09 01:08:05 PM PDT 24 May 09 01:08:08 PM PDT 24 37254691 ps
T1066 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2227710367 May 09 01:07:49 PM PDT 24 May 09 01:07:59 PM PDT 24 941708208 ps
T1067 /workspace/coverage/cover_reg_top/8.keymgr_intr_test.1234235136 May 09 01:07:39 PM PDT 24 May 09 01:07:42 PM PDT 24 18247927 ps
T1068 /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.4161570797 May 09 01:07:36 PM PDT 24 May 09 01:07:40 PM PDT 24 28334402 ps
T1069 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.3254463320 May 09 01:07:35 PM PDT 24 May 09 01:07:40 PM PDT 24 233063402 ps
T1070 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.3594721350 May 09 01:07:35 PM PDT 24 May 09 01:07:37 PM PDT 24 33526381 ps
T1071 /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.3830757380 May 09 01:07:54 PM PDT 24 May 09 01:07:57 PM PDT 24 72424872 ps
T1072 /workspace/coverage/cover_reg_top/21.keymgr_intr_test.3478879141 May 09 01:08:01 PM PDT 24 May 09 01:08:04 PM PDT 24 36749733 ps
T1073 /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.29347333 May 09 01:08:01 PM PDT 24 May 09 01:08:04 PM PDT 24 19983283 ps
T1074 /workspace/coverage/cover_reg_top/4.keymgr_intr_test.982626692 May 09 01:07:24 PM PDT 24 May 09 01:07:27 PM PDT 24 12253105 ps
T1075 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.639332782 May 09 01:07:49 PM PDT 24 May 09 01:07:53 PM PDT 24 528517979 ps
T1076 /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.3056712587 May 09 01:07:48 PM PDT 24 May 09 01:07:51 PM PDT 24 57667337 ps
T1077 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.631576099 May 09 01:07:25 PM PDT 24 May 09 01:07:29 PM PDT 24 108082164 ps
T1078 /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1077744156 May 09 01:07:44 PM PDT 24 May 09 01:07:46 PM PDT 24 48173640 ps
T158 /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.3050324464 May 09 01:07:38 PM PDT 24 May 09 01:07:50 PM PDT 24 269573854 ps
T1079 /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.2930680738 May 09 01:07:48 PM PDT 24 May 09 01:07:53 PM PDT 24 288960024 ps
T1080 /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.3686816175 May 09 01:07:27 PM PDT 24 May 09 01:07:30 PM PDT 24 211176318 ps
T1081 /workspace/coverage/cover_reg_top/18.keymgr_intr_test.3539400127 May 09 01:08:04 PM PDT 24 May 09 01:08:07 PM PDT 24 22042030 ps
T1082 /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.4252172389 May 09 01:07:36 PM PDT 24 May 09 01:07:40 PM PDT 24 393815850 ps
T1083 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.4278229840 May 09 01:07:46 PM PDT 24 May 09 01:07:56 PM PDT 24 461488942 ps
T1084 /workspace/coverage/cover_reg_top/2.keymgr_intr_test.4159793801 May 09 01:07:24 PM PDT 24 May 09 01:07:27 PM PDT 24 38051920 ps

Test location /workspace/coverage/default/14.keymgr_stress_all.4258561709
Short name T14
Test name
Test status
Simulation time 4693604531 ps
CPU time 78.79 seconds
Started May 09 12:34:03 PM PDT 24
Finished May 09 12:35:31 PM PDT 24
Peak memory 216196 kb
Host smart-a28047a2-735f-4923-ad5e-c06614f70ae2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258561709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.4258561709
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.412314327
Short name T4
Test name
Test status
Simulation time 7132749789 ps
CPU time 21.67 seconds
Started May 09 12:34:05 PM PDT 24
Finished May 09 12:34:35 PM PDT 24
Peak memory 222436 kb
Host smart-2600df55-137e-4038-884e-3d6eff0da88d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412314327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.412314327
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.1221513980
Short name T40
Test name
Test status
Simulation time 455243092 ps
CPU time 9 seconds
Started May 09 12:33:47 PM PDT 24
Finished May 09 12:34:06 PM PDT 24
Peak memory 234180 kb
Host smart-29dbf243-eeb0-4097-94ef-93e84e410de1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221513980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.1221513980
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.1365228043
Short name T117
Test name
Test status
Simulation time 1115582980 ps
CPU time 21.04 seconds
Started May 09 12:35:34 PM PDT 24
Finished May 09 12:36:03 PM PDT 24
Peak memory 220620 kb
Host smart-e95f88e1-6da6-438c-b89a-731d06b8bd9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365228043 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.1365228043
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.2560520351
Short name T49
Test name
Test status
Simulation time 1977054635 ps
CPU time 61.6 seconds
Started May 09 12:35:03 PM PDT 24
Finished May 09 12:36:13 PM PDT 24
Peak memory 214856 kb
Host smart-18cbedfe-1bdb-4c2e-8d8e-74bfa928bca0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560520351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.2560520351
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.1422353153
Short name T110
Test name
Test status
Simulation time 834294984 ps
CPU time 11.75 seconds
Started May 09 12:34:42 PM PDT 24
Finished May 09 12:34:58 PM PDT 24
Peak memory 214780 kb
Host smart-3263fa6c-9a75-44f2-a11f-e95c3c0074ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1422353153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.1422353153
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.1928494933
Short name T48
Test name
Test status
Simulation time 1675816515 ps
CPU time 21.46 seconds
Started May 09 12:34:57 PM PDT 24
Finished May 09 12:35:26 PM PDT 24
Peak memory 222288 kb
Host smart-556f6a05-bdd4-4f9a-94a4-9be58e3367c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928494933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.1928494933
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.747151604
Short name T13
Test name
Test status
Simulation time 54012593 ps
CPU time 2.61 seconds
Started May 09 12:33:54 PM PDT 24
Finished May 09 12:34:04 PM PDT 24
Peak memory 209532 kb
Host smart-aa6e73b3-c990-41eb-8227-45061d8af8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747151604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.747151604
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.2109416451
Short name T7
Test name
Test status
Simulation time 310279073 ps
CPU time 6.4 seconds
Started May 09 12:34:14 PM PDT 24
Finished May 09 12:34:29 PM PDT 24
Peak memory 218928 kb
Host smart-e7e31c91-7d54-4a66-9292-a17e50997452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109416451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.2109416451
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.2302057923
Short name T16
Test name
Test status
Simulation time 65376396 ps
CPU time 3.21 seconds
Started May 09 12:34:36 PM PDT 24
Finished May 09 12:34:43 PM PDT 24
Peak memory 222380 kb
Host smart-c82a0f94-209a-4bca-a9c6-e3c72d4b960e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302057923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.2302057923
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.2775754071
Short name T104
Test name
Test status
Simulation time 199879932 ps
CPU time 5.12 seconds
Started May 09 01:07:52 PM PDT 24
Finished May 09 01:07:59 PM PDT 24
Peak memory 214140 kb
Host smart-481387c3-6e2f-412d-979a-5156b1ddf0ae
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775754071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.2775754071
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.3564350385
Short name T355
Test name
Test status
Simulation time 2707391115 ps
CPU time 55.03 seconds
Started May 09 12:35:27 PM PDT 24
Finished May 09 12:36:32 PM PDT 24
Peak memory 216504 kb
Host smart-121d4d7e-33ea-46fd-a28d-2dcc099a89c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3564350385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.3564350385
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.2020904974
Short name T100
Test name
Test status
Simulation time 523392206 ps
CPU time 17.67 seconds
Started May 09 12:33:44 PM PDT 24
Finished May 09 12:34:12 PM PDT 24
Peak memory 222788 kb
Host smart-9e31ba80-c5da-4aad-bb6e-ad8ccc952fe8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020904974 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.2020904974
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.873553916
Short name T396
Test name
Test status
Simulation time 999900579 ps
CPU time 52.02 seconds
Started May 09 12:34:49 PM PDT 24
Finished May 09 12:35:46 PM PDT 24
Peak memory 214120 kb
Host smart-8291c280-d280-468c-82e6-c950b1f3ca6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=873553916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.873553916
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.1316169241
Short name T26
Test name
Test status
Simulation time 672097408 ps
CPU time 11.27 seconds
Started May 09 12:34:59 PM PDT 24
Finished May 09 12:35:18 PM PDT 24
Peak memory 219980 kb
Host smart-faca758d-ee83-45af-ba5e-f130b64839c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316169241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.1316169241
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.453553903
Short name T115
Test name
Test status
Simulation time 410358304 ps
CPU time 9.38 seconds
Started May 09 01:08:01 PM PDT 24
Finished May 09 01:08:13 PM PDT 24
Peak memory 222520 kb
Host smart-727f470b-d61e-41e6-be8c-7d49245306ac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453553903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
keymgr_shadow_reg_errors_with_csr_rw.453553903
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.2871925007
Short name T290
Test name
Test status
Simulation time 2657625330 ps
CPU time 129.6 seconds
Started May 09 12:34:07 PM PDT 24
Finished May 09 12:36:25 PM PDT 24
Peak memory 215976 kb
Host smart-34957d5c-77ec-40b6-982b-630c8e053ff0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2871925007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.2871925007
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.1271089740
Short name T127
Test name
Test status
Simulation time 6128081018 ps
CPU time 39.44 seconds
Started May 09 12:33:32 PM PDT 24
Finished May 09 12:34:23 PM PDT 24
Peak memory 222420 kb
Host smart-675e74a3-b936-4d90-99f5-c477d50aaff5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271089740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.1271089740
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.1250103753
Short name T394
Test name
Test status
Simulation time 508098892 ps
CPU time 8.29 seconds
Started May 09 12:35:36 PM PDT 24
Finished May 09 12:35:52 PM PDT 24
Peak memory 214624 kb
Host smart-c2b856e6-04c0-43cb-9f1a-73191c5d24c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1250103753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.1250103753
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.2444177933
Short name T251
Test name
Test status
Simulation time 191440821 ps
CPU time 9.79 seconds
Started May 09 12:34:18 PM PDT 24
Finished May 09 12:34:36 PM PDT 24
Peak memory 215376 kb
Host smart-9782e0df-8dfa-44a6-a9df-9ca16ed120f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2444177933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.2444177933
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.653159310
Short name T46
Test name
Test status
Simulation time 556760843 ps
CPU time 18.24 seconds
Started May 09 12:33:59 PM PDT 24
Finished May 09 12:34:25 PM PDT 24
Peak memory 215364 kb
Host smart-01aa3818-09c0-4f90-8898-2e80e4a0f6a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653159310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.653159310
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.3903393388
Short name T20
Test name
Test status
Simulation time 404658498 ps
CPU time 2.37 seconds
Started May 09 12:34:38 PM PDT 24
Finished May 09 12:34:44 PM PDT 24
Peak memory 217508 kb
Host smart-cf233060-1b4e-4b65-9f92-cee04cb4b76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903393388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.3903393388
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.3947569725
Short name T60
Test name
Test status
Simulation time 77957716 ps
CPU time 3.82 seconds
Started May 09 12:33:49 PM PDT 24
Finished May 09 12:34:01 PM PDT 24
Peak memory 218888 kb
Host smart-bd51879d-a34f-4491-9f87-8ccd8c777814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947569725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.3947569725
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.3860260026
Short name T384
Test name
Test status
Simulation time 98808330 ps
CPU time 3.53 seconds
Started May 09 12:33:59 PM PDT 24
Finished May 09 12:34:10 PM PDT 24
Peak memory 214616 kb
Host smart-5a4e7825-e28a-467d-b13a-f587dd0b94c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3860260026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.3860260026
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.3760658811
Short name T145
Test name
Test status
Simulation time 69205896 ps
CPU time 2.31 seconds
Started May 09 12:35:26 PM PDT 24
Finished May 09 12:35:39 PM PDT 24
Peak memory 216912 kb
Host smart-38a4aa35-f019-462a-8f6e-e4ef0648b898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760658811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.3760658811
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.2411501403
Short name T29
Test name
Test status
Simulation time 121308404 ps
CPU time 2.34 seconds
Started May 09 12:34:35 PM PDT 24
Finished May 09 12:34:41 PM PDT 24
Peak memory 214148 kb
Host smart-459c3498-bf8f-4c08-84a5-557406ca25c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411501403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.2411501403
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.1066846712
Short name T271
Test name
Test status
Simulation time 1135451398 ps
CPU time 15.33 seconds
Started May 09 12:34:03 PM PDT 24
Finished May 09 12:34:28 PM PDT 24
Peak memory 215240 kb
Host smart-5a50a43d-ed41-4e1f-9831-ee56e6b0fd8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1066846712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.1066846712
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.1573424982
Short name T82
Test name
Test status
Simulation time 370300173 ps
CPU time 6.67 seconds
Started May 09 12:35:47 PM PDT 24
Finished May 09 12:36:00 PM PDT 24
Peak memory 214320 kb
Host smart-88b8152d-3429-4788-b92d-cd1dad09853d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573424982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.1573424982
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.3694048955
Short name T388
Test name
Test status
Simulation time 126869318 ps
CPU time 7.13 seconds
Started May 09 12:34:25 PM PDT 24
Finished May 09 12:34:39 PM PDT 24
Peak memory 215176 kb
Host smart-3a0269ea-944b-4a93-a7b6-af1bfe49a743
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3694048955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.3694048955
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.1155086598
Short name T154
Test name
Test status
Simulation time 159049820 ps
CPU time 6.4 seconds
Started May 09 01:07:47 PM PDT 24
Finished May 09 01:07:54 PM PDT 24
Peak memory 213788 kb
Host smart-4d048920-6fd0-4a26-8c24-91507411dbde
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155086598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.1155086598
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.3533278105
Short name T228
Test name
Test status
Simulation time 1774726812 ps
CPU time 22.28 seconds
Started May 09 12:35:29 PM PDT 24
Finished May 09 12:36:01 PM PDT 24
Peak memory 222316 kb
Host smart-f420ee92-16e4-417b-8ac7-4b0f76890e9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533278105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.3533278105
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.1566654482
Short name T18
Test name
Test status
Simulation time 25858258 ps
CPU time 0.93 seconds
Started May 09 12:34:58 PM PDT 24
Finished May 09 12:35:07 PM PDT 24
Peak memory 205952 kb
Host smart-a6853f0a-a97c-4796-978a-a9d72e51f492
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566654482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.1566654482
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.3857190038
Short name T137
Test name
Test status
Simulation time 210000224 ps
CPU time 3.84 seconds
Started May 09 12:33:36 PM PDT 24
Finished May 09 12:33:51 PM PDT 24
Peak memory 214152 kb
Host smart-3496310d-3fd3-4882-8e10-5b0bd1eb22c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3857190038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.3857190038
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.2607591198
Short name T87
Test name
Test status
Simulation time 763852906 ps
CPU time 3.25 seconds
Started May 09 12:34:29 PM PDT 24
Finished May 09 12:34:38 PM PDT 24
Peak memory 208764 kb
Host smart-b6b6a28f-2df1-4355-9b29-6ab795059850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607591198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.2607591198
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.981073823
Short name T88
Test name
Test status
Simulation time 62354752 ps
CPU time 3.7 seconds
Started May 09 12:34:37 PM PDT 24
Finished May 09 12:34:45 PM PDT 24
Peak memory 222280 kb
Host smart-d89039b3-4236-4a4a-a8ed-c7aa63bb7ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981073823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.981073823
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.1181231608
Short name T47
Test name
Test status
Simulation time 154185231 ps
CPU time 2.38 seconds
Started May 09 12:35:40 PM PDT 24
Finished May 09 12:35:48 PM PDT 24
Peak memory 220552 kb
Host smart-e25f94b7-18e9-4c3a-82f5-74153ea72dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181231608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.1181231608
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.1709202460
Short name T63
Test name
Test status
Simulation time 2994733299 ps
CPU time 31.32 seconds
Started May 09 12:33:50 PM PDT 24
Finished May 09 12:34:30 PM PDT 24
Peak memory 215796 kb
Host smart-8d7da3fb-8444-4022-a88b-90b95c0a8839
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709202460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.1709202460
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.1111125775
Short name T58
Test name
Test status
Simulation time 6695929416 ps
CPU time 62.16 seconds
Started May 09 12:34:22 PM PDT 24
Finished May 09 12:35:31 PM PDT 24
Peak memory 216680 kb
Host smart-eda06ac5-5495-490a-8d71-5ecbce7e43fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111125775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.1111125775
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.2712282176
Short name T113
Test name
Test status
Simulation time 803544940 ps
CPU time 9.98 seconds
Started May 09 01:07:23 PM PDT 24
Finished May 09 01:07:36 PM PDT 24
Peak memory 214332 kb
Host smart-1ff6c717-a1d6-4af3-abc5-75587265aac2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712282176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.2712282176
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.3881561880
Short name T319
Test name
Test status
Simulation time 75839224 ps
CPU time 3.51 seconds
Started May 09 12:35:07 PM PDT 24
Finished May 09 12:35:22 PM PDT 24
Peak memory 214476 kb
Host smart-725834b7-d037-4e9d-9d99-de766bb1069a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3881561880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.3881561880
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.1300620324
Short name T218
Test name
Test status
Simulation time 1451193782 ps
CPU time 36.06 seconds
Started May 09 12:35:46 PM PDT 24
Finished May 09 12:36:28 PM PDT 24
Peak memory 222388 kb
Host smart-0e33d51f-79cc-444d-9fcf-332a905be991
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300620324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.1300620324
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.343190575
Short name T33
Test name
Test status
Simulation time 285341509 ps
CPU time 3.73 seconds
Started May 09 12:35:09 PM PDT 24
Finished May 09 12:35:24 PM PDT 24
Peak memory 216688 kb
Host smart-ce2fc83f-32da-4341-a97f-4148eda7dcf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343190575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.343190575
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.699657313
Short name T44
Test name
Test status
Simulation time 5294195048 ps
CPU time 23 seconds
Started May 09 12:34:26 PM PDT 24
Finished May 09 12:34:55 PM PDT 24
Peak memory 222616 kb
Host smart-845646bc-0c4e-4044-b63f-873c30523db6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699657313 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.699657313
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.1896848874
Short name T246
Test name
Test status
Simulation time 50759196 ps
CPU time 3.16 seconds
Started May 09 12:34:09 PM PDT 24
Finished May 09 12:34:21 PM PDT 24
Peak memory 214192 kb
Host smart-fdaed7c3-6b28-4483-84a6-e24ec228e538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896848874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.1896848874
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.1482732621
Short name T152
Test name
Test status
Simulation time 318120252 ps
CPU time 7.92 seconds
Started May 09 01:07:38 PM PDT 24
Finished May 09 01:07:48 PM PDT 24
Peak memory 213800 kb
Host smart-8f6ec7be-5f50-4f05-b504-5aca30b35a47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482732621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.1482732621
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.1648344854
Short name T159
Test name
Test status
Simulation time 248670853 ps
CPU time 9.82 seconds
Started May 09 01:07:54 PM PDT 24
Finished May 09 01:08:06 PM PDT 24
Peak memory 213916 kb
Host smart-4f5f1987-6b3e-4225-b8b9-0872947f17cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648344854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.1648344854
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.4232038834
Short name T146
Test name
Test status
Simulation time 38948378 ps
CPU time 2.41 seconds
Started May 09 12:34:15 PM PDT 24
Finished May 09 12:34:26 PM PDT 24
Peak memory 222384 kb
Host smart-8aabaa31-e47c-4a61-81ea-21af35fa2c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232038834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.4232038834
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.4194020998
Short name T213
Test name
Test status
Simulation time 68852475911 ps
CPU time 675.6 seconds
Started May 09 12:34:02 PM PDT 24
Finished May 09 12:45:26 PM PDT 24
Peak memory 222468 kb
Host smart-3a817d7d-bcc0-463e-8d2d-68f1fd5f3d22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194020998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.4194020998
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.2487181090
Short name T35
Test name
Test status
Simulation time 1231597389 ps
CPU time 15.83 seconds
Started May 09 12:34:39 PM PDT 24
Finished May 09 12:35:00 PM PDT 24
Peak memory 210828 kb
Host smart-de33bd9a-9734-4145-a502-987c2d00e8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487181090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.2487181090
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.2367647554
Short name T245
Test name
Test status
Simulation time 66236126 ps
CPU time 2.47 seconds
Started May 09 12:34:16 PM PDT 24
Finished May 09 12:34:26 PM PDT 24
Peak memory 214204 kb
Host smart-01003c4e-7aea-42ce-a5f2-9cccf28b1239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367647554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.2367647554
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.3352333929
Short name T189
Test name
Test status
Simulation time 2735291401 ps
CPU time 47.25 seconds
Started May 09 12:34:28 PM PDT 24
Finished May 09 12:35:21 PM PDT 24
Peak memory 222644 kb
Host smart-1c7cc1f6-0f26-4650-86cc-a66f88090529
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352333929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.3352333929
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.1297098632
Short name T226
Test name
Test status
Simulation time 16061882264 ps
CPU time 170.07 seconds
Started May 09 12:34:37 PM PDT 24
Finished May 09 12:37:31 PM PDT 24
Peak memory 214688 kb
Host smart-dd9f9a94-e216-4852-9ab2-4bdd28359a30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1297098632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.1297098632
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.2797033742
Short name T71
Test name
Test status
Simulation time 930163628 ps
CPU time 10.42 seconds
Started May 09 12:34:45 PM PDT 24
Finished May 09 12:35:01 PM PDT 24
Peak memory 222468 kb
Host smart-24748671-65d7-403c-b2f0-944eacec08cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797033742 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.2797033742
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.1923382571
Short name T151
Test name
Test status
Simulation time 332146010 ps
CPU time 6.26 seconds
Started May 09 01:07:46 PM PDT 24
Finished May 09 01:07:54 PM PDT 24
Peak memory 213760 kb
Host smart-e1185431-976c-4f93-b0e8-b3bc415aa690
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923382571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.1923382571
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.57112159
Short name T160
Test name
Test status
Simulation time 353118785 ps
CPU time 4.32 seconds
Started May 09 01:07:24 PM PDT 24
Finished May 09 01:07:32 PM PDT 24
Peak memory 213736 kb
Host smart-85386a7d-3c73-431a-834f-fa90f397542b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57112159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err.57112159
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.3412841524
Short name T163
Test name
Test status
Simulation time 185712088 ps
CPU time 6.46 seconds
Started May 09 01:07:20 PM PDT 24
Finished May 09 01:07:27 PM PDT 24
Peak memory 213872 kb
Host smart-ee99085e-1d4f-4b21-ba74-706bdb7bbb4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412841524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.3412841524
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.3951995849
Short name T147
Test name
Test status
Simulation time 99631018 ps
CPU time 4.45 seconds
Started May 09 12:34:58 PM PDT 24
Finished May 09 12:35:10 PM PDT 24
Peak memory 217744 kb
Host smart-6e68d872-5a05-47d9-9c51-710540c247e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951995849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.3951995849
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.2535559955
Short name T825
Test name
Test status
Simulation time 550604905 ps
CPU time 25.28 seconds
Started May 09 12:33:39 PM PDT 24
Finished May 09 12:34:15 PM PDT 24
Peak memory 215628 kb
Host smart-364b4955-211c-4a54-832a-efe4c256e248
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535559955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.2535559955
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.3389440472
Short name T302
Test name
Test status
Simulation time 96684552 ps
CPU time 3.46 seconds
Started May 09 12:34:01 PM PDT 24
Finished May 09 12:34:13 PM PDT 24
Peak memory 214208 kb
Host smart-da78db30-c297-4e57-aeeb-4af2c78dc446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389440472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.3389440472
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.1089634451
Short name T81
Test name
Test status
Simulation time 648292585 ps
CPU time 17.14 seconds
Started May 09 12:34:56 PM PDT 24
Finished May 09 12:35:21 PM PDT 24
Peak memory 214548 kb
Host smart-f4299f2b-2d04-4acf-a85c-874436acc98d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1089634451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.1089634451
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.3202834995
Short name T207
Test name
Test status
Simulation time 227433456 ps
CPU time 6.64 seconds
Started May 09 12:34:59 PM PDT 24
Finished May 09 12:35:13 PM PDT 24
Peak memory 214520 kb
Host smart-9942703f-7e53-498a-a334-ab33298228e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202834995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.3202834995
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.3141612149
Short name T399
Test name
Test status
Simulation time 37087934 ps
CPU time 2.92 seconds
Started May 09 12:35:26 PM PDT 24
Finished May 09 12:35:39 PM PDT 24
Peak memory 214188 kb
Host smart-c80e1189-dda1-4f7c-94d4-6a6bb318006f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3141612149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.3141612149
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.937420281
Short name T148
Test name
Test status
Simulation time 80330301 ps
CPU time 2.53 seconds
Started May 09 12:35:51 PM PDT 24
Finished May 09 12:36:00 PM PDT 24
Peak memory 215128 kb
Host smart-9c6dcda4-ccb1-4f0e-b8fa-387e6c980625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937420281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.937420281
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.2358912267
Short name T282
Test name
Test status
Simulation time 353860499 ps
CPU time 2.92 seconds
Started May 09 12:34:45 PM PDT 24
Finished May 09 12:34:53 PM PDT 24
Peak memory 214436 kb
Host smart-3d246313-d616-40f3-a327-17a87a52bac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358912267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.2358912267
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.2811424727
Short name T223
Test name
Test status
Simulation time 32876080 ps
CPU time 2.51 seconds
Started May 09 12:33:31 PM PDT 24
Finished May 09 12:33:45 PM PDT 24
Peak memory 222248 kb
Host smart-aec0fb7a-7eaf-435a-9657-6988992fd4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811424727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.2811424727
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.3180077837
Short name T911
Test name
Test status
Simulation time 203058109 ps
CPU time 2.71 seconds
Started May 09 12:35:07 PM PDT 24
Finished May 09 12:35:22 PM PDT 24
Peak memory 222276 kb
Host smart-4e42262d-518c-4f0a-9a4f-00ab085a9f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180077837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.3180077837
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.525928322
Short name T397
Test name
Test status
Simulation time 141643923 ps
CPU time 4.72 seconds
Started May 09 12:35:22 PM PDT 24
Finished May 09 12:35:38 PM PDT 24
Peak memory 215804 kb
Host smart-d5974342-872a-4f20-b606-c5525aa88f08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=525928322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.525928322
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.842900386
Short name T157
Test name
Test status
Simulation time 543067057 ps
CPU time 7.99 seconds
Started May 09 01:07:35 PM PDT 24
Finished May 09 01:07:45 PM PDT 24
Peak memory 206048 kb
Host smart-a6583d47-8bea-45e3-a82b-476bdd2b343a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842900386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err
.842900386
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.3253734029
Short name T168
Test name
Test status
Simulation time 54364178 ps
CPU time 3.13 seconds
Started May 09 01:07:24 PM PDT 24
Finished May 09 01:07:30 PM PDT 24
Peak memory 213880 kb
Host smart-a5e2ca68-97d0-407f-813d-b6e1afb674fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253734029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.3253734029
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.663142509
Short name T149
Test name
Test status
Simulation time 534725401 ps
CPU time 4.67 seconds
Started May 09 01:07:39 PM PDT 24
Finished May 09 01:07:46 PM PDT 24
Peak memory 213892 kb
Host smart-5da48f6f-7e85-4e5c-924a-ec0705a5e4a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663142509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err.
663142509
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.3050324464
Short name T158
Test name
Test status
Simulation time 269573854 ps
CPU time 10.18 seconds
Started May 09 01:07:38 PM PDT 24
Finished May 09 01:07:50 PM PDT 24
Peak memory 205652 kb
Host smart-f2e77145-4277-408a-9d53-245c1ebb0f4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050324464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.3050324464
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.200183497
Short name T171
Test name
Test status
Simulation time 212796364 ps
CPU time 6.57 seconds
Started May 09 01:07:41 PM PDT 24
Finished May 09 01:07:50 PM PDT 24
Peak memory 213880 kb
Host smart-7ff14c7a-71ad-4ca4-9d64-7dd828360e6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200183497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err.
200183497
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.1497555176
Short name T156
Test name
Test status
Simulation time 205748689 ps
CPU time 4.57 seconds
Started May 09 01:07:55 PM PDT 24
Finished May 09 01:08:01 PM PDT 24
Peak memory 213852 kb
Host smart-7638829d-2ef4-4de8-96fa-32d6557c9e95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497555176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.1497555176
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.2675816971
Short name T383
Test name
Test status
Simulation time 92687587 ps
CPU time 3.62 seconds
Started May 09 12:33:42 PM PDT 24
Finished May 09 12:33:56 PM PDT 24
Peak memory 222232 kb
Host smart-579f25c1-ae8c-4e3d-a74e-db34dd5719db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2675816971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.2675816971
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.2816094545
Short name T506
Test name
Test status
Simulation time 78828165 ps
CPU time 2.59 seconds
Started May 09 12:33:39 PM PDT 24
Finished May 09 12:33:54 PM PDT 24
Peak memory 209804 kb
Host smart-688fd4ba-ce4f-4917-84da-713edbe22658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816094545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.2816094545
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.1554838177
Short name T360
Test name
Test status
Simulation time 179386528 ps
CPU time 4.08 seconds
Started May 09 12:33:39 PM PDT 24
Finished May 09 12:33:55 PM PDT 24
Peak memory 214040 kb
Host smart-bb4418a2-c3f6-4a8b-a39d-efee376c00f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554838177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.1554838177
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.3500943337
Short name T742
Test name
Test status
Simulation time 156839053 ps
CPU time 1.48 seconds
Started May 09 12:34:17 PM PDT 24
Finished May 09 12:34:27 PM PDT 24
Peak memory 209448 kb
Host smart-c8a5b0d7-57c9-42fa-91d9-05663a49ac5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500943337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.3500943337
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.1031104526
Short name T263
Test name
Test status
Simulation time 141310127 ps
CPU time 2.89 seconds
Started May 09 12:34:19 PM PDT 24
Finished May 09 12:34:30 PM PDT 24
Peak memory 214096 kb
Host smart-f28a4fd9-774d-47a3-afe0-b82d7dc524e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1031104526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.1031104526
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.236760542
Short name T36
Test name
Test status
Simulation time 1120889686 ps
CPU time 21.09 seconds
Started May 09 12:34:02 PM PDT 24
Finished May 09 12:34:32 PM PDT 24
Peak memory 221268 kb
Host smart-419ecf18-a723-4b63-a63d-4b108520d72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236760542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.236760542
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.4238990552
Short name T321
Test name
Test status
Simulation time 121405435 ps
CPU time 6.28 seconds
Started May 09 12:34:03 PM PDT 24
Finished May 09 12:34:18 PM PDT 24
Peak memory 214476 kb
Host smart-48bec82f-98d8-4044-a4c2-733537f24f26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4238990552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.4238990552
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.268230016
Short name T75
Test name
Test status
Simulation time 872706396 ps
CPU time 6.27 seconds
Started May 09 12:34:37 PM PDT 24
Finished May 09 12:34:47 PM PDT 24
Peak memory 208532 kb
Host smart-c840171d-5012-4bc8-b20e-160932270faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268230016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.268230016
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.2604544910
Short name T334
Test name
Test status
Simulation time 60620157 ps
CPU time 2.69 seconds
Started May 09 12:34:29 PM PDT 24
Finished May 09 12:34:37 PM PDT 24
Peak memory 214148 kb
Host smart-0db06aa6-2da2-4318-9a92-c72644228c2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2604544910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.2604544910
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.22332216
Short name T264
Test name
Test status
Simulation time 1287799221 ps
CPU time 3.5 seconds
Started May 09 12:34:20 PM PDT 24
Finished May 09 12:34:35 PM PDT 24
Peak memory 208876 kb
Host smart-61d9802a-cf3c-4046-897a-7b1078df4085
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22332216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.22332216
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.3437855560
Short name T8
Test name
Test status
Simulation time 674385217 ps
CPU time 2.27 seconds
Started May 09 12:34:23 PM PDT 24
Finished May 09 12:34:33 PM PDT 24
Peak memory 209564 kb
Host smart-51c6a27a-9dc4-4685-b0cb-82de0f74fe05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437855560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.3437855560
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.1250982894
Short name T805
Test name
Test status
Simulation time 136025463 ps
CPU time 2.96 seconds
Started May 09 12:34:03 PM PDT 24
Finished May 09 12:34:15 PM PDT 24
Peak memory 208644 kb
Host smart-a4c98e5b-1f24-41ea-bd36-5c613bae2cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250982894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.1250982894
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.1700491028
Short name T325
Test name
Test status
Simulation time 137396298 ps
CPU time 3.22 seconds
Started May 09 12:34:40 PM PDT 24
Finished May 09 12:34:48 PM PDT 24
Peak memory 214132 kb
Host smart-fc8512e4-d5cb-4cfc-a4ee-44cf263abdfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700491028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.1700491028
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.2407888791
Short name T217
Test name
Test status
Simulation time 86645570 ps
CPU time 4.53 seconds
Started May 09 12:34:07 PM PDT 24
Finished May 09 12:34:20 PM PDT 24
Peak memory 220012 kb
Host smart-3c2ae194-192d-4322-b55e-2b046ff73ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407888791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.2407888791
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.3187180197
Short name T359
Test name
Test status
Simulation time 55228945 ps
CPU time 2.73 seconds
Started May 09 12:34:15 PM PDT 24
Finished May 09 12:34:26 PM PDT 24
Peak memory 220544 kb
Host smart-a96b6d8f-df02-4c7c-ba80-7a0678226241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187180197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.3187180197
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.3801796062
Short name T235
Test name
Test status
Simulation time 211521809 ps
CPU time 3.64 seconds
Started May 09 12:34:34 PM PDT 24
Finished May 09 12:34:42 PM PDT 24
Peak memory 209632 kb
Host smart-49d62563-65b7-42d7-b619-9624dfe47639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801796062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.3801796062
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.64006326
Short name T209
Test name
Test status
Simulation time 2756128451 ps
CPU time 15.38 seconds
Started May 09 12:35:06 PM PDT 24
Finished May 09 12:35:39 PM PDT 24
Peak memory 220988 kb
Host smart-89cbf403-76b5-473f-9ea0-ad9402aa2c37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64006326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.64006326
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.773466047
Short name T206
Test name
Test status
Simulation time 195773575 ps
CPU time 4.47 seconds
Started May 09 12:35:12 PM PDT 24
Finished May 09 12:35:33 PM PDT 24
Peak memory 208920 kb
Host smart-5c7ed4d8-f7b9-4016-ae46-2f19d4416057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773466047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.773466047
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.1586209168
Short name T225
Test name
Test status
Simulation time 1066127433 ps
CPU time 13.63 seconds
Started May 09 12:35:08 PM PDT 24
Finished May 09 12:35:33 PM PDT 24
Peak memory 215620 kb
Host smart-a759a9b9-baac-4c12-aab4-806ce68a9c51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586209168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.1586209168
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.3434475795
Short name T309
Test name
Test status
Simulation time 63537492 ps
CPU time 2.33 seconds
Started May 09 12:35:04 PM PDT 24
Finished May 09 12:35:17 PM PDT 24
Peak memory 214164 kb
Host smart-e51c210f-b627-425c-9a14-23830843d3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434475795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.3434475795
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.3992553707
Short name T314
Test name
Test status
Simulation time 450622986 ps
CPU time 17.91 seconds
Started May 09 12:35:15 PM PDT 24
Finished May 09 12:35:44 PM PDT 24
Peak memory 222544 kb
Host smart-f7073478-875e-46cf-ac0c-200d9acb8792
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992553707 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.3992553707
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.3877445947
Short name T222
Test name
Test status
Simulation time 6267166088 ps
CPU time 49.41 seconds
Started May 09 12:35:28 PM PDT 24
Finished May 09 12:36:28 PM PDT 24
Peak memory 215244 kb
Host smart-d6f6f75a-1ab3-452d-9252-0e18eae716fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877445947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.3877445947
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.2544038594
Short name T219
Test name
Test status
Simulation time 399319023 ps
CPU time 12.13 seconds
Started May 09 12:35:44 PM PDT 24
Finished May 09 12:36:02 PM PDT 24
Peak memory 222468 kb
Host smart-ddcce16d-7e59-4213-a508-dd73dbb90648
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544038594 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.2544038594
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.661183262
Short name T979
Test name
Test status
Simulation time 187210983 ps
CPU time 6.48 seconds
Started May 09 01:07:24 PM PDT 24
Finished May 09 01:07:33 PM PDT 24
Peak memory 205596 kb
Host smart-2794c5c5-081d-410c-94c6-d8f884736d4f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661183262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.661183262
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.1818812872
Short name T1058
Test name
Test status
Simulation time 1385724864 ps
CPU time 12.42 seconds
Started May 09 01:07:25 PM PDT 24
Finished May 09 01:07:40 PM PDT 24
Peak memory 205624 kb
Host smart-da94917c-ed30-4765-8c1a-eea44e518f5d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818812872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.1
818812872
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.3919081972
Short name T925
Test name
Test status
Simulation time 76820920 ps
CPU time 0.91 seconds
Started May 09 01:07:25 PM PDT 24
Finished May 09 01:07:28 PM PDT 24
Peak memory 205360 kb
Host smart-8c63f63e-119b-41e0-a4ef-09391a683a2c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919081972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.3
919081972
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.3686816175
Short name T1080
Test name
Test status
Simulation time 211176318 ps
CPU time 1.19 seconds
Started May 09 01:07:27 PM PDT 24
Finished May 09 01:07:30 PM PDT 24
Peak memory 205712 kb
Host smart-98d5bd22-20e1-42dc-9782-d81edcf91633
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686816175 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.3686816175
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.4255076278
Short name T958
Test name
Test status
Simulation time 30263806 ps
CPU time 1.61 seconds
Started May 09 01:07:24 PM PDT 24
Finished May 09 01:07:28 PM PDT 24
Peak memory 205460 kb
Host smart-196114fd-8dea-4a7b-9c0a-db4416046c46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255076278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.4255076278
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.3775293937
Short name T928
Test name
Test status
Simulation time 11770365 ps
CPU time 0.76 seconds
Started May 09 01:07:22 PM PDT 24
Finished May 09 01:07:25 PM PDT 24
Peak memory 205332 kb
Host smart-0c1683ee-776f-45b3-9d63-8468d40c96ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775293937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.3775293937
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.1973178943
Short name T987
Test name
Test status
Simulation time 270756849 ps
CPU time 2.02 seconds
Started May 09 01:07:22 PM PDT 24
Finished May 09 01:07:25 PM PDT 24
Peak memory 205636 kb
Host smart-7e0cce23-c83e-430d-b985-039e9caf99c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973178943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.1973178943
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.2275868854
Short name T971
Test name
Test status
Simulation time 390518640 ps
CPU time 2.1 seconds
Started May 09 01:07:24 PM PDT 24
Finished May 09 01:07:29 PM PDT 24
Peak memory 214168 kb
Host smart-bcf5a7de-5779-4754-a88a-648a95cf63e2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275868854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.2275868854
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.3813491295
Short name T1040
Test name
Test status
Simulation time 691659577 ps
CPU time 4.13 seconds
Started May 09 01:07:21 PM PDT 24
Finished May 09 01:07:25 PM PDT 24
Peak memory 220280 kb
Host smart-d4131aa1-f754-4e5a-a315-81d2623ff21f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813491295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.3813491295
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1963856510
Short name T1031
Test name
Test status
Simulation time 50399380 ps
CPU time 3.35 seconds
Started May 09 01:07:24 PM PDT 24
Finished May 09 01:07:30 PM PDT 24
Peak memory 216844 kb
Host smart-8f5e8560-5741-4853-b127-3a3a670d85b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963856510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.1963856510
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.295079821
Short name T1055
Test name
Test status
Simulation time 116496319 ps
CPU time 3.69 seconds
Started May 09 01:07:23 PM PDT 24
Finished May 09 01:07:29 PM PDT 24
Peak memory 213752 kb
Host smart-2885e3ae-2eb9-4e4d-ae37-aa485665d56b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295079821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.
295079821
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2053854088
Short name T1049
Test name
Test status
Simulation time 914855934 ps
CPU time 6.73 seconds
Started May 09 01:07:24 PM PDT 24
Finished May 09 01:07:34 PM PDT 24
Peak memory 205472 kb
Host smart-a8abccc7-7a51-44d7-9008-e4da395a66ca
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053854088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.2
053854088
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.2719028973
Short name T1032
Test name
Test status
Simulation time 1936399631 ps
CPU time 12.9 seconds
Started May 09 01:07:21 PM PDT 24
Finished May 09 01:07:35 PM PDT 24
Peak memory 205608 kb
Host smart-17fd53be-f235-43fa-b7be-8c49081f9445
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719028973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.2
719028973
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.1169126727
Short name T933
Test name
Test status
Simulation time 20071542 ps
CPU time 1.23 seconds
Started May 09 01:07:25 PM PDT 24
Finished May 09 01:07:30 PM PDT 24
Peak memory 205712 kb
Host smart-26b449a6-5200-41f5-975d-8de5d6a529db
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169126727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.1
169126727
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1159273439
Short name T1045
Test name
Test status
Simulation time 138276306 ps
CPU time 1.24 seconds
Started May 09 01:07:23 PM PDT 24
Finished May 09 01:07:26 PM PDT 24
Peak memory 213972 kb
Host smart-9b48f9bf-7016-40cd-b491-6bbdcace49b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159273439 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.1159273439
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.3810711192
Short name T934
Test name
Test status
Simulation time 37260565 ps
CPU time 1.18 seconds
Started May 09 01:07:27 PM PDT 24
Finished May 09 01:07:30 PM PDT 24
Peak memory 205648 kb
Host smart-2b020dcb-a867-4d35-84c6-da729d2eee60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810711192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.3810711192
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1976913350
Short name T917
Test name
Test status
Simulation time 9307661 ps
CPU time 0.9 seconds
Started May 09 01:07:22 PM PDT 24
Finished May 09 01:07:24 PM PDT 24
Peak memory 205172 kb
Host smart-dc949cd7-3a9f-4217-86f5-f232a4ba7e14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976913350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.1976913350
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.2086617567
Short name T995
Test name
Test status
Simulation time 355801699 ps
CPU time 2.52 seconds
Started May 09 01:07:22 PM PDT 24
Finished May 09 01:07:25 PM PDT 24
Peak memory 205472 kb
Host smart-ce3afad0-5e8f-4777-9ff8-9ff78eb1cbfd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086617567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.2086617567
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.964145168
Short name T107
Test name
Test status
Simulation time 197879255 ps
CPU time 3.19 seconds
Started May 09 01:07:22 PM PDT 24
Finished May 09 01:07:27 PM PDT 24
Peak memory 214180 kb
Host smart-82e0daa1-959e-4b57-b28c-159b0f2915fe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964145168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow
_reg_errors.964145168
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3406471872
Short name T962
Test name
Test status
Simulation time 271799056 ps
CPU time 4.54 seconds
Started May 09 01:07:27 PM PDT 24
Finished May 09 01:07:34 PM PDT 24
Peak memory 220188 kb
Host smart-b5703a70-7305-4b13-96c9-376db11b1a36
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406471872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.3406471872
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.2301266900
Short name T986
Test name
Test status
Simulation time 301286906 ps
CPU time 3.46 seconds
Started May 09 01:07:25 PM PDT 24
Finished May 09 01:07:31 PM PDT 24
Peak memory 216244 kb
Host smart-4adc7e0b-e0e4-4282-bb4b-59d570c867a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301266900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.2301266900
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.2948320422
Short name T1011
Test name
Test status
Simulation time 1316807628 ps
CPU time 4.16 seconds
Started May 09 01:07:23 PM PDT 24
Finished May 09 01:07:29 PM PDT 24
Peak memory 213908 kb
Host smart-0be06bb2-7214-488b-80e9-111a1d97e522
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948320422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.2948320422
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1848781131
Short name T926
Test name
Test status
Simulation time 104782638 ps
CPU time 1.63 seconds
Started May 09 01:07:37 PM PDT 24
Finished May 09 01:07:40 PM PDT 24
Peak memory 214224 kb
Host smart-a3732970-a126-4ef4-b4cd-11f8a8394591
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848781131 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.1848781131
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.1964878172
Short name T931
Test name
Test status
Simulation time 16709018 ps
CPU time 0.97 seconds
Started May 09 01:07:35 PM PDT 24
Finished May 09 01:07:38 PM PDT 24
Peak memory 205388 kb
Host smart-54cf11ab-6339-4960-8d2b-7f79fc471dad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964878172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.1964878172
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.3597579671
Short name T915
Test name
Test status
Simulation time 35429008 ps
CPU time 0.72 seconds
Started May 09 01:07:36 PM PDT 24
Finished May 09 01:07:38 PM PDT 24
Peak memory 205256 kb
Host smart-ffe38bea-0879-4e58-a413-632724d4f146
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597579671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.3597579671
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.3775692676
Short name T1027
Test name
Test status
Simulation time 61229961 ps
CPU time 2.19 seconds
Started May 09 01:07:40 PM PDT 24
Finished May 09 01:07:44 PM PDT 24
Peak memory 205696 kb
Host smart-3315455f-7f39-4bb3-9574-29020d48406c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775692676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.3775692676
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.961081631
Short name T1041
Test name
Test status
Simulation time 86729974 ps
CPU time 2.64 seconds
Started May 09 01:07:36 PM PDT 24
Finished May 09 01:07:40 PM PDT 24
Peak memory 214208 kb
Host smart-cd5770da-4c00-4c23-a3e0-4d4cf73c353f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961081631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shado
w_reg_errors.961081631
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.1242896758
Short name T989
Test name
Test status
Simulation time 437707998 ps
CPU time 14.84 seconds
Started May 09 01:07:36 PM PDT 24
Finished May 09 01:07:53 PM PDT 24
Peak memory 214376 kb
Host smart-23d1b968-ab7a-49f0-817d-c88df6cd91de
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242896758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.1242896758
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.3298368195
Short name T957
Test name
Test status
Simulation time 33361596 ps
CPU time 1.61 seconds
Started May 09 01:07:39 PM PDT 24
Finished May 09 01:07:43 PM PDT 24
Peak memory 213868 kb
Host smart-70e1454b-7be5-4372-97f3-528c533fd284
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298368195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.3298368195
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3158744983
Short name T1030
Test name
Test status
Simulation time 31936095 ps
CPU time 1.31 seconds
Started May 09 01:07:49 PM PDT 24
Finished May 09 01:07:52 PM PDT 24
Peak memory 205640 kb
Host smart-d72fb522-31bf-425b-83bb-808ae919d953
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158744983 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.3158744983
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.1873615386
Short name T1004
Test name
Test status
Simulation time 32621667 ps
CPU time 0.9 seconds
Started May 09 01:07:46 PM PDT 24
Finished May 09 01:07:47 PM PDT 24
Peak memory 205372 kb
Host smart-39dfddd0-97ba-4e1d-ace7-f043fdd54751
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873615386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.1873615386
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.3550039547
Short name T1057
Test name
Test status
Simulation time 149146780 ps
CPU time 0.81 seconds
Started May 09 01:07:46 PM PDT 24
Finished May 09 01:07:48 PM PDT 24
Peak memory 205352 kb
Host smart-4d31c169-36f0-4694-9c56-3f05a131a78b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550039547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.3550039547
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.653735547
Short name T1054
Test name
Test status
Simulation time 624704163 ps
CPU time 3.97 seconds
Started May 09 01:07:45 PM PDT 24
Finished May 09 01:07:50 PM PDT 24
Peak memory 205580 kb
Host smart-23f32d0c-ef65-45f2-975b-6b8e680f3e22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653735547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_sa
me_csr_outstanding.653735547
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.2211261756
Short name T1062
Test name
Test status
Simulation time 163695638 ps
CPU time 1.76 seconds
Started May 09 01:07:35 PM PDT 24
Finished May 09 01:07:38 PM PDT 24
Peak memory 214248 kb
Host smart-0196450e-60bf-4d9f-83b2-14897601e73b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211261756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.2211261756
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3138444601
Short name T114
Test name
Test status
Simulation time 244420809 ps
CPU time 6.7 seconds
Started May 09 01:07:35 PM PDT 24
Finished May 09 01:07:44 PM PDT 24
Peak memory 220164 kb
Host smart-5ac16168-0b4d-490b-9bc0-f2862394a39a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138444601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.3138444601
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.3415337674
Short name T951
Test name
Test status
Simulation time 79067931 ps
CPU time 2.82 seconds
Started May 09 01:07:37 PM PDT 24
Finished May 09 01:07:41 PM PDT 24
Peak memory 217128 kb
Host smart-f56d8cff-7916-43b6-8fdb-cd5bb6cd819c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415337674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.3415337674
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.457573362
Short name T964
Test name
Test status
Simulation time 38759276 ps
CPU time 1.33 seconds
Started May 09 01:07:54 PM PDT 24
Finished May 09 01:07:57 PM PDT 24
Peak memory 205668 kb
Host smart-98c985a0-9564-4182-8cdd-47f5b6d3358b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457573362 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.457573362
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.916366641
Short name T945
Test name
Test status
Simulation time 47508327 ps
CPU time 1.21 seconds
Started May 09 01:07:48 PM PDT 24
Finished May 09 01:07:50 PM PDT 24
Peak memory 205672 kb
Host smart-16066030-90ff-4846-bf52-f4219c10845d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916366641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.916366641
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.3135693676
Short name T1026
Test name
Test status
Simulation time 38490499 ps
CPU time 0.79 seconds
Started May 09 01:07:52 PM PDT 24
Finished May 09 01:07:53 PM PDT 24
Peak memory 205272 kb
Host smart-af11fa53-7fdd-441f-adbc-6f98ec1cff04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135693676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.3135693676
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3805051275
Short name T948
Test name
Test status
Simulation time 981709675 ps
CPU time 3.73 seconds
Started May 09 01:07:53 PM PDT 24
Finished May 09 01:07:58 PM PDT 24
Peak memory 205484 kb
Host smart-b8bf7ef6-a2c3-47e8-b288-b28d936bd646
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805051275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.3805051275
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.639332782
Short name T1075
Test name
Test status
Simulation time 528517979 ps
CPU time 2.94 seconds
Started May 09 01:07:49 PM PDT 24
Finished May 09 01:07:53 PM PDT 24
Peak memory 214268 kb
Host smart-8f5e2d21-9777-4c41-8b46-b3b3d373fbf0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639332782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shado
w_reg_errors.639332782
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.3029452881
Short name T956
Test name
Test status
Simulation time 545604028 ps
CPU time 3.02 seconds
Started May 09 01:07:52 PM PDT 24
Finished May 09 01:07:57 PM PDT 24
Peak memory 214008 kb
Host smart-d6de88b0-a9f8-43a5-9f4b-29a03a759e35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029452881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.3029452881
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.2002180051
Short name T1051
Test name
Test status
Simulation time 26148094 ps
CPU time 1.15 seconds
Started May 09 01:07:54 PM PDT 24
Finished May 09 01:07:57 PM PDT 24
Peak memory 205604 kb
Host smart-324d4189-46a8-452f-aed4-4f9376a9efb9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002180051 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.2002180051
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.4290343122
Short name T953
Test name
Test status
Simulation time 102249917 ps
CPU time 1.54 seconds
Started May 09 01:07:53 PM PDT 24
Finished May 09 01:07:56 PM PDT 24
Peak memory 205696 kb
Host smart-58c1040c-0bc1-49fa-aede-9465630ec67b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290343122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.4290343122
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3895716150
Short name T922
Test name
Test status
Simulation time 47056322 ps
CPU time 0.75 seconds
Started May 09 01:07:48 PM PDT 24
Finished May 09 01:07:50 PM PDT 24
Peak memory 205372 kb
Host smart-664a7a9d-2a0c-4172-bf0a-3e64355abbf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895716150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.3895716150
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2310471508
Short name T959
Test name
Test status
Simulation time 93917517 ps
CPU time 2.64 seconds
Started May 09 01:07:49 PM PDT 24
Finished May 09 01:07:53 PM PDT 24
Peak memory 205556 kb
Host smart-a208d59e-6525-46c4-b5db-3b234abf03c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310471508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.2310471508
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2739643345
Short name T1036
Test name
Test status
Simulation time 289928412 ps
CPU time 2.95 seconds
Started May 09 01:07:54 PM PDT 24
Finished May 09 01:07:59 PM PDT 24
Peak memory 214148 kb
Host smart-161ed457-7a3a-4d22-97d6-49f978289cae
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739643345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.2739643345
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2761580952
Short name T1013
Test name
Test status
Simulation time 360811009 ps
CPU time 4.05 seconds
Started May 09 01:07:55 PM PDT 24
Finished May 09 01:08:01 PM PDT 24
Peak memory 214240 kb
Host smart-6bd21438-4e3e-4d9f-a291-d46b13c63557
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761580952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.2761580952
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.4095812264
Short name T974
Test name
Test status
Simulation time 147484951 ps
CPU time 2.71 seconds
Started May 09 01:07:47 PM PDT 24
Finished May 09 01:07:52 PM PDT 24
Peak memory 213904 kb
Host smart-b9f7ac7a-dd3a-4f3f-9468-52d29e86a64d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095812264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.4095812264
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.3056712587
Short name T1076
Test name
Test status
Simulation time 57667337 ps
CPU time 1.22 seconds
Started May 09 01:07:48 PM PDT 24
Finished May 09 01:07:51 PM PDT 24
Peak memory 205720 kb
Host smart-7144a790-4b88-4315-9570-ff7c8bb4db44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056712587 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.3056712587
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.3626210174
Short name T1018
Test name
Test status
Simulation time 17482903 ps
CPU time 1.11 seconds
Started May 09 01:07:55 PM PDT 24
Finished May 09 01:07:57 PM PDT 24
Peak memory 205668 kb
Host smart-7585b38a-b788-46e2-95cb-364fc94b6778
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626210174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.3626210174
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.3687973779
Short name T939
Test name
Test status
Simulation time 9759520 ps
CPU time 0.71 seconds
Started May 09 01:07:53 PM PDT 24
Finished May 09 01:07:55 PM PDT 24
Peak memory 205248 kb
Host smart-67cbfbb1-3137-4719-a8d4-6180d764cb24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687973779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.3687973779
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.589967773
Short name T142
Test name
Test status
Simulation time 91295096 ps
CPU time 4.05 seconds
Started May 09 01:08:09 PM PDT 24
Finished May 09 01:08:15 PM PDT 24
Peak memory 205700 kb
Host smart-544bb7f9-5212-4675-9d72-cff37b903c2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589967773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_sa
me_csr_outstanding.589967773
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.260951081
Short name T999
Test name
Test status
Simulation time 275573250 ps
CPU time 2.54 seconds
Started May 09 01:07:47 PM PDT 24
Finished May 09 01:07:51 PM PDT 24
Peak memory 214100 kb
Host smart-aefde9c6-67b0-43f9-a1fa-523cb14c3bc2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260951081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shado
w_reg_errors.260951081
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.3509514461
Short name T988
Test name
Test status
Simulation time 645955690 ps
CPU time 12.73 seconds
Started May 09 01:07:56 PM PDT 24
Finished May 09 01:08:10 PM PDT 24
Peak memory 214252 kb
Host smart-5ab62270-7a52-4cbf-976b-109b88eafbd6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509514461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.3509514461
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.3270915498
Short name T1050
Test name
Test status
Simulation time 46229700 ps
CPU time 2.93 seconds
Started May 09 01:07:49 PM PDT 24
Finished May 09 01:07:54 PM PDT 24
Peak memory 213824 kb
Host smart-6627641c-b986-413b-89ca-0875d8567f28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270915498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.3270915498
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.2156033089
Short name T164
Test name
Test status
Simulation time 818921179 ps
CPU time 5.55 seconds
Started May 09 01:07:47 PM PDT 24
Finished May 09 01:07:53 PM PDT 24
Peak memory 205620 kb
Host smart-85072fe1-5b19-4ae1-b5ed-d5f20e2a5d99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156033089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.2156033089
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3912538072
Short name T970
Test name
Test status
Simulation time 75826369 ps
CPU time 1.45 seconds
Started May 09 01:07:47 PM PDT 24
Finished May 09 01:07:50 PM PDT 24
Peak memory 217872 kb
Host smart-822c3199-2686-4552-b877-7aacf5e0d07c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912538072 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.3912538072
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.1122108825
Short name T952
Test name
Test status
Simulation time 62066978 ps
CPU time 0.96 seconds
Started May 09 01:07:49 PM PDT 24
Finished May 09 01:07:52 PM PDT 24
Peak memory 205488 kb
Host smart-99b64bc3-173f-4b2a-8c48-50f135e61831
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122108825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.1122108825
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.194603925
Short name T947
Test name
Test status
Simulation time 61426676 ps
CPU time 0.83 seconds
Started May 09 01:07:55 PM PDT 24
Finished May 09 01:07:57 PM PDT 24
Peak memory 205276 kb
Host smart-811401e4-9e43-478e-a4f2-58f6f853b743
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194603925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.194603925
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.1743191988
Short name T139
Test name
Test status
Simulation time 429943339 ps
CPU time 2.54 seconds
Started May 09 01:07:46 PM PDT 24
Finished May 09 01:07:50 PM PDT 24
Peak memory 205608 kb
Host smart-e248f038-cb55-4477-864a-0eda5be6f6d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743191988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.1743191988
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.4055863690
Short name T108
Test name
Test status
Simulation time 136076468 ps
CPU time 1.44 seconds
Started May 09 01:07:46 PM PDT 24
Finished May 09 01:07:48 PM PDT 24
Peak memory 214144 kb
Host smart-a86b9e2a-9132-44e0-9d88-47814d300fd8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055863690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.4055863690
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.4278229840
Short name T1083
Test name
Test status
Simulation time 461488942 ps
CPU time 8.46 seconds
Started May 09 01:07:46 PM PDT 24
Finished May 09 01:07:56 PM PDT 24
Peak memory 214064 kb
Host smart-da3c83ee-d00b-40c6-b1b2-ccf16e956e1f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278229840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.4278229840
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.3808455382
Short name T955
Test name
Test status
Simulation time 29326556 ps
CPU time 2.21 seconds
Started May 09 01:07:47 PM PDT 24
Finished May 09 01:07:51 PM PDT 24
Peak memory 215016 kb
Host smart-2ba013d1-cbf5-42cd-af5a-4f855731ca64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808455382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.3808455382
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.2930680738
Short name T1079
Test name
Test status
Simulation time 288960024 ps
CPU time 3.1 seconds
Started May 09 01:07:48 PM PDT 24
Finished May 09 01:07:53 PM PDT 24
Peak memory 205552 kb
Host smart-e840a73f-7217-4d47-b06d-5057fd76dcc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930680738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.2930680738
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.3408457066
Short name T980
Test name
Test status
Simulation time 51640380 ps
CPU time 1.12 seconds
Started May 09 01:07:52 PM PDT 24
Finished May 09 01:07:55 PM PDT 24
Peak memory 205628 kb
Host smart-e12d066e-44fb-4650-9d36-2a861376a78e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408457066 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.3408457066
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.81117630
Short name T965
Test name
Test status
Simulation time 80660499 ps
CPU time 1.07 seconds
Started May 09 01:07:52 PM PDT 24
Finished May 09 01:07:55 PM PDT 24
Peak memory 205512 kb
Host smart-db48f4ed-d0be-4301-be61-ff1d7a888727
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81117630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.81117630
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.4061061859
Short name T976
Test name
Test status
Simulation time 20056578 ps
CPU time 0.72 seconds
Started May 09 01:07:55 PM PDT 24
Finished May 09 01:07:57 PM PDT 24
Peak memory 205344 kb
Host smart-16f63b7d-e11b-4e92-ac8c-106c9e3fb9db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061061859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.4061061859
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.3540007445
Short name T967
Test name
Test status
Simulation time 72936076 ps
CPU time 1.49 seconds
Started May 09 01:07:55 PM PDT 24
Finished May 09 01:07:58 PM PDT 24
Peak memory 205652 kb
Host smart-606c6493-4a97-40e6-aefd-08ef162171c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540007445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.3540007445
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.2543793658
Short name T950
Test name
Test status
Simulation time 439218229 ps
CPU time 1.9 seconds
Started May 09 01:07:55 PM PDT 24
Finished May 09 01:07:58 PM PDT 24
Peak memory 214224 kb
Host smart-26d57215-1c29-46ee-b1a6-fe0863d4b77e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543793658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.2543793658
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.4046020537
Short name T106
Test name
Test status
Simulation time 357464590 ps
CPU time 6.3 seconds
Started May 09 01:07:46 PM PDT 24
Finished May 09 01:07:54 PM PDT 24
Peak memory 214232 kb
Host smart-84d577e9-f20d-477f-87a9-31d44a0e907f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046020537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.4046020537
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.1799761097
Short name T961
Test name
Test status
Simulation time 71279399 ps
CPU time 2.6 seconds
Started May 09 01:07:47 PM PDT 24
Finished May 09 01:07:51 PM PDT 24
Peak memory 213924 kb
Host smart-ad4594af-0d95-45d8-b3d3-8c4b9621f7b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799761097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.1799761097
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3088901260
Short name T1020
Test name
Test status
Simulation time 112061226 ps
CPU time 1.53 seconds
Started May 09 01:07:46 PM PDT 24
Finished May 09 01:07:48 PM PDT 24
Peak memory 213740 kb
Host smart-da249e33-4c88-483e-908c-0865cf45b9ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088901260 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.3088901260
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.1322686134
Short name T1005
Test name
Test status
Simulation time 20231605 ps
CPU time 1.31 seconds
Started May 09 01:07:55 PM PDT 24
Finished May 09 01:07:58 PM PDT 24
Peak memory 205672 kb
Host smart-9bb0be65-3892-4dc2-a047-373e73a949a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322686134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.1322686134
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.3590170739
Short name T1022
Test name
Test status
Simulation time 213163685 ps
CPU time 0.72 seconds
Started May 09 01:07:55 PM PDT 24
Finished May 09 01:07:57 PM PDT 24
Peak memory 205352 kb
Host smart-8d79d836-7e36-4d70-99d9-3789d8fcd085
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590170739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.3590170739
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.1296885095
Short name T1003
Test name
Test status
Simulation time 34334956 ps
CPU time 1.45 seconds
Started May 09 01:07:53 PM PDT 24
Finished May 09 01:07:56 PM PDT 24
Peak memory 205632 kb
Host smart-d0bacbf8-bf8a-4caa-8a21-8eff1e789532
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296885095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.1296885095
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.2735283343
Short name T111
Test name
Test status
Simulation time 128128241 ps
CPU time 2.46 seconds
Started May 09 01:07:47 PM PDT 24
Finished May 09 01:07:51 PM PDT 24
Peak memory 214240 kb
Host smart-8b663f4c-4dc1-4475-bab9-91aeb20d8f26
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735283343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.2735283343
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2227710367
Short name T1066
Test name
Test status
Simulation time 941708208 ps
CPU time 8.59 seconds
Started May 09 01:07:49 PM PDT 24
Finished May 09 01:07:59 PM PDT 24
Peak memory 214200 kb
Host smart-bc9089c3-0528-4dc2-90d9-04df76790b58
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227710367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.2227710367
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.3830757380
Short name T1071
Test name
Test status
Simulation time 72424872 ps
CPU time 2.09 seconds
Started May 09 01:07:54 PM PDT 24
Finished May 09 01:07:57 PM PDT 24
Peak memory 213828 kb
Host smart-adea19fc-5dad-4795-8388-80f2492d565e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830757380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.3830757380
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.426849077
Short name T921
Test name
Test status
Simulation time 106206259 ps
CPU time 1.91 seconds
Started May 09 01:08:00 PM PDT 24
Finished May 09 01:08:04 PM PDT 24
Peak memory 213804 kb
Host smart-efe08d34-6322-458f-9f89-8683b3facd8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426849077 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.426849077
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.238542554
Short name T140
Test name
Test status
Simulation time 45110460 ps
CPU time 1.17 seconds
Started May 09 01:08:01 PM PDT 24
Finished May 09 01:08:05 PM PDT 24
Peak memory 205620 kb
Host smart-b490ab12-60d6-4dc6-820b-7b6c99676047
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238542554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.238542554
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.3539400127
Short name T1081
Test name
Test status
Simulation time 22042030 ps
CPU time 0.8 seconds
Started May 09 01:08:04 PM PDT 24
Finished May 09 01:08:07 PM PDT 24
Peak memory 205244 kb
Host smart-9caa1a7a-7465-4ddb-83aa-cefb4cdbf993
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539400127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.3539400127
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.511449020
Short name T1052
Test name
Test status
Simulation time 480946890 ps
CPU time 4.03 seconds
Started May 09 01:08:00 PM PDT 24
Finished May 09 01:08:06 PM PDT 24
Peak memory 205612 kb
Host smart-185f7062-7282-48b9-8de6-9ad510d241a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511449020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_sa
me_csr_outstanding.511449020
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.408220551
Short name T109
Test name
Test status
Simulation time 86724141 ps
CPU time 1.77 seconds
Started May 09 01:07:48 PM PDT 24
Finished May 09 01:07:51 PM PDT 24
Peak memory 214252 kb
Host smart-e5654e86-72b0-4447-8135-5ad3e5cd83c6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408220551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shado
w_reg_errors.408220551
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.2749739833
Short name T1056
Test name
Test status
Simulation time 593833796 ps
CPU time 5.85 seconds
Started May 09 01:08:02 PM PDT 24
Finished May 09 01:08:11 PM PDT 24
Peak memory 214064 kb
Host smart-c4f3d05e-9d4e-441a-abe2-1e57c3e9dcc9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749739833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.2749739833
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.3124150446
Short name T166
Test name
Test status
Simulation time 207258638 ps
CPU time 4.97 seconds
Started May 09 01:08:04 PM PDT 24
Finished May 09 01:08:11 PM PDT 24
Peak memory 213892 kb
Host smart-1b505aa6-3c7d-44f8-a14e-81afeb946209
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124150446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.3124150446
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.2014998586
Short name T1021
Test name
Test status
Simulation time 276494192 ps
CPU time 2.32 seconds
Started May 09 01:08:02 PM PDT 24
Finished May 09 01:08:07 PM PDT 24
Peak memory 213768 kb
Host smart-bb6bed34-5637-40db-b2a3-0be3c9e1890b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014998586 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.2014998586
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.29347333
Short name T1073
Test name
Test status
Simulation time 19983283 ps
CPU time 0.96 seconds
Started May 09 01:08:01 PM PDT 24
Finished May 09 01:08:04 PM PDT 24
Peak memory 205396 kb
Host smart-c31474a1-7662-4903-90e1-f6e3e8f79620
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29347333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.29347333
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.419370728
Short name T975
Test name
Test status
Simulation time 162391295 ps
CPU time 0.75 seconds
Started May 09 01:08:01 PM PDT 24
Finished May 09 01:08:03 PM PDT 24
Peak memory 205296 kb
Host smart-818f714e-9605-4c22-bb54-ba99c56b6a3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419370728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.419370728
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1259968629
Short name T998
Test name
Test status
Simulation time 455381914 ps
CPU time 2.25 seconds
Started May 09 01:08:00 PM PDT 24
Finished May 09 01:08:04 PM PDT 24
Peak memory 205656 kb
Host smart-a7c4f9ad-336f-4e84-b9e4-7a820f0bb7e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259968629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.1259968629
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.582606783
Short name T1016
Test name
Test status
Simulation time 310328828 ps
CPU time 2.52 seconds
Started May 09 01:08:01 PM PDT 24
Finished May 09 01:08:05 PM PDT 24
Peak memory 214220 kb
Host smart-dbb36fbf-ce47-4f36-a85a-5162679325d1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582606783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shado
w_reg_errors.582606783
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.3441066016
Short name T1006
Test name
Test status
Simulation time 251104365 ps
CPU time 8.48 seconds
Started May 09 01:08:05 PM PDT 24
Finished May 09 01:08:15 PM PDT 24
Peak memory 214268 kb
Host smart-448f2601-3082-4b29-9806-dff56d6d8124
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441066016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.3441066016
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.614395329
Short name T963
Test name
Test status
Simulation time 454989629 ps
CPU time 3.42 seconds
Started May 09 01:08:03 PM PDT 24
Finished May 09 01:08:09 PM PDT 24
Peak memory 216532 kb
Host smart-67b410ac-28ec-4f36-92cb-61576b11bc86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614395329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.614395329
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.649749864
Short name T155
Test name
Test status
Simulation time 213281955 ps
CPU time 4.2 seconds
Started May 09 01:08:02 PM PDT 24
Finished May 09 01:08:08 PM PDT 24
Peak memory 213932 kb
Host smart-26dedb62-d8ab-4506-b562-f4fa7adacd52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649749864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_err
.649749864
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.679160047
Short name T1014
Test name
Test status
Simulation time 715631909 ps
CPU time 9.91 seconds
Started May 09 01:07:24 PM PDT 24
Finished May 09 01:07:36 PM PDT 24
Peak memory 205720 kb
Host smart-96ec1ce2-f754-4565-a5cd-e2f4c2cf3ca5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679160047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.679160047
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.2189178640
Short name T1034
Test name
Test status
Simulation time 1408314013 ps
CPU time 14.26 seconds
Started May 09 01:07:24 PM PDT 24
Finished May 09 01:07:41 PM PDT 24
Peak memory 205640 kb
Host smart-222b4632-2ef0-4fc8-81cd-577d7e4b4e96
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189178640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.2
189178640
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.3898072276
Short name T1023
Test name
Test status
Simulation time 124875995 ps
CPU time 1.21 seconds
Started May 09 01:07:22 PM PDT 24
Finished May 09 01:07:25 PM PDT 24
Peak memory 205732 kb
Host smart-138b0fd4-83c4-4a38-9420-8efd2912352e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898072276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.3
898072276
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1814095590
Short name T1043
Test name
Test status
Simulation time 86531654 ps
CPU time 1.12 seconds
Started May 09 01:07:24 PM PDT 24
Finished May 09 01:07:28 PM PDT 24
Peak memory 205528 kb
Host smart-9ba5561e-ea7d-439e-ab3f-d635a66c1c94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814095590 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.1814095590
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.631576099
Short name T1077
Test name
Test status
Simulation time 108082164 ps
CPU time 1.26 seconds
Started May 09 01:07:25 PM PDT 24
Finished May 09 01:07:29 PM PDT 24
Peak memory 205920 kb
Host smart-ff474856-fef6-4a3e-b9ef-9e480f4c7363
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631576099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.631576099
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.4159793801
Short name T1084
Test name
Test status
Simulation time 38051920 ps
CPU time 0.81 seconds
Started May 09 01:07:24 PM PDT 24
Finished May 09 01:07:27 PM PDT 24
Peak memory 205340 kb
Host smart-2865c8c4-3c77-4fbd-9a12-e4c31844b07d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159793801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.4159793801
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2421246156
Short name T1061
Test name
Test status
Simulation time 105231556 ps
CPU time 1.63 seconds
Started May 09 01:07:25 PM PDT 24
Finished May 09 01:07:30 PM PDT 24
Peak memory 205548 kb
Host smart-c33c1afa-ea06-428c-a294-2120f65d0568
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421246156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.2421246156
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.2631505601
Short name T1039
Test name
Test status
Simulation time 265074929 ps
CPU time 2.87 seconds
Started May 09 01:07:22 PM PDT 24
Finished May 09 01:07:26 PM PDT 24
Peak memory 214228 kb
Host smart-bf1c5d02-95e7-4d01-9d2b-1e37023d4697
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631505601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.2631505601
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.3012290101
Short name T1017
Test name
Test status
Simulation time 116303958 ps
CPU time 2.8 seconds
Started May 09 01:07:24 PM PDT 24
Finished May 09 01:07:30 PM PDT 24
Peak memory 213952 kb
Host smart-f36ccded-0f66-4e97-b639-af17bdffadd5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012290101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.3012290101
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.2723023886
Short name T1060
Test name
Test status
Simulation time 11613696 ps
CPU time 0.73 seconds
Started May 09 01:08:03 PM PDT 24
Finished May 09 01:08:06 PM PDT 24
Peak memory 205256 kb
Host smart-9a3871a6-9418-4156-9609-fb8c94bbec57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723023886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.2723023886
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.3478879141
Short name T1072
Test name
Test status
Simulation time 36749733 ps
CPU time 0.7 seconds
Started May 09 01:08:01 PM PDT 24
Finished May 09 01:08:04 PM PDT 24
Peak memory 205332 kb
Host smart-46e09ff4-157e-4735-a26f-997495e91b87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478879141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.3478879141
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.1574068141
Short name T1038
Test name
Test status
Simulation time 26719723 ps
CPU time 0.81 seconds
Started May 09 01:08:02 PM PDT 24
Finished May 09 01:08:06 PM PDT 24
Peak memory 205336 kb
Host smart-b8685f3e-26c7-4179-8c39-65c04f91a233
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574068141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.1574068141
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.1726699612
Short name T1012
Test name
Test status
Simulation time 18128468 ps
CPU time 0.86 seconds
Started May 09 01:08:05 PM PDT 24
Finished May 09 01:08:08 PM PDT 24
Peak memory 205356 kb
Host smart-13ce6c60-635c-4dc9-a137-39b00f0878af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726699612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.1726699612
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.3369446059
Short name T1009
Test name
Test status
Simulation time 19098718 ps
CPU time 0.81 seconds
Started May 09 01:08:01 PM PDT 24
Finished May 09 01:08:04 PM PDT 24
Peak memory 205304 kb
Host smart-265b7000-6a98-445e-96f6-63fa2a75524c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369446059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.3369446059
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.85170569
Short name T1065
Test name
Test status
Simulation time 37254691 ps
CPU time 0.83 seconds
Started May 09 01:08:05 PM PDT 24
Finished May 09 01:08:08 PM PDT 24
Peak memory 205368 kb
Host smart-c403edd5-a4cb-4195-a487-c67af8327521
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85170569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.85170569
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.2927893880
Short name T936
Test name
Test status
Simulation time 10587580 ps
CPU time 0.7 seconds
Started May 09 01:08:00 PM PDT 24
Finished May 09 01:08:02 PM PDT 24
Peak memory 205364 kb
Host smart-4665ac0b-7537-43d1-9ee8-7fbe5660d064
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927893880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.2927893880
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.3974271771
Short name T1044
Test name
Test status
Simulation time 38517422 ps
CPU time 0.72 seconds
Started May 09 01:08:01 PM PDT 24
Finished May 09 01:08:03 PM PDT 24
Peak memory 205320 kb
Host smart-4168d2e9-6cb5-4825-ae7d-89f64fc32ae4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974271771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.3974271771
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.2626945161
Short name T960
Test name
Test status
Simulation time 10368505 ps
CPU time 0.73 seconds
Started May 09 01:08:03 PM PDT 24
Finished May 09 01:08:07 PM PDT 24
Peak memory 205376 kb
Host smart-9369528e-7604-44ed-bd59-e28b5f903b1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626945161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.2626945161
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.4170726432
Short name T1001
Test name
Test status
Simulation time 9946846 ps
CPU time 0.85 seconds
Started May 09 01:08:02 PM PDT 24
Finished May 09 01:08:05 PM PDT 24
Peak memory 205288 kb
Host smart-3a9be7f4-a0a7-4bdb-8279-8808aed057af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170726432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.4170726432
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.1383629291
Short name T1000
Test name
Test status
Simulation time 246139752 ps
CPU time 7.17 seconds
Started May 09 01:07:22 PM PDT 24
Finished May 09 01:07:31 PM PDT 24
Peak memory 205668 kb
Host smart-eba94870-2e8a-473f-bc6f-21b70c1a0591
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383629291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.1
383629291
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2206782463
Short name T1029
Test name
Test status
Simulation time 2592268749 ps
CPU time 9.42 seconds
Started May 09 01:07:25 PM PDT 24
Finished May 09 01:07:37 PM PDT 24
Peak memory 205936 kb
Host smart-fd62410a-9fdd-475b-8eaa-bb7615831146
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206782463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.2
206782463
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.2174471181
Short name T997
Test name
Test status
Simulation time 59230890 ps
CPU time 1.5 seconds
Started May 09 01:07:21 PM PDT 24
Finished May 09 01:07:24 PM PDT 24
Peak memory 205508 kb
Host smart-ec1412bf-fbe0-496d-af29-911aaf1502bd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174471181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.2
174471181
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2798095514
Short name T1008
Test name
Test status
Simulation time 129652978 ps
CPU time 2.08 seconds
Started May 09 01:07:24 PM PDT 24
Finished May 09 01:07:29 PM PDT 24
Peak memory 213868 kb
Host smart-364bd1da-9361-4de6-a0f4-77e252c30eec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798095514 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.2798095514
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.3928363427
Short name T1048
Test name
Test status
Simulation time 75488089 ps
CPU time 1.13 seconds
Started May 09 01:07:23 PM PDT 24
Finished May 09 01:07:26 PM PDT 24
Peak memory 205692 kb
Host smart-177f2e9e-e336-4a9e-bd29-2b8a6c3f8b94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928363427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.3928363427
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.370226983
Short name T968
Test name
Test status
Simulation time 20616926 ps
CPU time 0.83 seconds
Started May 09 01:07:29 PM PDT 24
Finished May 09 01:07:31 PM PDT 24
Peak memory 205180 kb
Host smart-8502d130-d350-4648-b9ea-59ac44750aba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370226983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.370226983
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.2685846197
Short name T1019
Test name
Test status
Simulation time 39234647 ps
CPU time 1.31 seconds
Started May 09 01:07:21 PM PDT 24
Finished May 09 01:07:22 PM PDT 24
Peak memory 205656 kb
Host smart-44b3773d-e8ad-4ebd-8fba-5ec36dff9bf4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685846197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.2685846197
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.2451832366
Short name T996
Test name
Test status
Simulation time 108225452 ps
CPU time 1.89 seconds
Started May 09 01:07:23 PM PDT 24
Finished May 09 01:07:27 PM PDT 24
Peak memory 214232 kb
Host smart-6dcd3561-8a68-49cb-a0ae-0d0929663754
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451832366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.2451832366
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.3015021123
Short name T937
Test name
Test status
Simulation time 1456947889 ps
CPU time 4.13 seconds
Started May 09 01:07:29 PM PDT 24
Finished May 09 01:07:35 PM PDT 24
Peak memory 214148 kb
Host smart-81a66eda-cec9-43db-af93-595cd813b29c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015021123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.3015021123
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.3564346881
Short name T985
Test name
Test status
Simulation time 189162108 ps
CPU time 4.17 seconds
Started May 09 01:07:26 PM PDT 24
Finished May 09 01:07:33 PM PDT 24
Peak memory 213868 kb
Host smart-3f765700-5cd1-44f3-b00e-935ce22df2a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564346881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.3564346881
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.3999910968
Short name T941
Test name
Test status
Simulation time 27924430 ps
CPU time 0.76 seconds
Started May 09 01:08:04 PM PDT 24
Finished May 09 01:08:07 PM PDT 24
Peak memory 205376 kb
Host smart-09285dba-815c-4b80-85b5-a074746f2886
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999910968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.3999910968
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.392286281
Short name T929
Test name
Test status
Simulation time 12555596 ps
CPU time 0.73 seconds
Started May 09 01:08:02 PM PDT 24
Finished May 09 01:08:05 PM PDT 24
Peak memory 205420 kb
Host smart-51d9998d-5a26-4e57-b9e3-0fafd9f5e50c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392286281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.392286281
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.1818084937
Short name T927
Test name
Test status
Simulation time 41979814 ps
CPU time 0.73 seconds
Started May 09 01:08:01 PM PDT 24
Finished May 09 01:08:04 PM PDT 24
Peak memory 205284 kb
Host smart-aadc4f12-51b9-4ec3-abe6-94f48b2f9e85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818084937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.1818084937
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.724005680
Short name T984
Test name
Test status
Simulation time 12372197 ps
CPU time 0.79 seconds
Started May 09 01:08:01 PM PDT 24
Finished May 09 01:08:04 PM PDT 24
Peak memory 205292 kb
Host smart-5c4cf68a-3920-44d9-9a82-6d0242bc7db3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724005680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.724005680
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.2265234517
Short name T1042
Test name
Test status
Simulation time 58609231 ps
CPU time 0.74 seconds
Started May 09 01:08:02 PM PDT 24
Finished May 09 01:08:06 PM PDT 24
Peak memory 205212 kb
Host smart-ed426756-07bb-4a8d-ae0a-fbe2bb572af5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265234517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.2265234517
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.2714168639
Short name T982
Test name
Test status
Simulation time 8514221 ps
CPU time 0.76 seconds
Started May 09 01:08:04 PM PDT 24
Finished May 09 01:08:07 PM PDT 24
Peak memory 205360 kb
Host smart-8ef8c9aa-ee06-4c12-a6b3-1791c01a982e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714168639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.2714168639
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.4044852328
Short name T1015
Test name
Test status
Simulation time 26942139 ps
CPU time 0.9 seconds
Started May 09 01:08:05 PM PDT 24
Finished May 09 01:08:08 PM PDT 24
Peak memory 205356 kb
Host smart-370be756-dc28-4fb1-8c42-793c1b338599
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044852328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.4044852328
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.877717441
Short name T923
Test name
Test status
Simulation time 23552432 ps
CPU time 0.77 seconds
Started May 09 01:08:02 PM PDT 24
Finished May 09 01:08:05 PM PDT 24
Peak memory 205364 kb
Host smart-92dd87a0-ca83-401d-83d0-27d396a6d401
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877717441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.877717441
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.2132592969
Short name T942
Test name
Test status
Simulation time 29097020 ps
CPU time 0.8 seconds
Started May 09 01:08:02 PM PDT 24
Finished May 09 01:08:06 PM PDT 24
Peak memory 205352 kb
Host smart-fa61595a-b679-47e7-bae4-b69e3db2fcf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132592969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.2132592969
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.2919540145
Short name T991
Test name
Test status
Simulation time 20576725 ps
CPU time 0.72 seconds
Started May 09 01:08:04 PM PDT 24
Finished May 09 01:08:07 PM PDT 24
Peak memory 205164 kb
Host smart-741ef27b-f6ea-48d8-936a-dbfe024fb0cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919540145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.2919540145
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.3981970268
Short name T972
Test name
Test status
Simulation time 227145030 ps
CPU time 7.35 seconds
Started May 09 01:07:22 PM PDT 24
Finished May 09 01:07:30 PM PDT 24
Peak memory 205644 kb
Host smart-91bb93d1-3d22-4a35-bd91-48f1ea94cf9f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981970268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.3
981970268
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2461460167
Short name T935
Test name
Test status
Simulation time 1747990374 ps
CPU time 24.2 seconds
Started May 09 01:07:21 PM PDT 24
Finished May 09 01:07:47 PM PDT 24
Peak memory 205580 kb
Host smart-a6364d38-37c9-4bb9-a500-7bce971e1053
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461460167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.2
461460167
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.2574859541
Short name T1064
Test name
Test status
Simulation time 27581828 ps
CPU time 1.12 seconds
Started May 09 01:07:26 PM PDT 24
Finished May 09 01:07:30 PM PDT 24
Peak memory 205652 kb
Host smart-e39a34d6-303e-4f6b-9666-0466ae491b4c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574859541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.2
574859541
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.2704088680
Short name T924
Test name
Test status
Simulation time 39547154 ps
CPU time 1.47 seconds
Started May 09 01:07:35 PM PDT 24
Finished May 09 01:07:38 PM PDT 24
Peak memory 213896 kb
Host smart-d0596718-3846-4235-b7b3-04f452a2fc9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704088680 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.2704088680
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.370797548
Short name T141
Test name
Test status
Simulation time 85049615 ps
CPU time 1.17 seconds
Started May 09 01:07:24 PM PDT 24
Finished May 09 01:07:28 PM PDT 24
Peak memory 205672 kb
Host smart-87b25c08-77c9-4fde-af71-5bea1d330083
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370797548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.370797548
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.982626692
Short name T1074
Test name
Test status
Simulation time 12253105 ps
CPU time 0.7 seconds
Started May 09 01:07:24 PM PDT 24
Finished May 09 01:07:27 PM PDT 24
Peak memory 205340 kb
Host smart-b68a2e08-61b7-4156-9cc6-fdb6b831b833
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982626692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.982626692
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2117580488
Short name T143
Test name
Test status
Simulation time 143633578 ps
CPU time 2.11 seconds
Started May 09 01:07:37 PM PDT 24
Finished May 09 01:07:41 PM PDT 24
Peak memory 205540 kb
Host smart-6fbb529d-d260-4407-b086-45a62dee410f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117580488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.2117580488
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.2760531358
Short name T1028
Test name
Test status
Simulation time 514789448 ps
CPU time 2.98 seconds
Started May 09 01:07:25 PM PDT 24
Finished May 09 01:07:31 PM PDT 24
Peak memory 214184 kb
Host smart-ab3a61c5-d475-42e3-a914-be58a7603c6e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760531358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.2760531358
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.2927237640
Short name T1063
Test name
Test status
Simulation time 652689115 ps
CPU time 6.68 seconds
Started May 09 01:07:23 PM PDT 24
Finished May 09 01:07:31 PM PDT 24
Peak memory 214080 kb
Host smart-f9e981af-c819-4bec-a341-3528581f44c9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927237640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.2927237640
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.4132373136
Short name T918
Test name
Test status
Simulation time 56777090 ps
CPU time 1.89 seconds
Started May 09 01:07:29 PM PDT 24
Finished May 09 01:07:32 PM PDT 24
Peak memory 215920 kb
Host smart-e097447b-e866-4c63-b239-48e5664daaaa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132373136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.4132373136
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.1274826970
Short name T916
Test name
Test status
Simulation time 18120883 ps
CPU time 0.77 seconds
Started May 09 01:08:02 PM PDT 24
Finished May 09 01:08:05 PM PDT 24
Peak memory 205272 kb
Host smart-f1587f5e-6c21-466e-8974-e3e79b759f0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274826970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.1274826970
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.83084132
Short name T1024
Test name
Test status
Simulation time 52960212 ps
CPU time 0.72 seconds
Started May 09 01:08:03 PM PDT 24
Finished May 09 01:08:06 PM PDT 24
Peak memory 205336 kb
Host smart-f9cfa2ec-2d47-4576-aee2-e2551a2553b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83084132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.83084132
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.2956837321
Short name T1010
Test name
Test status
Simulation time 58048939 ps
CPU time 0.84 seconds
Started May 09 01:08:01 PM PDT 24
Finished May 09 01:08:04 PM PDT 24
Peak memory 205372 kb
Host smart-6b535dd5-7c03-42a8-b828-a9b3d639a72e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956837321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.2956837321
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.3831132811
Short name T944
Test name
Test status
Simulation time 12621047 ps
CPU time 0.85 seconds
Started May 09 01:08:02 PM PDT 24
Finished May 09 01:08:05 PM PDT 24
Peak memory 205360 kb
Host smart-cd00b2d4-e82e-457a-8c11-b2289ffb66cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831132811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.3831132811
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.3778910557
Short name T978
Test name
Test status
Simulation time 11155229 ps
CPU time 0.71 seconds
Started May 09 01:08:01 PM PDT 24
Finished May 09 01:08:03 PM PDT 24
Peak memory 205340 kb
Host smart-47fd4892-bf7a-4b7a-aaf4-786830cefc66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778910557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.3778910557
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.2100829742
Short name T1046
Test name
Test status
Simulation time 48526539 ps
CPU time 0.74 seconds
Started May 09 01:08:01 PM PDT 24
Finished May 09 01:08:04 PM PDT 24
Peak memory 205348 kb
Host smart-db3d47e4-29a8-4fec-a478-c08d3a6caeb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100829742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.2100829742
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.740723115
Short name T943
Test name
Test status
Simulation time 10564275 ps
CPU time 0.75 seconds
Started May 09 01:08:01 PM PDT 24
Finished May 09 01:08:04 PM PDT 24
Peak memory 205220 kb
Host smart-d4f440a7-ec70-4071-8823-aee23aef1282
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740723115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.740723115
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.3981863069
Short name T992
Test name
Test status
Simulation time 11179877 ps
CPU time 0.75 seconds
Started May 09 01:08:03 PM PDT 24
Finished May 09 01:08:07 PM PDT 24
Peak memory 205376 kb
Host smart-cd72dce6-b3a9-4cea-9b11-6358e20589dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981863069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.3981863069
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.3933396876
Short name T1047
Test name
Test status
Simulation time 27933993 ps
CPU time 0.74 seconds
Started May 09 01:08:01 PM PDT 24
Finished May 09 01:08:04 PM PDT 24
Peak memory 205300 kb
Host smart-1102c0fe-0479-4771-8bea-b1343a5809ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933396876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.3933396876
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.1523440880
Short name T949
Test name
Test status
Simulation time 15408161 ps
CPU time 0.77 seconds
Started May 09 01:08:01 PM PDT 24
Finished May 09 01:08:04 PM PDT 24
Peak memory 205360 kb
Host smart-857677e5-c747-41b7-8377-358807c9a013
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523440880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.1523440880
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.2352573200
Short name T919
Test name
Test status
Simulation time 220337976 ps
CPU time 1.76 seconds
Started May 09 01:07:38 PM PDT 24
Finished May 09 01:07:41 PM PDT 24
Peak memory 213916 kb
Host smart-1ab886ac-89b9-4d1a-815e-9abf6e887d29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352573200 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.2352573200
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.1620739277
Short name T1025
Test name
Test status
Simulation time 14254820 ps
CPU time 0.93 seconds
Started May 09 01:07:39 PM PDT 24
Finished May 09 01:07:42 PM PDT 24
Peak memory 205328 kb
Host smart-b20309e2-ac97-4a1a-96e4-cf72b8f80639
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620739277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.1620739277
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.335048012
Short name T969
Test name
Test status
Simulation time 19176184 ps
CPU time 0.72 seconds
Started May 09 01:07:39 PM PDT 24
Finished May 09 01:07:42 PM PDT 24
Peak memory 205332 kb
Host smart-dff4a8b6-ef1e-4e20-bf20-e480fe1ab8c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335048012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.335048012
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.86075798
Short name T930
Test name
Test status
Simulation time 137109788 ps
CPU time 2.24 seconds
Started May 09 01:07:36 PM PDT 24
Finished May 09 01:07:40 PM PDT 24
Peak memory 205616 kb
Host smart-4124fe71-add8-44fb-87a0-2188d938559f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86075798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_same
_csr_outstanding.86075798
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.2465544203
Short name T105
Test name
Test status
Simulation time 536206831 ps
CPU time 1.67 seconds
Started May 09 01:07:38 PM PDT 24
Finished May 09 01:07:41 PM PDT 24
Peak memory 214240 kb
Host smart-f4292d90-cbdb-4acb-862c-29997be4905e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465544203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.2465544203
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.3396186036
Short name T1002
Test name
Test status
Simulation time 196442895 ps
CPU time 7.03 seconds
Started May 09 01:07:36 PM PDT 24
Finished May 09 01:07:45 PM PDT 24
Peak memory 220224 kb
Host smart-181c719c-b56d-432b-8a1f-280c4f29a4f9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396186036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.3396186036
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.16457430
Short name T920
Test name
Test status
Simulation time 97869412 ps
CPU time 1.94 seconds
Started May 09 01:07:36 PM PDT 24
Finished May 09 01:07:39 PM PDT 24
Peak memory 213944 kb
Host smart-9d147a76-fc2e-4d70-8eae-c7487e7b63d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16457430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.16457430
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.2272825634
Short name T150
Test name
Test status
Simulation time 72355097 ps
CPU time 1.51 seconds
Started May 09 01:07:35 PM PDT 24
Finished May 09 01:07:38 PM PDT 24
Peak memory 213928 kb
Host smart-495222fc-3aa6-44da-99a5-1dd4630e1a90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272825634 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.2272825634
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1077744156
Short name T1078
Test name
Test status
Simulation time 48173640 ps
CPU time 1.18 seconds
Started May 09 01:07:44 PM PDT 24
Finished May 09 01:07:46 PM PDT 24
Peak memory 205600 kb
Host smart-0626ab80-e940-4340-b21d-99af0e7fd6bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077744156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.1077744156
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.3117648196
Short name T973
Test name
Test status
Simulation time 22921206 ps
CPU time 0.9 seconds
Started May 09 01:07:38 PM PDT 24
Finished May 09 01:07:41 PM PDT 24
Peak memory 205132 kb
Host smart-32b3fb35-cc47-46df-90c9-8cbf4e9e10e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117648196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.3117648196
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1675411367
Short name T1007
Test name
Test status
Simulation time 20465898 ps
CPU time 1.58 seconds
Started May 09 01:07:36 PM PDT 24
Finished May 09 01:07:39 PM PDT 24
Peak memory 205620 kb
Host smart-cf16ddba-90d9-4b2b-b39d-da967cce27c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675411367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.1675411367
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.1889549913
Short name T112
Test name
Test status
Simulation time 443307541 ps
CPU time 4.75 seconds
Started May 09 01:07:39 PM PDT 24
Finished May 09 01:07:46 PM PDT 24
Peak memory 214264 kb
Host smart-62689ec5-3031-4b06-ad8b-cf92ed3ac112
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889549913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.1889549913
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3153595271
Short name T1035
Test name
Test status
Simulation time 582067117 ps
CPU time 8.44 seconds
Started May 09 01:07:35 PM PDT 24
Finished May 09 01:07:45 PM PDT 24
Peak memory 214240 kb
Host smart-e75641cb-c1c5-463a-80fb-7da4f37b3f1a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153595271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.3153595271
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.3001262816
Short name T946
Test name
Test status
Simulation time 218274040 ps
CPU time 4.42 seconds
Started May 09 01:07:35 PM PDT 24
Finished May 09 01:07:41 PM PDT 24
Peak memory 216092 kb
Host smart-25064e2c-f436-447e-94cb-fc1f451c42f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001262816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.3001262816
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.3583797237
Short name T161
Test name
Test status
Simulation time 128585488 ps
CPU time 5.49 seconds
Started May 09 01:07:41 PM PDT 24
Finished May 09 01:07:49 PM PDT 24
Peak memory 205576 kb
Host smart-821db43d-5bd0-4095-8a71-d69f454a82b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583797237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.3583797237
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3698397600
Short name T993
Test name
Test status
Simulation time 181582181 ps
CPU time 1.67 seconds
Started May 09 01:07:37 PM PDT 24
Finished May 09 01:07:40 PM PDT 24
Peak memory 213940 kb
Host smart-ddddec03-8b24-460a-a8d9-a3dbb257c4db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698397600 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.3698397600
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.3594721350
Short name T1070
Test name
Test status
Simulation time 33526381 ps
CPU time 0.92 seconds
Started May 09 01:07:35 PM PDT 24
Finished May 09 01:07:37 PM PDT 24
Peak memory 205416 kb
Host smart-e4ba68f1-5655-4366-95d0-8d97dc8081de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594721350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.3594721350
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.3006115056
Short name T994
Test name
Test status
Simulation time 9823203 ps
CPU time 0.83 seconds
Started May 09 01:07:39 PM PDT 24
Finished May 09 01:07:42 PM PDT 24
Peak memory 205332 kb
Host smart-f6976c67-56ec-4a78-bf40-9135290005eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006115056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.3006115056
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2632059961
Short name T932
Test name
Test status
Simulation time 140464848 ps
CPU time 2.38 seconds
Started May 09 01:07:44 PM PDT 24
Finished May 09 01:07:47 PM PDT 24
Peak memory 205684 kb
Host smart-0b9c1ebe-7614-484c-857f-3d58c5be740f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632059961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.2632059961
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.4039204991
Short name T1059
Test name
Test status
Simulation time 120387963 ps
CPU time 2.45 seconds
Started May 09 01:07:39 PM PDT 24
Finished May 09 01:07:44 PM PDT 24
Peak memory 219164 kb
Host smart-7ecc6708-2a94-4308-962e-d803bbf8782f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039204991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.4039204991
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3330992475
Short name T954
Test name
Test status
Simulation time 367633128 ps
CPU time 13.57 seconds
Started May 09 01:07:40 PM PDT 24
Finished May 09 01:07:56 PM PDT 24
Peak memory 220400 kb
Host smart-3fb830d7-dd45-47b6-b5ce-743f5066ea32
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330992475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.3330992475
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.1348949445
Short name T940
Test name
Test status
Simulation time 78673697 ps
CPU time 2.74 seconds
Started May 09 01:07:44 PM PDT 24
Finished May 09 01:07:48 PM PDT 24
Peak memory 213652 kb
Host smart-58ce76c0-b26b-4ad6-b298-8d498197b501
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348949445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.1348949445
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1653291364
Short name T1053
Test name
Test status
Simulation time 87325848 ps
CPU time 1.14 seconds
Started May 09 01:07:38 PM PDT 24
Finished May 09 01:07:41 PM PDT 24
Peak memory 205556 kb
Host smart-d2cffba2-eb2d-4622-a1f1-e0315e18e6e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653291364 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.1653291364
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.2242538083
Short name T977
Test name
Test status
Simulation time 30051917 ps
CPU time 1.08 seconds
Started May 09 01:07:36 PM PDT 24
Finished May 09 01:07:39 PM PDT 24
Peak memory 205664 kb
Host smart-02fa7ba8-b592-4494-881b-a78639417051
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242538083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.2242538083
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.1234235136
Short name T1067
Test name
Test status
Simulation time 18247927 ps
CPU time 0.73 seconds
Started May 09 01:07:39 PM PDT 24
Finished May 09 01:07:42 PM PDT 24
Peak memory 205360 kb
Host smart-cda6d428-c340-4952-9de0-98c5b0b2e781
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234235136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.1234235136
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.4161570797
Short name T1068
Test name
Test status
Simulation time 28334402 ps
CPU time 1.65 seconds
Started May 09 01:07:36 PM PDT 24
Finished May 09 01:07:40 PM PDT 24
Peak memory 205572 kb
Host smart-5da4795e-9565-4515-8535-5a75e1d8000f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161570797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.4161570797
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.4225182785
Short name T990
Test name
Test status
Simulation time 145554808 ps
CPU time 4.51 seconds
Started May 09 01:07:39 PM PDT 24
Finished May 09 01:07:45 PM PDT 24
Peak memory 214188 kb
Host smart-fcdc908a-d246-48bb-8bab-40179ca72eea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225182785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.4225182785
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.218360334
Short name T981
Test name
Test status
Simulation time 1198184446 ps
CPU time 6.89 seconds
Started May 09 01:07:35 PM PDT 24
Finished May 09 01:07:43 PM PDT 24
Peak memory 220316 kb
Host smart-577dba83-d8ab-445f-a5fd-aa4a64e30ecd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218360334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.k
eymgr_shadow_reg_errors_with_csr_rw.218360334
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1486949793
Short name T983
Test name
Test status
Simulation time 28096032 ps
CPU time 2.28 seconds
Started May 09 01:07:44 PM PDT 24
Finished May 09 01:07:47 PM PDT 24
Peak memory 216804 kb
Host smart-d5a432ec-5bb7-47ec-98cd-75fcecf1564c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486949793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.1486949793
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.1108001017
Short name T169
Test name
Test status
Simulation time 53670935 ps
CPU time 2.56 seconds
Started May 09 01:07:41 PM PDT 24
Finished May 09 01:07:45 PM PDT 24
Peak memory 213864 kb
Host smart-e96b7b9b-4bee-4fb2-bc9e-1ce63430fbb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108001017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.1108001017
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1598879586
Short name T1033
Test name
Test status
Simulation time 107389944 ps
CPU time 1.99 seconds
Started May 09 01:07:36 PM PDT 24
Finished May 09 01:07:40 PM PDT 24
Peak memory 213884 kb
Host smart-780b8814-d62b-4072-a127-12c2f700044b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598879586 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.1598879586
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.1210523477
Short name T144
Test name
Test status
Simulation time 102793678 ps
CPU time 1.43 seconds
Started May 09 01:07:36 PM PDT 24
Finished May 09 01:07:39 PM PDT 24
Peak memory 205524 kb
Host smart-f9acbe35-4450-4b27-99fe-a2626566cbb3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210523477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.1210523477
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.2185638766
Short name T966
Test name
Test status
Simulation time 12416827 ps
CPU time 0.72 seconds
Started May 09 01:07:40 PM PDT 24
Finished May 09 01:07:43 PM PDT 24
Peak memory 205348 kb
Host smart-f00a481a-4ec1-438a-8362-b242b1ee1ee0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185638766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.2185638766
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.1103417377
Short name T938
Test name
Test status
Simulation time 43088236 ps
CPU time 1.35 seconds
Started May 09 01:07:39 PM PDT 24
Finished May 09 01:07:42 PM PDT 24
Peak memory 205628 kb
Host smart-af9c5c16-ea4c-4b70-823e-f8ee62af5b7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103417377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.1103417377
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.3254463320
Short name T1069
Test name
Test status
Simulation time 233063402 ps
CPU time 3.8 seconds
Started May 09 01:07:35 PM PDT 24
Finished May 09 01:07:40 PM PDT 24
Peak memory 214232 kb
Host smart-aae2e17d-67ee-4f03-b9fc-e14dfdad7b92
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254463320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.3254463320
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.3835701775
Short name T1037
Test name
Test status
Simulation time 205934999 ps
CPU time 5.09 seconds
Started May 09 01:07:38 PM PDT 24
Finished May 09 01:07:45 PM PDT 24
Peak memory 214244 kb
Host smart-e376c23c-dc78-4d60-9828-fc2ac1b2ffd1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835701775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.3835701775
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.4252172389
Short name T1082
Test name
Test status
Simulation time 393815850 ps
CPU time 1.92 seconds
Started May 09 01:07:36 PM PDT 24
Finished May 09 01:07:40 PM PDT 24
Peak memory 205552 kb
Host smart-6f6a3c21-0916-4b76-a35b-0c34b066adb0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252172389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.4252172389
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.2475011085
Short name T452
Test name
Test status
Simulation time 179624738 ps
CPU time 0.82 seconds
Started May 09 12:33:35 PM PDT 24
Finished May 09 12:33:47 PM PDT 24
Peak memory 205752 kb
Host smart-be280e86-ff6d-4181-8284-e27db24d5b7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475011085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.2475011085
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.3388543586
Short name T787
Test name
Test status
Simulation time 1456237989 ps
CPU time 4.54 seconds
Started May 09 12:33:34 PM PDT 24
Finished May 09 12:33:49 PM PDT 24
Peak memory 220804 kb
Host smart-f9898f39-fdf9-4a55-959a-20002f71c5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388543586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.3388543586
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.1665602650
Short name T69
Test name
Test status
Simulation time 49704096 ps
CPU time 1.65 seconds
Started May 09 12:33:45 PM PDT 24
Finished May 09 12:33:57 PM PDT 24
Peak memory 207140 kb
Host smart-8d6050f4-7a3d-469a-874c-5068657d565c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665602650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.1665602650
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.2697191274
Short name T303
Test name
Test status
Simulation time 50030378 ps
CPU time 2.07 seconds
Started May 09 12:33:50 PM PDT 24
Finished May 09 12:34:00 PM PDT 24
Peak memory 214364 kb
Host smart-4327c7d0-3d25-41c6-8209-b1fec1c4121e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697191274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.2697191274
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.2903852305
Short name T913
Test name
Test status
Simulation time 296796344 ps
CPU time 3.46 seconds
Started May 09 12:33:47 PM PDT 24
Finished May 09 12:34:00 PM PDT 24
Peak memory 213972 kb
Host smart-17b003fb-a0fc-4cb4-83a6-78756847dc39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903852305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.2903852305
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.1216059763
Short name T216
Test name
Test status
Simulation time 1955949743 ps
CPU time 8.4 seconds
Started May 09 12:33:36 PM PDT 24
Finished May 09 12:33:55 PM PDT 24
Peak memory 208600 kb
Host smart-d2420722-8074-4980-8b4f-1bd755623490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216059763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.1216059763
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.1532157985
Short name T466
Test name
Test status
Simulation time 674863701 ps
CPU time 5.2 seconds
Started May 09 12:33:34 PM PDT 24
Finished May 09 12:33:50 PM PDT 24
Peak memory 209472 kb
Host smart-4895e890-d453-4114-9034-dddbac1ace26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532157985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.1532157985
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload.3856420406
Short name T853
Test name
Test status
Simulation time 38776500 ps
CPU time 2.17 seconds
Started May 09 12:33:46 PM PDT 24
Finished May 09 12:33:58 PM PDT 24
Peak memory 207848 kb
Host smart-a0e5db5e-92d5-41da-9559-929c4b89443c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856420406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.3856420406
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.1295420335
Short name T626
Test name
Test status
Simulation time 196923488 ps
CPU time 5.14 seconds
Started May 09 12:33:51 PM PDT 24
Finished May 09 12:34:04 PM PDT 24
Peak memory 208568 kb
Host smart-7c46487d-2847-481e-98a9-69b1c6fe9870
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295420335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.1295420335
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.1703914229
Short name T854
Test name
Test status
Simulation time 368484755 ps
CPU time 3.47 seconds
Started May 09 12:33:38 PM PDT 24
Finished May 09 12:33:52 PM PDT 24
Peak memory 208848 kb
Host smart-05e245c2-8512-4a83-a8b5-7ca4997bc122
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703914229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.1703914229
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.1543246535
Short name T493
Test name
Test status
Simulation time 62322071 ps
CPU time 2.2 seconds
Started May 09 12:33:28 PM PDT 24
Finished May 09 12:33:41 PM PDT 24
Peak memory 206632 kb
Host smart-7a03c67d-e06e-4de3-a250-a9ca7e0fbaa6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543246535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.1543246535
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.108386668
Short name T693
Test name
Test status
Simulation time 279454178 ps
CPU time 2.65 seconds
Started May 09 12:33:41 PM PDT 24
Finished May 09 12:33:54 PM PDT 24
Peak memory 208504 kb
Host smart-5a4152c3-ed8b-4741-a39c-372d9ece2763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108386668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.108386668
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.1442162794
Short name T440
Test name
Test status
Simulation time 225092104 ps
CPU time 2.73 seconds
Started May 09 12:33:43 PM PDT 24
Finished May 09 12:33:56 PM PDT 24
Peak memory 207252 kb
Host smart-20cba7da-fd84-4c32-8577-f4a5bfdd813e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442162794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.1442162794
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.1186061894
Short name T275
Test name
Test status
Simulation time 118809501 ps
CPU time 3.98 seconds
Started May 09 12:33:46 PM PDT 24
Finished May 09 12:34:00 PM PDT 24
Peak memory 207644 kb
Host smart-95fe82c3-64c6-4698-be80-61765e21db81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186061894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.1186061894
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.1774364039
Short name T686
Test name
Test status
Simulation time 8990590 ps
CPU time 0.75 seconds
Started May 09 12:33:38 PM PDT 24
Finished May 09 12:33:50 PM PDT 24
Peak memory 205804 kb
Host smart-fb4691ac-b546-49d4-afe6-3cd11fb7ff00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774364039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.1774364039
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.1541969052
Short name T351
Test name
Test status
Simulation time 185943710 ps
CPU time 2.59 seconds
Started May 09 12:33:38 PM PDT 24
Finished May 09 12:33:51 PM PDT 24
Peak memory 214204 kb
Host smart-d8b78048-81bc-43df-a3dd-5e36e525eb2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1541969052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.1541969052
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.1207058521
Short name T32
Test name
Test status
Simulation time 108205565 ps
CPU time 3.78 seconds
Started May 09 12:33:37 PM PDT 24
Finished May 09 12:33:52 PM PDT 24
Peak memory 221756 kb
Host smart-06a68ee5-af0b-4b60-9107-cbd1e6d03f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207058521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.1207058521
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.731368072
Short name T230
Test name
Test status
Simulation time 291365205 ps
CPU time 3.52 seconds
Started May 09 12:33:36 PM PDT 24
Finished May 09 12:33:50 PM PDT 24
Peak memory 214160 kb
Host smart-9ab05028-9a21-454a-b26d-d5f6cbe90ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731368072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.731368072
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.3168143009
Short name T843
Test name
Test status
Simulation time 22557060 ps
CPU time 1.81 seconds
Started May 09 12:33:41 PM PDT 24
Finished May 09 12:33:54 PM PDT 24
Peak memory 214100 kb
Host smart-49e7f6d8-123e-49a9-b9a0-1c553ecadb27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168143009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.3168143009
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.1022966309
Short name T56
Test name
Test status
Simulation time 81896239 ps
CPU time 3.22 seconds
Started May 09 12:33:32 PM PDT 24
Finished May 09 12:33:47 PM PDT 24
Peak memory 220268 kb
Host smart-ed2bd514-e53a-4636-9114-465e4d2a1753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022966309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.1022966309
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.2667981364
Short name T353
Test name
Test status
Simulation time 333420489 ps
CPU time 7.09 seconds
Started May 09 12:33:38 PM PDT 24
Finished May 09 12:33:57 PM PDT 24
Peak memory 208868 kb
Host smart-9a16b575-9704-4f86-a766-05832fc419f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667981364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.2667981364
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.268260027
Short name T10
Test name
Test status
Simulation time 1834135386 ps
CPU time 15.32 seconds
Started May 09 12:33:57 PM PDT 24
Finished May 09 12:34:20 PM PDT 24
Peak memory 238436 kb
Host smart-ff70cf24-c095-46a6-9f48-16da922df0d0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268260027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.268260027
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.923285284
Short name T721
Test name
Test status
Simulation time 121640371 ps
CPU time 3.7 seconds
Started May 09 12:33:36 PM PDT 24
Finished May 09 12:33:51 PM PDT 24
Peak memory 208468 kb
Host smart-a0ff55a2-ff0b-4399-aaec-ad074040ffc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923285284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.923285284
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.2895154660
Short name T74
Test name
Test status
Simulation time 135298229 ps
CPU time 4.31 seconds
Started May 09 12:33:37 PM PDT 24
Finished May 09 12:33:52 PM PDT 24
Peak memory 206736 kb
Host smart-cc487e7b-8ecc-45c3-9013-898e4e3fb98f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895154660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.2895154660
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.3515845948
Short name T465
Test name
Test status
Simulation time 56056216 ps
CPU time 2.73 seconds
Started May 09 12:33:46 PM PDT 24
Finished May 09 12:33:59 PM PDT 24
Peak memory 207912 kb
Host smart-833e1f45-6d8b-4616-81c0-b3d3b72b8464
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515845948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.3515845948
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.297865459
Short name T272
Test name
Test status
Simulation time 782972120 ps
CPU time 6.39 seconds
Started May 09 12:33:40 PM PDT 24
Finished May 09 12:33:58 PM PDT 24
Peak memory 208444 kb
Host smart-05251ec0-d48e-49d8-a62a-0c164367ebf7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297865459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.297865459
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.3578918836
Short name T130
Test name
Test status
Simulation time 322154781 ps
CPU time 7.05 seconds
Started May 09 12:33:40 PM PDT 24
Finished May 09 12:33:58 PM PDT 24
Peak memory 208592 kb
Host smart-edef5b85-f052-4748-9b0a-6b52f4005aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578918836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.3578918836
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.3875449758
Short name T740
Test name
Test status
Simulation time 89524010 ps
CPU time 2.65 seconds
Started May 09 12:33:46 PM PDT 24
Finished May 09 12:33:58 PM PDT 24
Peak memory 208256 kb
Host smart-e5384d67-5245-4cbc-b691-7b347823869d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875449758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.3875449758
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.3359252192
Short name T329
Test name
Test status
Simulation time 6804893934 ps
CPU time 9.34 seconds
Started May 09 12:33:34 PM PDT 24
Finished May 09 12:33:54 PM PDT 24
Peak memory 216928 kb
Host smart-f404336e-dd34-4183-a4c5-4400295930c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359252192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.3359252192
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.1138627282
Short name T422
Test name
Test status
Simulation time 3789807012 ps
CPU time 66.59 seconds
Started May 09 12:33:39 PM PDT 24
Finished May 09 12:34:56 PM PDT 24
Peak memory 210008 kb
Host smart-a326d9e3-3dca-4a94-9ae1-ef062aeb7abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138627282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.1138627282
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.2266593503
Short name T912
Test name
Test status
Simulation time 80123923 ps
CPU time 1.65 seconds
Started May 09 12:33:36 PM PDT 24
Finished May 09 12:33:49 PM PDT 24
Peak memory 209932 kb
Host smart-1bf59829-1822-433a-b716-2cc1580e3047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266593503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.2266593503
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.2697909090
Short name T888
Test name
Test status
Simulation time 62161110 ps
CPU time 0.9 seconds
Started May 09 12:34:15 PM PDT 24
Finished May 09 12:34:24 PM PDT 24
Peak memory 205940 kb
Host smart-608ebcae-12e6-49b4-9b44-545a09ae780f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697909090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.2697909090
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.1086255488
Short name T387
Test name
Test status
Simulation time 3660027164 ps
CPU time 25.21 seconds
Started May 09 12:33:50 PM PDT 24
Finished May 09 12:34:23 PM PDT 24
Peak memory 214584 kb
Host smart-4bea8e85-b6e5-4f92-9e11-896bf2ba4d73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1086255488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.1086255488
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.415749796
Short name T542
Test name
Test status
Simulation time 220360252 ps
CPU time 2.77 seconds
Started May 09 12:33:56 PM PDT 24
Finished May 09 12:34:06 PM PDT 24
Peak memory 209844 kb
Host smart-4fb9b367-3dcf-4710-9dff-d020826757dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415749796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.415749796
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.1402911616
Short name T889
Test name
Test status
Simulation time 29341956 ps
CPU time 2.19 seconds
Started May 09 12:34:04 PM PDT 24
Finished May 09 12:34:15 PM PDT 24
Peak memory 214112 kb
Host smart-76349702-e1bf-47b1-924b-806ab75cf763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402911616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.1402911616
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.3831003122
Short name T306
Test name
Test status
Simulation time 104200887 ps
CPU time 4.68 seconds
Started May 09 12:33:52 PM PDT 24
Finished May 09 12:34:04 PM PDT 24
Peak memory 222268 kb
Host smart-8a06f579-8354-4a80-af00-9163a4d51a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831003122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.3831003122
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.22860177
Short name T96
Test name
Test status
Simulation time 33458220 ps
CPU time 1.84 seconds
Started May 09 12:34:05 PM PDT 24
Finished May 09 12:34:15 PM PDT 24
Peak memory 214088 kb
Host smart-dcffbe58-55b3-4a90-9e4f-13e24ab9daae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22860177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.22860177
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.828109332
Short name T256
Test name
Test status
Simulation time 187278335 ps
CPU time 5.99 seconds
Started May 09 12:34:00 PM PDT 24
Finished May 09 12:34:13 PM PDT 24
Peak memory 210184 kb
Host smart-ec2a7910-a3ac-457b-97f3-b1954309bc16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828109332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.828109332
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.1285146962
Short name T834
Test name
Test status
Simulation time 206553240 ps
CPU time 5.99 seconds
Started May 09 12:34:05 PM PDT 24
Finished May 09 12:34:20 PM PDT 24
Peak memory 209764 kb
Host smart-44ce7ee6-1007-4e87-ac9b-d5ab22534e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285146962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.1285146962
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.3365551742
Short name T582
Test name
Test status
Simulation time 64651190 ps
CPU time 2.36 seconds
Started May 09 12:34:01 PM PDT 24
Finished May 09 12:34:11 PM PDT 24
Peak memory 207108 kb
Host smart-8b0b3bd3-ac89-4774-85bc-ad03e28c7e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365551742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.3365551742
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.3223659022
Short name T709
Test name
Test status
Simulation time 151261096 ps
CPU time 2.7 seconds
Started May 09 12:34:03 PM PDT 24
Finished May 09 12:34:14 PM PDT 24
Peak memory 208540 kb
Host smart-12e24228-09d4-4f5c-9ea4-72160ce229b0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223659022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.3223659022
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.3370263823
Short name T818
Test name
Test status
Simulation time 131508057 ps
CPU time 3.53 seconds
Started May 09 12:33:55 PM PDT 24
Finished May 09 12:34:05 PM PDT 24
Peak memory 208560 kb
Host smart-1d591128-9b6a-4e1c-b6c6-c559de778f69
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370263823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.3370263823
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.3445099911
Short name T498
Test name
Test status
Simulation time 113457605 ps
CPU time 2.91 seconds
Started May 09 12:34:01 PM PDT 24
Finished May 09 12:34:12 PM PDT 24
Peak memory 206664 kb
Host smart-c19b0322-1bec-4ef2-b261-b6f2751129f2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445099911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.3445099911
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.1991047742
Short name T376
Test name
Test status
Simulation time 65866730 ps
CPU time 2.2 seconds
Started May 09 12:34:03 PM PDT 24
Finished May 09 12:34:14 PM PDT 24
Peak memory 215360 kb
Host smart-33e2b547-e150-4f0f-bd33-4be71b16e774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991047742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.1991047742
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.2685933790
Short name T413
Test name
Test status
Simulation time 280381696 ps
CPU time 3.69 seconds
Started May 09 12:34:09 PM PDT 24
Finished May 09 12:34:22 PM PDT 24
Peak memory 207904 kb
Host smart-0d6edfac-e73f-477f-8ecd-10f997548294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685933790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.2685933790
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.1458999869
Short name T191
Test name
Test status
Simulation time 2202806956 ps
CPU time 28.39 seconds
Started May 09 12:34:04 PM PDT 24
Finished May 09 12:34:41 PM PDT 24
Peak memory 219640 kb
Host smart-06b3c1a8-690b-465b-82b0-cd443c479bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458999869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.1458999869
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.728400798
Short name T400
Test name
Test status
Simulation time 45141291 ps
CPU time 0.83 seconds
Started May 09 12:34:02 PM PDT 24
Finished May 09 12:34:10 PM PDT 24
Peak memory 205748 kb
Host smart-1ceaa649-5091-46db-b9d6-8e935051d57e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728400798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.728400798
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.442948802
Short name T210
Test name
Test status
Simulation time 67148141 ps
CPU time 2.44 seconds
Started May 09 12:34:04 PM PDT 24
Finished May 09 12:34:15 PM PDT 24
Peak memory 222188 kb
Host smart-9ec34d1b-62ec-4d09-8645-1ead27c03e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442948802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.442948802
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.3451959987
Short name T782
Test name
Test status
Simulation time 53688765 ps
CPU time 1.86 seconds
Started May 09 12:34:06 PM PDT 24
Finished May 09 12:34:16 PM PDT 24
Peak memory 207872 kb
Host smart-3a289448-ae09-4b87-a08e-2cbce2d7c09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451959987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.3451959987
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.1127537787
Short name T541
Test name
Test status
Simulation time 630492442 ps
CPU time 4.96 seconds
Started May 09 12:34:25 PM PDT 24
Finished May 09 12:34:37 PM PDT 24
Peak memory 214192 kb
Host smart-02b572c0-c0e8-41bd-8fc2-27a19b95f5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127537787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.1127537787
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.2745069783
Short name T307
Test name
Test status
Simulation time 280854563 ps
CPU time 4.13 seconds
Started May 09 12:34:07 PM PDT 24
Finished May 09 12:34:20 PM PDT 24
Peak memory 214064 kb
Host smart-454dd32e-68b2-4782-839c-d5cb8752bff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745069783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.2745069783
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.1681440357
Short name T906
Test name
Test status
Simulation time 75567101 ps
CPU time 2.45 seconds
Started May 09 12:34:23 PM PDT 24
Finished May 09 12:34:33 PM PDT 24
Peak memory 214176 kb
Host smart-c902b290-fc2e-4e90-b4c3-19eecf705bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681440357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.1681440357
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.3131785511
Short name T362
Test name
Test status
Simulation time 549792087 ps
CPU time 4.41 seconds
Started May 09 12:34:06 PM PDT 24
Finished May 09 12:34:19 PM PDT 24
Peak memory 218132 kb
Host smart-6b7bb00e-2237-4b90-80d1-00457264a832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131785511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.3131785511
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.1900305033
Short name T447
Test name
Test status
Simulation time 175013343 ps
CPU time 4.4 seconds
Started May 09 12:34:10 PM PDT 24
Finished May 09 12:34:23 PM PDT 24
Peak memory 206548 kb
Host smart-8d9904c7-1b5a-4cab-96fe-6fc5210dda1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900305033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.1900305033
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.4223181034
Short name T613
Test name
Test status
Simulation time 1980304503 ps
CPU time 25.84 seconds
Started May 09 12:34:27 PM PDT 24
Finished May 09 12:34:59 PM PDT 24
Peak memory 208612 kb
Host smart-f9a8836d-729b-4715-aea6-83236ff55635
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223181034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.4223181034
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.3564332762
Short name T856
Test name
Test status
Simulation time 3939882630 ps
CPU time 49.69 seconds
Started May 09 12:34:05 PM PDT 24
Finished May 09 12:35:03 PM PDT 24
Peak memory 208308 kb
Host smart-28d9fa8a-8e6b-465a-9fb7-a0511f656be4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564332762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.3564332762
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.769842839
Short name T454
Test name
Test status
Simulation time 76745275 ps
CPU time 3.47 seconds
Started May 09 12:34:02 PM PDT 24
Finished May 09 12:34:14 PM PDT 24
Peak memory 208416 kb
Host smart-37defdd9-560d-4d83-b8ea-146613d7b51f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769842839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.769842839
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.1218026786
Short name T826
Test name
Test status
Simulation time 268682226 ps
CPU time 1.97 seconds
Started May 09 12:34:03 PM PDT 24
Finished May 09 12:34:14 PM PDT 24
Peak memory 214536 kb
Host smart-1fa0efee-2d90-417e-bc03-938a7fd25163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218026786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.1218026786
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.3568078072
Short name T762
Test name
Test status
Simulation time 82160824 ps
CPU time 1.79 seconds
Started May 09 12:33:56 PM PDT 24
Finished May 09 12:34:05 PM PDT 24
Peak memory 206564 kb
Host smart-eda0aded-2aef-424e-ba08-51cebcadaa2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568078072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.3568078072
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.3877777528
Short name T347
Test name
Test status
Simulation time 2284227713 ps
CPU time 24.58 seconds
Started May 09 12:34:09 PM PDT 24
Finished May 09 12:34:42 PM PDT 24
Peak memory 216444 kb
Host smart-ef0a5dc8-2ca8-4089-8508-0d59429e0e3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877777528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.3877777528
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.407969377
Short name T101
Test name
Test status
Simulation time 637950053 ps
CPU time 11.77 seconds
Started May 09 12:34:02 PM PDT 24
Finished May 09 12:34:22 PM PDT 24
Peak memory 222492 kb
Host smart-de7335b0-1565-4b55-80ce-17e4f38379f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407969377 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.407969377
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.3712360269
Short name T488
Test name
Test status
Simulation time 197965201 ps
CPU time 4.43 seconds
Started May 09 12:34:27 PM PDT 24
Finished May 09 12:34:37 PM PDT 24
Peak memory 207264 kb
Host smart-471d2a0c-2646-48fd-b8f7-a15b6f206451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712360269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.3712360269
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.3566514897
Short name T363
Test name
Test status
Simulation time 69685609 ps
CPU time 2.04 seconds
Started May 09 12:34:03 PM PDT 24
Finished May 09 12:34:13 PM PDT 24
Peak memory 209588 kb
Host smart-b96e53eb-0810-47dc-b7d8-abfd626ef6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566514897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.3566514897
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.2777792042
Short name T643
Test name
Test status
Simulation time 30964970 ps
CPU time 0.77 seconds
Started May 09 12:34:02 PM PDT 24
Finished May 09 12:34:11 PM PDT 24
Peak memory 205772 kb
Host smart-0e81977e-c242-477a-b060-59061308670a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777792042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.2777792042
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.2661234967
Short name T285
Test name
Test status
Simulation time 45497415 ps
CPU time 3.53 seconds
Started May 09 12:34:04 PM PDT 24
Finished May 09 12:34:17 PM PDT 24
Peak memory 215492 kb
Host smart-e7f9c6fe-fe78-4917-8ca4-83ee83e1e5cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2661234967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.2661234967
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.3929619894
Short name T372
Test name
Test status
Simulation time 62801662 ps
CPU time 2.38 seconds
Started May 09 12:34:10 PM PDT 24
Finished May 09 12:34:21 PM PDT 24
Peak memory 208908 kb
Host smart-0e63f1a5-a9af-4efe-aff2-50f14a50777b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929619894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.3929619894
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.2996616181
Short name T809
Test name
Test status
Simulation time 56865125 ps
CPU time 2.19 seconds
Started May 09 12:34:24 PM PDT 24
Finished May 09 12:34:33 PM PDT 24
Peak memory 208192 kb
Host smart-4866e9fe-692d-4e43-9747-67d45972441c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996616181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.2996616181
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.426695392
Short name T804
Test name
Test status
Simulation time 271648776 ps
CPU time 3.37 seconds
Started May 09 12:34:06 PM PDT 24
Finished May 09 12:34:18 PM PDT 24
Peak memory 218044 kb
Host smart-10de385d-731e-41cd-864f-2d719f6d9c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426695392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.426695392
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.3409696732
Short name T179
Test name
Test status
Simulation time 130188644 ps
CPU time 3.56 seconds
Started May 09 12:34:16 PM PDT 24
Finished May 09 12:34:28 PM PDT 24
Peak memory 217784 kb
Host smart-e662d9af-63fa-4834-823c-1298e28da998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409696732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.3409696732
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.2868597865
Short name T492
Test name
Test status
Simulation time 7563076657 ps
CPU time 30.09 seconds
Started May 09 12:34:09 PM PDT 24
Finished May 09 12:34:48 PM PDT 24
Peak memory 207960 kb
Host smart-2a70be2b-f658-4ea9-a5f2-c87a7e833387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868597865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.2868597865
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.1296356573
Short name T733
Test name
Test status
Simulation time 47611138 ps
CPU time 2.06 seconds
Started May 09 12:34:02 PM PDT 24
Finished May 09 12:34:12 PM PDT 24
Peak memory 208516 kb
Host smart-fd20a7e4-aa45-4dba-9b05-bb460589dbfd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296356573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.1296356573
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.2853138013
Short name T458
Test name
Test status
Simulation time 50174627 ps
CPU time 2.68 seconds
Started May 09 12:34:20 PM PDT 24
Finished May 09 12:34:30 PM PDT 24
Peak memory 206728 kb
Host smart-01cc8a8d-167d-423b-97d2-c9333103c7de
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853138013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.2853138013
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.104008587
Short name T706
Test name
Test status
Simulation time 612997470 ps
CPU time 5.77 seconds
Started May 09 12:33:55 PM PDT 24
Finished May 09 12:34:08 PM PDT 24
Peak memory 208644 kb
Host smart-b052ddb4-dfcd-48b8-8e9c-4a42845d0d29
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104008587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.104008587
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.2956999204
Short name T416
Test name
Test status
Simulation time 57461658 ps
CPU time 2.35 seconds
Started May 09 12:34:00 PM PDT 24
Finished May 09 12:34:11 PM PDT 24
Peak memory 209260 kb
Host smart-27202961-a24d-44cf-a103-882b8b2da004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956999204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.2956999204
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.867570034
Short name T589
Test name
Test status
Simulation time 492065455 ps
CPU time 3.28 seconds
Started May 09 12:34:02 PM PDT 24
Finished May 09 12:34:13 PM PDT 24
Peak memory 206572 kb
Host smart-048da11a-1302-4aa2-839c-abb76471d063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867570034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.867570034
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.465407493
Short name T886
Test name
Test status
Simulation time 60720926 ps
CPU time 3.69 seconds
Started May 09 12:34:06 PM PDT 24
Finished May 09 12:34:18 PM PDT 24
Peak memory 214216 kb
Host smart-c3e060af-5a9c-4bea-9b6e-f325968111df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465407493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.465407493
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.3526726348
Short name T19
Test name
Test status
Simulation time 57858453 ps
CPU time 2.2 seconds
Started May 09 12:34:02 PM PDT 24
Finished May 09 12:34:13 PM PDT 24
Peak memory 209740 kb
Host smart-d54110df-454e-4160-bc20-e021a38e35f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526726348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.3526726348
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.2250535419
Short name T533
Test name
Test status
Simulation time 23886989 ps
CPU time 0.75 seconds
Started May 09 12:34:04 PM PDT 24
Finished May 09 12:34:14 PM PDT 24
Peak memory 205828 kb
Host smart-6ceae15b-c797-4f77-b3e4-d27620a1e9be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250535419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.2250535419
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.1113076223
Short name T390
Test name
Test status
Simulation time 33994844 ps
CPU time 2.65 seconds
Started May 09 12:34:08 PM PDT 24
Finished May 09 12:34:20 PM PDT 24
Peak memory 214124 kb
Host smart-a27367c9-54c7-418e-9f83-0506b6a1a034
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1113076223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.1113076223
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.1888881388
Short name T591
Test name
Test status
Simulation time 55231148 ps
CPU time 1.27 seconds
Started May 09 12:34:06 PM PDT 24
Finished May 09 12:34:15 PM PDT 24
Peak memory 207524 kb
Host smart-b64fb1e7-53dd-4210-863e-716d8a5268da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888881388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.1888881388
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.1599628591
Short name T205
Test name
Test status
Simulation time 695845835 ps
CPU time 19.06 seconds
Started May 09 12:34:03 PM PDT 24
Finished May 09 12:34:31 PM PDT 24
Peak memory 214164 kb
Host smart-fab95443-b559-4213-ac01-da4091a0f0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599628591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.1599628591
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.4194259078
Short name T557
Test name
Test status
Simulation time 53600813 ps
CPU time 3.41 seconds
Started May 09 12:34:02 PM PDT 24
Finished May 09 12:34:13 PM PDT 24
Peak memory 214700 kb
Host smart-d7ecbbde-09f8-4d6e-bcfd-f70759a50af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194259078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.4194259078
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.3678254776
Short name T449
Test name
Test status
Simulation time 315512988 ps
CPU time 3.4 seconds
Started May 09 12:34:14 PM PDT 24
Finished May 09 12:34:26 PM PDT 24
Peak memory 207896 kb
Host smart-00b005da-400a-4229-a759-deaf0b8249d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678254776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.3678254776
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.973163628
Short name T318
Test name
Test status
Simulation time 262896033 ps
CPU time 8.93 seconds
Started May 09 12:34:02 PM PDT 24
Finished May 09 12:34:19 PM PDT 24
Peak memory 214168 kb
Host smart-be7ad1d2-4d49-4136-965f-de7454d753a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973163628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.973163628
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.356949646
Short name T833
Test name
Test status
Simulation time 459600831 ps
CPU time 11.21 seconds
Started May 09 12:34:08 PM PDT 24
Finished May 09 12:34:28 PM PDT 24
Peak memory 208272 kb
Host smart-fb1b2b4b-adaf-405b-9ef8-924761c8384a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356949646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.356949646
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.3175230024
Short name T551
Test name
Test status
Simulation time 167581626 ps
CPU time 4.79 seconds
Started May 09 12:34:05 PM PDT 24
Finished May 09 12:34:24 PM PDT 24
Peak memory 208240 kb
Host smart-7ade57e9-a6b1-445a-a936-6ca67d5a741f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175230024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.3175230024
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.2298811609
Short name T739
Test name
Test status
Simulation time 23122269248 ps
CPU time 40.38 seconds
Started May 09 12:34:44 PM PDT 24
Finished May 09 12:35:29 PM PDT 24
Peak memory 208348 kb
Host smart-a1166630-4355-4850-8d40-c7f715681ffb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298811609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.2298811609
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.619898671
Short name T688
Test name
Test status
Simulation time 73076435 ps
CPU time 3.19 seconds
Started May 09 12:34:05 PM PDT 24
Finished May 09 12:34:17 PM PDT 24
Peak memory 208412 kb
Host smart-57ce6157-2a14-47ca-a63a-601989d9c51a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619898671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.619898671
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.787077008
Short name T645
Test name
Test status
Simulation time 87333044 ps
CPU time 2.21 seconds
Started May 09 12:34:04 PM PDT 24
Finished May 09 12:34:15 PM PDT 24
Peak memory 208392 kb
Host smart-dde062b0-7df6-435d-95e1-17395fbe4476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787077008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.787077008
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.1515751586
Short name T519
Test name
Test status
Simulation time 37040116 ps
CPU time 2.24 seconds
Started May 09 12:34:23 PM PDT 24
Finished May 09 12:34:32 PM PDT 24
Peak memory 207340 kb
Host smart-47856b71-e76b-4fb3-8b5f-4e9c27041adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515751586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.1515751586
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.1278797511
Short name T72
Test name
Test status
Simulation time 1703669920 ps
CPU time 19.97 seconds
Started May 09 12:34:24 PM PDT 24
Finished May 09 12:34:51 PM PDT 24
Peak memory 215752 kb
Host smart-a5ed2aa5-a516-4ce4-bf96-9dd32040dc3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278797511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.1278797511
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.1987040560
Short name T504
Test name
Test status
Simulation time 128461284 ps
CPU time 2.57 seconds
Started May 09 12:34:03 PM PDT 24
Finished May 09 12:34:15 PM PDT 24
Peak memory 207496 kb
Host smart-466c2dfe-9727-4bf1-93f5-f697bf1d5e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987040560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.1987040560
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.949730121
Short name T830
Test name
Test status
Simulation time 45425417 ps
CPU time 0.86 seconds
Started May 09 12:33:59 PM PDT 24
Finished May 09 12:34:08 PM PDT 24
Peak memory 205764 kb
Host smart-3fcc3dd7-f3ed-4bc4-8f54-e469888d41a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949730121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.949730121
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.101118320
Short name T195
Test name
Test status
Simulation time 42705325 ps
CPU time 1.66 seconds
Started May 09 12:34:40 PM PDT 24
Finished May 09 12:34:47 PM PDT 24
Peak memory 209204 kb
Host smart-cd2419f2-4bb5-47ba-a49a-2042b009de7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101118320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.101118320
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.3480818792
Short name T25
Test name
Test status
Simulation time 1927318448 ps
CPU time 6.25 seconds
Started May 09 12:34:05 PM PDT 24
Finished May 09 12:34:20 PM PDT 24
Peak memory 214184 kb
Host smart-31f4ca47-5eeb-4eca-be90-d09406d7d040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480818792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.3480818792
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.4124330719
Short name T43
Test name
Test status
Simulation time 360640405 ps
CPU time 1.79 seconds
Started May 09 12:34:01 PM PDT 24
Finished May 09 12:34:11 PM PDT 24
Peak memory 214112 kb
Host smart-1de288f9-ec1e-49cd-b8ed-97c99e882662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124330719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.4124330719
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.2740409211
Short name T883
Test name
Test status
Simulation time 135333336 ps
CPU time 3.44 seconds
Started May 09 12:34:07 PM PDT 24
Finished May 09 12:34:19 PM PDT 24
Peak memory 222268 kb
Host smart-c762d2f2-b17c-4e0f-ae6c-fbc4d38e1c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740409211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.2740409211
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.2644256495
Short name T746
Test name
Test status
Simulation time 1346633995 ps
CPU time 42.32 seconds
Started May 09 12:34:57 PM PDT 24
Finished May 09 12:35:47 PM PDT 24
Peak memory 208768 kb
Host smart-35c26606-98b2-45c6-a64b-a2e47b032936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644256495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.2644256495
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.3521919764
Short name T566
Test name
Test status
Simulation time 158910408 ps
CPU time 2.67 seconds
Started May 09 12:34:59 PM PDT 24
Finished May 09 12:35:16 PM PDT 24
Peak memory 208364 kb
Host smart-fa70a1fd-031b-42da-9545-8faec6d5cb6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521919764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.3521919764
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.163732784
Short name T748
Test name
Test status
Simulation time 1224783864 ps
CPU time 6.22 seconds
Started May 09 12:34:54 PM PDT 24
Finished May 09 12:35:06 PM PDT 24
Peak memory 208752 kb
Host smart-2018b24a-d26a-4643-9272-6997e06442e4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163732784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.163732784
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.3558176395
Short name T899
Test name
Test status
Simulation time 9761453148 ps
CPU time 21.61 seconds
Started May 09 12:34:13 PM PDT 24
Finished May 09 12:34:43 PM PDT 24
Peak memory 208456 kb
Host smart-bf2f9241-c4b9-4308-a515-ae753cd9e162
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558176395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.3558176395
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.3453521959
Short name T536
Test name
Test status
Simulation time 150453935 ps
CPU time 4.85 seconds
Started May 09 12:34:27 PM PDT 24
Finished May 09 12:34:38 PM PDT 24
Peak memory 206700 kb
Host smart-80a090a7-f4dd-4574-a6fc-d48cbdb21873
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453521959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.3453521959
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.2600962566
Short name T284
Test name
Test status
Simulation time 4861731777 ps
CPU time 12.8 seconds
Started May 09 12:34:03 PM PDT 24
Finished May 09 12:34:24 PM PDT 24
Peak memory 214316 kb
Host smart-4e32acb0-0e68-4a67-9e8d-1798178c4102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600962566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.2600962566
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.2543949377
Short name T708
Test name
Test status
Simulation time 73101710 ps
CPU time 2.55 seconds
Started May 09 12:34:44 PM PDT 24
Finished May 09 12:34:52 PM PDT 24
Peak memory 208584 kb
Host smart-10b51260-3f67-4059-b4ec-7a36467f2965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543949377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.2543949377
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.4083622297
Short name T173
Test name
Test status
Simulation time 1553384497 ps
CPU time 9.46 seconds
Started May 09 12:34:06 PM PDT 24
Finished May 09 12:34:24 PM PDT 24
Peak memory 219896 kb
Host smart-993f6952-38a9-4982-a21e-b509c10fa3d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083622297 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.4083622297
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.3690334564
Short name T366
Test name
Test status
Simulation time 41892038 ps
CPU time 2.28 seconds
Started May 09 12:34:13 PM PDT 24
Finished May 09 12:34:24 PM PDT 24
Peak memory 209932 kb
Host smart-dae154b5-8556-4a92-bb60-1d4735104f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690334564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.3690334564
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.2953700178
Short name T616
Test name
Test status
Simulation time 13608827 ps
CPU time 0.83 seconds
Started May 09 12:34:02 PM PDT 24
Finished May 09 12:34:11 PM PDT 24
Peak memory 205976 kb
Host smart-e15eab96-f2ee-4f38-ba06-6bc09b85e0c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953700178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.2953700178
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.249528049
Short name T439
Test name
Test status
Simulation time 49813577 ps
CPU time 2.65 seconds
Started May 09 12:34:13 PM PDT 24
Finished May 09 12:34:25 PM PDT 24
Peak memory 208660 kb
Host smart-c15cf9f9-08a7-4664-b427-476a696f9ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249528049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.249528049
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.1241046350
Short name T24
Test name
Test status
Simulation time 49525790 ps
CPU time 3.13 seconds
Started May 09 12:34:09 PM PDT 24
Finished May 09 12:34:21 PM PDT 24
Peak memory 214180 kb
Host smart-ee33b4cd-7571-4b30-9e77-aca35708176e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241046350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.1241046350
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.3168154754
Short name T280
Test name
Test status
Simulation time 75557491 ps
CPU time 3.82 seconds
Started May 09 12:34:13 PM PDT 24
Finished May 09 12:34:25 PM PDT 24
Peak memory 214164 kb
Host smart-8b86be0d-0716-40a5-823d-81bbfae95764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168154754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.3168154754
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.1782611266
Short name T678
Test name
Test status
Simulation time 80601317 ps
CPU time 3.78 seconds
Started May 09 12:34:09 PM PDT 24
Finished May 09 12:34:21 PM PDT 24
Peak memory 219908 kb
Host smart-0e06ba28-5eb9-4e5c-887d-bec7c0287b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782611266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.1782611266
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.1425570453
Short name T338
Test name
Test status
Simulation time 339849898 ps
CPU time 8.15 seconds
Started May 09 12:34:09 PM PDT 24
Finished May 09 12:34:26 PM PDT 24
Peak memory 208536 kb
Host smart-2b8cc2a4-e916-47bd-b911-615c177beef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425570453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.1425570453
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.1262365142
Short name T677
Test name
Test status
Simulation time 164293313 ps
CPU time 6.04 seconds
Started May 09 12:34:18 PM PDT 24
Finished May 09 12:34:32 PM PDT 24
Peak memory 206656 kb
Host smart-3f596289-f4df-4155-baae-350655973a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262365142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.1262365142
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.71950228
Short name T819
Test name
Test status
Simulation time 131654677 ps
CPU time 3.99 seconds
Started May 09 12:34:20 PM PDT 24
Finished May 09 12:34:31 PM PDT 24
Peak memory 206740 kb
Host smart-49438b7f-a8cd-4429-a6a7-4a2d03140d28
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71950228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.71950228
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.990497847
Short name T849
Test name
Test status
Simulation time 638635239 ps
CPU time 9.01 seconds
Started May 09 12:34:09 PM PDT 24
Finished May 09 12:34:27 PM PDT 24
Peak memory 206864 kb
Host smart-4a6245e4-9413-477f-8750-a76d02b86e23
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990497847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.990497847
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.3117406906
Short name T336
Test name
Test status
Simulation time 37934787 ps
CPU time 2.23 seconds
Started May 09 12:34:12 PM PDT 24
Finished May 09 12:34:23 PM PDT 24
Peak memory 214260 kb
Host smart-74be3bba-37d0-4929-b579-45fea58d0552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117406906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.3117406906
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.3043986768
Short name T451
Test name
Test status
Simulation time 283623951 ps
CPU time 3.86 seconds
Started May 09 12:33:55 PM PDT 24
Finished May 09 12:34:06 PM PDT 24
Peak memory 206652 kb
Host smart-c3a24e46-a34f-4920-ae90-af3baf203282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043986768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.3043986768
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.2558974782
Short name T345
Test name
Test status
Simulation time 819364159 ps
CPU time 27.31 seconds
Started May 09 12:34:19 PM PDT 24
Finished May 09 12:34:54 PM PDT 24
Peak memory 220680 kb
Host smart-dc5c7489-047e-4e08-ac7c-2f247c1d2845
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558974782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.2558974782
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.4216370785
Short name T716
Test name
Test status
Simulation time 316960507 ps
CPU time 19.18 seconds
Started May 09 12:34:08 PM PDT 24
Finished May 09 12:34:36 PM PDT 24
Peak memory 222492 kb
Host smart-b1e66dc1-d080-4ec2-bb38-739706d981bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216370785 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.4216370785
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.486860739
Short name T407
Test name
Test status
Simulation time 1202587107 ps
CPU time 7.43 seconds
Started May 09 12:34:28 PM PDT 24
Finished May 09 12:34:41 PM PDT 24
Peak memory 208468 kb
Host smart-3cd81cd2-a2ac-4dd7-bc4a-d9e80698d013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486860739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.486860739
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.2685044039
Short name T162
Test name
Test status
Simulation time 24509232 ps
CPU time 1.7 seconds
Started May 09 12:34:24 PM PDT 24
Finished May 09 12:34:33 PM PDT 24
Peak memory 209756 kb
Host smart-b7bd3291-9a09-4994-8f72-148264bf1794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685044039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.2685044039
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.3182654346
Short name T404
Test name
Test status
Simulation time 23089084 ps
CPU time 0.73 seconds
Started May 09 12:34:16 PM PDT 24
Finished May 09 12:34:25 PM PDT 24
Peak memory 205816 kb
Host smart-aae7242b-9026-48ec-8cab-acd7e81f40ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182654346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.3182654346
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.1084328945
Short name T876
Test name
Test status
Simulation time 39449332 ps
CPU time 2.73 seconds
Started May 09 12:34:42 PM PDT 24
Finished May 09 12:34:50 PM PDT 24
Peak memory 215324 kb
Host smart-558d053e-09c3-4a0f-a799-2bb58dbe8983
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1084328945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.1084328945
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.4076262999
Short name T718
Test name
Test status
Simulation time 30035754866 ps
CPU time 37.07 seconds
Started May 09 12:34:36 PM PDT 24
Finished May 09 12:35:16 PM PDT 24
Peak memory 210168 kb
Host smart-78e3d153-fc8b-4067-bb2a-78e5fd929d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076262999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.4076262999
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.3521098533
Short name T42
Test name
Test status
Simulation time 87631828 ps
CPU time 3.89 seconds
Started May 09 12:34:06 PM PDT 24
Finished May 09 12:34:19 PM PDT 24
Peak memory 210256 kb
Host smart-9c4e8740-39f3-47f0-8a1d-ef4878f85c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521098533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.3521098533
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.1816431687
Short name T561
Test name
Test status
Simulation time 298054206 ps
CPU time 6.4 seconds
Started May 09 12:34:10 PM PDT 24
Finished May 09 12:34:25 PM PDT 24
Peak memory 214164 kb
Host smart-12596209-80f7-49c9-b197-e93b4ab11224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816431687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.1816431687
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.637064209
Short name T294
Test name
Test status
Simulation time 2681573079 ps
CPU time 23.92 seconds
Started May 09 12:34:13 PM PDT 24
Finished May 09 12:34:45 PM PDT 24
Peak memory 208464 kb
Host smart-c9d17102-f427-40bd-a9f9-d8676a063eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637064209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.637064209
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.79739792
Short name T538
Test name
Test status
Simulation time 17487101462 ps
CPU time 70.38 seconds
Started May 09 12:34:13 PM PDT 24
Finished May 09 12:35:31 PM PDT 24
Peak memory 208192 kb
Host smart-0f6733fe-b6b4-4174-b115-ce69104acca6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79739792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.79739792
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.1661345072
Short name T523
Test name
Test status
Simulation time 236974253 ps
CPU time 6.12 seconds
Started May 09 12:34:28 PM PDT 24
Finished May 09 12:34:40 PM PDT 24
Peak memory 207732 kb
Host smart-d62ade99-ec4b-417a-b701-83c16b230efc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661345072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.1661345072
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.1009966001
Short name T702
Test name
Test status
Simulation time 26459554 ps
CPU time 1.72 seconds
Started May 09 12:34:27 PM PDT 24
Finished May 09 12:34:35 PM PDT 24
Peak memory 206684 kb
Host smart-a028e50f-a212-4910-b338-1a4012794253
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009966001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.1009966001
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.2292178855
Short name T870
Test name
Test status
Simulation time 272452193 ps
CPU time 3.16 seconds
Started May 09 12:34:08 PM PDT 24
Finished May 09 12:34:20 PM PDT 24
Peak memory 210208 kb
Host smart-f50e5094-bc9c-4fa6-b9bb-8d85f80fc588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292178855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.2292178855
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.3983148247
Short name T858
Test name
Test status
Simulation time 628928342 ps
CPU time 2.97 seconds
Started May 09 12:34:14 PM PDT 24
Finished May 09 12:34:25 PM PDT 24
Peak memory 206884 kb
Host smart-b21897d5-f092-4873-aca4-89ba70a20565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983148247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.3983148247
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.3933066105
Short name T901
Test name
Test status
Simulation time 157097505 ps
CPU time 5.83 seconds
Started May 09 12:34:42 PM PDT 24
Finished May 09 12:34:52 PM PDT 24
Peak memory 222472 kb
Host smart-1e205a20-c565-42d1-9d76-be75a566a507
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933066105 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.3933066105
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.119731451
Short name T860
Test name
Test status
Simulation time 224865779 ps
CPU time 3.84 seconds
Started May 09 12:34:13 PM PDT 24
Finished May 09 12:34:25 PM PDT 24
Peak memory 218360 kb
Host smart-c826193d-fcd8-4059-9e74-961741c5b25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119731451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.119731451
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.3956743894
Short name T133
Test name
Test status
Simulation time 112166221 ps
CPU time 2.12 seconds
Started May 09 12:34:11 PM PDT 24
Finished May 09 12:34:22 PM PDT 24
Peak memory 209920 kb
Host smart-54a3072c-20ad-4648-b15b-3fa8b9daf32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956743894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.3956743894
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.2821380259
Short name T424
Test name
Test status
Simulation time 31925509 ps
CPU time 0.74 seconds
Started May 09 12:34:42 PM PDT 24
Finished May 09 12:34:48 PM PDT 24
Peak memory 205796 kb
Host smart-b80ed1c4-5f14-4133-9023-1250c50bc2f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821380259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.2821380259
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.2762095041
Short name T878
Test name
Test status
Simulation time 139879995 ps
CPU time 3.06 seconds
Started May 09 12:34:09 PM PDT 24
Finished May 09 12:34:21 PM PDT 24
Peak memory 209748 kb
Host smart-2789652b-2716-4fa1-83d9-1877ff0fa1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762095041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.2762095041
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.718500774
Short name T569
Test name
Test status
Simulation time 107774541 ps
CPU time 3.63 seconds
Started May 09 12:34:27 PM PDT 24
Finished May 09 12:34:37 PM PDT 24
Peak memory 214168 kb
Host smart-76c61578-3bff-4de5-b613-f83bcda16558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718500774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.718500774
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.3625996220
Short name T806
Test name
Test status
Simulation time 221890594 ps
CPU time 3.11 seconds
Started May 09 12:34:12 PM PDT 24
Finished May 09 12:34:23 PM PDT 24
Peak memory 214136 kb
Host smart-faa3f823-b5e6-468c-819a-915afc91e7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625996220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.3625996220
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_random.3048438628
Short name T547
Test name
Test status
Simulation time 1087135360 ps
CPU time 8.31 seconds
Started May 09 12:34:14 PM PDT 24
Finished May 09 12:34:30 PM PDT 24
Peak memory 214176 kb
Host smart-f5167c32-0ffa-4f57-ac94-1a4b52aea273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048438628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.3048438628
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.2280955932
Short name T352
Test name
Test status
Simulation time 64328811 ps
CPU time 2.8 seconds
Started May 09 12:34:23 PM PDT 24
Finished May 09 12:34:33 PM PDT 24
Peak memory 207968 kb
Host smart-b1b44e64-1f26-4487-a80b-da620dcb914d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280955932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.2280955932
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.2761168449
Short name T813
Test name
Test status
Simulation time 144248583 ps
CPU time 4.75 seconds
Started May 09 12:34:19 PM PDT 24
Finished May 09 12:34:32 PM PDT 24
Peak memory 207568 kb
Host smart-8c0525d1-4427-4c09-8891-0e34c6798222
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761168449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.2761168449
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.136899569
Short name T744
Test name
Test status
Simulation time 105061386 ps
CPU time 2.11 seconds
Started May 09 12:34:44 PM PDT 24
Finished May 09 12:34:51 PM PDT 24
Peak memory 208676 kb
Host smart-b35a5eef-9b6f-48c0-adf9-a0894c6b4f5a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136899569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.136899569
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.3948643774
Short name T483
Test name
Test status
Simulation time 525165396 ps
CPU time 2.65 seconds
Started May 09 12:34:30 PM PDT 24
Finished May 09 12:34:38 PM PDT 24
Peak memory 207396 kb
Host smart-66ebf9e4-31d3-49bc-805d-6f9de3b62764
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948643774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.3948643774
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.1745691828
Short name T910
Test name
Test status
Simulation time 1204180545 ps
CPU time 7.33 seconds
Started May 09 12:34:28 PM PDT 24
Finished May 09 12:34:41 PM PDT 24
Peak memory 209992 kb
Host smart-38a7307e-15b3-4f63-a8ca-808462c440f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745691828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.1745691828
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.1990413587
Short name T428
Test name
Test status
Simulation time 34581412 ps
CPU time 2.34 seconds
Started May 09 12:34:13 PM PDT 24
Finished May 09 12:34:24 PM PDT 24
Peak memory 208444 kb
Host smart-31a3ed40-2c77-43df-aa2a-a3e4ae94e908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990413587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.1990413587
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.3397370881
Short name T879
Test name
Test status
Simulation time 1616973821 ps
CPU time 55.3 seconds
Started May 09 12:34:17 PM PDT 24
Finished May 09 12:35:20 PM PDT 24
Peak memory 221020 kb
Host smart-6295492d-aaf0-44ab-8c15-b06eda4a1ddf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397370881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.3397370881
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.2503218953
Short name T464
Test name
Test status
Simulation time 80716246 ps
CPU time 3.89 seconds
Started May 09 12:34:10 PM PDT 24
Finished May 09 12:34:22 PM PDT 24
Peak memory 214160 kb
Host smart-1493502e-0dc6-4795-b162-759ae7152bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503218953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.2503218953
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.3841865141
Short name T661
Test name
Test status
Simulation time 53826303 ps
CPU time 2.4 seconds
Started May 09 12:34:22 PM PDT 24
Finished May 09 12:34:32 PM PDT 24
Peak memory 209980 kb
Host smart-e935e8f0-a4a5-4fb0-8ddb-540fa9d46ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841865141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.3841865141
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.1166896665
Short name T609
Test name
Test status
Simulation time 18645037 ps
CPU time 0.83 seconds
Started May 09 12:34:20 PM PDT 24
Finished May 09 12:34:29 PM PDT 24
Peak memory 205800 kb
Host smart-21b91847-78d2-4f6a-ab7b-61d011523d91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166896665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.1166896665
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.963256163
Short name T241
Test name
Test status
Simulation time 254633625 ps
CPU time 3.36 seconds
Started May 09 12:34:16 PM PDT 24
Finished May 09 12:34:27 PM PDT 24
Peak memory 209340 kb
Host smart-a0864717-4c4c-4d1e-b495-7fdd10475b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963256163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.963256163
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.1258010975
Short name T827
Test name
Test status
Simulation time 35887945 ps
CPU time 1.45 seconds
Started May 09 12:34:17 PM PDT 24
Finished May 09 12:34:26 PM PDT 24
Peak memory 206828 kb
Host smart-5ac35953-57e6-4ebb-96b1-64265e42be26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258010975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.1258010975
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.2462143758
Short name T308
Test name
Test status
Simulation time 118910373 ps
CPU time 3.59 seconds
Started May 09 12:34:08 PM PDT 24
Finished May 09 12:34:20 PM PDT 24
Peak memory 214368 kb
Host smart-9933bcdf-3642-459f-b30e-9f0c9c4ea769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462143758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.2462143758
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_random.479915500
Short name T690
Test name
Test status
Simulation time 1068746618 ps
CPU time 19.49 seconds
Started May 09 12:34:13 PM PDT 24
Finished May 09 12:34:40 PM PDT 24
Peak memory 208668 kb
Host smart-59361aae-4a27-42cf-807f-e6c8d6e348a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479915500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.479915500
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.289088381
Short name T880
Test name
Test status
Simulation time 33219092 ps
CPU time 2.22 seconds
Started May 09 12:34:14 PM PDT 24
Finished May 09 12:34:25 PM PDT 24
Peak memory 208536 kb
Host smart-2467cabf-2aa2-4843-8878-76993a122bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289088381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.289088381
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.1980927205
Short name T77
Test name
Test status
Simulation time 118241003 ps
CPU time 3 seconds
Started May 09 12:34:17 PM PDT 24
Finished May 09 12:34:28 PM PDT 24
Peak memory 206876 kb
Host smart-475a1610-6b33-4dd7-830e-0965a94910b4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980927205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.1980927205
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.2885467754
Short name T621
Test name
Test status
Simulation time 709671705 ps
CPU time 5.8 seconds
Started May 09 12:34:46 PM PDT 24
Finished May 09 12:34:57 PM PDT 24
Peak memory 207884 kb
Host smart-5fd597df-d1eb-493e-9e74-e9db3040bb11
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885467754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.2885467754
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.2724765343
Short name T627
Test name
Test status
Simulation time 163105058 ps
CPU time 5.03 seconds
Started May 09 12:34:15 PM PDT 24
Finished May 09 12:34:28 PM PDT 24
Peak memory 207800 kb
Host smart-259c3945-a57f-4ce4-994f-71278e8c948f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724765343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.2724765343
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.3838824899
Short name T715
Test name
Test status
Simulation time 91353589 ps
CPU time 1.63 seconds
Started May 09 12:34:19 PM PDT 24
Finished May 09 12:34:28 PM PDT 24
Peak memory 208548 kb
Host smart-452f56a2-ce20-44ff-a9a4-9396c8752552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838824899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.3838824899
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.999611440
Short name T406
Test name
Test status
Simulation time 210987569 ps
CPU time 6.47 seconds
Started May 09 12:34:22 PM PDT 24
Finished May 09 12:34:36 PM PDT 24
Peak memory 208560 kb
Host smart-77c56766-0c00-4956-85a0-1e62fbb8c11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999611440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.999611440
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.2012398713
Short name T713
Test name
Test status
Simulation time 137719170 ps
CPU time 5.1 seconds
Started May 09 12:34:20 PM PDT 24
Finished May 09 12:34:33 PM PDT 24
Peak memory 209688 kb
Host smart-542b824f-a314-4be9-baa1-23735e1fc276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012398713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.2012398713
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.2833923731
Short name T55
Test name
Test status
Simulation time 213178951 ps
CPU time 1.96 seconds
Started May 09 12:34:10 PM PDT 24
Finished May 09 12:34:21 PM PDT 24
Peak memory 209864 kb
Host smart-39dad04a-f755-417c-99f0-967bfdc901ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833923731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.2833923731
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.3129764069
Short name T414
Test name
Test status
Simulation time 25048439 ps
CPU time 0.92 seconds
Started May 09 12:34:32 PM PDT 24
Finished May 09 12:34:37 PM PDT 24
Peak memory 205780 kb
Host smart-5d86ed49-8b2e-4b25-afc0-8102f026cfba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129764069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.3129764069
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.3865961332
Short name T342
Test name
Test status
Simulation time 131695452 ps
CPU time 3.66 seconds
Started May 09 12:34:48 PM PDT 24
Finished May 09 12:34:57 PM PDT 24
Peak memory 214176 kb
Host smart-c5fd8ddf-3eeb-48b6-8cc5-50880a8836cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865961332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.3865961332
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.438614784
Short name T743
Test name
Test status
Simulation time 3374487593 ps
CPU time 9.16 seconds
Started May 09 12:34:24 PM PDT 24
Finished May 09 12:34:40 PM PDT 24
Peak memory 209888 kb
Host smart-ddbf1e29-7b84-46ef-ba17-628d790b4303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438614784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.438614784
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.68511823
Short name T436
Test name
Test status
Simulation time 236100487 ps
CPU time 2.5 seconds
Started May 09 12:34:31 PM PDT 24
Finished May 09 12:34:38 PM PDT 24
Peak memory 214244 kb
Host smart-7a613fc1-6742-4551-9a78-84bbd6dd41a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68511823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.68511823
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.601907051
Short name T313
Test name
Test status
Simulation time 209628693 ps
CPU time 4.86 seconds
Started May 09 12:34:42 PM PDT 24
Finished May 09 12:34:51 PM PDT 24
Peak memory 207888 kb
Host smart-e46968c2-fec5-40c4-b8a6-295c34e23a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601907051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.601907051
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.2852137402
Short name T894
Test name
Test status
Simulation time 258109141 ps
CPU time 2.72 seconds
Started May 09 12:34:06 PM PDT 24
Finished May 09 12:34:17 PM PDT 24
Peak memory 208428 kb
Host smart-74d23f4f-2fe0-4211-bead-0a20a02ad2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852137402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.2852137402
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.3012759848
Short name T810
Test name
Test status
Simulation time 2277511772 ps
CPU time 12.93 seconds
Started May 09 12:34:18 PM PDT 24
Finished May 09 12:34:38 PM PDT 24
Peak memory 208560 kb
Host smart-cda851ae-0a13-4b0b-a326-dfa60ea47671
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012759848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.3012759848
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.191034002
Short name T864
Test name
Test status
Simulation time 790957065 ps
CPU time 3.29 seconds
Started May 09 12:34:08 PM PDT 24
Finished May 09 12:34:20 PM PDT 24
Peak memory 208500 kb
Host smart-9108fb0f-025d-41ae-bcfb-5e689af3e278
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191034002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.191034002
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.3253195454
Short name T438
Test name
Test status
Simulation time 1319298188 ps
CPU time 5.5 seconds
Started May 09 12:34:28 PM PDT 24
Finished May 09 12:34:39 PM PDT 24
Peak memory 207872 kb
Host smart-36d11955-3c7c-456c-bd39-26c5f32c3cf5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253195454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.3253195454
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_smoke.2244542304
Short name T601
Test name
Test status
Simulation time 130955450 ps
CPU time 2.47 seconds
Started May 09 12:34:43 PM PDT 24
Finished May 09 12:34:51 PM PDT 24
Peak memory 207704 kb
Host smart-f574e4f1-f3df-4ea0-a08b-5a9a0b05a3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244542304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.2244542304
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.2694188683
Short name T187
Test name
Test status
Simulation time 1997849058 ps
CPU time 12.71 seconds
Started May 09 12:34:50 PM PDT 24
Finished May 09 12:35:08 PM PDT 24
Peak memory 216224 kb
Host smart-a6f2c36a-819a-4ca1-8884-dddfdfec3833
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694188683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.2694188683
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.3747854969
Short name T178
Test name
Test status
Simulation time 1172553912 ps
CPU time 12.05 seconds
Started May 09 12:34:21 PM PDT 24
Finished May 09 12:34:40 PM PDT 24
Peak memory 222496 kb
Host smart-96da3496-6ba2-48d2-9921-e7b052987e08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747854969 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.3747854969
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.4175045116
Short name T340
Test name
Test status
Simulation time 615497641 ps
CPU time 4.94 seconds
Started May 09 12:34:24 PM PDT 24
Finished May 09 12:34:37 PM PDT 24
Peak memory 214160 kb
Host smart-c7377360-494e-4eb1-86c4-cdf1000c4c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175045116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.4175045116
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.2078051031
Short name T791
Test name
Test status
Simulation time 213886703 ps
CPU time 2.13 seconds
Started May 09 12:34:18 PM PDT 24
Finished May 09 12:34:28 PM PDT 24
Peak memory 210056 kb
Host smart-df3c8486-d903-45f5-ab4d-5cb099edcbfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078051031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.2078051031
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.2834759669
Short name T412
Test name
Test status
Simulation time 32670918 ps
CPU time 0.76 seconds
Started May 09 12:33:36 PM PDT 24
Finished May 09 12:33:48 PM PDT 24
Peak memory 205828 kb
Host smart-0bbf65ed-1328-4c8d-9428-81aac491605b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834759669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.2834759669
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.1135257568
Short name T382
Test name
Test status
Simulation time 460909602 ps
CPU time 6.3 seconds
Started May 09 12:33:42 PM PDT 24
Finished May 09 12:33:59 PM PDT 24
Peak memory 214188 kb
Host smart-a6116463-26e7-4ce4-bf30-250e0fc2f9e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1135257568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.1135257568
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.213100122
Short name T877
Test name
Test status
Simulation time 91244819 ps
CPU time 4 seconds
Started May 09 12:33:42 PM PDT 24
Finished May 09 12:33:57 PM PDT 24
Peak memory 214336 kb
Host smart-b40e6506-ced8-4d39-87fe-77af7bcd1c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213100122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.213100122
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.2925452240
Short name T895
Test name
Test status
Simulation time 64430352 ps
CPU time 3.14 seconds
Started May 09 12:33:42 PM PDT 24
Finished May 09 12:33:56 PM PDT 24
Peak memory 213876 kb
Host smart-59d73187-f16d-4769-bd55-f0faed9c5cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925452240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.2925452240
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.912986370
Short name T279
Test name
Test status
Simulation time 46170630 ps
CPU time 1.9 seconds
Started May 09 12:33:54 PM PDT 24
Finished May 09 12:34:03 PM PDT 24
Peak memory 206700 kb
Host smart-bf6452ac-da0a-401c-b929-696552c53d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912986370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.912986370
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.839890504
Short name T358
Test name
Test status
Simulation time 310471592 ps
CPU time 2.65 seconds
Started May 09 12:33:42 PM PDT 24
Finished May 09 12:33:56 PM PDT 24
Peak memory 205720 kb
Host smart-cc455572-7646-4c77-a22d-63b4dacc3c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839890504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.839890504
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_random.1907140227
Short name T426
Test name
Test status
Simulation time 360625610 ps
CPU time 5.39 seconds
Started May 09 12:33:36 PM PDT 24
Finished May 09 12:33:52 PM PDT 24
Peak memory 207248 kb
Host smart-0290de68-8fb6-4ad8-b3a6-293314f7040d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907140227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.1907140227
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.386284207
Short name T12
Test name
Test status
Simulation time 4426703643 ps
CPU time 12.9 seconds
Started May 09 12:33:32 PM PDT 24
Finished May 09 12:33:56 PM PDT 24
Peak memory 237624 kb
Host smart-81f82e44-442f-4b32-b9c2-98a684a561e2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386284207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.386284207
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.1088472702
Short name T669
Test name
Test status
Simulation time 79197936 ps
CPU time 1.74 seconds
Started May 09 12:33:58 PM PDT 24
Finished May 09 12:34:07 PM PDT 24
Peak memory 206740 kb
Host smart-4220cf45-54c2-4005-988b-b2440b10126e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088472702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.1088472702
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.3053232880
Short name T469
Test name
Test status
Simulation time 3741006033 ps
CPU time 32.58 seconds
Started May 09 12:33:42 PM PDT 24
Finished May 09 12:34:26 PM PDT 24
Peak memory 208188 kb
Host smart-3f01eb35-0f45-4742-9655-3f24f7ab6625
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053232880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.3053232880
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.4173857703
Short name T446
Test name
Test status
Simulation time 147149192 ps
CPU time 3.3 seconds
Started May 09 12:33:55 PM PDT 24
Finished May 09 12:34:05 PM PDT 24
Peak memory 208268 kb
Host smart-527caeb5-c7ef-4883-94af-10bbe6d9f705
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173857703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.4173857703
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.4085381059
Short name T489
Test name
Test status
Simulation time 1049167776 ps
CPU time 26.89 seconds
Started May 09 12:33:49 PM PDT 24
Finished May 09 12:34:24 PM PDT 24
Peak memory 207908 kb
Host smart-2d80df4c-842d-4c55-b498-b1177609071c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085381059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.4085381059
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.3935546784
Short name T255
Test name
Test status
Simulation time 88234241 ps
CPU time 2.1 seconds
Started May 09 12:33:38 PM PDT 24
Finished May 09 12:33:50 PM PDT 24
Peak memory 216080 kb
Host smart-c23dbc1f-b68d-4172-870b-26949b2a963f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935546784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.3935546784
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.2912326997
Short name T831
Test name
Test status
Simulation time 81580708 ps
CPU time 3.31 seconds
Started May 09 12:33:38 PM PDT 24
Finished May 09 12:33:52 PM PDT 24
Peak memory 208532 kb
Host smart-78cd6ee9-d8f5-44b4-b022-1cec93fe63cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912326997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.2912326997
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.882457363
Short name T732
Test name
Test status
Simulation time 728455405 ps
CPU time 6.32 seconds
Started May 09 12:33:36 PM PDT 24
Finished May 09 12:33:53 PM PDT 24
Peak memory 207704 kb
Host smart-a67acea1-b8b0-4e83-ab1b-878016149caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882457363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.882457363
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.3902904823
Short name T605
Test name
Test status
Simulation time 386503920 ps
CPU time 5.88 seconds
Started May 09 12:33:51 PM PDT 24
Finished May 09 12:34:05 PM PDT 24
Peak memory 210036 kb
Host smart-6672ffd7-09ab-4d2b-9c2c-3436e58f8d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902904823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.3902904823
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.2588005048
Short name T788
Test name
Test status
Simulation time 12025609 ps
CPU time 0.75 seconds
Started May 09 12:34:37 PM PDT 24
Finished May 09 12:34:42 PM PDT 24
Peak memory 205880 kb
Host smart-710a6e61-6658-4989-af20-57f82e2e49a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588005048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.2588005048
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.1526252003
Short name T73
Test name
Test status
Simulation time 69336371 ps
CPU time 3.31 seconds
Started May 09 12:34:44 PM PDT 24
Finished May 09 12:34:53 PM PDT 24
Peak memory 209800 kb
Host smart-2f5007b5-2571-452d-b6f1-299e4b6a3962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526252003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.1526252003
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.2481506475
Short name T433
Test name
Test status
Simulation time 243595732 ps
CPU time 2.84 seconds
Started May 09 12:34:37 PM PDT 24
Finished May 09 12:34:44 PM PDT 24
Peak memory 217388 kb
Host smart-155765a2-7b1c-4646-96b6-b526bb0c2af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481506475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.2481506475
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.3651930451
Short name T674
Test name
Test status
Simulation time 91507599 ps
CPU time 4.42 seconds
Started May 09 12:34:24 PM PDT 24
Finished May 09 12:34:36 PM PDT 24
Peak memory 209148 kb
Host smart-9f0c4d15-eed4-4662-8d87-dc7b5006aaee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651930451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.3651930451
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.1130279720
Short name T725
Test name
Test status
Simulation time 39404717 ps
CPU time 1.69 seconds
Started May 09 12:34:30 PM PDT 24
Finished May 09 12:34:36 PM PDT 24
Peak memory 206716 kb
Host smart-4a790e45-39a1-49c0-be7f-95c06222d3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130279720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.1130279720
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.1187287049
Short name T540
Test name
Test status
Simulation time 493873617 ps
CPU time 2.35 seconds
Started May 09 12:34:22 PM PDT 24
Finished May 09 12:34:32 PM PDT 24
Peak memory 207016 kb
Host smart-d022a7c5-eaa0-4372-a0e4-38b71bef4954
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187287049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.1187287049
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.95823682
Short name T445
Test name
Test status
Simulation time 206383053 ps
CPU time 2.87 seconds
Started May 09 12:34:18 PM PDT 24
Finished May 09 12:34:29 PM PDT 24
Peak memory 206804 kb
Host smart-de1653df-67de-4b69-bf9c-8d01f235d2db
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95823682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.95823682
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.532591472
Short name T511
Test name
Test status
Simulation time 286931667 ps
CPU time 4.6 seconds
Started May 09 12:34:31 PM PDT 24
Finished May 09 12:34:40 PM PDT 24
Peak memory 208436 kb
Host smart-8b13296a-59ad-4633-b2df-d6f94e595171
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532591472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.532591472
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.1276120496
Short name T771
Test name
Test status
Simulation time 881386607 ps
CPU time 19.6 seconds
Started May 09 12:34:19 PM PDT 24
Finished May 09 12:34:47 PM PDT 24
Peak memory 207808 kb
Host smart-76a9847e-0c23-4467-8bdc-cdafc28a8de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276120496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.1276120496
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.1033379908
Short name T559
Test name
Test status
Simulation time 107700969 ps
CPU time 3.98 seconds
Started May 09 12:34:34 PM PDT 24
Finished May 09 12:34:42 PM PDT 24
Peak memory 208364 kb
Host smart-cd1e39b6-03e1-4868-aa33-084f30df0e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033379908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.1033379908
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.3717338053
Short name T896
Test name
Test status
Simulation time 418680099 ps
CPU time 10.89 seconds
Started May 09 12:34:41 PM PDT 24
Finished May 09 12:34:57 PM PDT 24
Peak memory 214628 kb
Host smart-6e1889ef-9111-4ca5-b978-a2701a6bc969
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717338053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.3717338053
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.3983238428
Short name T177
Test name
Test status
Simulation time 476276963 ps
CPU time 15.32 seconds
Started May 09 12:34:43 PM PDT 24
Finished May 09 12:35:03 PM PDT 24
Peak memory 219916 kb
Host smart-4bc29f0b-deaa-4322-8cdc-b474b92098cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983238428 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.3983238428
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.538156847
Short name T197
Test name
Test status
Simulation time 1279921043 ps
CPU time 16.43 seconds
Started May 09 12:34:20 PM PDT 24
Finished May 09 12:34:44 PM PDT 24
Peak memory 214168 kb
Host smart-bea26bca-2712-4ae1-8a6d-5ceb7806e195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538156847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.538156847
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.192976453
Short name T815
Test name
Test status
Simulation time 61727287 ps
CPU time 1.34 seconds
Started May 09 12:34:27 PM PDT 24
Finished May 09 12:34:34 PM PDT 24
Peak memory 209908 kb
Host smart-55ddf113-05a0-47d1-af5a-ad8a2a2ba6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192976453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.192976453
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.2209330044
Short name T764
Test name
Test status
Simulation time 37218444 ps
CPU time 0.84 seconds
Started May 09 12:34:46 PM PDT 24
Finished May 09 12:34:52 PM PDT 24
Peak memory 205796 kb
Host smart-2bf00f7b-1f53-4358-9e8b-06ea566f8085
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209330044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.2209330044
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.2286488877
Short name T371
Test name
Test status
Simulation time 158973148 ps
CPU time 3.65 seconds
Started May 09 12:34:54 PM PDT 24
Finished May 09 12:35:03 PM PDT 24
Peak memory 214096 kb
Host smart-fa139261-d5ef-41ef-8e1c-185ecafaf635
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2286488877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.2286488877
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.3754457704
Short name T719
Test name
Test status
Simulation time 237995489 ps
CPU time 2.7 seconds
Started May 09 12:34:50 PM PDT 24
Finished May 09 12:34:58 PM PDT 24
Peak memory 221792 kb
Host smart-01e736d8-8756-4d27-a2c8-1d33c89cdd75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754457704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.3754457704
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.2416391648
Short name T323
Test name
Test status
Simulation time 341060018 ps
CPU time 2.59 seconds
Started May 09 12:34:45 PM PDT 24
Finished May 09 12:34:52 PM PDT 24
Peak memory 206992 kb
Host smart-7a252beb-da38-4c5d-8d6d-f450a8171bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416391648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.2416391648
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.4102731453
Short name T599
Test name
Test status
Simulation time 199248661 ps
CPU time 5.63 seconds
Started May 09 12:34:30 PM PDT 24
Finished May 09 12:34:40 PM PDT 24
Peak memory 209408 kb
Host smart-cd885aa3-bacb-48f7-905c-bc9d20347ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102731453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.4102731453
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.3545577955
Short name T326
Test name
Test status
Simulation time 159720154 ps
CPU time 5.65 seconds
Started May 09 12:34:33 PM PDT 24
Finished May 09 12:34:43 PM PDT 24
Peak memory 206984 kb
Host smart-00800b36-ec20-496c-b909-f107b3e2f513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545577955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.3545577955
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.398850472
Short name T885
Test name
Test status
Simulation time 192382750 ps
CPU time 3.52 seconds
Started May 09 12:34:31 PM PDT 24
Finished May 09 12:34:39 PM PDT 24
Peak memory 208668 kb
Host smart-03b0592b-e52e-4f05-86f1-78fb50c1a185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398850472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.398850472
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.3802855854
Short name T537
Test name
Test status
Simulation time 227549128 ps
CPU time 5.61 seconds
Started May 09 12:34:46 PM PDT 24
Finished May 09 12:34:57 PM PDT 24
Peak memory 209516 kb
Host smart-39c2d9bc-cc1d-4eea-95e0-4aaf804a4cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802855854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.3802855854
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.864650175
Short name T487
Test name
Test status
Simulation time 71479261 ps
CPU time 2.98 seconds
Started May 09 12:34:20 PM PDT 24
Finished May 09 12:34:31 PM PDT 24
Peak memory 207920 kb
Host smart-cd5e7d01-5d42-4700-9ddd-01c95465b8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864650175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.864650175
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.4184341499
Short name T695
Test name
Test status
Simulation time 104423931 ps
CPU time 2.23 seconds
Started May 09 12:34:42 PM PDT 24
Finished May 09 12:34:49 PM PDT 24
Peak memory 208504 kb
Host smart-7bfc4d4b-e6d0-4221-8d81-764be205f625
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184341499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.4184341499
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.166598355
Short name T835
Test name
Test status
Simulation time 838754314 ps
CPU time 7.61 seconds
Started May 09 12:34:40 PM PDT 24
Finished May 09 12:34:52 PM PDT 24
Peak memory 208292 kb
Host smart-9af740e2-f02d-46c2-bada-227d9d74fa16
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166598355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.166598355
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.1920141293
Short name T525
Test name
Test status
Simulation time 590261946 ps
CPU time 2.91 seconds
Started May 09 12:34:49 PM PDT 24
Finished May 09 12:34:57 PM PDT 24
Peak memory 208168 kb
Host smart-177d7849-9b37-4697-ae83-fdc3cc00ed52
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920141293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.1920141293
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.2419465487
Short name T287
Test name
Test status
Simulation time 45129861 ps
CPU time 2.52 seconds
Started May 09 12:34:45 PM PDT 24
Finished May 09 12:34:53 PM PDT 24
Peak memory 208748 kb
Host smart-15c85e30-46b5-49d6-bdf7-2422f1e76e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419465487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.2419465487
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.4108517783
Short name T602
Test name
Test status
Simulation time 577212775 ps
CPU time 6.25 seconds
Started May 09 12:34:28 PM PDT 24
Finished May 09 12:34:40 PM PDT 24
Peak memory 207912 kb
Host smart-1c9c71e4-4ef4-4135-8afb-eba3944dd42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108517783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.4108517783
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.3128052515
Short name T243
Test name
Test status
Simulation time 687352303 ps
CPU time 10.99 seconds
Started May 09 12:34:34 PM PDT 24
Finished May 09 12:34:49 PM PDT 24
Peak memory 220016 kb
Host smart-176f19a6-f381-4636-a5ae-dcd5ede1beda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128052515 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.3128052515
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.4168296284
Short name T610
Test name
Test status
Simulation time 469391640 ps
CPU time 5.28 seconds
Started May 09 12:34:50 PM PDT 24
Finished May 09 12:35:00 PM PDT 24
Peak memory 208928 kb
Host smart-e0700795-c27a-4ee3-a93f-ced6e4ac19e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168296284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.4168296284
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.2012532218
Short name T761
Test name
Test status
Simulation time 504386714 ps
CPU time 3.6 seconds
Started May 09 12:34:45 PM PDT 24
Finished May 09 12:34:54 PM PDT 24
Peak memory 210240 kb
Host smart-26d06fde-6852-49f9-9d2d-020a86b9d712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012532218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.2012532218
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.993328823
Short name T783
Test name
Test status
Simulation time 14843886 ps
CPU time 0.77 seconds
Started May 09 12:34:32 PM PDT 24
Finished May 09 12:34:36 PM PDT 24
Peak memory 205856 kb
Host smart-6f3a93b4-f149-4310-9b1f-a21a36ec3c82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993328823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.993328823
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.3975714521
Short name T227
Test name
Test status
Simulation time 62445599 ps
CPU time 3.84 seconds
Started May 09 12:34:30 PM PDT 24
Finished May 09 12:34:38 PM PDT 24
Peak memory 214244 kb
Host smart-add1d059-8942-4b83-9edf-fda95da024e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3975714521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.3975714521
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.3473853430
Short name T585
Test name
Test status
Simulation time 75911718 ps
CPU time 2.66 seconds
Started May 09 12:34:47 PM PDT 24
Finished May 09 12:34:55 PM PDT 24
Peak memory 209364 kb
Host smart-798ead7b-44f2-49b5-9e61-7f9e37f3d4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473853430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.3473853430
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.12903153
Short name T442
Test name
Test status
Simulation time 123120985 ps
CPU time 4.43 seconds
Started May 09 12:34:35 PM PDT 24
Finished May 09 12:34:43 PM PDT 24
Peak memory 209572 kb
Host smart-694d57d3-44e1-4b6f-b624-392a0e0d5b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12903153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.12903153
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.2290061957
Short name T811
Test name
Test status
Simulation time 341765971 ps
CPU time 3.12 seconds
Started May 09 12:34:36 PM PDT 24
Finished May 09 12:34:43 PM PDT 24
Peak memory 222472 kb
Host smart-d2d1b400-3525-421c-b640-bbaa5d290115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290061957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.2290061957
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.387058022
Short name T248
Test name
Test status
Simulation time 110453748 ps
CPU time 4.91 seconds
Started May 09 12:34:50 PM PDT 24
Finished May 09 12:35:00 PM PDT 24
Peak memory 221140 kb
Host smart-8aaba857-e0e4-44d6-a91a-68dbfeee2cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387058022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.387058022
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.2883767641
Short name T214
Test name
Test status
Simulation time 101334644 ps
CPU time 2.75 seconds
Started May 09 12:34:46 PM PDT 24
Finished May 09 12:34:54 PM PDT 24
Peak memory 214180 kb
Host smart-423bc6ca-44c0-46d9-b884-45be9405e7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883767641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.2883767641
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.2189737404
Short name T845
Test name
Test status
Simulation time 358586823 ps
CPU time 3.43 seconds
Started May 09 12:34:36 PM PDT 24
Finished May 09 12:34:43 PM PDT 24
Peak memory 222324 kb
Host smart-56b6b248-ab04-42c3-b251-289a6337950a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189737404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.2189737404
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.3340656693
Short name T485
Test name
Test status
Simulation time 208808824 ps
CPU time 5.11 seconds
Started May 09 12:34:59 PM PDT 24
Finished May 09 12:35:12 PM PDT 24
Peak memory 207072 kb
Host smart-f591b95d-7cc6-4dd7-a430-5533d22fcaa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340656693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.3340656693
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.578308907
Short name T757
Test name
Test status
Simulation time 1012321287 ps
CPU time 18.82 seconds
Started May 09 12:34:36 PM PDT 24
Finished May 09 12:35:00 PM PDT 24
Peak memory 207932 kb
Host smart-bda9974e-8afd-420b-91c0-107d0a00fdcb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578308907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.578308907
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.601500876
Short name T180
Test name
Test status
Simulation time 68823094 ps
CPU time 2.39 seconds
Started May 09 12:34:43 PM PDT 24
Finished May 09 12:34:50 PM PDT 24
Peak memory 206652 kb
Host smart-81773767-763e-4f68-816c-f21b81f4d35b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601500876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.601500876
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.4100346732
Short name T648
Test name
Test status
Simulation time 20471137 ps
CPU time 1.7 seconds
Started May 09 12:34:50 PM PDT 24
Finished May 09 12:34:57 PM PDT 24
Peak memory 206612 kb
Host smart-1209b2c2-0a58-45b7-9eef-08c3e116d51d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100346732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.4100346732
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.2253061076
Short name T568
Test name
Test status
Simulation time 64015542 ps
CPU time 3.04 seconds
Started May 09 12:34:34 PM PDT 24
Finished May 09 12:34:47 PM PDT 24
Peak memory 209276 kb
Host smart-c6383e43-3e21-4679-a574-f000c5a2ae9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253061076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.2253061076
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.98623623
Short name T672
Test name
Test status
Simulation time 169926113 ps
CPU time 4.17 seconds
Started May 09 12:34:35 PM PDT 24
Finished May 09 12:34:43 PM PDT 24
Peak memory 207672 kb
Host smart-b323d881-3e75-45a8-b2b6-698abdcc36c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98623623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.98623623
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.1446378378
Short name T611
Test name
Test status
Simulation time 2917630229 ps
CPU time 54.61 seconds
Started May 09 12:34:37 PM PDT 24
Finished May 09 12:35:36 PM PDT 24
Peak memory 215532 kb
Host smart-b23aec30-977f-48b2-869c-f96ebfc2f389
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446378378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.1446378378
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.2403066458
Short name T644
Test name
Test status
Simulation time 2084415936 ps
CPU time 51.65 seconds
Started May 09 12:34:43 PM PDT 24
Finished May 09 12:35:40 PM PDT 24
Peak memory 221380 kb
Host smart-12d4243d-71b7-440e-8a33-cf08adaea860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403066458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.2403066458
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.3791354422
Short name T577
Test name
Test status
Simulation time 809489973 ps
CPU time 3.06 seconds
Started May 09 12:34:29 PM PDT 24
Finished May 09 12:34:37 PM PDT 24
Peak memory 210232 kb
Host smart-8b935ea2-041e-42df-b92b-1689e2e038ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791354422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.3791354422
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.4076497946
Short name T745
Test name
Test status
Simulation time 45510720 ps
CPU time 0.72 seconds
Started May 09 12:34:37 PM PDT 24
Finished May 09 12:34:42 PM PDT 24
Peak memory 205800 kb
Host smart-b7c3bf53-08bf-48e3-b70b-a26c56d261b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076497946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.4076497946
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.3474856026
Short name T277
Test name
Test status
Simulation time 187912279 ps
CPU time 3.7 seconds
Started May 09 12:34:32 PM PDT 24
Finished May 09 12:34:39 PM PDT 24
Peak memory 214160 kb
Host smart-95a7bfa6-ca22-4d25-a1f0-9685bb3584a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3474856026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.3474856026
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.657745435
Short name T898
Test name
Test status
Simulation time 273089601 ps
CPU time 2.57 seconds
Started May 09 12:34:31 PM PDT 24
Finished May 09 12:34:38 PM PDT 24
Peak memory 214408 kb
Host smart-78233f1e-3e5a-4899-80d0-a2cfdf93eec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657745435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.657745435
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.327525562
Short name T535
Test name
Test status
Simulation time 145156659 ps
CPU time 2.14 seconds
Started May 09 12:34:40 PM PDT 24
Finished May 09 12:34:47 PM PDT 24
Peak memory 209388 kb
Host smart-24fdeee1-73a4-4036-99d1-c8528a6f2484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327525562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.327525562
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.3691431317
Short name T441
Test name
Test status
Simulation time 494382735 ps
CPU time 4.98 seconds
Started May 09 12:34:57 PM PDT 24
Finished May 09 12:35:09 PM PDT 24
Peak memory 214072 kb
Host smart-7921c040-265a-491c-a08d-3fe134700055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691431317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.3691431317
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.281669996
Short name T507
Test name
Test status
Simulation time 218646152 ps
CPU time 3.37 seconds
Started May 09 12:34:57 PM PDT 24
Finished May 09 12:35:08 PM PDT 24
Peak memory 214176 kb
Host smart-6c7a3dcf-ff32-4971-a52f-21db3bd92e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281669996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.281669996
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.139441468
Short name T61
Test name
Test status
Simulation time 69224317 ps
CPU time 2.72 seconds
Started May 09 12:34:32 PM PDT 24
Finished May 09 12:34:45 PM PDT 24
Peak memory 209532 kb
Host smart-c95382de-24af-4c79-9afc-1c5229bb677d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139441468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.139441468
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.3342964251
Short name T274
Test name
Test status
Simulation time 896912952 ps
CPU time 6.82 seconds
Started May 09 12:34:50 PM PDT 24
Finished May 09 12:35:02 PM PDT 24
Peak memory 214288 kb
Host smart-c94d7986-ad17-4f35-8046-460424fa11a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342964251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.3342964251
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.327586611
Short name T692
Test name
Test status
Simulation time 457874909 ps
CPU time 3.85 seconds
Started May 09 12:34:31 PM PDT 24
Finished May 09 12:34:44 PM PDT 24
Peak memory 208312 kb
Host smart-437bd06d-2e27-4e43-908d-91cb2dcae637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327586611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.327586611
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.4153250555
Short name T373
Test name
Test status
Simulation time 234165275 ps
CPU time 5.77 seconds
Started May 09 12:34:47 PM PDT 24
Finished May 09 12:34:58 PM PDT 24
Peak memory 208072 kb
Host smart-d8519997-aaa1-425f-9d8f-70aa99914c17
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153250555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.4153250555
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.3829328574
Short name T620
Test name
Test status
Simulation time 509866962 ps
CPU time 6.25 seconds
Started May 09 12:34:50 PM PDT 24
Finished May 09 12:35:02 PM PDT 24
Peak memory 207860 kb
Host smart-0165e02b-dc89-4e11-994e-a6da588b06dc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829328574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.3829328574
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.1303590441
Short name T311
Test name
Test status
Simulation time 23403811 ps
CPU time 1.93 seconds
Started May 09 12:34:52 PM PDT 24
Finished May 09 12:34:58 PM PDT 24
Peak memory 208384 kb
Host smart-0e5529d8-c0b4-4353-87e4-2d592a685dd3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303590441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.1303590441
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.4292380203
Short name T676
Test name
Test status
Simulation time 168676835 ps
CPU time 2.59 seconds
Started May 09 12:34:56 PM PDT 24
Finished May 09 12:35:06 PM PDT 24
Peak memory 209344 kb
Host smart-94e7aa60-b503-4e1b-aef5-3c8ac3520758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292380203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.4292380203
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.749941751
Short name T694
Test name
Test status
Simulation time 97552231 ps
CPU time 3.45 seconds
Started May 09 12:34:43 PM PDT 24
Finished May 09 12:34:52 PM PDT 24
Peak memory 206652 kb
Host smart-0ca5da38-3fc5-448b-bf6c-fb9daff09b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749941751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.749941751
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.3371762929
Short name T188
Test name
Test status
Simulation time 3156744606 ps
CPU time 72.81 seconds
Started May 09 12:34:33 PM PDT 24
Finished May 09 12:35:49 PM PDT 24
Peak memory 222384 kb
Host smart-852d1164-2a03-4120-8953-8cfac72f3f7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371762929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.3371762929
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.3336322644
Short name T51
Test name
Test status
Simulation time 4359721544 ps
CPU time 21.65 seconds
Started May 09 12:34:32 PM PDT 24
Finished May 09 12:34:58 PM PDT 24
Peak memory 221252 kb
Host smart-2bf99ecf-4157-43a2-a9e8-cc3536f5cc2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336322644 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.3336322644
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.1966604882
Short name T120
Test name
Test status
Simulation time 459850334 ps
CPU time 5.83 seconds
Started May 09 12:34:46 PM PDT 24
Finished May 09 12:34:57 PM PDT 24
Peak memory 214240 kb
Host smart-9797f3ab-5017-4340-bc42-e531b71f5341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966604882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.1966604882
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.3227611841
Short name T641
Test name
Test status
Simulation time 458417225 ps
CPU time 3.91 seconds
Started May 09 12:34:58 PM PDT 24
Finished May 09 12:35:10 PM PDT 24
Peak memory 210504 kb
Host smart-23958f28-0f88-47d3-9a92-8d23ebcb1932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227611841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.3227611841
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.3200135117
Short name T606
Test name
Test status
Simulation time 12110650 ps
CPU time 0.74 seconds
Started May 09 12:34:36 PM PDT 24
Finished May 09 12:34:41 PM PDT 24
Peak memory 205808 kb
Host smart-01f118ce-b6ae-417e-b70f-1fb0d1718865
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200135117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.3200135117
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.596676925
Short name T186
Test name
Test status
Simulation time 69026961 ps
CPU time 2.9 seconds
Started May 09 12:35:01 PM PDT 24
Finished May 09 12:35:12 PM PDT 24
Peak memory 214156 kb
Host smart-a95c52d0-fc98-4609-8f62-53c886f03f86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=596676925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.596676925
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.3755332849
Short name T619
Test name
Test status
Simulation time 95114102 ps
CPU time 2.62 seconds
Started May 09 12:34:36 PM PDT 24
Finished May 09 12:34:43 PM PDT 24
Peak memory 220248 kb
Host smart-d533d6f9-5209-45af-96c2-d58ff3283b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755332849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.3755332849
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.1965758501
Short name T780
Test name
Test status
Simulation time 477432309 ps
CPU time 10.47 seconds
Started May 09 12:34:41 PM PDT 24
Finished May 09 12:34:56 PM PDT 24
Peak memory 218468 kb
Host smart-8092a33a-13c1-4c56-a6a7-d03cadaa5db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965758501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.1965758501
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.2380710451
Short name T232
Test name
Test status
Simulation time 34469397 ps
CPU time 1.74 seconds
Started May 09 12:34:56 PM PDT 24
Finished May 09 12:35:05 PM PDT 24
Peak memory 214180 kb
Host smart-bab73f89-39a9-4248-bbfd-3683a6fec45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380710451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.2380710451
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.2439767081
Short name T136
Test name
Test status
Simulation time 49056977 ps
CPU time 3.45 seconds
Started May 09 12:35:10 PM PDT 24
Finished May 09 12:35:25 PM PDT 24
Peak memory 220000 kb
Host smart-9b7d7be5-3eef-4437-b592-725ce6746806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439767081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.2439767081
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.1314407354
Short name T884
Test name
Test status
Simulation time 186219486 ps
CPU time 5.87 seconds
Started May 09 12:34:50 PM PDT 24
Finished May 09 12:35:01 PM PDT 24
Peak memory 214200 kb
Host smart-9c5a2c0b-4654-4511-acbd-63c886b2fe49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314407354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.1314407354
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.1843522369
Short name T800
Test name
Test status
Simulation time 459423467 ps
CPU time 3.16 seconds
Started May 09 12:34:35 PM PDT 24
Finished May 09 12:34:42 PM PDT 24
Peak memory 206736 kb
Host smart-54fa6dd3-5ddd-448c-936e-53d7983cdf97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843522369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.1843522369
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.2148894147
Short name T494
Test name
Test status
Simulation time 43297226 ps
CPU time 2.36 seconds
Started May 09 12:34:39 PM PDT 24
Finished May 09 12:34:46 PM PDT 24
Peak memory 208032 kb
Host smart-6d8bf392-70ec-4dcc-9a89-c378ccf9e49c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148894147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.2148894147
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.4133907934
Short name T703
Test name
Test status
Simulation time 8343821629 ps
CPU time 41.12 seconds
Started May 09 12:34:33 PM PDT 24
Finished May 09 12:35:17 PM PDT 24
Peak memory 208460 kb
Host smart-4900d0ad-cc2a-4c32-adad-1f1599af947c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133907934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.4133907934
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.4130568416
Short name T185
Test name
Test status
Simulation time 266465274 ps
CPU time 3.24 seconds
Started May 09 12:35:00 PM PDT 24
Finished May 09 12:35:12 PM PDT 24
Peak memory 208704 kb
Host smart-59d8c1b7-56be-4136-ae99-896cd427a1f7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130568416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.4130568416
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.473247849
Short name T134
Test name
Test status
Simulation time 1048728051 ps
CPU time 3.22 seconds
Started May 09 12:34:38 PM PDT 24
Finished May 09 12:34:46 PM PDT 24
Peak memory 207800 kb
Host smart-5b7e7543-541a-4691-8a23-9df58f643403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473247849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.473247849
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.76002371
Short name T593
Test name
Test status
Simulation time 88884124 ps
CPU time 2.85 seconds
Started May 09 12:34:39 PM PDT 24
Finished May 09 12:34:46 PM PDT 24
Peak memory 207228 kb
Host smart-6a63faf9-195d-4afd-bc56-e99ec37cbe79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76002371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.76002371
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.2479275252
Short name T823
Test name
Test status
Simulation time 150733994 ps
CPU time 10.08 seconds
Started May 09 12:34:36 PM PDT 24
Finished May 09 12:34:50 PM PDT 24
Peak memory 220440 kb
Host smart-2f58393b-d9ce-40d8-ad60-986d98bf8a53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479275252 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.2479275252
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.55214958
Short name T500
Test name
Test status
Simulation time 464962236 ps
CPU time 4.25 seconds
Started May 09 12:34:48 PM PDT 24
Finished May 09 12:34:57 PM PDT 24
Peak memory 209272 kb
Host smart-e5b1d815-8f91-4bdf-ad16-657e2051f0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55214958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.55214958
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.2284139811
Short name T365
Test name
Test status
Simulation time 349731665 ps
CPU time 2.78 seconds
Started May 09 12:34:58 PM PDT 24
Finished May 09 12:35:08 PM PDT 24
Peak memory 210104 kb
Host smart-c25f5a92-fdf0-4aad-ae67-421932af54d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284139811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.2284139811
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.1827509072
Short name T572
Test name
Test status
Simulation time 20595401 ps
CPU time 0.69 seconds
Started May 09 12:34:40 PM PDT 24
Finished May 09 12:34:45 PM PDT 24
Peak memory 205748 kb
Host smart-d58e5642-0469-4b54-a389-f2c47c06ccc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827509072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.1827509072
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.1925196028
Short name T229
Test name
Test status
Simulation time 1306093713 ps
CPU time 62.42 seconds
Started May 09 12:34:40 PM PDT 24
Finished May 09 12:35:47 PM PDT 24
Peak memory 214176 kb
Host smart-db9ba919-5a4f-4f78-80d8-a84c99d8c004
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1925196028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.1925196028
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.1214030668
Short name T21
Test name
Test status
Simulation time 117689315 ps
CPU time 2.36 seconds
Started May 09 12:34:55 PM PDT 24
Finished May 09 12:35:03 PM PDT 24
Peak memory 214380 kb
Host smart-8f522a73-de45-4718-88bf-0fef4a5b8581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214030668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.1214030668
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.3453008651
Short name T837
Test name
Test status
Simulation time 252879461 ps
CPU time 3.42 seconds
Started May 09 12:34:48 PM PDT 24
Finished May 09 12:34:56 PM PDT 24
Peak memory 207836 kb
Host smart-1ab552a6-7a41-4418-bc87-3d75e3058c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453008651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.3453008651
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.3955036833
Short name T808
Test name
Test status
Simulation time 1086382533 ps
CPU time 6.93 seconds
Started May 09 12:34:45 PM PDT 24
Finished May 09 12:34:57 PM PDT 24
Peak memory 209080 kb
Host smart-f49be6b1-894f-464a-9099-a4170fd0e542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955036833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.3955036833
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.2979929677
Short name T560
Test name
Test status
Simulation time 344330287 ps
CPU time 3.21 seconds
Started May 09 12:34:47 PM PDT 24
Finished May 09 12:34:56 PM PDT 24
Peak memory 219740 kb
Host smart-e6429811-2103-4476-9c45-f64753a32e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979929677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.2979929677
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.1723267460
Short name T512
Test name
Test status
Simulation time 145465608 ps
CPU time 4.23 seconds
Started May 09 12:34:50 PM PDT 24
Finished May 09 12:35:00 PM PDT 24
Peak memory 209232 kb
Host smart-8092a6ef-0361-4690-9b60-f032db71644b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723267460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.1723267460
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.259884032
Short name T914
Test name
Test status
Simulation time 65530373 ps
CPU time 3.22 seconds
Started May 09 12:34:33 PM PDT 24
Finished May 09 12:34:40 PM PDT 24
Peak memory 207412 kb
Host smart-ff0b9f82-8f09-48a4-831c-584158fc15b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259884032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.259884032
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.59219861
Short name T663
Test name
Test status
Simulation time 99833715 ps
CPU time 2.77 seconds
Started May 09 12:34:37 PM PDT 24
Finished May 09 12:34:44 PM PDT 24
Peak memory 206776 kb
Host smart-3f84993c-b227-413d-8790-b443aacb00c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59219861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.59219861
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.72491150
Short name T679
Test name
Test status
Simulation time 386222817 ps
CPU time 3.44 seconds
Started May 09 12:34:46 PM PDT 24
Finished May 09 12:34:55 PM PDT 24
Peak memory 207368 kb
Host smart-4e9ec9b8-6914-4455-a499-dcdf1b5e64b4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72491150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.72491150
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.806988650
Short name T312
Test name
Test status
Simulation time 2129556324 ps
CPU time 52.98 seconds
Started May 09 12:34:37 PM PDT 24
Finished May 09 12:35:34 PM PDT 24
Peak memory 208672 kb
Host smart-45e14987-c4e6-4153-8d22-0ef7689941cf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806988650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.806988650
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.1624651367
Short name T346
Test name
Test status
Simulation time 305617587 ps
CPU time 4.71 seconds
Started May 09 12:34:48 PM PDT 24
Finished May 09 12:34:58 PM PDT 24
Peak memory 208340 kb
Host smart-63f0b173-a003-4332-acc5-9d1c37d921fb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624651367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.1624651367
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.3673867396
Short name T95
Test name
Test status
Simulation time 245477491 ps
CPU time 5.09 seconds
Started May 09 12:34:50 PM PDT 24
Finished May 09 12:35:00 PM PDT 24
Peak memory 209772 kb
Host smart-38cf2b3c-8947-4503-93c0-bc6a5bcfe512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673867396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.3673867396
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.3615407774
Short name T421
Test name
Test status
Simulation time 137469084 ps
CPU time 1.89 seconds
Started May 09 12:35:12 PM PDT 24
Finished May 09 12:35:26 PM PDT 24
Peak memory 208264 kb
Host smart-2bce708c-6b09-4901-aff8-01f6132b3b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615407774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.3615407774
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.3390371982
Short name T211
Test name
Test status
Simulation time 8206261479 ps
CPU time 35 seconds
Started May 09 12:34:39 PM PDT 24
Finished May 09 12:35:19 PM PDT 24
Peak memory 222368 kb
Host smart-4750fd43-ffea-4f41-b286-641d8398d5d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390371982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.3390371982
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.2742738782
Short name T712
Test name
Test status
Simulation time 417810010 ps
CPU time 14.02 seconds
Started May 09 12:34:40 PM PDT 24
Finished May 09 12:34:59 PM PDT 24
Peak memory 222596 kb
Host smart-c5a934ee-22f3-4abe-ba29-722706d1cfac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742738782 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.2742738782
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.2464977329
Short name T556
Test name
Test status
Simulation time 196544058 ps
CPU time 5.89 seconds
Started May 09 12:34:58 PM PDT 24
Finished May 09 12:35:19 PM PDT 24
Peak memory 209312 kb
Host smart-d4ebbb33-6c0d-464c-844d-ab601a244d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464977329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.2464977329
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.1478132168
Short name T419
Test name
Test status
Simulation time 115082803 ps
CPU time 3.49 seconds
Started May 09 12:34:57 PM PDT 24
Finished May 09 12:35:08 PM PDT 24
Peak memory 210052 kb
Host smart-1aee381d-58db-4358-911f-e2c9ae4e229b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478132168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.1478132168
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.166419053
Short name T91
Test name
Test status
Simulation time 50306292 ps
CPU time 0.91 seconds
Started May 09 12:34:41 PM PDT 24
Finished May 09 12:34:46 PM PDT 24
Peak memory 206060 kb
Host smart-d14b165e-c2c4-4b77-a877-7d11289dddb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166419053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.166419053
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.1011547877
Short name T31
Test name
Test status
Simulation time 199397022 ps
CPU time 3.29 seconds
Started May 09 12:34:53 PM PDT 24
Finished May 09 12:35:00 PM PDT 24
Peak memory 209492 kb
Host smart-80dbbb08-1a09-4220-98c4-aef31802c69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011547877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.1011547877
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.2326139385
Short name T734
Test name
Test status
Simulation time 71233477 ps
CPU time 1.76 seconds
Started May 09 12:34:55 PM PDT 24
Finished May 09 12:35:04 PM PDT 24
Peak memory 207988 kb
Host smart-2480d535-5b03-4125-89bc-6599265bfafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326139385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.2326139385
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.3267159156
Short name T503
Test name
Test status
Simulation time 55223504 ps
CPU time 3.5 seconds
Started May 09 12:34:53 PM PDT 24
Finished May 09 12:35:01 PM PDT 24
Peak memory 214136 kb
Host smart-8247ab41-2faf-4a5f-84df-e05eb6e2649b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267159156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.3267159156
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.3501848250
Short name T265
Test name
Test status
Simulation time 191380107 ps
CPU time 2.92 seconds
Started May 09 12:34:57 PM PDT 24
Finished May 09 12:35:07 PM PDT 24
Peak memory 222280 kb
Host smart-0ade46c4-8c07-4b67-90fa-ea9296e7db7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501848250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.3501848250
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.1666307125
Short name T6
Test name
Test status
Simulation time 80573599 ps
CPU time 2.9 seconds
Started May 09 12:34:36 PM PDT 24
Finished May 09 12:34:43 PM PDT 24
Peak memory 214556 kb
Host smart-f389156e-36f9-42f4-a84e-a64a01482e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666307125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.1666307125
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.3036401789
Short name T555
Test name
Test status
Simulation time 109585686 ps
CPU time 4.66 seconds
Started May 09 12:34:53 PM PDT 24
Finished May 09 12:35:02 PM PDT 24
Peak memory 209880 kb
Host smart-a7cb36ca-0d22-4f16-a401-aa57896112f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036401789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.3036401789
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.3481718720
Short name T3
Test name
Test status
Simulation time 2472356855 ps
CPU time 12 seconds
Started May 09 12:34:57 PM PDT 24
Finished May 09 12:35:16 PM PDT 24
Peak memory 208696 kb
Host smart-0f9edbd2-6991-4054-a8f8-35c8dfcf94e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481718720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.3481718720
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.2387526245
Short name T638
Test name
Test status
Simulation time 44583010 ps
CPU time 1.78 seconds
Started May 09 12:34:49 PM PDT 24
Finished May 09 12:34:56 PM PDT 24
Peak memory 206700 kb
Host smart-450a0551-8d90-44a5-a366-fedeabab3427
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387526245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.2387526245
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.617644355
Short name T203
Test name
Test status
Simulation time 20399746 ps
CPU time 1.8 seconds
Started May 09 12:34:43 PM PDT 24
Finished May 09 12:34:50 PM PDT 24
Peak memory 207396 kb
Host smart-2669a936-d054-4ae8-898f-9e4e0f324ed9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617644355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.617644355
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.1792098376
Short name T254
Test name
Test status
Simulation time 63371268 ps
CPU time 3.01 seconds
Started May 09 12:34:55 PM PDT 24
Finished May 09 12:35:05 PM PDT 24
Peak memory 208480 kb
Host smart-42e9bb67-136c-43af-84d3-6f77d2e92912
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792098376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.1792098376
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.2133545440
Short name T196
Test name
Test status
Simulation time 152157579 ps
CPU time 1.67 seconds
Started May 09 12:34:57 PM PDT 24
Finished May 09 12:35:06 PM PDT 24
Peak memory 208400 kb
Host smart-1b5c1501-86c0-4dc2-8404-532a36c92d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133545440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.2133545440
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.3628835279
Short name T689
Test name
Test status
Simulation time 85430693 ps
CPU time 2.5 seconds
Started May 09 12:34:46 PM PDT 24
Finished May 09 12:34:54 PM PDT 24
Peak memory 208548 kb
Host smart-d8bfcf82-be5f-4899-b68c-88d70dabddae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628835279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.3628835279
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.1963065319
Short name T68
Test name
Test status
Simulation time 3624205205 ps
CPU time 24.6 seconds
Started May 09 12:34:33 PM PDT 24
Finished May 09 12:35:01 PM PDT 24
Peak memory 222480 kb
Host smart-b3d2a82a-01b3-435f-ad01-47e0cab4f6e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963065319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.1963065319
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.4037141806
Short name T765
Test name
Test status
Simulation time 159997629 ps
CPU time 4.36 seconds
Started May 09 12:34:40 PM PDT 24
Finished May 09 12:34:49 PM PDT 24
Peak memory 214160 kb
Host smart-c4b97a88-9a95-44da-9e20-8ab7ee467fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037141806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.4037141806
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.773624094
Short name T907
Test name
Test status
Simulation time 89469195 ps
CPU time 2.37 seconds
Started May 09 12:34:36 PM PDT 24
Finished May 09 12:34:43 PM PDT 24
Peak memory 209856 kb
Host smart-e0fe26c8-be17-4cc9-9c22-d61005590fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773624094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.773624094
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.724509853
Short name T460
Test name
Test status
Simulation time 17586047 ps
CPU time 0.74 seconds
Started May 09 12:34:40 PM PDT 24
Finished May 09 12:34:46 PM PDT 24
Peak memory 205772 kb
Host smart-46fbe216-8076-4f7b-a4fb-3b2fb9b2af78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724509853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.724509853
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.4268655068
Short name T64
Test name
Test status
Simulation time 79509748 ps
CPU time 3.32 seconds
Started May 09 12:34:56 PM PDT 24
Finished May 09 12:35:07 PM PDT 24
Peak memory 214152 kb
Host smart-3ad367e5-9c4d-4e2b-a71a-08aa2b405202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268655068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.4268655068
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.20659670
Short name T477
Test name
Test status
Simulation time 22951190 ps
CPU time 1.72 seconds
Started May 09 12:34:50 PM PDT 24
Finished May 09 12:34:57 PM PDT 24
Peak memory 207668 kb
Host smart-f4a02a58-e8e3-43f8-a92d-23825e3ea66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20659670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.20659670
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.4058240315
Short name T698
Test name
Test status
Simulation time 36080676 ps
CPU time 2.43 seconds
Started May 09 12:35:06 PM PDT 24
Finished May 09 12:35:19 PM PDT 24
Peak memory 214184 kb
Host smart-0d78665e-5ffe-43b0-9139-357895e54f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058240315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.4058240315
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.996974731
Short name T548
Test name
Test status
Simulation time 76915078 ps
CPU time 2.56 seconds
Started May 09 12:35:01 PM PDT 24
Finished May 09 12:35:12 PM PDT 24
Peak memory 214232 kb
Host smart-1a0089b4-fd42-4619-8a10-9a3b7dd3e45c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996974731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.996974731
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.1954071791
Short name T776
Test name
Test status
Simulation time 54167965 ps
CPU time 1.95 seconds
Started May 09 12:34:58 PM PDT 24
Finished May 09 12:35:08 PM PDT 24
Peak memory 205960 kb
Host smart-3ba31d46-77a8-4819-a5d4-5b7b4ac2dd16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954071791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.1954071791
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.3628365469
Short name T900
Test name
Test status
Simulation time 483527433 ps
CPU time 4.36 seconds
Started May 09 12:34:55 PM PDT 24
Finished May 09 12:35:05 PM PDT 24
Peak memory 207052 kb
Host smart-5f8f6be0-45f2-4908-a658-fcadd9359754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628365469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.3628365469
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.3016670730
Short name T125
Test name
Test status
Simulation time 33276610 ps
CPU time 2.09 seconds
Started May 09 12:34:34 PM PDT 24
Finished May 09 12:34:39 PM PDT 24
Peak memory 206852 kb
Host smart-9e8b882f-4780-4f29-99d7-2b71cf7d7d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016670730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.3016670730
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.3603793615
Short name T684
Test name
Test status
Simulation time 84598205 ps
CPU time 3.81 seconds
Started May 09 12:34:37 PM PDT 24
Finished May 09 12:34:45 PM PDT 24
Peak memory 208528 kb
Host smart-104b3ad0-9b7b-48ce-804b-e029f340f566
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603793615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.3603793615
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.3563298814
Short name T204
Test name
Test status
Simulation time 258801165 ps
CPU time 2.47 seconds
Started May 09 12:34:37 PM PDT 24
Finished May 09 12:34:43 PM PDT 24
Peak memory 206596 kb
Host smart-d3be9e93-2539-48c5-9843-f415507a00fe
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563298814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.3563298814
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.3709482414
Short name T131
Test name
Test status
Simulation time 201285392 ps
CPU time 3.15 seconds
Started May 09 12:34:34 PM PDT 24
Finished May 09 12:34:40 PM PDT 24
Peak memory 208340 kb
Host smart-e9a2b5bf-79eb-4e57-a9e0-69a3fa6f675d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709482414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.3709482414
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.2607541783
Short name T665
Test name
Test status
Simulation time 2155962113 ps
CPU time 18.64 seconds
Started May 09 12:35:22 PM PDT 24
Finished May 09 12:35:52 PM PDT 24
Peak memory 209340 kb
Host smart-acff8ebe-34bf-4316-99aa-2183fe3ae785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607541783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.2607541783
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.2425497141
Short name T634
Test name
Test status
Simulation time 741484429 ps
CPU time 4.8 seconds
Started May 09 12:34:41 PM PDT 24
Finished May 09 12:34:50 PM PDT 24
Peak memory 207816 kb
Host smart-94fc9d36-fd84-4d90-86c4-26794ddc47c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425497141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.2425497141
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.1674189444
Short name T333
Test name
Test status
Simulation time 92165672 ps
CPU time 6.94 seconds
Started May 09 12:34:54 PM PDT 24
Finished May 09 12:35:06 PM PDT 24
Peak memory 222408 kb
Host smart-e9bfa10d-19dc-4fdf-b345-1387ab72c416
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674189444 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.1674189444
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.980735457
Short name T497
Test name
Test status
Simulation time 305218339 ps
CPU time 4.55 seconds
Started May 09 12:34:57 PM PDT 24
Finished May 09 12:35:08 PM PDT 24
Peak memory 214140 kb
Host smart-dec3a988-bd30-4f44-8e17-fbf2b57aa730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980735457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.980735457
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.518127352
Short name T76
Test name
Test status
Simulation time 60680436 ps
CPU time 1.94 seconds
Started May 09 12:34:56 PM PDT 24
Finished May 09 12:35:04 PM PDT 24
Peak memory 209952 kb
Host smart-618b4b02-3bea-4c27-9989-befdd49cedf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518127352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.518127352
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.2488104464
Short name T574
Test name
Test status
Simulation time 20114346 ps
CPU time 0.79 seconds
Started May 09 12:34:59 PM PDT 24
Finished May 09 12:35:15 PM PDT 24
Peak memory 205812 kb
Host smart-c0acd84d-a666-4d2b-b905-7f71c39ca854
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488104464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.2488104464
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.1797746805
Short name T395
Test name
Test status
Simulation time 137079857 ps
CPU time 2.39 seconds
Started May 09 12:35:00 PM PDT 24
Finished May 09 12:35:11 PM PDT 24
Peak memory 214260 kb
Host smart-3ccb163b-d159-469e-bc62-6dc55d344e26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1797746805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.1797746805
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.3772097561
Short name T38
Test name
Test status
Simulation time 61851218 ps
CPU time 2.34 seconds
Started May 09 12:34:51 PM PDT 24
Finished May 09 12:34:58 PM PDT 24
Peak memory 214048 kb
Host smart-957fcc6c-88a4-4b8b-8da9-e96dc0e7700e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772097561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.3772097561
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.589229376
Short name T567
Test name
Test status
Simulation time 19744508 ps
CPU time 1.58 seconds
Started May 09 12:35:05 PM PDT 24
Finished May 09 12:35:18 PM PDT 24
Peak memory 207628 kb
Host smart-e15a7f06-823d-4c83-b944-92d35d62103d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589229376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.589229376
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.3586412066
Short name T86
Test name
Test status
Simulation time 136507528 ps
CPU time 4.93 seconds
Started May 09 12:34:58 PM PDT 24
Finished May 09 12:35:10 PM PDT 24
Peak memory 214188 kb
Host smart-c9246586-79fc-44fe-8d3b-3592439b0dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586412066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.3586412066
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.2887194400
Short name T250
Test name
Test status
Simulation time 65683360 ps
CPU time 2.22 seconds
Started May 09 12:35:22 PM PDT 24
Finished May 09 12:35:36 PM PDT 24
Peak memory 214148 kb
Host smart-011462a6-8540-499c-83d0-af2e93a32ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887194400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.2887194400
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.123432002
Short name T332
Test name
Test status
Simulation time 132959596 ps
CPU time 3.72 seconds
Started May 09 12:34:42 PM PDT 24
Finished May 09 12:34:51 PM PDT 24
Peak memory 220432 kb
Host smart-5452fda9-5c5a-4130-b258-0d3a0e23f99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123432002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.123432002
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.2595558810
Short name T437
Test name
Test status
Simulation time 76002536 ps
CPU time 2.74 seconds
Started May 09 12:34:57 PM PDT 24
Finished May 09 12:35:08 PM PDT 24
Peak memory 207480 kb
Host smart-42f186ef-e6d1-4c82-b5db-5886c8410b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595558810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.2595558810
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.3263977121
Short name T462
Test name
Test status
Simulation time 204303359 ps
CPU time 2.49 seconds
Started May 09 12:34:51 PM PDT 24
Finished May 09 12:34:58 PM PDT 24
Peak memory 206664 kb
Host smart-902b56f2-6f0f-438c-8080-880ae4878423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263977121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.3263977121
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.26880870
Short name T296
Test name
Test status
Simulation time 63211462 ps
CPU time 1.69 seconds
Started May 09 12:34:59 PM PDT 24
Finished May 09 12:35:08 PM PDT 24
Peak memory 206600 kb
Host smart-39e8ea1c-b6a9-44db-852b-a5d9f09341a0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26880870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.26880870
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.2641141020
Short name T583
Test name
Test status
Simulation time 63578296 ps
CPU time 2.42 seconds
Started May 09 12:35:18 PM PDT 24
Finished May 09 12:35:32 PM PDT 24
Peak memory 206808 kb
Host smart-dcfb3a0f-965f-481b-ad2e-6180fa059ad1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641141020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.2641141020
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.3657060566
Short name T639
Test name
Test status
Simulation time 430293765 ps
CPU time 2.28 seconds
Started May 09 12:34:57 PM PDT 24
Finished May 09 12:35:07 PM PDT 24
Peak memory 208724 kb
Host smart-2a275f6b-0467-492b-ac39-e37329ba9117
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657060566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.3657060566
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.3196830747
Short name T193
Test name
Test status
Simulation time 532744082 ps
CPU time 2.82 seconds
Started May 09 12:35:10 PM PDT 24
Finished May 09 12:35:24 PM PDT 24
Peak memory 208960 kb
Host smart-9b8b124a-2086-417e-a041-2fbe8df1365a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196830747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.3196830747
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.1856642232
Short name T194
Test name
Test status
Simulation time 87086889 ps
CPU time 2.3 seconds
Started May 09 12:35:00 PM PDT 24
Finished May 09 12:35:10 PM PDT 24
Peak memory 206772 kb
Host smart-8e85da0a-8f55-4b4a-bef9-110aa23e19d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856642232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.1856642232
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.3420461853
Short name T841
Test name
Test status
Simulation time 12018660775 ps
CPU time 200.18 seconds
Started May 09 12:35:14 PM PDT 24
Finished May 09 12:38:46 PM PDT 24
Peak memory 219864 kb
Host smart-fb78d002-8efe-4b19-921b-dd4095e3704a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420461853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.3420461853
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.4266585549
Short name T244
Test name
Test status
Simulation time 1504305575 ps
CPU time 5.87 seconds
Started May 09 12:35:00 PM PDT 24
Finished May 09 12:35:15 PM PDT 24
Peak memory 208188 kb
Host smart-376ef9a0-4a41-410b-95f5-03ba9ee11175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266585549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.4266585549
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.1936208273
Short name T165
Test name
Test status
Simulation time 898667776 ps
CPU time 2.33 seconds
Started May 09 12:34:45 PM PDT 24
Finished May 09 12:34:52 PM PDT 24
Peak memory 210832 kb
Host smart-c85c86ae-ef87-46fe-934b-afe3316f0f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936208273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.1936208273
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.1804431291
Short name T513
Test name
Test status
Simulation time 50386760 ps
CPU time 0.9 seconds
Started May 09 12:34:43 PM PDT 24
Finished May 09 12:34:49 PM PDT 24
Peak memory 205980 kb
Host smart-5dcab5f9-0c7d-4f37-acee-3bf9c6467957
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804431291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.1804431291
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.17084586
Short name T385
Test name
Test status
Simulation time 269775250 ps
CPU time 14.59 seconds
Started May 09 12:34:47 PM PDT 24
Finished May 09 12:35:07 PM PDT 24
Peak memory 214624 kb
Host smart-e8cf1ecb-c848-462e-b323-93bdbfd12672
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=17084586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.17084586
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.2554498291
Short name T450
Test name
Test status
Simulation time 34156521 ps
CPU time 2.3 seconds
Started May 09 12:34:57 PM PDT 24
Finished May 09 12:35:07 PM PDT 24
Peak memory 222324 kb
Host smart-c928175b-cb66-45cb-a376-2f97ef7372d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554498291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.2554498291
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.619384924
Short name T581
Test name
Test status
Simulation time 159639117 ps
CPU time 4.14 seconds
Started May 09 12:34:40 PM PDT 24
Finished May 09 12:34:49 PM PDT 24
Peak memory 214132 kb
Host smart-12978fae-814d-4737-8eff-196d90e285bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619384924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.619384924
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.827554955
Short name T528
Test name
Test status
Simulation time 337116278 ps
CPU time 3.13 seconds
Started May 09 12:34:58 PM PDT 24
Finished May 09 12:35:09 PM PDT 24
Peak memory 215172 kb
Host smart-3c8580a1-a964-42e8-9eb1-7be5487a7007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827554955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.827554955
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.4234138775
Short name T753
Test name
Test status
Simulation time 186063316 ps
CPU time 4.2 seconds
Started May 09 12:35:20 PM PDT 24
Finished May 09 12:35:35 PM PDT 24
Peak memory 209124 kb
Host smart-cd784295-402b-41cb-9ad4-ce7f70006151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234138775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.4234138775
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.4013361204
Short name T866
Test name
Test status
Simulation time 156506451 ps
CPU time 2.51 seconds
Started May 09 12:35:00 PM PDT 24
Finished May 09 12:35:11 PM PDT 24
Peak memory 205912 kb
Host smart-3ba7117a-0725-4922-91fb-21823a56e169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013361204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.4013361204
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.3801778227
Short name T881
Test name
Test status
Simulation time 650864427 ps
CPU time 20.6 seconds
Started May 09 12:34:42 PM PDT 24
Finished May 09 12:35:07 PM PDT 24
Peak memory 208204 kb
Host smart-acf330fe-69e2-40dd-ad23-1aad43351efd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801778227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.3801778227
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.2999727841
Short name T624
Test name
Test status
Simulation time 465100612 ps
CPU time 6.25 seconds
Started May 09 12:35:12 PM PDT 24
Finished May 09 12:35:30 PM PDT 24
Peak memory 207816 kb
Host smart-980fde6c-d42f-463c-9c16-7eea95aa4b70
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999727841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.2999727841
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.1621223167
Short name T377
Test name
Test status
Simulation time 917785967 ps
CPU time 6.35 seconds
Started May 09 12:35:01 PM PDT 24
Finished May 09 12:35:16 PM PDT 24
Peak memory 207656 kb
Host smart-987d80b5-00d1-48a8-a333-e3bae8b42c50
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621223167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.1621223167
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.1823540793
Short name T637
Test name
Test status
Simulation time 80092551 ps
CPU time 3.7 seconds
Started May 09 12:34:57 PM PDT 24
Finished May 09 12:35:09 PM PDT 24
Peak memory 222700 kb
Host smart-73949476-0039-4f3f-9491-d09248192b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823540793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.1823540793
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.296403383
Short name T785
Test name
Test status
Simulation time 221491685 ps
CPU time 5.18 seconds
Started May 09 12:35:08 PM PDT 24
Finished May 09 12:35:24 PM PDT 24
Peak memory 206500 kb
Host smart-bef99982-04a7-4c5a-baae-610da0acc148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296403383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.296403383
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.1005047563
Short name T604
Test name
Test status
Simulation time 126908265 ps
CPU time 6.16 seconds
Started May 09 12:34:57 PM PDT 24
Finished May 09 12:35:10 PM PDT 24
Peak memory 219896 kb
Host smart-4249e082-8adc-4618-9e4b-4806c59a553c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005047563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.1005047563
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.2513515035
Short name T516
Test name
Test status
Simulation time 173182828 ps
CPU time 4.31 seconds
Started May 09 12:34:56 PM PDT 24
Finished May 09 12:35:08 PM PDT 24
Peak memory 207696 kb
Host smart-317725c5-44d8-46ca-8360-5ea9d755b64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513515035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.2513515035
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.2429083866
Short name T728
Test name
Test status
Simulation time 73779011 ps
CPU time 1.46 seconds
Started May 09 12:34:41 PM PDT 24
Finished May 09 12:34:47 PM PDT 24
Peak memory 209904 kb
Host smart-e0015464-a101-41a8-95f1-b5fbc1d48ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429083866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.2429083866
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.4117993315
Short name T403
Test name
Test status
Simulation time 95326553 ps
CPU time 0.86 seconds
Started May 09 12:33:53 PM PDT 24
Finished May 09 12:34:01 PM PDT 24
Peak memory 205764 kb
Host smart-7f6778ff-1024-4892-adb4-14f2beb3e986
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117993315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.4117993315
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.766939423
Short name T467
Test name
Test status
Simulation time 167164393 ps
CPU time 2.28 seconds
Started May 09 12:33:51 PM PDT 24
Finished May 09 12:34:02 PM PDT 24
Peak memory 208364 kb
Host smart-e078710b-5081-4579-9694-b5d3db51f803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766939423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.766939423
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.51345881
Short name T293
Test name
Test status
Simulation time 2609279467 ps
CPU time 44.77 seconds
Started May 09 12:33:39 PM PDT 24
Finished May 09 12:34:35 PM PDT 24
Peak memory 218508 kb
Host smart-dc0c0ca2-32cd-4c25-bf1b-74f8d70782bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51345881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.51345881
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.4260568895
Short name T2
Test name
Test status
Simulation time 423392004 ps
CPU time 4.35 seconds
Started May 09 12:33:36 PM PDT 24
Finished May 09 12:33:51 PM PDT 24
Peak memory 209348 kb
Host smart-1c7ce031-5030-493d-ade8-c5c76c43851f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260568895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.4260568895
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.4223308760
Short name T281
Test name
Test status
Simulation time 115339421 ps
CPU time 4.98 seconds
Started May 09 12:33:47 PM PDT 24
Finished May 09 12:34:02 PM PDT 24
Peak memory 222260 kb
Host smart-de152b45-d852-4881-9cfc-3db1dc01089d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223308760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.4223308760
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.186907039
Short name T234
Test name
Test status
Simulation time 282976184 ps
CPU time 3.1 seconds
Started May 09 12:33:39 PM PDT 24
Finished May 09 12:33:54 PM PDT 24
Peak memory 219996 kb
Host smart-89e8f2aa-6d22-44e1-8c25-80f0479e149d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186907039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.186907039
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.1136566060
Short name T691
Test name
Test status
Simulation time 934031421 ps
CPU time 8.85 seconds
Started May 09 12:34:00 PM PDT 24
Finished May 09 12:34:17 PM PDT 24
Peak memory 207400 kb
Host smart-896d46a9-abae-422f-b159-49909d17b8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136566060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.1136566060
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.699189453
Short name T11
Test name
Test status
Simulation time 1043999653 ps
CPU time 17.54 seconds
Started May 09 12:33:49 PM PDT 24
Finished May 09 12:34:15 PM PDT 24
Peak memory 232032 kb
Host smart-d01c9b0f-c89b-49aa-90dd-f8813f7fda8f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699189453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.699189453
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.3390465000
Short name T642
Test name
Test status
Simulation time 228207582 ps
CPU time 5.93 seconds
Started May 09 12:33:51 PM PDT 24
Finished May 09 12:34:05 PM PDT 24
Peak memory 208636 kb
Host smart-d5663cd8-e845-4a09-bb73-7c9783cad636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390465000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.3390465000
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.2302967550
Short name T635
Test name
Test status
Simulation time 127649398 ps
CPU time 2.61 seconds
Started May 09 12:33:38 PM PDT 24
Finished May 09 12:33:51 PM PDT 24
Peak memory 206756 kb
Host smart-22c33da5-805e-4e12-a74f-3c04db6e7dce
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302967550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.2302967550
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.709128196
Short name T671
Test name
Test status
Simulation time 157534070 ps
CPU time 2.58 seconds
Started May 09 12:33:39 PM PDT 24
Finished May 09 12:33:52 PM PDT 24
Peak memory 208908 kb
Host smart-67583a07-7522-4bb5-94b7-55a508442010
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709128196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.709128196
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.2626504869
Short name T710
Test name
Test status
Simulation time 58921627 ps
CPU time 2.54 seconds
Started May 09 12:33:33 PM PDT 24
Finished May 09 12:33:46 PM PDT 24
Peak memory 206788 kb
Host smart-ff16cb8d-e74b-4eb7-a71b-47b8484b2068
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626504869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.2626504869
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.1679624417
Short name T286
Test name
Test status
Simulation time 57714155 ps
CPU time 2.98 seconds
Started May 09 12:33:54 PM PDT 24
Finished May 09 12:34:05 PM PDT 24
Peak memory 218096 kb
Host smart-faf7a4e8-b9f9-4671-b115-cabd4aed7ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679624417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.1679624417
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.3452844271
Short name T683
Test name
Test status
Simulation time 198185365 ps
CPU time 2.54 seconds
Started May 09 12:33:47 PM PDT 24
Finished May 09 12:33:59 PM PDT 24
Peak memory 206640 kb
Host smart-6a392b52-46f9-4811-99cb-6cb9a665b347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452844271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.3452844271
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.534533469
Short name T299
Test name
Test status
Simulation time 684544025 ps
CPU time 7.57 seconds
Started May 09 12:33:56 PM PDT 24
Finished May 09 12:34:11 PM PDT 24
Peak memory 207396 kb
Host smart-cb70b159-3bed-4a61-a5d7-055bb766e507
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534533469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.534533469
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.1754071036
Short name T182
Test name
Test status
Simulation time 10263090445 ps
CPU time 57.46 seconds
Started May 09 12:33:40 PM PDT 24
Finished May 09 12:34:49 PM PDT 24
Peak memory 209176 kb
Host smart-ec6d67ad-41d9-40e0-9deb-53e4f800bf1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754071036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.1754071036
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.2604132572
Short name T184
Test name
Test status
Simulation time 416081482 ps
CPU time 2.55 seconds
Started May 09 12:33:50 PM PDT 24
Finished May 09 12:34:01 PM PDT 24
Peak memory 210372 kb
Host smart-1e43779a-4987-4da7-902b-28279cfdfe6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604132572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.2604132572
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.3141913442
Short name T405
Test name
Test status
Simulation time 126143360 ps
CPU time 0.73 seconds
Started May 09 12:35:00 PM PDT 24
Finished May 09 12:35:09 PM PDT 24
Peak memory 205812 kb
Host smart-73302d4b-f86c-47e7-97fb-07b65c304472
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141913442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.3141913442
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.1162154308
Short name T138
Test name
Test status
Simulation time 258571020 ps
CPU time 3.37 seconds
Started May 09 12:34:58 PM PDT 24
Finished May 09 12:35:09 PM PDT 24
Peak memory 214144 kb
Host smart-e4dc1603-1d81-450e-9c31-d8ca27555976
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1162154308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.1162154308
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.4186315771
Short name T499
Test name
Test status
Simulation time 52762617 ps
CPU time 2.74 seconds
Started May 09 12:34:56 PM PDT 24
Finished May 09 12:35:06 PM PDT 24
Peak memory 222544 kb
Host smart-569d1d9a-7958-4ad4-bd17-9705adc08c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186315771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.4186315771
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.420844131
Short name T443
Test name
Test status
Simulation time 702560060 ps
CPU time 5.36 seconds
Started May 09 12:35:29 PM PDT 24
Finished May 09 12:35:44 PM PDT 24
Peak memory 207772 kb
Host smart-87da5be1-8bb6-469f-b64c-381ddfffbbc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420844131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.420844131
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.1078388060
Short name T821
Test name
Test status
Simulation time 560929176 ps
CPU time 2.76 seconds
Started May 09 12:35:13 PM PDT 24
Finished May 09 12:35:32 PM PDT 24
Peak memory 214440 kb
Host smart-ef141a8f-b0e8-4800-84fd-d18d11d61248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078388060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.1078388060
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.3884758632
Short name T247
Test name
Test status
Simulation time 299628469 ps
CPU time 5.73 seconds
Started May 09 12:34:58 PM PDT 24
Finished May 09 12:35:12 PM PDT 24
Peak memory 214548 kb
Host smart-33d592a6-c5c1-4a56-baf1-03d86de242c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884758632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.3884758632
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.893683738
Short name T57
Test name
Test status
Simulation time 644571080 ps
CPU time 3.2 seconds
Started May 09 12:34:57 PM PDT 24
Finished May 09 12:35:08 PM PDT 24
Peak memory 222420 kb
Host smart-addfbf7a-051e-4422-9853-4b94fc38cdc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893683738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.893683738
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.2340949084
Short name T625
Test name
Test status
Simulation time 506481302 ps
CPU time 4.77 seconds
Started May 09 12:35:07 PM PDT 24
Finished May 09 12:35:24 PM PDT 24
Peak memory 207780 kb
Host smart-7dd099da-f1fe-487f-879e-3dcebf86fa9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340949084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.2340949084
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.2551622343
Short name T623
Test name
Test status
Simulation time 150665127 ps
CPU time 2.3 seconds
Started May 09 12:34:57 PM PDT 24
Finished May 09 12:35:07 PM PDT 24
Peak memory 206648 kb
Host smart-2657b0ee-1df0-4e6f-b481-761e97717bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551622343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.2551622343
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.2862631665
Short name T481
Test name
Test status
Simulation time 225303740 ps
CPU time 2.82 seconds
Started May 09 12:35:17 PM PDT 24
Finished May 09 12:35:31 PM PDT 24
Peak memory 206792 kb
Host smart-1da43af5-eb20-4880-9033-57af16fde9d7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862631665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.2862631665
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.3740825606
Short name T603
Test name
Test status
Simulation time 58362369 ps
CPU time 2.92 seconds
Started May 09 12:34:46 PM PDT 24
Finished May 09 12:34:54 PM PDT 24
Peak memory 206860 kb
Host smart-dc191c47-a719-4a8e-b782-c1aba204b1aa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740825606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.3740825606
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.2991961951
Short name T97
Test name
Test status
Simulation time 187403431 ps
CPU time 2.64 seconds
Started May 09 12:35:00 PM PDT 24
Finished May 09 12:35:11 PM PDT 24
Peak memory 208488 kb
Host smart-39aa1e24-04f7-48ab-8160-069918cd0b57
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991961951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.2991961951
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.7472235
Short name T409
Test name
Test status
Simulation time 28000435 ps
CPU time 1.33 seconds
Started May 09 12:35:21 PM PDT 24
Finished May 09 12:35:34 PM PDT 24
Peak memory 208004 kb
Host smart-f7add7a9-2451-4bfb-b8b6-337d666872af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7472235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.7472235
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.2289353965
Short name T867
Test name
Test status
Simulation time 19768342 ps
CPU time 1.71 seconds
Started May 09 12:35:00 PM PDT 24
Finished May 09 12:35:10 PM PDT 24
Peak memory 206568 kb
Host smart-9ab411f5-48d3-4ae4-9e98-a527859c89bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289353965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.2289353965
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.3052248498
Short name T94
Test name
Test status
Simulation time 850073476 ps
CPU time 13.85 seconds
Started May 09 12:34:54 PM PDT 24
Finished May 09 12:35:12 PM PDT 24
Peak memory 215716 kb
Host smart-4c2371ec-1b9d-470a-9d98-a269214cdd64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052248498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.3052248498
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.157793314
Short name T737
Test name
Test status
Simulation time 159590318 ps
CPU time 5.95 seconds
Started May 09 12:35:13 PM PDT 24
Finished May 09 12:35:31 PM PDT 24
Peak memory 219076 kb
Host smart-78297e3f-c8ba-4e5f-ad1b-bfa43a09f6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157793314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.157793314
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.3783482269
Short name T39
Test name
Test status
Simulation time 610728086 ps
CPU time 5.44 seconds
Started May 09 12:35:06 PM PDT 24
Finished May 09 12:35:22 PM PDT 24
Peak memory 210344 kb
Host smart-83bd05ad-5480-4bbe-8ee3-cd4a3f41d16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783482269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.3783482269
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.744196240
Short name T420
Test name
Test status
Simulation time 18844534 ps
CPU time 0.73 seconds
Started May 09 12:35:03 PM PDT 24
Finished May 09 12:35:12 PM PDT 24
Peak memory 205768 kb
Host smart-651ddc3b-99a7-4808-886f-e1ccc439458f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744196240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.744196240
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.413142404
Short name T380
Test name
Test status
Simulation time 1054110917 ps
CPU time 4.59 seconds
Started May 09 12:35:27 PM PDT 24
Finished May 09 12:35:42 PM PDT 24
Peak memory 214216 kb
Host smart-9d61980e-e80d-48db-8688-829f6a285a6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=413142404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.413142404
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.4052255367
Short name T807
Test name
Test status
Simulation time 1258662118 ps
CPU time 8.31 seconds
Started May 09 12:34:56 PM PDT 24
Finished May 09 12:35:12 PM PDT 24
Peak memory 214380 kb
Host smart-6094b352-64c7-470e-91a9-b219854fa2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052255367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.4052255367
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.3500700931
Short name T696
Test name
Test status
Simulation time 175240612 ps
CPU time 2.65 seconds
Started May 09 12:35:32 PM PDT 24
Finished May 09 12:35:44 PM PDT 24
Peak memory 218200 kb
Host smart-f07448b8-183a-4de6-81e7-411ef8b0c357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500700931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.3500700931
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.1138645038
Short name T268
Test name
Test status
Simulation time 259629980 ps
CPU time 3.34 seconds
Started May 09 12:35:05 PM PDT 24
Finished May 09 12:35:19 PM PDT 24
Peak memory 220640 kb
Host smart-e41f3f60-9eec-43b8-89f0-f441b5a24e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138645038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.1138645038
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.2401850332
Short name T529
Test name
Test status
Simulation time 1155513905 ps
CPU time 3.27 seconds
Started May 09 12:35:49 PM PDT 24
Finished May 09 12:35:58 PM PDT 24
Peak memory 206276 kb
Host smart-bc61cb7a-942d-4fa6-b693-550504ca19a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401850332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.2401850332
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.3703918134
Short name T15
Test name
Test status
Simulation time 94724760 ps
CPU time 3.26 seconds
Started May 09 12:35:25 PM PDT 24
Finished May 09 12:35:39 PM PDT 24
Peak memory 207968 kb
Host smart-043106d1-2704-4ea2-b64a-e576691c3b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703918134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.3703918134
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.3926328702
Short name T320
Test name
Test status
Simulation time 710223524 ps
CPU time 8.05 seconds
Started May 09 12:35:00 PM PDT 24
Finished May 09 12:35:17 PM PDT 24
Peak memory 208520 kb
Host smart-fce61f17-830a-4f45-893c-735f02e51187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926328702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.3926328702
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.3135899128
Short name T659
Test name
Test status
Simulation time 54049777 ps
CPU time 2.91 seconds
Started May 09 12:35:08 PM PDT 24
Finished May 09 12:35:22 PM PDT 24
Peak memory 208604 kb
Host smart-a021ce22-bcf9-49a5-a4a9-25a0652f0dca
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135899128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.3135899128
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.2948965260
Short name T802
Test name
Test status
Simulation time 21432538 ps
CPU time 1.83 seconds
Started May 09 12:34:59 PM PDT 24
Finished May 09 12:35:08 PM PDT 24
Peak memory 207224 kb
Host smart-50857afb-a836-4386-b523-b898d9eb4a1c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948965260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.2948965260
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.4219731561
Short name T711
Test name
Test status
Simulation time 106983890 ps
CPU time 2.01 seconds
Started May 09 12:35:08 PM PDT 24
Finished May 09 12:35:22 PM PDT 24
Peak memory 208612 kb
Host smart-d059f014-2edb-4d1d-b3ef-c9e9ba102721
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219731561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.4219731561
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.1612653720
Short name T475
Test name
Test status
Simulation time 57908999 ps
CPU time 1.92 seconds
Started May 09 12:34:58 PM PDT 24
Finished May 09 12:35:07 PM PDT 24
Peak memory 209584 kb
Host smart-d984a271-ac3c-4f2e-bc42-7cf5fadd2f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612653720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.1612653720
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.1615363586
Short name T444
Test name
Test status
Simulation time 909990324 ps
CPU time 8.53 seconds
Started May 09 12:34:59 PM PDT 24
Finished May 09 12:35:15 PM PDT 24
Peak memory 208788 kb
Host smart-edf4877f-d37f-4a8a-b571-b15b4e10064c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615363586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.1615363586
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.2124067958
Short name T118
Test name
Test status
Simulation time 467684718 ps
CPU time 15.34 seconds
Started May 09 12:35:02 PM PDT 24
Finished May 09 12:35:26 PM PDT 24
Peak memory 222440 kb
Host smart-149e39ca-b919-4ab9-8583-915b145255f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124067958 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.2124067958
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.3576005326
Short name T655
Test name
Test status
Simulation time 7012415620 ps
CPU time 66.84 seconds
Started May 09 12:35:09 PM PDT 24
Finished May 09 12:36:28 PM PDT 24
Peak memory 217592 kb
Host smart-b14b016a-4c38-45ef-b33f-daf047a1192e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576005326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.3576005326
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.1119468219
Short name T435
Test name
Test status
Simulation time 246511859 ps
CPU time 2.68 seconds
Started May 09 12:35:08 PM PDT 24
Finished May 09 12:35:22 PM PDT 24
Peak memory 209764 kb
Host smart-3a7c0c07-a810-43ee-96ea-f4064fdeadf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119468219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.1119468219
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.820519931
Short name T78
Test name
Test status
Simulation time 38837837 ps
CPU time 0.7 seconds
Started May 09 12:35:07 PM PDT 24
Finished May 09 12:35:19 PM PDT 24
Peak memory 205800 kb
Host smart-8dc8ca64-3a21-41a6-9e20-24dce9ed6479
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820519931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.820519931
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.786384509
Short name T368
Test name
Test status
Simulation time 64543247 ps
CPU time 3.92 seconds
Started May 09 12:35:11 PM PDT 24
Finished May 09 12:35:27 PM PDT 24
Peak memory 214084 kb
Host smart-d29d6221-2e58-49f0-b053-6abb98f1715f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=786384509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.786384509
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.3517933701
Short name T66
Test name
Test status
Simulation time 9235831777 ps
CPU time 21.02 seconds
Started May 09 12:34:57 PM PDT 24
Finished May 09 12:35:25 PM PDT 24
Peak memory 218232 kb
Host smart-25c53b83-f56a-4f64-ada1-37a34a51f992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517933701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.3517933701
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.3596139218
Short name T266
Test name
Test status
Simulation time 71369442 ps
CPU time 2.39 seconds
Started May 09 12:35:08 PM PDT 24
Finished May 09 12:35:22 PM PDT 24
Peak memory 205912 kb
Host smart-6b5cd326-d326-4980-a129-3814b2041c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596139218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.3596139218
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.347140538
Short name T731
Test name
Test status
Simulation time 138078593 ps
CPU time 4.6 seconds
Started May 09 12:35:00 PM PDT 24
Finished May 09 12:35:13 PM PDT 24
Peak memory 220788 kb
Host smart-f13ce052-3681-4775-8542-780a34505529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347140538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.347140538
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.1317847333
Short name T375
Test name
Test status
Simulation time 289840843 ps
CPU time 3.36 seconds
Started May 09 12:35:11 PM PDT 24
Finished May 09 12:35:26 PM PDT 24
Peak memory 209276 kb
Host smart-ee04ab75-c998-411f-b614-1582f4f5b6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317847333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.1317847333
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.3437213769
Short name T727
Test name
Test status
Simulation time 2556658398 ps
CPU time 14.31 seconds
Started May 09 12:35:11 PM PDT 24
Finished May 09 12:35:37 PM PDT 24
Peak memory 209376 kb
Host smart-6bcdaa95-18af-4b1b-9193-4f3613f82627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437213769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.3437213769
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.2069036508
Short name T341
Test name
Test status
Simulation time 8839641673 ps
CPU time 46.42 seconds
Started May 09 12:35:11 PM PDT 24
Finished May 09 12:36:10 PM PDT 24
Peak memory 208856 kb
Host smart-f1ef39a3-5c09-4368-9070-4d92ef75ae0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069036508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.2069036508
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.824226977
Short name T869
Test name
Test status
Simulation time 217060015 ps
CPU time 5.24 seconds
Started May 09 12:34:58 PM PDT 24
Finished May 09 12:35:11 PM PDT 24
Peak memory 207768 kb
Host smart-08832aa3-4dcc-40dc-a097-2e05b6a22acc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824226977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.824226977
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.1490904053
Short name T640
Test name
Test status
Simulation time 79193850 ps
CPU time 2.32 seconds
Started May 09 12:35:14 PM PDT 24
Finished May 09 12:35:29 PM PDT 24
Peak memory 206620 kb
Host smart-2341fc5a-4d36-4688-9242-815486f2fd33
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490904053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.1490904053
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.1950107748
Short name T578
Test name
Test status
Simulation time 703981783 ps
CPU time 5.2 seconds
Started May 09 12:35:11 PM PDT 24
Finished May 09 12:35:28 PM PDT 24
Peak memory 208152 kb
Host smart-acc1efc4-0409-4753-a653-f3aa23a7fe18
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950107748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.1950107748
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.1079078972
Short name T654
Test name
Test status
Simulation time 59123783 ps
CPU time 2.85 seconds
Started May 09 12:35:13 PM PDT 24
Finished May 09 12:35:28 PM PDT 24
Peak memory 209276 kb
Host smart-68d8c40a-5d1f-4fea-beca-58072f13c55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079078972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.1079078972
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.3958840530
Short name T401
Test name
Test status
Simulation time 67357738 ps
CPU time 1.56 seconds
Started May 09 12:34:56 PM PDT 24
Finished May 09 12:35:05 PM PDT 24
Peak memory 206404 kb
Host smart-b010494d-bb32-4753-a028-d6e69d1ca0a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958840530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.3958840530
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.2565571683
Short name T175
Test name
Test status
Simulation time 269839819 ps
CPU time 7.87 seconds
Started May 09 12:35:00 PM PDT 24
Finished May 09 12:35:17 PM PDT 24
Peak memory 222568 kb
Host smart-9ef0411b-8653-426a-baa5-23528cdb83ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565571683 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.2565571683
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.1431311196
Short name T632
Test name
Test status
Simulation time 2537669035 ps
CPU time 43.88 seconds
Started May 09 12:35:19 PM PDT 24
Finished May 09 12:36:14 PM PDT 24
Peak memory 214236 kb
Host smart-60398d72-c761-49a9-a8c5-9ebde0b575ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431311196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.1431311196
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.462047554
Short name T575
Test name
Test status
Simulation time 350495954 ps
CPU time 2.46 seconds
Started May 09 12:34:56 PM PDT 24
Finished May 09 12:35:06 PM PDT 24
Peak memory 210896 kb
Host smart-0eccf318-4415-41fa-8b0a-04e1038cfa35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462047554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.462047554
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.3456402731
Short name T664
Test name
Test status
Simulation time 17007353 ps
CPU time 0.8 seconds
Started May 09 12:35:32 PM PDT 24
Finished May 09 12:35:42 PM PDT 24
Peak memory 205784 kb
Host smart-1de9c5fa-bda4-43c4-99bc-b6f8c4444241
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456402731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.3456402731
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.480527163
Short name T381
Test name
Test status
Simulation time 508270516 ps
CPU time 26.97 seconds
Started May 09 12:35:15 PM PDT 24
Finished May 09 12:35:54 PM PDT 24
Peak memory 214380 kb
Host smart-c4a56cab-6c26-4e85-87dc-f9d067804f3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=480527163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.480527163
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.2112397651
Short name T59
Test name
Test status
Simulation time 200559609 ps
CPU time 2.73 seconds
Started May 09 12:35:06 PM PDT 24
Finished May 09 12:35:20 PM PDT 24
Peak memory 221828 kb
Host smart-70b2b090-f920-4cc4-85f4-81aaa099aa16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112397651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.2112397651
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.3537066161
Short name T330
Test name
Test status
Simulation time 82623863 ps
CPU time 3.13 seconds
Started May 09 12:34:55 PM PDT 24
Finished May 09 12:35:05 PM PDT 24
Peak memory 209772 kb
Host smart-a05a6380-836e-4946-a2a8-02100824e19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537066161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.3537066161
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.1018481133
Short name T304
Test name
Test status
Simulation time 85448844 ps
CPU time 3.26 seconds
Started May 09 12:35:06 PM PDT 24
Finished May 09 12:35:20 PM PDT 24
Peak memory 222348 kb
Host smart-365cb273-35a6-4b13-be70-6c6e748a0799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018481133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.1018481133
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.2846693925
Short name T597
Test name
Test status
Simulation time 219996738 ps
CPU time 4.73 seconds
Started May 09 12:35:14 PM PDT 24
Finished May 09 12:35:31 PM PDT 24
Peak memory 218320 kb
Host smart-618c868b-01fa-4a88-a779-4f46cd9c9a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846693925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.2846693925
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.2289900562
Short name T322
Test name
Test status
Simulation time 3418763900 ps
CPU time 44.46 seconds
Started May 09 12:34:41 PM PDT 24
Finished May 09 12:35:31 PM PDT 24
Peak memory 208636 kb
Host smart-5bedf389-08d2-4b37-b4b8-0520b07ce364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289900562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.2289900562
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.2585144059
Short name T803
Test name
Test status
Simulation time 81906536 ps
CPU time 1.9 seconds
Started May 09 12:34:54 PM PDT 24
Finished May 09 12:35:02 PM PDT 24
Peak memory 207096 kb
Host smart-06631fd3-8c4b-49a9-afdb-ba4093120f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585144059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.2585144059
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.466315100
Short name T121
Test name
Test status
Simulation time 83117413 ps
CPU time 3.39 seconds
Started May 09 12:35:10 PM PDT 24
Finished May 09 12:35:25 PM PDT 24
Peak memory 208588 kb
Host smart-e5be91d3-fbd6-41f6-8555-3fe4f148030a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466315100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.466315100
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.2779006735
Short name T875
Test name
Test status
Simulation time 493193199 ps
CPU time 5.47 seconds
Started May 09 12:35:07 PM PDT 24
Finished May 09 12:35:23 PM PDT 24
Peak memory 207228 kb
Host smart-4d6de523-52ee-4dce-a8a4-b1a338e98198
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779006735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.2779006735
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.1619800661
Short name T736
Test name
Test status
Simulation time 865073031 ps
CPU time 6.72 seconds
Started May 09 12:35:03 PM PDT 24
Finished May 09 12:35:25 PM PDT 24
Peak memory 208544 kb
Host smart-d006fe26-da4b-4ac0-8a67-aefca4cc656d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619800661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.1619800661
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.3128384364
Short name T259
Test name
Test status
Simulation time 348986971 ps
CPU time 4.21 seconds
Started May 09 12:35:10 PM PDT 24
Finished May 09 12:35:25 PM PDT 24
Peak memory 208820 kb
Host smart-739ad77a-e776-4479-b0fa-f2d87dc10027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128384364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.3128384364
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.2712635241
Short name T402
Test name
Test status
Simulation time 395355365 ps
CPU time 6.26 seconds
Started May 09 12:34:58 PM PDT 24
Finished May 09 12:35:12 PM PDT 24
Peak memory 208616 kb
Host smart-3b3c7ee5-9a4c-4b57-97c5-4117114e4645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712635241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.2712635241
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.2302637374
Short name T300
Test name
Test status
Simulation time 53210920758 ps
CPU time 129.42 seconds
Started May 09 12:35:05 PM PDT 24
Finished May 09 12:37:25 PM PDT 24
Peak memory 216176 kb
Host smart-8dbf8940-5651-4a55-998b-b0e721256d3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302637374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.2302637374
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.1894372639
Short name T132
Test name
Test status
Simulation time 322835394 ps
CPU time 4.02 seconds
Started May 09 12:34:52 PM PDT 24
Finished May 09 12:35:00 PM PDT 24
Peak memory 207536 kb
Host smart-7451de2d-d751-4e32-a49a-90a9e18e986d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894372639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.1894372639
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.3139268144
Short name T102
Test name
Test status
Simulation time 157742769 ps
CPU time 2.17 seconds
Started May 09 12:35:11 PM PDT 24
Finished May 09 12:35:25 PM PDT 24
Peak memory 210308 kb
Host smart-c70a0e20-9000-41c7-8239-6b1525340f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139268144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.3139268144
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.2778628630
Short name T820
Test name
Test status
Simulation time 21974253 ps
CPU time 0.79 seconds
Started May 09 12:34:52 PM PDT 24
Finished May 09 12:34:57 PM PDT 24
Peak memory 205816 kb
Host smart-69d54c64-6a27-457b-ac43-52e0df8d4692
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778628630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.2778628630
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.626753175
Short name T273
Test name
Test status
Simulation time 50700365 ps
CPU time 3.7 seconds
Started May 09 12:34:53 PM PDT 24
Finished May 09 12:35:01 PM PDT 24
Peak memory 214228 kb
Host smart-f75a5ed7-92ff-4e4f-8fe8-016a0c274510
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=626753175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.626753175
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.867130624
Short name T571
Test name
Test status
Simulation time 799295304 ps
CPU time 2.36 seconds
Started May 09 12:35:11 PM PDT 24
Finished May 09 12:35:25 PM PDT 24
Peak memory 217008 kb
Host smart-7fd90e9c-fe21-4801-82eb-3c945ee0519e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867130624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.867130624
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.2013510810
Short name T667
Test name
Test status
Simulation time 82943144 ps
CPU time 2 seconds
Started May 09 12:34:55 PM PDT 24
Finished May 09 12:35:04 PM PDT 24
Peak memory 207008 kb
Host smart-6f7c2814-13d1-4233-890f-566c733e11a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013510810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.2013510810
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.2458309840
Short name T700
Test name
Test status
Simulation time 68426835 ps
CPU time 3.07 seconds
Started May 09 12:34:56 PM PDT 24
Finished May 09 12:35:06 PM PDT 24
Peak memory 214236 kb
Host smart-27a2a7c4-e03d-42de-9ea3-9fb8412da4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458309840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.2458309840
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.3355139067
Short name T52
Test name
Test status
Simulation time 590195816 ps
CPU time 5.2 seconds
Started May 09 12:35:02 PM PDT 24
Finished May 09 12:35:16 PM PDT 24
Peak memory 214196 kb
Host smart-95cfb214-6305-4f67-8a43-566332223da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355139067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.3355139067
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.853858745
Short name T520
Test name
Test status
Simulation time 344995468 ps
CPU time 5.14 seconds
Started May 09 12:34:57 PM PDT 24
Finished May 09 12:35:09 PM PDT 24
Peak memory 206896 kb
Host smart-317efeaa-69f3-413e-9894-cd794414aaf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853858745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.853858745
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.3871115166
Short name T758
Test name
Test status
Simulation time 39353524 ps
CPU time 2.21 seconds
Started May 09 12:35:10 PM PDT 24
Finished May 09 12:35:23 PM PDT 24
Peak memory 206796 kb
Host smart-9c799b38-1fe9-48f9-8de3-a8b826ee6712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871115166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.3871115166
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.1949484717
Short name T457
Test name
Test status
Simulation time 522542860 ps
CPU time 6.69 seconds
Started May 09 12:35:46 PM PDT 24
Finished May 09 12:35:58 PM PDT 24
Peak memory 208704 kb
Host smart-0117cbd3-306b-4d00-858e-3ae5ec807042
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949484717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.1949484717
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.3143532408
Short name T844
Test name
Test status
Simulation time 59528782 ps
CPU time 2.92 seconds
Started May 09 12:34:58 PM PDT 24
Finished May 09 12:35:09 PM PDT 24
Peak memory 207860 kb
Host smart-67604b52-dd10-4732-89b0-b044378c93a1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143532408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.3143532408
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.365690043
Short name T586
Test name
Test status
Simulation time 694981810 ps
CPU time 5.27 seconds
Started May 09 12:34:56 PM PDT 24
Finished May 09 12:35:09 PM PDT 24
Peak memory 208792 kb
Host smart-a1eb760b-1855-471e-aac4-cd6e60ddf82f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365690043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.365690043
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.1727391289
Short name T747
Test name
Test status
Simulation time 410489879 ps
CPU time 3.46 seconds
Started May 09 12:34:57 PM PDT 24
Finished May 09 12:35:08 PM PDT 24
Peak memory 206860 kb
Host smart-25b4e9e9-1aaf-412b-a312-f25c78e083c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727391289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.1727391289
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.4207486307
Short name T126
Test name
Test status
Simulation time 409467835 ps
CPU time 1.78 seconds
Started May 09 12:35:13 PM PDT 24
Finished May 09 12:35:27 PM PDT 24
Peak memory 206536 kb
Host smart-f8e38ab6-71c0-4042-96df-e8e3fdd1dec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207486307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.4207486307
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.3303494037
Short name T258
Test name
Test status
Simulation time 1653799918 ps
CPU time 39.26 seconds
Started May 09 12:35:11 PM PDT 24
Finished May 09 12:36:02 PM PDT 24
Peak memory 216468 kb
Host smart-85a949bd-a531-4cd0-ae55-aee13e351ae1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303494037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.3303494037
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.3081534806
Short name T123
Test name
Test status
Simulation time 169492800 ps
CPU time 8.5 seconds
Started May 09 12:35:14 PM PDT 24
Finished May 09 12:35:34 PM PDT 24
Peak memory 219404 kb
Host smart-960475db-de6d-45d4-b2c6-4a81a65dc533
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081534806 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.3081534806
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.4236161105
Short name T887
Test name
Test status
Simulation time 291133470 ps
CPU time 10.71 seconds
Started May 09 12:35:13 PM PDT 24
Finished May 09 12:35:35 PM PDT 24
Peak memory 208556 kb
Host smart-7ae3b86a-3b56-4b72-ab05-6cbdede5cf34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236161105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.4236161105
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.1971744131
Short name T630
Test name
Test status
Simulation time 166703497 ps
CPU time 2.88 seconds
Started May 09 12:35:21 PM PDT 24
Finished May 09 12:35:35 PM PDT 24
Peak memory 210608 kb
Host smart-89d5fc94-0213-4553-8458-2341ad975323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971744131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.1971744131
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.1644301860
Short name T30
Test name
Test status
Simulation time 70904796 ps
CPU time 3.21 seconds
Started May 09 12:35:06 PM PDT 24
Finished May 09 12:35:21 PM PDT 24
Peak memory 214188 kb
Host smart-86dcd92b-22c7-43d9-a368-8c0d1dd1fd26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644301860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.1644301860
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.2410514078
Short name T595
Test name
Test status
Simulation time 382730832 ps
CPU time 3.71 seconds
Started May 09 12:35:08 PM PDT 24
Finished May 09 12:35:23 PM PDT 24
Peak memory 208340 kb
Host smart-d556853c-1991-4ad9-8d01-815e9dfdb439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410514078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.2410514078
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.1487822821
Short name T328
Test name
Test status
Simulation time 65291303 ps
CPU time 2.37 seconds
Started May 09 12:34:56 PM PDT 24
Finished May 09 12:35:05 PM PDT 24
Peak memory 214136 kb
Host smart-43e202cc-6756-4bb0-97d1-661bd303428c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487822821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.1487822821
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.553428455
Short name T750
Test name
Test status
Simulation time 216424873 ps
CPU time 3.31 seconds
Started May 09 12:35:12 PM PDT 24
Finished May 09 12:35:27 PM PDT 24
Peak memory 221520 kb
Host smart-88c30d35-4db4-4649-afeb-1ac4176c5288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553428455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.553428455
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.2735146305
Short name T596
Test name
Test status
Simulation time 158293112 ps
CPU time 3.48 seconds
Started May 09 12:35:21 PM PDT 24
Finished May 09 12:35:36 PM PDT 24
Peak memory 209732 kb
Host smart-6e7a8b06-7ccc-463f-bf4a-7cdead2036fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735146305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.2735146305
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.2876414607
Short name T789
Test name
Test status
Simulation time 2172641753 ps
CPU time 57.46 seconds
Started May 09 12:35:14 PM PDT 24
Finished May 09 12:36:23 PM PDT 24
Peak memory 208968 kb
Host smart-2bc7f963-8573-4ef3-9d6e-f006ba4321ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876414607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.2876414607
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.4068374041
Short name T183
Test name
Test status
Simulation time 39910429 ps
CPU time 2.4 seconds
Started May 09 12:35:13 PM PDT 24
Finished May 09 12:35:27 PM PDT 24
Peak memory 206672 kb
Host smart-e4dec371-031f-4fab-a2e0-6234225f1279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068374041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.4068374041
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.1233872777
Short name T317
Test name
Test status
Simulation time 132736366 ps
CPU time 3.09 seconds
Started May 09 12:34:57 PM PDT 24
Finished May 09 12:35:07 PM PDT 24
Peak memory 208232 kb
Host smart-27a43f8c-f870-4ded-9758-1c155f947041
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233872777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.1233872777
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.2721437713
Short name T295
Test name
Test status
Simulation time 4705125402 ps
CPU time 27.55 seconds
Started May 09 12:35:08 PM PDT 24
Finished May 09 12:35:47 PM PDT 24
Peak memory 208116 kb
Host smart-fcdd68cc-37e1-4b1f-8d06-2a7a964e23d4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721437713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.2721437713
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.3420991326
Short name T588
Test name
Test status
Simulation time 88356914 ps
CPU time 1.82 seconds
Started May 09 12:35:10 PM PDT 24
Finished May 09 12:35:24 PM PDT 24
Peak memory 206792 kb
Host smart-d4750bda-ccc5-47e0-b1ab-20c6d4775daf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420991326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.3420991326
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.3672615111
Short name T564
Test name
Test status
Simulation time 247680716 ps
CPU time 3.16 seconds
Started May 09 12:35:07 PM PDT 24
Finished May 09 12:35:22 PM PDT 24
Peak memory 209176 kb
Host smart-c04ee4e4-da12-4409-a049-d8a2906d4b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672615111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.3672615111
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.1057098138
Short name T814
Test name
Test status
Simulation time 132666697 ps
CPU time 2.2 seconds
Started May 09 12:35:03 PM PDT 24
Finished May 09 12:35:15 PM PDT 24
Peak memory 206624 kb
Host smart-9365a2d5-3a7c-42b0-8d8c-911882675e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057098138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.1057098138
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.4110078592
Short name T868
Test name
Test status
Simulation time 1051573282 ps
CPU time 34.01 seconds
Started May 09 12:35:14 PM PDT 24
Finished May 09 12:36:00 PM PDT 24
Peak memory 215668 kb
Host smart-70514c2a-c199-47e2-8109-3162c58b2d11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110078592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.4110078592
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.381812348
Short name T122
Test name
Test status
Simulation time 83683662 ps
CPU time 3.6 seconds
Started May 09 12:34:57 PM PDT 24
Finished May 09 12:35:08 PM PDT 24
Peak memory 214192 kb
Host smart-599eb05c-9674-483c-852f-44363800b8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381812348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.381812348
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.1833327232
Short name T415
Test name
Test status
Simulation time 57081493 ps
CPU time 1.81 seconds
Started May 09 12:35:20 PM PDT 24
Finished May 09 12:35:33 PM PDT 24
Peak memory 209792 kb
Host smart-67c66486-3be2-4a84-aed5-b7bd4669783a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833327232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.1833327232
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.1553437170
Short name T410
Test name
Test status
Simulation time 43957949 ps
CPU time 0.85 seconds
Started May 09 12:35:12 PM PDT 24
Finished May 09 12:35:25 PM PDT 24
Peak memory 205720 kb
Host smart-e7db18a3-3d4e-4f1c-b3b3-37d030c07a56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553437170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.1553437170
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.4147695509
Short name T398
Test name
Test status
Simulation time 100275854 ps
CPU time 5.53 seconds
Started May 09 12:35:24 PM PDT 24
Finished May 09 12:35:40 PM PDT 24
Peak memory 214200 kb
Host smart-51af3bc2-c612-4460-a2c5-ec1010b951fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4147695509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.4147695509
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.1104312020
Short name T646
Test name
Test status
Simulation time 644259174 ps
CPU time 2.53 seconds
Started May 09 12:35:09 PM PDT 24
Finished May 09 12:35:23 PM PDT 24
Peak memory 209284 kb
Host smart-e14912e7-f330-4827-8aff-be8195cb4c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104312020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.1104312020
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.2969786624
Short name T859
Test name
Test status
Simulation time 27362423 ps
CPU time 1.32 seconds
Started May 09 12:35:20 PM PDT 24
Finished May 09 12:35:32 PM PDT 24
Peak memory 207952 kb
Host smart-9b8fde64-1767-48f7-ab62-1f83e507de06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969786624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.2969786624
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.1128672743
Short name T902
Test name
Test status
Simulation time 47320247 ps
CPU time 2.59 seconds
Started May 09 12:35:05 PM PDT 24
Finished May 09 12:35:19 PM PDT 24
Peak memory 220860 kb
Host smart-d3ff5440-c1d0-4621-a79b-3f46e979163b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128672743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.1128672743
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.3604826456
Short name T473
Test name
Test status
Simulation time 252237674 ps
CPU time 3.26 seconds
Started May 09 12:35:18 PM PDT 24
Finished May 09 12:35:33 PM PDT 24
Peak memory 222364 kb
Host smart-3a514d6b-472b-46ba-ad22-b86c9242424e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604826456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.3604826456
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.1001584336
Short name T760
Test name
Test status
Simulation time 3808613003 ps
CPU time 5.81 seconds
Started May 09 12:35:18 PM PDT 24
Finished May 09 12:35:35 PM PDT 24
Peak memory 208200 kb
Host smart-cc929a0c-47ed-4f2f-aa39-b8858f266214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001584336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.1001584336
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.1510952804
Short name T202
Test name
Test status
Simulation time 149045226 ps
CPU time 3.66 seconds
Started May 09 12:34:59 PM PDT 24
Finished May 09 12:35:10 PM PDT 24
Peak memory 206880 kb
Host smart-1023ae9d-18ce-43ff-b854-cdd4fb8042c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510952804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.1510952804
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.3983096454
Short name T871
Test name
Test status
Simulation time 1150114453 ps
CPU time 38.63 seconds
Started May 09 12:35:10 PM PDT 24
Finished May 09 12:36:00 PM PDT 24
Peak memory 208972 kb
Host smart-8aed4577-01ba-420a-ba3c-64539babe71f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983096454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.3983096454
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.2687563384
Short name T517
Test name
Test status
Simulation time 472323725 ps
CPU time 6.31 seconds
Started May 09 12:34:59 PM PDT 24
Finished May 09 12:35:13 PM PDT 24
Peak memory 207828 kb
Host smart-40b52692-089d-4c6f-9282-7e04c499a014
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687563384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.2687563384
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.2741938475
Short name T862
Test name
Test status
Simulation time 1575770992 ps
CPU time 41.57 seconds
Started May 09 12:34:58 PM PDT 24
Finished May 09 12:35:48 PM PDT 24
Peak memory 207812 kb
Host smart-f84ff1b0-3fa5-4c81-8b28-c77bf3149651
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741938475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.2741938475
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.1049761801
Short name T257
Test name
Test status
Simulation time 569859271 ps
CPU time 4.3 seconds
Started May 09 12:35:10 PM PDT 24
Finished May 09 12:35:25 PM PDT 24
Peak memory 208604 kb
Host smart-36f41960-9ebb-4efc-bbad-d95063670ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049761801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.1049761801
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.3847556218
Short name T482
Test name
Test status
Simulation time 670644054 ps
CPU time 18.36 seconds
Started May 09 12:35:07 PM PDT 24
Finished May 09 12:35:37 PM PDT 24
Peak memory 208412 kb
Host smart-00cd993f-4238-472c-8a03-8448620bf5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847556218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.3847556218
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.2264486904
Short name T751
Test name
Test status
Simulation time 384554870 ps
CPU time 4.53 seconds
Started May 09 12:35:14 PM PDT 24
Finished May 09 12:35:31 PM PDT 24
Peak memory 214144 kb
Host smart-15f3cd8c-f8b7-4eb3-b836-17973259a319
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264486904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.2264486904
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.3518659509
Short name T832
Test name
Test status
Simulation time 149338073 ps
CPU time 2.18 seconds
Started May 09 12:35:21 PM PDT 24
Finished May 09 12:35:35 PM PDT 24
Peak memory 207912 kb
Host smart-022a6bdd-da66-4d10-a2d7-97d8d8642981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518659509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.3518659509
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.1248990762
Short name T456
Test name
Test status
Simulation time 503716255 ps
CPU time 2.73 seconds
Started May 09 12:35:14 PM PDT 24
Finished May 09 12:35:29 PM PDT 24
Peak memory 209824 kb
Host smart-ba07be3f-d483-4b5a-96ac-82572707deeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248990762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.1248990762
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.821063220
Short name T584
Test name
Test status
Simulation time 14982861 ps
CPU time 0.73 seconds
Started May 09 12:34:58 PM PDT 24
Finished May 09 12:35:07 PM PDT 24
Peak memory 205864 kb
Host smart-1629d1fd-5c3d-466a-816c-4d4e38bd8531
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821063220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.821063220
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.4276391001
Short name T324
Test name
Test status
Simulation time 363987429 ps
CPU time 2.07 seconds
Started May 09 12:35:08 PM PDT 24
Finished May 09 12:35:21 PM PDT 24
Peak memory 207580 kb
Host smart-7fd860e1-4003-4d2e-98ae-26fd8fd442d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276391001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.4276391001
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.2782430674
Short name T486
Test name
Test status
Simulation time 35042360 ps
CPU time 2.61 seconds
Started May 09 12:35:12 PM PDT 24
Finished May 09 12:35:27 PM PDT 24
Peak memory 209164 kb
Host smart-3de1386d-5bb1-477c-8a31-0ba9431c25cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782430674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.2782430674
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.2790488315
Short name T54
Test name
Test status
Simulation time 600317846 ps
CPU time 7.5 seconds
Started May 09 12:35:27 PM PDT 24
Finished May 09 12:35:45 PM PDT 24
Peak memory 222184 kb
Host smart-b9cecd97-bc0b-4eb6-afcf-c3b197edd173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790488315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.2790488315
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.1688887162
Short name T590
Test name
Test status
Simulation time 84481625 ps
CPU time 3.85 seconds
Started May 09 12:35:13 PM PDT 24
Finished May 09 12:35:30 PM PDT 24
Peak memory 209300 kb
Host smart-501d6223-8bb9-48eb-b7fb-d336724b899b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688887162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.1688887162
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.1861603482
Short name T681
Test name
Test status
Simulation time 4603673630 ps
CPU time 8.41 seconds
Started May 09 12:35:09 PM PDT 24
Finished May 09 12:35:29 PM PDT 24
Peak memory 207980 kb
Host smart-575f51ce-8b10-417b-b371-deca9c519649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861603482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.1861603482
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.312966948
Short name T478
Test name
Test status
Simulation time 129087733 ps
CPU time 3.89 seconds
Started May 09 12:35:18 PM PDT 24
Finished May 09 12:35:34 PM PDT 24
Peak memory 207780 kb
Host smart-3dda28cd-8f84-499c-bc37-db9af8174295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312966948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.312966948
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.4123420166
Short name T614
Test name
Test status
Simulation time 69676326 ps
CPU time 2.64 seconds
Started May 09 12:35:11 PM PDT 24
Finished May 09 12:35:25 PM PDT 24
Peak memory 207528 kb
Host smart-64971b9f-a419-459b-8bb5-3e94409966f5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123420166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.4123420166
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.2595588226
Short name T842
Test name
Test status
Simulation time 70635142 ps
CPU time 1.94 seconds
Started May 09 12:34:59 PM PDT 24
Finished May 09 12:35:08 PM PDT 24
Peak memory 208600 kb
Host smart-c6274d13-2b5d-4c33-a16f-c0e9a62e3b03
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595588226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.2595588226
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.798534738
Short name T828
Test name
Test status
Simulation time 6594482756 ps
CPU time 43.3 seconds
Started May 09 12:35:18 PM PDT 24
Finished May 09 12:36:13 PM PDT 24
Peak memory 208412 kb
Host smart-1f83ef88-0bba-41c3-b347-cb3c1ee69d75
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798534738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.798534738
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.2572507353
Short name T631
Test name
Test status
Simulation time 35711698 ps
CPU time 2.36 seconds
Started May 09 12:35:00 PM PDT 24
Finished May 09 12:35:11 PM PDT 24
Peak memory 208060 kb
Host smart-573fc3b0-bbe1-4f61-a0d0-4893a482c8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572507353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.2572507353
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.3397554855
Short name T200
Test name
Test status
Simulation time 264362369 ps
CPU time 3.12 seconds
Started May 09 12:35:16 PM PDT 24
Finished May 09 12:35:31 PM PDT 24
Peak memory 208496 kb
Host smart-97e4ebdb-43b8-44ef-a8c9-3f6c60d00b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397554855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.3397554855
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.2035551859
Short name T65
Test name
Test status
Simulation time 634022036 ps
CPU time 9.3 seconds
Started May 09 12:35:12 PM PDT 24
Finished May 09 12:35:34 PM PDT 24
Peak memory 208108 kb
Host smart-54e40430-b21d-4707-a7eb-d376e055dbc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035551859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.2035551859
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.1621137824
Short name T650
Test name
Test status
Simulation time 119010041 ps
CPU time 6.96 seconds
Started May 09 12:34:58 PM PDT 24
Finished May 09 12:35:13 PM PDT 24
Peak memory 222448 kb
Host smart-329d95d9-ce88-4cc2-bc48-28806ebe4192
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621137824 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.1621137824
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.1409566690
Short name T795
Test name
Test status
Simulation time 247455572 ps
CPU time 3.48 seconds
Started May 09 12:35:25 PM PDT 24
Finished May 09 12:35:40 PM PDT 24
Peak memory 210008 kb
Host smart-d7958edf-ac0e-4973-8595-a8372464a7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409566690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.1409566690
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.2688444434
Short name T797
Test name
Test status
Simulation time 134078712 ps
CPU time 2.14 seconds
Started May 09 12:35:00 PM PDT 24
Finished May 09 12:35:11 PM PDT 24
Peak memory 209896 kb
Host smart-be1c815c-5145-4414-8a8d-328dc9d5a1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688444434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.2688444434
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.1742302902
Short name T471
Test name
Test status
Simulation time 9489124 ps
CPU time 0.69 seconds
Started May 09 12:35:19 PM PDT 24
Finished May 09 12:35:31 PM PDT 24
Peak memory 205844 kb
Host smart-b6e850dd-0040-43cf-87a3-de9745d4c81c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742302902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.1742302902
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.2989088803
Short name T367
Test name
Test status
Simulation time 179038540 ps
CPU time 3.16 seconds
Started May 09 12:35:18 PM PDT 24
Finished May 09 12:35:37 PM PDT 24
Peak memory 214152 kb
Host smart-7b6ca27e-86d1-42ab-946f-44c067e46dd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2989088803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.2989088803
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.1895950336
Short name T754
Test name
Test status
Simulation time 186133089 ps
CPU time 2.53 seconds
Started May 09 12:35:32 PM PDT 24
Finished May 09 12:35:44 PM PDT 24
Peak memory 214400 kb
Host smart-5cf68dc2-6ebe-4b38-bd6a-bdd8373d91f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895950336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.1895950336
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.1531790290
Short name T522
Test name
Test status
Simulation time 94111303 ps
CPU time 2.36 seconds
Started May 09 12:34:58 PM PDT 24
Finished May 09 12:35:09 PM PDT 24
Peak memory 208196 kb
Host smart-0facfb39-0236-4c9c-bd57-5bfaa2af3e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531790290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.1531790290
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.3686624016
Short name T85
Test name
Test status
Simulation time 256546514 ps
CPU time 2.4 seconds
Started May 09 12:35:21 PM PDT 24
Finished May 09 12:35:35 PM PDT 24
Peak memory 214152 kb
Host smart-136367f5-41a4-4810-99f6-37d0da09c44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686624016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.3686624016
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.2077875517
Short name T893
Test name
Test status
Simulation time 91458885 ps
CPU time 3.7 seconds
Started May 09 12:35:19 PM PDT 24
Finished May 09 12:35:34 PM PDT 24
Peak memory 221136 kb
Host smart-c1035961-794c-41ab-a117-c3855a94013c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077875517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.2077875517
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.4028032933
Short name T580
Test name
Test status
Simulation time 167047985 ps
CPU time 3.41 seconds
Started May 09 12:34:59 PM PDT 24
Finished May 09 12:35:17 PM PDT 24
Peak memory 209092 kb
Host smart-5669b61c-984b-4b12-878a-fe79cc4982ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028032933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.4028032933
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.439933161
Short name T79
Test name
Test status
Simulation time 666424634 ps
CPU time 5.11 seconds
Started May 09 12:34:58 PM PDT 24
Finished May 09 12:35:11 PM PDT 24
Peak memory 214140 kb
Host smart-70a3eac7-afc3-4d98-b325-b992e6f02eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439933161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.439933161
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.2122830540
Short name T315
Test name
Test status
Simulation time 1029908798 ps
CPU time 7.38 seconds
Started May 09 12:34:59 PM PDT 24
Finished May 09 12:35:14 PM PDT 24
Peak memory 208548 kb
Host smart-5350abc5-7e02-4ede-b988-f3a57aed98e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122830540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.2122830540
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.2076575840
Short name T521
Test name
Test status
Simulation time 502774443 ps
CPU time 5.56 seconds
Started May 09 12:35:02 PM PDT 24
Finished May 09 12:35:17 PM PDT 24
Peak memory 208084 kb
Host smart-2a1418ef-0d8e-4cc8-bbfe-85c9b57d241d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076575840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.2076575840
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.1912020954
Short name T723
Test name
Test status
Simulation time 234029320 ps
CPU time 4.94 seconds
Started May 09 12:35:18 PM PDT 24
Finished May 09 12:35:35 PM PDT 24
Peak memory 206712 kb
Host smart-4b148ee4-a190-4cad-b5cc-273ce15707da
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912020954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.1912020954
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.215086157
Short name T343
Test name
Test status
Simulation time 676343085 ps
CPU time 7.18 seconds
Started May 09 12:35:11 PM PDT 24
Finished May 09 12:35:30 PM PDT 24
Peak memory 208384 kb
Host smart-5ee37eae-0f72-4c67-b40a-45988c860dc5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215086157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.215086157
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.3580421415
Short name T796
Test name
Test status
Simulation time 74197928 ps
CPU time 2.97 seconds
Started May 09 12:35:09 PM PDT 24
Finished May 09 12:35:23 PM PDT 24
Peak memory 218192 kb
Host smart-ccad4df7-4731-40ce-806c-dfd8140c0a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580421415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.3580421415
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.3433168795
Short name T501
Test name
Test status
Simulation time 231224046 ps
CPU time 5.47 seconds
Started May 09 12:35:22 PM PDT 24
Finished May 09 12:35:39 PM PDT 24
Peak memory 207936 kb
Host smart-5d2df4e0-d41a-46c6-af9a-74ce3103e55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433168795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.3433168795
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.1713436092
Short name T5
Test name
Test status
Simulation time 2167841730 ps
CPU time 38.18 seconds
Started May 09 12:34:58 PM PDT 24
Finished May 09 12:35:44 PM PDT 24
Peak memory 216776 kb
Host smart-d77a1f91-242d-47d8-b56e-c3f2ccd59c79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713436092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.1713436092
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.2231114452
Short name T119
Test name
Test status
Simulation time 5517084126 ps
CPU time 27.62 seconds
Started May 09 12:35:26 PM PDT 24
Finished May 09 12:36:07 PM PDT 24
Peak memory 222624 kb
Host smart-3cf84f71-c31f-4e04-ae31-10e677f683e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231114452 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.2231114452
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.2329984656
Short name T337
Test name
Test status
Simulation time 116698332 ps
CPU time 4.86 seconds
Started May 09 12:35:03 PM PDT 24
Finished May 09 12:35:17 PM PDT 24
Peak memory 209664 kb
Host smart-5fe4409c-4832-4f2e-ad11-9089421e85e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329984656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.2329984656
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.1965178808
Short name T364
Test name
Test status
Simulation time 123285598 ps
CPU time 3.95 seconds
Started May 09 12:35:01 PM PDT 24
Finished May 09 12:35:13 PM PDT 24
Peak memory 210504 kb
Host smart-e0ad3353-86d4-4104-a473-af9e7a00db71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965178808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.1965178808
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.3947619067
Short name T429
Test name
Test status
Simulation time 20010844 ps
CPU time 1.03 seconds
Started May 09 12:35:19 PM PDT 24
Finished May 09 12:35:31 PM PDT 24
Peak memory 205944 kb
Host smart-a8ea4096-8a1f-482e-9cac-33802cbd471f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947619067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.3947619067
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.1328776472
Short name T386
Test name
Test status
Simulation time 32529552 ps
CPU time 2.15 seconds
Started May 09 12:35:20 PM PDT 24
Finished May 09 12:35:34 PM PDT 24
Peak memory 214216 kb
Host smart-c8b2f8b9-e238-47cb-88c2-ee9d33b9c31d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1328776472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.1328776472
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.2873088041
Short name T9
Test name
Test status
Simulation time 346274658 ps
CPU time 3.67 seconds
Started May 09 12:35:43 PM PDT 24
Finished May 09 12:35:52 PM PDT 24
Peak memory 217500 kb
Host smart-1c1716dc-da21-4ff4-8e08-281421ae22c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873088041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.2873088041
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.4228865344
Short name T649
Test name
Test status
Simulation time 560781540 ps
CPU time 13.69 seconds
Started May 09 12:35:17 PM PDT 24
Finished May 09 12:35:42 PM PDT 24
Peak memory 209488 kb
Host smart-7f4b621e-7fe8-42fc-98dd-d546d368f21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228865344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.4228865344
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.3498632509
Short name T502
Test name
Test status
Simulation time 6900474878 ps
CPU time 46.23 seconds
Started May 09 12:35:24 PM PDT 24
Finished May 09 12:36:21 PM PDT 24
Peak memory 214452 kb
Host smart-ac604441-e2fe-4077-8897-24444da3dc9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498632509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.3498632509
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.1293052100
Short name T357
Test name
Test status
Simulation time 152613100 ps
CPU time 5.48 seconds
Started May 09 12:35:21 PM PDT 24
Finished May 09 12:35:39 PM PDT 24
Peak memory 214168 kb
Host smart-112bcac4-baa7-4e0d-9c9b-cb30844cca1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293052100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.1293052100
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.3222914557
Short name T682
Test name
Test status
Simulation time 57674521 ps
CPU time 2.12 seconds
Started May 09 12:35:18 PM PDT 24
Finished May 09 12:35:32 PM PDT 24
Peak memory 214416 kb
Host smart-b741ad92-d5f9-428e-b982-a4907054d442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222914557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.3222914557
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.1186743225
Short name T687
Test name
Test status
Simulation time 981938244 ps
CPU time 8.67 seconds
Started May 09 12:35:18 PM PDT 24
Finished May 09 12:35:38 PM PDT 24
Peak memory 214204 kb
Host smart-0c3eccb8-0cb8-4f61-8ee3-aa810bd835ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186743225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.1186743225
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.3252949421
Short name T558
Test name
Test status
Simulation time 1442851013 ps
CPU time 5.91 seconds
Started May 09 12:35:06 PM PDT 24
Finished May 09 12:35:23 PM PDT 24
Peak memory 206720 kb
Host smart-39b92038-d9de-4edf-8b72-08ed805a8250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252949421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.3252949421
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.2494839702
Short name T448
Test name
Test status
Simulation time 113603881 ps
CPU time 2.85 seconds
Started May 09 12:35:17 PM PDT 24
Finished May 09 12:35:32 PM PDT 24
Peak memory 208780 kb
Host smart-c0ebdf66-c1d3-4fc8-91df-5e0ee8770cf5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494839702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.2494839702
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.2744462393
Short name T552
Test name
Test status
Simulation time 608616126 ps
CPU time 18.97 seconds
Started May 09 12:35:22 PM PDT 24
Finished May 09 12:35:53 PM PDT 24
Peak memory 207744 kb
Host smart-985a8dae-f20e-4706-b618-af448c3a7d6a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744462393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.2744462393
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.3470884476
Short name T784
Test name
Test status
Simulation time 62375120 ps
CPU time 2.31 seconds
Started May 09 12:35:26 PM PDT 24
Finished May 09 12:35:39 PM PDT 24
Peak memory 207128 kb
Host smart-b8e024b3-f530-4235-8fbe-4fea2f19dade
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470884476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.3470884476
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.672595844
Short name T660
Test name
Test status
Simulation time 533075727 ps
CPU time 6.09 seconds
Started May 09 12:35:16 PM PDT 24
Finished May 09 12:35:33 PM PDT 24
Peak memory 208560 kb
Host smart-562289d4-eb9d-44eb-bc4c-de83240fefe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672595844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.672595844
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.1102358690
Short name T379
Test name
Test status
Simulation time 175268437 ps
CPU time 5.76 seconds
Started May 09 12:35:09 PM PDT 24
Finished May 09 12:35:26 PM PDT 24
Peak memory 208164 kb
Host smart-bbe4fda8-df7d-4237-8741-dc174e983e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102358690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.1102358690
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.3761942286
Short name T67
Test name
Test status
Simulation time 5392233613 ps
CPU time 91.9 seconds
Started May 09 12:35:14 PM PDT 24
Finished May 09 12:36:58 PM PDT 24
Peak memory 216912 kb
Host smart-1766227d-1c21-4551-847f-10ca0d3728ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761942286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.3761942286
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.2242672265
Short name T176
Test name
Test status
Simulation time 1439429092 ps
CPU time 14.28 seconds
Started May 09 12:35:21 PM PDT 24
Finished May 09 12:35:46 PM PDT 24
Peak memory 218716 kb
Host smart-154075d0-d0ed-47e5-a70f-1151a5593271
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242672265 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.2242672265
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.893174289
Short name T786
Test name
Test status
Simulation time 1078505570 ps
CPU time 27.6 seconds
Started May 09 12:35:28 PM PDT 24
Finished May 09 12:36:06 PM PDT 24
Peak memory 208704 kb
Host smart-cf7bac0a-794b-4fc9-a60b-406123019020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893174289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.893174289
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.674909728
Short name T103
Test name
Test status
Simulation time 138894246 ps
CPU time 1.83 seconds
Started May 09 12:35:18 PM PDT 24
Finished May 09 12:35:31 PM PDT 24
Peak memory 209844 kb
Host smart-b392b3b6-4566-4f5a-9663-7cc461b55fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674909728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.674909728
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.997157170
Short name T872
Test name
Test status
Simulation time 19883579 ps
CPU time 0.69 seconds
Started May 09 12:34:03 PM PDT 24
Finished May 09 12:34:13 PM PDT 24
Peak memory 205708 kb
Host smart-9c16fcfe-5d61-4211-b3f6-d96414d5c1cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997157170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.997157170
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.2093872998
Short name T370
Test name
Test status
Simulation time 848099535 ps
CPU time 8.7 seconds
Started May 09 12:33:40 PM PDT 24
Finished May 09 12:34:04 PM PDT 24
Peak memory 214156 kb
Host smart-c62f80be-537b-4729-aae6-dde19df9008b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2093872998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.2093872998
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.3835044461
Short name T531
Test name
Test status
Simulation time 22999023 ps
CPU time 1.45 seconds
Started May 09 12:33:53 PM PDT 24
Finished May 09 12:34:01 PM PDT 24
Peak memory 209224 kb
Host smart-f324ee8a-e01f-4f27-9ee8-c9f1b6271e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835044461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.3835044461
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.3528861446
Short name T283
Test name
Test status
Simulation time 65897024 ps
CPU time 2.34 seconds
Started May 09 12:34:00 PM PDT 24
Finished May 09 12:34:10 PM PDT 24
Peak memory 214112 kb
Host smart-e562708f-d2c9-4048-b3dd-69af797477be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528861446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.3528861446
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.3614079712
Short name T90
Test name
Test status
Simulation time 418995000 ps
CPU time 5.54 seconds
Started May 09 12:34:03 PM PDT 24
Finished May 09 12:34:17 PM PDT 24
Peak memory 214216 kb
Host smart-da283617-5266-48d2-af16-66276f7206f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614079712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.3614079712
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.2320969333
Short name T93
Test name
Test status
Simulation time 198511556 ps
CPU time 5.24 seconds
Started May 09 12:33:42 PM PDT 24
Finished May 09 12:33:58 PM PDT 24
Peak memory 214080 kb
Host smart-6e162017-58de-4910-8d49-523a6cf2e699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320969333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.2320969333
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.478091117
Short name T685
Test name
Test status
Simulation time 157009264 ps
CPU time 3.93 seconds
Started May 09 12:33:53 PM PDT 24
Finished May 09 12:34:04 PM PDT 24
Peak memory 209872 kb
Host smart-489c41cd-f054-4018-84ad-7c4905457176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478091117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.478091117
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.4111340774
Short name T847
Test name
Test status
Simulation time 860510277 ps
CPU time 9.94 seconds
Started May 09 12:34:02 PM PDT 24
Finished May 09 12:34:21 PM PDT 24
Peak memory 218064 kb
Host smart-a2b9d5b6-a6dd-40fe-8304-c7568da8e607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111340774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.4111340774
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.1719763113
Short name T92
Test name
Test status
Simulation time 1035266826 ps
CPU time 13.27 seconds
Started May 09 12:33:41 PM PDT 24
Finished May 09 12:34:05 PM PDT 24
Peak memory 231252 kb
Host smart-f7ac337f-c06c-45f6-b8f3-5eb6f46c635e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719763113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.1719763113
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.611053059
Short name T530
Test name
Test status
Simulation time 711087560 ps
CPU time 7.19 seconds
Started May 09 12:34:01 PM PDT 24
Finished May 09 12:34:16 PM PDT 24
Peak memory 206820 kb
Host smart-56e95b6f-3999-43cd-aba6-88ffc1934917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611053059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.611053059
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.1420442724
Short name T769
Test name
Test status
Simulation time 43788849 ps
CPU time 1.78 seconds
Started May 09 12:33:56 PM PDT 24
Finished May 09 12:34:04 PM PDT 24
Peak memory 207340 kb
Host smart-c8e929df-b487-44c2-96d5-fc7e769f62dd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420442724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.1420442724
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.2201082825
Short name T735
Test name
Test status
Simulation time 45655194 ps
CPU time 2.6 seconds
Started May 09 12:33:39 PM PDT 24
Finished May 09 12:33:52 PM PDT 24
Peak memory 208504 kb
Host smart-28d6f809-2fe7-451b-bf4c-8fc420ba04bd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201082825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.2201082825
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.2609457506
Short name T730
Test name
Test status
Simulation time 765985076 ps
CPU time 10.93 seconds
Started May 09 12:33:59 PM PDT 24
Finished May 09 12:34:17 PM PDT 24
Peak memory 208696 kb
Host smart-5def69b5-60e0-442e-8d11-b40926769068
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609457506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.2609457506
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.2127389193
Short name T729
Test name
Test status
Simulation time 994326688 ps
CPU time 4.65 seconds
Started May 09 12:33:44 PM PDT 24
Finished May 09 12:33:59 PM PDT 24
Peak memory 208248 kb
Host smart-be3f903a-307f-4c77-b39b-48b063335f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127389193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.2127389193
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.3148533262
Short name T417
Test name
Test status
Simulation time 402809706 ps
CPU time 3.29 seconds
Started May 09 12:33:55 PM PDT 24
Finished May 09 12:34:06 PM PDT 24
Peak memory 206484 kb
Host smart-a0221e37-4348-4bbe-8052-fa3055cb4cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148533262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.3148533262
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.2162936745
Short name T861
Test name
Test status
Simulation time 16180863178 ps
CPU time 102.72 seconds
Started May 09 12:33:51 PM PDT 24
Finished May 09 12:35:41 PM PDT 24
Peak memory 222432 kb
Host smart-9d3df6cd-716f-4881-82ec-ede57e87ad4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162936745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.2162936745
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.3450505163
Short name T480
Test name
Test status
Simulation time 712270106 ps
CPU time 4.7 seconds
Started May 09 12:33:43 PM PDT 24
Finished May 09 12:33:58 PM PDT 24
Peak memory 214112 kb
Host smart-5e8ff516-2df0-4cfd-8260-d9e8cf58ef1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450505163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.3450505163
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.3354982705
Short name T576
Test name
Test status
Simulation time 206820058 ps
CPU time 2.68 seconds
Started May 09 12:33:39 PM PDT 24
Finished May 09 12:33:53 PM PDT 24
Peak memory 210348 kb
Host smart-c7a25a88-a58b-46c9-9b0d-0261b2670fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354982705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.3354982705
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.2885904498
Short name T622
Test name
Test status
Simulation time 14325875 ps
CPU time 0.74 seconds
Started May 09 12:35:29 PM PDT 24
Finished May 09 12:35:39 PM PDT 24
Peak memory 205736 kb
Host smart-732c8f78-2188-4fa3-a086-708724af6a81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885904498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.2885904498
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.1778568204
Short name T356
Test name
Test status
Simulation time 112452211 ps
CPU time 4.12 seconds
Started May 09 12:35:18 PM PDT 24
Finished May 09 12:35:33 PM PDT 24
Peak memory 214228 kb
Host smart-f8686cc1-1878-457f-b81b-be6efc99cebb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1778568204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.1778568204
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.420856990
Short name T509
Test name
Test status
Simulation time 710102864 ps
CPU time 6.65 seconds
Started May 09 12:35:25 PM PDT 24
Finished May 09 12:35:42 PM PDT 24
Peak memory 220456 kb
Host smart-209f4824-5224-4682-8ecb-adcc26fb9caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420856990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.420856990
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.248745878
Short name T463
Test name
Test status
Simulation time 343899903 ps
CPU time 3.09 seconds
Started May 09 12:35:24 PM PDT 24
Finished May 09 12:35:38 PM PDT 24
Peak memory 207324 kb
Host smart-00d076f5-9966-485b-be02-4a1cce2d0a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248745878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.248745878
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.1035588814
Short name T267
Test name
Test status
Simulation time 87019371 ps
CPU time 2.85 seconds
Started May 09 12:35:22 PM PDT 24
Finished May 09 12:35:36 PM PDT 24
Peak memory 214176 kb
Host smart-f791e333-9f29-4f23-9d7f-5ce1a85687f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035588814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.1035588814
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.3571579773
Short name T798
Test name
Test status
Simulation time 86405027 ps
CPU time 3.85 seconds
Started May 09 12:35:25 PM PDT 24
Finished May 09 12:35:40 PM PDT 24
Peak memory 214132 kb
Host smart-79beca49-4a23-47f1-b7bb-b0942f2ffea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571579773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.3571579773
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.185226525
Short name T374
Test name
Test status
Simulation time 97485002 ps
CPU time 2.93 seconds
Started May 09 12:35:19 PM PDT 24
Finished May 09 12:35:33 PM PDT 24
Peak memory 214584 kb
Host smart-5db6f423-8b6e-4385-9772-0e1a29674d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185226525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.185226525
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.1970378270
Short name T181
Test name
Test status
Simulation time 43760241 ps
CPU time 2.9 seconds
Started May 09 12:35:14 PM PDT 24
Finished May 09 12:35:29 PM PDT 24
Peak memory 209076 kb
Host smart-36444c8b-bf0f-4e77-9450-ef9b625c27fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970378270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.1970378270
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.796203041
Short name T890
Test name
Test status
Simulation time 40198369 ps
CPU time 2.32 seconds
Started May 09 12:35:24 PM PDT 24
Finished May 09 12:35:37 PM PDT 24
Peak memory 206720 kb
Host smart-d91729e7-f2bf-45d9-8f96-6507e74930af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796203041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.796203041
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.2832994194
Short name T726
Test name
Test status
Simulation time 331373265 ps
CPU time 5.24 seconds
Started May 09 12:35:20 PM PDT 24
Finished May 09 12:35:36 PM PDT 24
Peak memory 208880 kb
Host smart-7dea6a5b-e24a-4310-9229-dd18078f6c8e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832994194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.2832994194
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.972202089
Short name T704
Test name
Test status
Simulation time 355342571 ps
CPU time 12.02 seconds
Started May 09 12:35:30 PM PDT 24
Finished May 09 12:35:51 PM PDT 24
Peak memory 206740 kb
Host smart-e2ea1460-230a-4110-87db-d2748d88fc48
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972202089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.972202089
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.1322499051
Short name T253
Test name
Test status
Simulation time 106204163 ps
CPU time 2.94 seconds
Started May 09 12:35:26 PM PDT 24
Finished May 09 12:35:39 PM PDT 24
Peak memory 207196 kb
Host smart-5da9a67b-183b-41fa-b6f3-56ad32a99048
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322499051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.1322499051
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.1089125813
Short name T252
Test name
Test status
Simulation time 255269338 ps
CPU time 3.9 seconds
Started May 09 12:35:13 PM PDT 24
Finished May 09 12:35:29 PM PDT 24
Peak memory 210304 kb
Host smart-660fad18-ecbe-417c-be77-8f9ef509a60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089125813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.1089125813
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.4075173745
Short name T459
Test name
Test status
Simulation time 4043250516 ps
CPU time 8.53 seconds
Started May 09 12:35:30 PM PDT 24
Finished May 09 12:35:48 PM PDT 24
Peak memory 208296 kb
Host smart-effaa4b1-94bc-48ef-8054-b5baede076fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075173745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.4075173745
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.2196252948
Short name T190
Test name
Test status
Simulation time 1462462974 ps
CPU time 55.87 seconds
Started May 09 12:35:14 PM PDT 24
Finished May 09 12:36:21 PM PDT 24
Peak memory 216372 kb
Host smart-0f4d7083-812f-4df9-95eb-c73a49a27dfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196252948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.2196252948
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.1858394482
Short name T775
Test name
Test status
Simulation time 1002207681 ps
CPU time 19.11 seconds
Started May 09 12:35:17 PM PDT 24
Finished May 09 12:35:48 PM PDT 24
Peak memory 222436 kb
Host smart-f5f8ddef-7b37-4d5d-ae4b-ab11970a029e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858394482 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.1858394482
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.993671367
Short name T573
Test name
Test status
Simulation time 184527661 ps
CPU time 5.68 seconds
Started May 09 12:35:24 PM PDT 24
Finished May 09 12:35:41 PM PDT 24
Peak memory 218380 kb
Host smart-43837d62-e7df-48f9-a4c9-7a472440a55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993671367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.993671367
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.1164536547
Short name T170
Test name
Test status
Simulation time 200104220 ps
CPU time 4.28 seconds
Started May 09 12:35:14 PM PDT 24
Finished May 09 12:35:30 PM PDT 24
Peak memory 210056 kb
Host smart-38cd8bfc-fa0d-4276-a462-3fea2e05d785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164536547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.1164536547
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.2085091601
Short name T755
Test name
Test status
Simulation time 23230599 ps
CPU time 0.73 seconds
Started May 09 12:35:24 PM PDT 24
Finished May 09 12:35:36 PM PDT 24
Peak memory 205772 kb
Host smart-64c71061-81b5-402c-b714-db5d6ec60785
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085091601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.2085091601
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.2185256186
Short name T22
Test name
Test status
Simulation time 577576793 ps
CPU time 2.13 seconds
Started May 09 12:35:29 PM PDT 24
Finished May 09 12:35:41 PM PDT 24
Peak memory 221084 kb
Host smart-f2df5e04-dca1-4060-bacb-fb956803b723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185256186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.2185256186
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.2994167253
Short name T70
Test name
Test status
Simulation time 37153277 ps
CPU time 1.39 seconds
Started May 09 12:35:40 PM PDT 24
Finished May 09 12:35:47 PM PDT 24
Peak memory 206688 kb
Host smart-231d7745-5330-4387-9f70-8b189a2de3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994167253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.2994167253
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.4156533848
Short name T339
Test name
Test status
Simulation time 27842275 ps
CPU time 1.87 seconds
Started May 09 12:35:27 PM PDT 24
Finished May 09 12:35:39 PM PDT 24
Peak memory 214164 kb
Host smart-1284e53e-aaee-4cbc-8e9d-ec916d1e19ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156533848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.4156533848
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.2933570669
Short name T41
Test name
Test status
Simulation time 1090062443 ps
CPU time 2.64 seconds
Started May 09 12:35:38 PM PDT 24
Finished May 09 12:35:47 PM PDT 24
Peak memory 214088 kb
Host smart-bc4f97d4-76f2-4f00-abe8-3890eaf5c0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933570669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.2933570669
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.3049255957
Short name T220
Test name
Test status
Simulation time 37665056 ps
CPU time 2.29 seconds
Started May 09 12:35:28 PM PDT 24
Finished May 09 12:35:41 PM PDT 24
Peak memory 207648 kb
Host smart-c0fc24e8-797b-44a9-8d5f-cd728f654a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049255957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.3049255957
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.1254976731
Short name T770
Test name
Test status
Simulation time 39272794 ps
CPU time 2.92 seconds
Started May 09 12:35:31 PM PDT 24
Finished May 09 12:35:43 PM PDT 24
Peak memory 207352 kb
Host smart-8ef0c0b1-887f-43fd-88b2-04a4c8e8e58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254976731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.1254976731
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.2420607239
Short name T270
Test name
Test status
Simulation time 210213755 ps
CPU time 4.89 seconds
Started May 09 12:35:24 PM PDT 24
Finished May 09 12:35:40 PM PDT 24
Peak memory 208292 kb
Host smart-e028f079-bd3e-4562-b275-c1d491659c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420607239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.2420607239
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.3636485036
Short name T455
Test name
Test status
Simulation time 282182975 ps
CPU time 3.11 seconds
Started May 09 12:35:34 PM PDT 24
Finished May 09 12:35:45 PM PDT 24
Peak memory 207896 kb
Host smart-00a39b33-5847-4d28-b146-6e8c2b7bebee
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636485036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.3636485036
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.1098684062
Short name T434
Test name
Test status
Simulation time 47239230 ps
CPU time 2.85 seconds
Started May 09 12:35:24 PM PDT 24
Finished May 09 12:35:38 PM PDT 24
Peak memory 208600 kb
Host smart-68d2583d-e6db-47db-b7a2-0295d107fe8e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098684062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.1098684062
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.472976475
Short name T579
Test name
Test status
Simulation time 52951243 ps
CPU time 2.65 seconds
Started May 09 12:35:24 PM PDT 24
Finished May 09 12:35:38 PM PDT 24
Peak memory 208412 kb
Host smart-30e84736-c854-4fe3-bd2c-3365dd9401c2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472976475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.472976475
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.1250969272
Short name T524
Test name
Test status
Simulation time 129348856 ps
CPU time 2.36 seconds
Started May 09 12:35:32 PM PDT 24
Finished May 09 12:35:45 PM PDT 24
Peak memory 215244 kb
Host smart-10ced086-2de1-4905-adec-193b960d839d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250969272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.1250969272
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.3458664708
Short name T816
Test name
Test status
Simulation time 120607016 ps
CPU time 2.25 seconds
Started May 09 12:35:25 PM PDT 24
Finished May 09 12:35:38 PM PDT 24
Peak memory 206608 kb
Host smart-2402274a-81a8-45b7-b6ee-7b0a90a6865e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458664708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.3458664708
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.4056805404
Short name T278
Test name
Test status
Simulation time 3831790288 ps
CPU time 20.33 seconds
Started May 09 12:35:29 PM PDT 24
Finished May 09 12:35:59 PM PDT 24
Peak memory 215700 kb
Host smart-96195c1d-a329-4613-928a-115726f12d8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056805404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.4056805404
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.2466488015
Short name T269
Test name
Test status
Simulation time 378127400 ps
CPU time 4.99 seconds
Started May 09 12:35:29 PM PDT 24
Finished May 09 12:35:44 PM PDT 24
Peak memory 214080 kb
Host smart-5e1be220-3ee2-4679-97b9-b101f83f01ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466488015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.2466488015
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.2364459679
Short name T766
Test name
Test status
Simulation time 493187656 ps
CPU time 2.9 seconds
Started May 09 12:35:09 PM PDT 24
Finished May 09 12:35:24 PM PDT 24
Peak memory 210548 kb
Host smart-7cff5584-5518-48db-bdd1-109760e10d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364459679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.2364459679
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.2430263826
Short name T484
Test name
Test status
Simulation time 35975363 ps
CPU time 0.76 seconds
Started May 09 12:35:31 PM PDT 24
Finished May 09 12:35:41 PM PDT 24
Peak memory 205768 kb
Host smart-73b87596-a678-4229-88c3-29dbc89a4f9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430263826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.2430263826
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.3130808720
Short name T62
Test name
Test status
Simulation time 281982196 ps
CPU time 3.06 seconds
Started May 09 12:35:26 PM PDT 24
Finished May 09 12:35:43 PM PDT 24
Peak memory 222576 kb
Host smart-69e66dfd-dd1e-42db-b742-691a09e7496d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130808720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.3130808720
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.3834239742
Short name T767
Test name
Test status
Simulation time 183245162 ps
CPU time 3.19 seconds
Started May 09 12:35:15 PM PDT 24
Finished May 09 12:35:30 PM PDT 24
Peak memory 214176 kb
Host smart-46115a9a-4f30-449b-8789-46f305ea7c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834239742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.3834239742
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.928090288
Short name T474
Test name
Test status
Simulation time 5609232343 ps
CPU time 39.83 seconds
Started May 09 12:35:26 PM PDT 24
Finished May 09 12:36:16 PM PDT 24
Peak memory 214256 kb
Host smart-0297bf1e-e168-4a66-aa4d-ce395cc0c88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928090288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.928090288
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.3797982427
Short name T647
Test name
Test status
Simulation time 335314126 ps
CPU time 4.06 seconds
Started May 09 12:35:24 PM PDT 24
Finished May 09 12:35:39 PM PDT 24
Peak memory 222292 kb
Host smart-02614f2b-20f5-4830-93d0-3cd62075dcca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797982427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.3797982427
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.2892120346
Short name T534
Test name
Test status
Simulation time 65621259 ps
CPU time 2.47 seconds
Started May 09 12:35:26 PM PDT 24
Finished May 09 12:35:39 PM PDT 24
Peak memory 206032 kb
Host smart-309cdf79-b589-4925-9b12-ac5bf89020c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892120346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.2892120346
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.981388057
Short name T297
Test name
Test status
Simulation time 1227574055 ps
CPU time 9.4 seconds
Started May 09 12:35:19 PM PDT 24
Finished May 09 12:35:39 PM PDT 24
Peak memory 214232 kb
Host smart-ee1f8f0f-6464-46ad-8f01-f2f3556709dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981388057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.981388057
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.2941148819
Short name T829
Test name
Test status
Simulation time 62064726 ps
CPU time 3.13 seconds
Started May 09 12:35:34 PM PDT 24
Finished May 09 12:35:45 PM PDT 24
Peak memory 206592 kb
Host smart-06aa47ec-fa06-4fdb-b87b-09f58026a244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941148819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.2941148819
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.3782133161
Short name T673
Test name
Test status
Simulation time 67086812 ps
CPU time 3.25 seconds
Started May 09 12:35:24 PM PDT 24
Finished May 09 12:35:38 PM PDT 24
Peak memory 208104 kb
Host smart-b8c88b9a-6eef-4042-bbd1-a0649b5e6c90
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782133161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.3782133161
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.1802533724
Short name T298
Test name
Test status
Simulation time 266669765 ps
CPU time 7.41 seconds
Started May 09 12:35:32 PM PDT 24
Finished May 09 12:35:48 PM PDT 24
Peak memory 207804 kb
Host smart-f9a602eb-05d6-419a-bfb5-fed984c4477d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802533724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.1802533724
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.553297643
Short name T354
Test name
Test status
Simulation time 86270523 ps
CPU time 3.13 seconds
Started May 09 12:35:19 PM PDT 24
Finished May 09 12:35:33 PM PDT 24
Peak memory 206856 kb
Host smart-8c048af1-b1c4-4b1d-bfa3-b1dbbebb2c12
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553297643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.553297643
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.661647708
Short name T316
Test name
Test status
Simulation time 627474216 ps
CPU time 3.82 seconds
Started May 09 12:35:26 PM PDT 24
Finished May 09 12:35:40 PM PDT 24
Peak memory 218176 kb
Host smart-a218dfa7-b3be-41dc-85ad-95c42663150c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661647708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.661647708
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.2079218023
Short name T839
Test name
Test status
Simulation time 1351040490 ps
CPU time 19.36 seconds
Started May 09 12:35:28 PM PDT 24
Finished May 09 12:35:57 PM PDT 24
Peak memory 208048 kb
Host smart-0f0b24f5-c554-48b5-acd2-bb18e1df549c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079218023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.2079218023
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.667367444
Short name T411
Test name
Test status
Simulation time 1370400007 ps
CPU time 8.93 seconds
Started May 09 12:35:22 PM PDT 24
Finished May 09 12:35:43 PM PDT 24
Peak memory 208500 kb
Host smart-a57c2a4f-0432-40a1-8583-b3c244209806
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667367444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.667367444
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.698147503
Short name T292
Test name
Test status
Simulation time 1484422378 ps
CPU time 36.55 seconds
Started May 09 12:35:24 PM PDT 24
Finished May 09 12:36:12 PM PDT 24
Peak memory 214144 kb
Host smart-6e03f674-e1e9-454d-88cb-a3db19380028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698147503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.698147503
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.2576279568
Short name T563
Test name
Test status
Simulation time 378762256 ps
CPU time 1.98 seconds
Started May 09 12:35:32 PM PDT 24
Finished May 09 12:35:43 PM PDT 24
Peak memory 209912 kb
Host smart-33c3a699-e10a-4863-a9ad-dea755fb02d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576279568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.2576279568
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.1165511666
Short name T759
Test name
Test status
Simulation time 20056645 ps
CPU time 1.05 seconds
Started May 09 12:35:25 PM PDT 24
Finished May 09 12:35:37 PM PDT 24
Peak memory 205908 kb
Host smart-f22f82ac-8a07-427b-a494-d383af6fdb33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165511666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.1165511666
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.363384741
Short name T392
Test name
Test status
Simulation time 335303525 ps
CPU time 8.59 seconds
Started May 09 12:35:26 PM PDT 24
Finished May 09 12:35:45 PM PDT 24
Peak memory 214268 kb
Host smart-4bdedbaa-c288-4aa3-9455-2a23d600f982
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=363384741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.363384741
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.2533678240
Short name T37
Test name
Test status
Simulation time 712313983 ps
CPU time 2.59 seconds
Started May 09 12:35:19 PM PDT 24
Finished May 09 12:35:32 PM PDT 24
Peak memory 208656 kb
Host smart-7a89042b-4a16-4280-b9d2-fc40cc39eef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533678240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.2533678240
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.341349589
Short name T773
Test name
Test status
Simulation time 39440721 ps
CPU time 2.35 seconds
Started May 09 12:35:26 PM PDT 24
Finished May 09 12:35:39 PM PDT 24
Peak memory 207248 kb
Host smart-2d4dbf88-2125-4e79-8d69-8772261a634a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341349589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.341349589
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.246992968
Short name T83
Test name
Test status
Simulation time 58735080 ps
CPU time 3.15 seconds
Started May 09 12:35:26 PM PDT 24
Finished May 09 12:35:39 PM PDT 24
Peak memory 214248 kb
Host smart-26a94c80-e5d6-45b3-a85f-48cb05cc02ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246992968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.246992968
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.642033902
Short name T361
Test name
Test status
Simulation time 349546632 ps
CPU time 2.94 seconds
Started May 09 12:35:32 PM PDT 24
Finished May 09 12:35:44 PM PDT 24
Peak memory 214080 kb
Host smart-409fb3d3-8c04-4f29-8f1e-064d5fc6a25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642033902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.642033902
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.1875862380
Short name T208
Test name
Test status
Simulation time 89092217 ps
CPU time 3.66 seconds
Started May 09 12:35:24 PM PDT 24
Finished May 09 12:35:39 PM PDT 24
Peak memory 220100 kb
Host smart-2fa547a3-837e-4bff-a8ce-f94c3daf954a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875862380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.1875862380
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.4101448204
Short name T491
Test name
Test status
Simulation time 75348605 ps
CPU time 3.71 seconds
Started May 09 12:35:29 PM PDT 24
Finished May 09 12:35:42 PM PDT 24
Peak memory 209444 kb
Host smart-0755eec0-0198-4b8a-b093-e9bcbd6f8c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101448204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.4101448204
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.3365391968
Short name T562
Test name
Test status
Simulation time 109238406 ps
CPU time 2.88 seconds
Started May 09 12:35:24 PM PDT 24
Finished May 09 12:35:38 PM PDT 24
Peak memory 206536 kb
Host smart-888c79f3-d911-42bd-8fd5-10b66a9d184d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365391968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.3365391968
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.1160457495
Short name T99
Test name
Test status
Simulation time 482353995 ps
CPU time 6.92 seconds
Started May 09 12:35:23 PM PDT 24
Finished May 09 12:35:41 PM PDT 24
Peak memory 208184 kb
Host smart-0f3ea12a-ad33-4299-95c9-b8d956bf358a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160457495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.1160457495
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.886808272
Short name T565
Test name
Test status
Simulation time 239053927 ps
CPU time 8.58 seconds
Started May 09 12:35:23 PM PDT 24
Finished May 09 12:35:43 PM PDT 24
Peak memory 206692 kb
Host smart-00580d17-e1af-46f4-9b9e-322c734b9b20
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886808272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.886808272
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.1244709731
Short name T192
Test name
Test status
Simulation time 102695552 ps
CPU time 2.82 seconds
Started May 09 12:35:38 PM PDT 24
Finished May 09 12:35:48 PM PDT 24
Peak memory 206852 kb
Host smart-cf762a4e-5bc2-40b6-9596-4c2b81661d6b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244709731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.1244709731
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.1121569437
Short name T349
Test name
Test status
Simulation time 30753851 ps
CPU time 1.78 seconds
Started May 09 12:35:25 PM PDT 24
Finished May 09 12:35:37 PM PDT 24
Peak memory 208868 kb
Host smart-cf5acdbe-9f7e-411c-8559-32667245e71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121569437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.1121569437
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.2997285258
Short name T479
Test name
Test status
Simulation time 370302674 ps
CPU time 3.16 seconds
Started May 09 12:35:25 PM PDT 24
Finished May 09 12:35:39 PM PDT 24
Peak memory 206712 kb
Host smart-d33d7c1e-a9e2-4d35-8d19-5ca08b6566ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997285258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.2997285258
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.3230599332
Short name T45
Test name
Test status
Simulation time 14857792877 ps
CPU time 157.85 seconds
Started May 09 12:35:33 PM PDT 24
Finished May 09 12:38:19 PM PDT 24
Peak memory 222480 kb
Host smart-04e9f2b3-ca4d-4cfc-b31f-2ee9e0998a1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230599332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.3230599332
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.2551567791
Short name T124
Test name
Test status
Simulation time 722095832 ps
CPU time 12.83 seconds
Started May 09 12:35:25 PM PDT 24
Finished May 09 12:35:49 PM PDT 24
Peak memory 222404 kb
Host smart-47a72dcf-f126-4cfd-94f5-fda9708ab154
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551567791 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.2551567791
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.2694708765
Short name T198
Test name
Test status
Simulation time 231419437 ps
CPU time 6.54 seconds
Started May 09 12:35:25 PM PDT 24
Finished May 09 12:35:42 PM PDT 24
Peak memory 209968 kb
Host smart-8c1c1a23-9f08-45ca-a426-4312109d3a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694708765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.2694708765
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.338745850
Short name T615
Test name
Test status
Simulation time 128783621 ps
CPU time 2.5 seconds
Started May 09 12:35:26 PM PDT 24
Finished May 09 12:35:40 PM PDT 24
Peak memory 209796 kb
Host smart-a0b23e60-14a2-4067-b12b-937f75b65155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338745850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.338745850
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.1802825498
Short name T128
Test name
Test status
Simulation time 12595433 ps
CPU time 0.71 seconds
Started May 09 12:35:41 PM PDT 24
Finished May 09 12:35:48 PM PDT 24
Peak memory 205816 kb
Host smart-0bed4694-36fd-4475-9c2d-fd1098966b5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802825498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.1802825498
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.1249232628
Short name T389
Test name
Test status
Simulation time 128425143 ps
CPU time 7.43 seconds
Started May 09 12:35:45 PM PDT 24
Finished May 09 12:35:57 PM PDT 24
Peak memory 214660 kb
Host smart-2a4e07dd-7b64-4c92-8202-5865abd3796d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1249232628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.1249232628
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.3721641463
Short name T1
Test name
Test status
Simulation time 43079619 ps
CPU time 3 seconds
Started May 09 12:35:35 PM PDT 24
Finished May 09 12:35:46 PM PDT 24
Peak memory 209232 kb
Host smart-f908b1e9-3c10-4a3b-a605-62ac3cf63cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721641463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.3721641463
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.1450924449
Short name T768
Test name
Test status
Simulation time 374417446 ps
CPU time 3.62 seconds
Started May 09 12:35:33 PM PDT 24
Finished May 09 12:35:45 PM PDT 24
Peak memory 208664 kb
Host smart-66487b6b-2787-4804-969d-636e49ae12f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450924449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.1450924449
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.1716531557
Short name T675
Test name
Test status
Simulation time 533002039 ps
CPU time 6.92 seconds
Started May 09 12:35:22 PM PDT 24
Finished May 09 12:35:40 PM PDT 24
Peak memory 214276 kb
Host smart-8560cea8-81e2-4aac-bf75-46309d1e0f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716531557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.1716531557
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.463544536
Short name T344
Test name
Test status
Simulation time 467577858 ps
CPU time 3.09 seconds
Started May 09 12:35:40 PM PDT 24
Finished May 09 12:35:49 PM PDT 24
Peak memory 210160 kb
Host smart-1b72649c-6449-485a-93dd-a867229bdb0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463544536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.463544536
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.145089795
Short name T781
Test name
Test status
Simulation time 90256629 ps
CPU time 4.29 seconds
Started May 09 12:35:30 PM PDT 24
Finished May 09 12:35:44 PM PDT 24
Peak memory 209292 kb
Host smart-e4ab6479-9cf6-498b-91fc-e7a35a655e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145089795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.145089795
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.1991194308
Short name T855
Test name
Test status
Simulation time 33989338 ps
CPU time 2.34 seconds
Started May 09 12:35:42 PM PDT 24
Finished May 09 12:35:49 PM PDT 24
Peak memory 206744 kb
Host smart-e8c2fed7-9230-4fb2-876a-e4fa344992f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991194308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.1991194308
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.667353291
Short name T527
Test name
Test status
Simulation time 196642864 ps
CPU time 6.95 seconds
Started May 09 12:36:39 PM PDT 24
Finished May 09 12:36:54 PM PDT 24
Peak memory 207416 kb
Host smart-5214f0d7-d032-4f34-b27d-214f9afc868c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667353291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.667353291
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.513108183
Short name T651
Test name
Test status
Simulation time 521301920 ps
CPU time 4.48 seconds
Started May 09 12:35:45 PM PDT 24
Finished May 09 12:35:55 PM PDT 24
Peak memory 206608 kb
Host smart-305a99f7-b0ed-47c6-bca6-3bb4ea634b23
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513108183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.513108183
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.356594101
Short name T378
Test name
Test status
Simulation time 146747134 ps
CPU time 4.16 seconds
Started May 09 12:36:39 PM PDT 24
Finished May 09 12:36:51 PM PDT 24
Peak memory 206640 kb
Host smart-369895cb-deee-42fc-b22d-00f136328356
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356594101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.356594101
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.3956357487
Short name T840
Test name
Test status
Simulation time 275622412 ps
CPU time 3.07 seconds
Started May 09 12:35:42 PM PDT 24
Finished May 09 12:35:51 PM PDT 24
Peak memory 209904 kb
Host smart-1634b9cd-a83d-4674-85a1-463800db56d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956357487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.3956357487
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.1821486636
Short name T470
Test name
Test status
Simulation time 50849136 ps
CPU time 2.43 seconds
Started May 09 12:35:46 PM PDT 24
Finished May 09 12:35:54 PM PDT 24
Peak memory 206592 kb
Host smart-24d4f493-b39a-415b-966e-f1759450aa41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821486636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.1821486636
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.1999747259
Short name T628
Test name
Test status
Simulation time 245803241 ps
CPU time 5.5 seconds
Started May 09 12:35:42 PM PDT 24
Finished May 09 12:35:53 PM PDT 24
Peak memory 214244 kb
Host smart-d2802bec-8ff4-41a7-be0d-03786776cb2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999747259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.1999747259
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.3419710187
Short name T116
Test name
Test status
Simulation time 121125514 ps
CPU time 2.46 seconds
Started May 09 12:36:49 PM PDT 24
Finished May 09 12:37:02 PM PDT 24
Peak memory 209480 kb
Host smart-687df428-7355-456b-828d-49f39ed39b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419710187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.3419710187
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.1931840099
Short name T857
Test name
Test status
Simulation time 8623258 ps
CPU time 0.8 seconds
Started May 09 12:35:45 PM PDT 24
Finished May 09 12:35:52 PM PDT 24
Peak memory 205792 kb
Host smart-c1b86208-10dc-418b-8e0b-ee05c60d26c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931840099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.1931840099
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.2627910294
Short name T393
Test name
Test status
Simulation time 135142481 ps
CPU time 2.55 seconds
Started May 09 12:35:39 PM PDT 24
Finished May 09 12:35:48 PM PDT 24
Peak memory 215040 kb
Host smart-dc547e05-5ec7-4fd2-8a78-fad1be3391b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2627910294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.2627910294
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.3065805054
Short name T23
Test name
Test status
Simulation time 123868963 ps
CPU time 2.52 seconds
Started May 09 12:35:41 PM PDT 24
Finished May 09 12:35:49 PM PDT 24
Peak memory 222568 kb
Host smart-a2b73d45-5220-44bd-8e30-95ade13367a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065805054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.3065805054
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.2024635343
Short name T612
Test name
Test status
Simulation time 49613710 ps
CPU time 2.18 seconds
Started May 09 12:35:24 PM PDT 24
Finished May 09 12:35:37 PM PDT 24
Peak memory 208144 kb
Host smart-aa435bcb-93fd-4ec2-a473-e4157b4f4688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024635343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.2024635343
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.4060071779
Short name T89
Test name
Test status
Simulation time 486489653 ps
CPU time 5.58 seconds
Started May 09 12:35:46 PM PDT 24
Finished May 09 12:35:57 PM PDT 24
Peak memory 214160 kb
Host smart-7f5b6b68-81ed-4f81-8d8a-fd381dacc7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060071779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.4060071779
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.2048466645
Short name T238
Test name
Test status
Simulation time 2215641189 ps
CPU time 26.66 seconds
Started May 09 12:35:25 PM PDT 24
Finished May 09 12:36:03 PM PDT 24
Peak memory 214172 kb
Host smart-639f0469-6578-4a5c-8650-db49b6670717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048466645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.2048466645
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.1015382939
Short name T135
Test name
Test status
Simulation time 38572256 ps
CPU time 2.77 seconds
Started May 09 12:35:58 PM PDT 24
Finished May 09 12:36:10 PM PDT 24
Peak memory 207736 kb
Host smart-92fda19b-8999-4f66-ad1f-7b2ba8320a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015382939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.1015382939
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.1237713746
Short name T662
Test name
Test status
Simulation time 1676104512 ps
CPU time 12.87 seconds
Started May 09 12:35:33 PM PDT 24
Finished May 09 12:35:54 PM PDT 24
Peak memory 208676 kb
Host smart-cc3d5dbc-ebf8-44e6-ad0c-0ce32a25cf21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237713746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.1237713746
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.243891374
Short name T617
Test name
Test status
Simulation time 1728779837 ps
CPU time 12.11 seconds
Started May 09 12:35:33 PM PDT 24
Finished May 09 12:35:53 PM PDT 24
Peak memory 206644 kb
Host smart-11326e87-527b-4939-9e9e-6fa6701f9ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243891374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.243891374
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.2556948546
Short name T239
Test name
Test status
Simulation time 57838415 ps
CPU time 2.94 seconds
Started May 09 12:35:40 PM PDT 24
Finished May 09 12:35:49 PM PDT 24
Peak memory 206840 kb
Host smart-969a3129-5634-493a-ab14-c8068d2a7748
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556948546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.2556948546
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.4021935225
Short name T430
Test name
Test status
Simulation time 111396663 ps
CPU time 4.54 seconds
Started May 09 12:35:40 PM PDT 24
Finished May 09 12:35:50 PM PDT 24
Peak memory 207880 kb
Host smart-a8241faf-b51a-48bd-8acc-000924b12658
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021935225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.4021935225
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.3943111924
Short name T763
Test name
Test status
Simulation time 446762496 ps
CPU time 4.31 seconds
Started May 09 12:35:36 PM PDT 24
Finished May 09 12:35:47 PM PDT 24
Peak memory 209600 kb
Host smart-eef94d07-8881-4cbf-972f-6181762e2e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943111924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.3943111924
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.3959963029
Short name T496
Test name
Test status
Simulation time 143218319 ps
CPU time 2.66 seconds
Started May 09 12:35:38 PM PDT 24
Finished May 09 12:35:47 PM PDT 24
Peak memory 206644 kb
Host smart-9639afe1-9e08-41e0-8716-aa0fa597e069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959963029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.3959963029
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.277213665
Short name T174
Test name
Test status
Simulation time 240826393 ps
CPU time 9.09 seconds
Started May 09 12:35:24 PM PDT 24
Finished May 09 12:35:44 PM PDT 24
Peak memory 222424 kb
Host smart-4d7d1101-6879-4708-a395-c6f3335bede0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277213665 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.277213665
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.1409032649
Short name T201
Test name
Test status
Simulation time 90835674 ps
CPU time 3.99 seconds
Started May 09 12:35:25 PM PDT 24
Finished May 09 12:35:40 PM PDT 24
Peak memory 208124 kb
Host smart-bad87e19-5fae-4ce6-8639-1464ac86df75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409032649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.1409032649
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.4252539649
Short name T598
Test name
Test status
Simulation time 205126216 ps
CPU time 1.49 seconds
Started May 09 12:35:23 PM PDT 24
Finished May 09 12:35:36 PM PDT 24
Peak memory 209788 kb
Host smart-05fcf19e-21e8-4546-a35d-cd2ca04d453e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252539649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.4252539649
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.3711087772
Short name T129
Test name
Test status
Simulation time 17222572 ps
CPU time 0.79 seconds
Started May 09 12:35:42 PM PDT 24
Finished May 09 12:35:48 PM PDT 24
Peak memory 205768 kb
Host smart-141403d2-c0d3-4e73-959a-86c5d70fb903
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711087772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.3711087772
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.3835370641
Short name T801
Test name
Test status
Simulation time 271493436 ps
CPU time 2.58 seconds
Started May 09 12:35:26 PM PDT 24
Finished May 09 12:35:39 PM PDT 24
Peak memory 221272 kb
Host smart-3f32631a-fa50-4c53-b21c-6f5fa3322626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835370641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.3835370641
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.3264109214
Short name T236
Test name
Test status
Simulation time 28875308 ps
CPU time 2.17 seconds
Started May 09 12:35:47 PM PDT 24
Finished May 09 12:35:55 PM PDT 24
Peak memory 209760 kb
Host smart-02fb11a8-40fb-49ee-ae24-7b0a150e15c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264109214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.3264109214
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.3167322642
Short name T84
Test name
Test status
Simulation time 112435887 ps
CPU time 4.73 seconds
Started May 09 12:35:30 PM PDT 24
Finished May 09 12:35:44 PM PDT 24
Peak memory 218204 kb
Host smart-afab5487-07c6-4e60-b9f4-76374eb0f43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167322642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.3167322642
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.2959647235
Short name T594
Test name
Test status
Simulation time 84576615 ps
CPU time 2.72 seconds
Started May 09 12:36:07 PM PDT 24
Finished May 09 12:36:17 PM PDT 24
Peak memory 206356 kb
Host smart-8bd5beee-f541-4f12-9c79-8bdc1a12eb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959647235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.2959647235
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.3841188871
Short name T310
Test name
Test status
Simulation time 67902115 ps
CPU time 3.19 seconds
Started May 09 12:35:37 PM PDT 24
Finished May 09 12:35:47 PM PDT 24
Peak memory 220072 kb
Host smart-66bbc459-2aa5-4faa-badd-c4aee8b57b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841188871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.3841188871
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.645467821
Short name T543
Test name
Test status
Simulation time 418107399 ps
CPU time 4.91 seconds
Started May 09 12:35:46 PM PDT 24
Finished May 09 12:35:57 PM PDT 24
Peak memory 218092 kb
Host smart-a2946042-93c3-400f-93ba-6e071c645324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645467821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.645467821
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.3039197677
Short name T777
Test name
Test status
Simulation time 632518811 ps
CPU time 4.6 seconds
Started May 09 12:35:29 PM PDT 24
Finished May 09 12:35:43 PM PDT 24
Peak memory 208688 kb
Host smart-410520e5-9ec6-4041-b799-e96bf745f074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039197677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.3039197677
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.408102957
Short name T846
Test name
Test status
Simulation time 37001921 ps
CPU time 2.4 seconds
Started May 09 12:35:36 PM PDT 24
Finished May 09 12:35:45 PM PDT 24
Peak memory 208440 kb
Host smart-07cb471e-2036-4a0b-ab9e-371151eb45d3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408102957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.408102957
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.1337160430
Short name T423
Test name
Test status
Simulation time 222485460 ps
CPU time 2.4 seconds
Started May 09 12:35:26 PM PDT 24
Finished May 09 12:35:39 PM PDT 24
Peak memory 206748 kb
Host smart-e2fe996c-f291-4ffe-99f5-e9c293afab40
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337160430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.1337160430
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.995384185
Short name T774
Test name
Test status
Simulation time 120314708 ps
CPU time 3.4 seconds
Started May 09 12:36:49 PM PDT 24
Finished May 09 12:37:04 PM PDT 24
Peak memory 208280 kb
Host smart-0ec22645-5242-4607-a61c-5bcd28aff1a5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995384185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.995384185
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.2716195342
Short name T697
Test name
Test status
Simulation time 161043392 ps
CPU time 2.16 seconds
Started May 09 12:35:42 PM PDT 24
Finished May 09 12:35:50 PM PDT 24
Peak memory 208144 kb
Host smart-9f4ead5c-baa5-4f8b-897f-4e7204e0a0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716195342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2716195342
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.3453030165
Short name T425
Test name
Test status
Simulation time 988813562 ps
CPU time 3.84 seconds
Started May 09 12:35:24 PM PDT 24
Finished May 09 12:35:39 PM PDT 24
Peak memory 206640 kb
Host smart-783a3e69-e908-438c-b5cb-010845ced46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453030165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.3453030165
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.2842509548
Short name T680
Test name
Test status
Simulation time 827573453 ps
CPU time 28.26 seconds
Started May 09 12:35:38 PM PDT 24
Finished May 09 12:36:13 PM PDT 24
Peak memory 215680 kb
Host smart-8674bbc9-9a25-49f4-89fc-1a8411d1da98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842509548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.2842509548
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.2659008573
Short name T724
Test name
Test status
Simulation time 828022468 ps
CPU time 9.82 seconds
Started May 09 12:35:51 PM PDT 24
Finished May 09 12:36:08 PM PDT 24
Peak memory 214144 kb
Host smart-e1ea39e2-8df1-498b-a08b-ea658b5cc89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659008573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.2659008573
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.111627444
Short name T587
Test name
Test status
Simulation time 77160739 ps
CPU time 2.68 seconds
Started May 09 12:35:42 PM PDT 24
Finished May 09 12:35:50 PM PDT 24
Peak memory 219000 kb
Host smart-c36ba4b0-a5d1-4fff-8cf8-97682bb6012f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111627444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.111627444
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.1318365889
Short name T863
Test name
Test status
Simulation time 22744402 ps
CPU time 0.83 seconds
Started May 09 12:35:57 PM PDT 24
Finished May 09 12:36:12 PM PDT 24
Peak memory 205772 kb
Host smart-52f17c18-188b-4dd0-a13c-88c61269ef64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318365889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.1318365889
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.1156907736
Short name T369
Test name
Test status
Simulation time 146805666 ps
CPU time 8.15 seconds
Started May 09 12:35:40 PM PDT 24
Finished May 09 12:35:54 PM PDT 24
Peak memory 214632 kb
Host smart-deedf0a7-d8ea-4223-a56c-e740e491e986
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1156907736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.1156907736
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.2034550318
Short name T699
Test name
Test status
Simulation time 284987632 ps
CPU time 6.59 seconds
Started May 09 12:35:42 PM PDT 24
Finished May 09 12:35:54 PM PDT 24
Peak memory 208080 kb
Host smart-1ce5199d-5cbc-4a8a-9a48-178e8e68e5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034550318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.2034550318
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.3932326488
Short name T327
Test name
Test status
Simulation time 33763885 ps
CPU time 1.9 seconds
Started May 09 12:35:24 PM PDT 24
Finished May 09 12:35:37 PM PDT 24
Peak memory 214128 kb
Host smart-106207f0-e3c2-4450-ba0f-0b4b277c8f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932326488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.3932326488
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.548168759
Short name T50
Test name
Test status
Simulation time 85860305 ps
CPU time 3.86 seconds
Started May 09 12:35:35 PM PDT 24
Finished May 09 12:35:46 PM PDT 24
Peak memory 220236 kb
Host smart-287ac699-1065-464a-b299-fb09a928b7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548168759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.548168759
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.323197543
Short name T461
Test name
Test status
Simulation time 287486332 ps
CPU time 3.8 seconds
Started May 09 12:35:52 PM PDT 24
Finished May 09 12:36:03 PM PDT 24
Peak memory 208644 kb
Host smart-a4b91306-3431-4f69-9fdb-cde223837f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323197543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.323197543
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.3342508220
Short name T652
Test name
Test status
Simulation time 25028024 ps
CPU time 1.99 seconds
Started May 09 12:35:37 PM PDT 24
Finished May 09 12:35:46 PM PDT 24
Peak memory 208560 kb
Host smart-ac2d34f9-89ab-462e-beee-1ce32abaca7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342508220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.3342508220
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.96036634
Short name T431
Test name
Test status
Simulation time 75023297 ps
CPU time 2.81 seconds
Started May 09 12:36:48 PM PDT 24
Finished May 09 12:37:01 PM PDT 24
Peak memory 206372 kb
Host smart-e03d8a0f-7c04-4e1b-aee3-2093edf66487
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96036634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.96036634
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.2075155928
Short name T836
Test name
Test status
Simulation time 57119457 ps
CPU time 2.91 seconds
Started May 09 12:36:48 PM PDT 24
Finished May 09 12:37:02 PM PDT 24
Peak memory 208416 kb
Host smart-cd07d148-25d4-484d-baa2-a6724fd382b7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075155928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.2075155928
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.3280399720
Short name T518
Test name
Test status
Simulation time 6760184949 ps
CPU time 25.91 seconds
Started May 09 12:35:41 PM PDT 24
Finished May 09 12:36:18 PM PDT 24
Peak memory 208776 kb
Host smart-1582b6c1-f2d0-43ff-881c-595c07e577b9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280399720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.3280399720
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.4041161595
Short name T779
Test name
Test status
Simulation time 79507538 ps
CPU time 1.79 seconds
Started May 09 12:35:41 PM PDT 24
Finished May 09 12:35:48 PM PDT 24
Peak memory 218148 kb
Host smart-4e6c0298-f554-4d74-a258-2dc0ae7e2667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041161595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.4041161595
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.2601032166
Short name T874
Test name
Test status
Simulation time 229947387 ps
CPU time 5.27 seconds
Started May 09 12:35:36 PM PDT 24
Finished May 09 12:35:49 PM PDT 24
Peak memory 206600 kb
Host smart-c8498f72-384c-4538-9443-9c08f75558cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601032166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.2601032166
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.4067545486
Short name T348
Test name
Test status
Simulation time 1163370396 ps
CPU time 34.05 seconds
Started May 09 12:35:28 PM PDT 24
Finished May 09 12:36:16 PM PDT 24
Peak memory 215080 kb
Host smart-4f4c55df-faf4-4a9f-9184-4bdf3ea3cc0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067545486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.4067545486
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.1449883963
Short name T741
Test name
Test status
Simulation time 135525724 ps
CPU time 5.44 seconds
Started May 09 12:35:28 PM PDT 24
Finished May 09 12:35:44 PM PDT 24
Peak memory 218224 kb
Host smart-a4fc210e-db96-463d-b392-5c7dcb9500e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449883963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.1449883963
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.4147412
Short name T167
Test name
Test status
Simulation time 76257920 ps
CPU time 1.63 seconds
Started May 09 12:35:37 PM PDT 24
Finished May 09 12:35:45 PM PDT 24
Peak memory 209720 kb
Host smart-a0ba1ee1-2417-471f-a82b-dbf3ceb195c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.4147412
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.2503494520
Short name T453
Test name
Test status
Simulation time 42759691 ps
CPU time 0.7 seconds
Started May 09 12:36:49 PM PDT 24
Finished May 09 12:37:01 PM PDT 24
Peak memory 205668 kb
Host smart-70b5d0fe-5fee-4788-b54b-e8993e9af7f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503494520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.2503494520
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.409165124
Short name T242
Test name
Test status
Simulation time 2173070904 ps
CPU time 53.57 seconds
Started May 09 12:35:36 PM PDT 24
Finished May 09 12:36:37 PM PDT 24
Peak memory 215392 kb
Host smart-ee365069-c55b-4b04-8703-c8bbda3e19b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=409165124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.409165124
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.1365663853
Short name T53
Test name
Test status
Simulation time 7241497839 ps
CPU time 36.03 seconds
Started May 09 12:35:41 PM PDT 24
Finished May 09 12:36:22 PM PDT 24
Peak memory 214252 kb
Host smart-158897aa-fdc4-4a33-a01a-6825e915b5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365663853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.1365663853
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.2587337908
Short name T817
Test name
Test status
Simulation time 197741214 ps
CPU time 3.12 seconds
Started May 09 12:36:48 PM PDT 24
Finished May 09 12:37:02 PM PDT 24
Peak memory 222176 kb
Host smart-d10a813d-b3cd-44f1-a7e7-85037b66ca68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587337908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.2587337908
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.273215050
Short name T233
Test name
Test status
Simulation time 306207856 ps
CPU time 2.62 seconds
Started May 09 12:35:50 PM PDT 24
Finished May 09 12:35:59 PM PDT 24
Peak memory 214192 kb
Host smart-08648ebb-2324-4cb9-b9b1-835fc1babd78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273215050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.273215050
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.1267239
Short name T224
Test name
Test status
Simulation time 208048224 ps
CPU time 4.34 seconds
Started May 09 12:35:47 PM PDT 24
Finished May 09 12:35:57 PM PDT 24
Peak memory 214188 kb
Host smart-f0f3768f-2668-49bb-8ae1-463214ed6a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.1267239
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.2120360163
Short name T905
Test name
Test status
Simulation time 123326303 ps
CPU time 5.68 seconds
Started May 09 12:35:48 PM PDT 24
Finished May 09 12:35:59 PM PDT 24
Peak memory 208452 kb
Host smart-ca912c8b-c250-4a05-abc7-0031b0149979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120360163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.2120360163
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.683909543
Short name T510
Test name
Test status
Simulation time 101234861 ps
CPU time 3.99 seconds
Started May 09 12:35:38 PM PDT 24
Finished May 09 12:35:48 PM PDT 24
Peak memory 208504 kb
Host smart-1d91ed49-3ca4-4cdd-a1bb-d543ced2f2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683909543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.683909543
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.505002150
Short name T882
Test name
Test status
Simulation time 616256702 ps
CPU time 4.65 seconds
Started May 09 12:35:57 PM PDT 24
Finished May 09 12:36:11 PM PDT 24
Peak memory 207892 kb
Host smart-62692fb7-5a5b-4763-b69d-7ac0677b24ec
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505002150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.505002150
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.1581155906
Short name T756
Test name
Test status
Simulation time 63096990 ps
CPU time 2.2 seconds
Started May 09 12:35:37 PM PDT 24
Finished May 09 12:35:46 PM PDT 24
Peak memory 206716 kb
Host smart-1b009810-2c26-4dca-a4a9-dcbad72d56bd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581155906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.1581155906
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.1636340824
Short name T468
Test name
Test status
Simulation time 106059094 ps
CPU time 2.28 seconds
Started May 09 12:35:49 PM PDT 24
Finished May 09 12:35:58 PM PDT 24
Peak memory 206580 kb
Host smart-1532fdbc-7ec8-4ecd-af0a-453276e886af
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636340824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.1636340824
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.4123595997
Short name T554
Test name
Test status
Simulation time 165094967 ps
CPU time 4.23 seconds
Started May 09 12:35:57 PM PDT 24
Finished May 09 12:36:10 PM PDT 24
Peak memory 209912 kb
Host smart-d4cfd408-2001-4990-aaa4-2527a9d6e6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123595997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.4123595997
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.713965849
Short name T490
Test name
Test status
Simulation time 35980618 ps
CPU time 2.24 seconds
Started May 09 12:35:45 PM PDT 24
Finished May 09 12:35:53 PM PDT 24
Peak memory 208504 kb
Host smart-79a1476c-1b8b-43c6-952a-a4ccd774ebc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713965849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.713965849
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.175983321
Short name T549
Test name
Test status
Simulation time 149924606 ps
CPU time 3.18 seconds
Started May 09 12:36:49 PM PDT 24
Finished May 09 12:37:03 PM PDT 24
Peak memory 222012 kb
Host smart-c3a03cb3-653a-4b59-98ae-acd0358ba393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175983321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.175983321
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.3590630111
Short name T432
Test name
Test status
Simulation time 62799378 ps
CPU time 2.01 seconds
Started May 09 12:35:36 PM PDT 24
Finished May 09 12:35:45 PM PDT 24
Peak memory 208820 kb
Host smart-3f2eeafd-ac7d-4c9b-9dee-53704ef597a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590630111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.3590630111
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.565009709
Short name T418
Test name
Test status
Simulation time 55227818 ps
CPU time 0.9 seconds
Started May 09 12:36:03 PM PDT 24
Finished May 09 12:36:13 PM PDT 24
Peak memory 205940 kb
Host smart-c8bf5708-2bda-49c9-8101-f4d99d4d7355
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565009709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.565009709
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.3858723216
Short name T794
Test name
Test status
Simulation time 62014825 ps
CPU time 2.37 seconds
Started May 09 12:35:52 PM PDT 24
Finished May 09 12:36:02 PM PDT 24
Peak memory 208604 kb
Host smart-09d7c634-ad2e-458e-a0e0-f38cf3941ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858723216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.3858723216
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.472144154
Short name T34
Test name
Test status
Simulation time 145037486 ps
CPU time 2.9 seconds
Started May 09 12:35:53 PM PDT 24
Finished May 09 12:36:04 PM PDT 24
Peak memory 207416 kb
Host smart-44578d02-3d91-4fc5-8aac-fc6ad9944c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472144154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.472144154
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.3326657045
Short name T892
Test name
Test status
Simulation time 427243653 ps
CPU time 2.37 seconds
Started May 09 12:36:49 PM PDT 24
Finished May 09 12:37:02 PM PDT 24
Peak memory 214032 kb
Host smart-4eb2c84c-8d5e-4a5b-a950-41555dd2cf50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326657045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.3326657045
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.4031919408
Short name T749
Test name
Test status
Simulation time 131490419 ps
CPU time 3.86 seconds
Started May 09 12:35:36 PM PDT 24
Finished May 09 12:35:47 PM PDT 24
Peak memory 219744 kb
Host smart-1656986b-a795-4b4c-b68a-0ca322963ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031919408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.4031919408
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.2607235787
Short name T515
Test name
Test status
Simulation time 146594628 ps
CPU time 5.4 seconds
Started May 09 12:35:43 PM PDT 24
Finished May 09 12:35:54 PM PDT 24
Peak memory 209224 kb
Host smart-d7f45b96-91c9-4522-9d14-1fdc40683f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607235787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.2607235787
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.2705240109
Short name T799
Test name
Test status
Simulation time 1282937727 ps
CPU time 6.35 seconds
Started May 09 12:35:43 PM PDT 24
Finished May 09 12:35:55 PM PDT 24
Peak memory 207812 kb
Host smart-98453c63-0444-4c44-a75f-19a1ce789c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705240109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.2705240109
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.1983594909
Short name T633
Test name
Test status
Simulation time 117679459 ps
CPU time 2.11 seconds
Started May 09 12:36:49 PM PDT 24
Finished May 09 12:37:02 PM PDT 24
Peak memory 208704 kb
Host smart-5dd7e80f-1037-4e81-934a-8bc4202241bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983594909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.1983594909
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.770450200
Short name T707
Test name
Test status
Simulation time 538955162 ps
CPU time 5.79 seconds
Started May 09 12:35:26 PM PDT 24
Finished May 09 12:35:42 PM PDT 24
Peak memory 206700 kb
Host smart-8b39f6c1-033f-408e-a880-b17be896e094
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770450200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.770450200
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.1741714600
Short name T668
Test name
Test status
Simulation time 234656584 ps
CPU time 6.56 seconds
Started May 09 12:35:27 PM PDT 24
Finished May 09 12:35:44 PM PDT 24
Peak memory 208528 kb
Host smart-62554825-e45c-4d5c-bac6-a79bab84f216
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741714600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.1741714600
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.3294450116
Short name T865
Test name
Test status
Simulation time 913602054 ps
CPU time 26.39 seconds
Started May 09 12:35:59 PM PDT 24
Finished May 09 12:36:34 PM PDT 24
Peak memory 206788 kb
Host smart-5e0d144b-5186-4add-9695-259a5e94547e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294450116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.3294450116
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.655038872
Short name T812
Test name
Test status
Simulation time 155185319 ps
CPU time 2.51 seconds
Started May 09 12:35:49 PM PDT 24
Finished May 09 12:35:58 PM PDT 24
Peak memory 208652 kb
Host smart-f78a5f7b-cb38-4d77-87f8-bde3a31f18bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655038872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.655038872
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.2197983615
Short name T427
Test name
Test status
Simulation time 734186490 ps
CPU time 4.9 seconds
Started May 09 12:35:32 PM PDT 24
Finished May 09 12:35:46 PM PDT 24
Peak memory 206468 kb
Host smart-c604e1ff-eb7f-41cf-b9a8-d36f593489cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197983615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.2197983615
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.3780416078
Short name T335
Test name
Test status
Simulation time 744551707 ps
CPU time 9.64 seconds
Started May 09 12:35:50 PM PDT 24
Finished May 09 12:36:07 PM PDT 24
Peak memory 207716 kb
Host smart-87c325b4-872a-4520-bbac-7d790b3cb0e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780416078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.3780416078
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.222123621
Short name T714
Test name
Test status
Simulation time 55983100 ps
CPU time 3.38 seconds
Started May 09 12:35:53 PM PDT 24
Finished May 09 12:36:15 PM PDT 24
Peak memory 208004 kb
Host smart-86a30e55-33eb-401a-baba-0a90981857aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222123621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.222123621
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.3791077687
Short name T790
Test name
Test status
Simulation time 52581346 ps
CPU time 2.82 seconds
Started May 09 12:35:48 PM PDT 24
Finished May 09 12:35:57 PM PDT 24
Peak memory 210336 kb
Host smart-08eddf64-f578-4337-858c-ee212c885713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791077687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.3791077687
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.1217259419
Short name T408
Test name
Test status
Simulation time 9207396 ps
CPU time 0.7 seconds
Started May 09 12:33:56 PM PDT 24
Finished May 09 12:34:03 PM PDT 24
Peak memory 205740 kb
Host smart-32fb9b63-f871-4673-bcec-ae402408f60a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217259419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.1217259419
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.1814577278
Short name T391
Test name
Test status
Simulation time 285685607 ps
CPU time 14.56 seconds
Started May 09 12:34:01 PM PDT 24
Finished May 09 12:34:24 PM PDT 24
Peak memory 215664 kb
Host smart-b5ea493c-a9a2-4337-8e69-7133534cd8aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1814577278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.1814577278
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.2481846251
Short name T670
Test name
Test status
Simulation time 200443704 ps
CPU time 4.46 seconds
Started May 09 12:34:01 PM PDT 24
Finished May 09 12:34:14 PM PDT 24
Peak memory 208808 kb
Host smart-d2794fa8-c95d-49f8-b6e8-7c9913f84365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481846251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.2481846251
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.3273716239
Short name T592
Test name
Test status
Simulation time 260897767 ps
CPU time 4.19 seconds
Started May 09 12:33:52 PM PDT 24
Finished May 09 12:34:04 PM PDT 24
Peak memory 208984 kb
Host smart-d57c43c8-6602-4fc6-b3d9-c473c1a38b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273716239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.3273716239
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.991890127
Short name T262
Test name
Test status
Simulation time 184063297 ps
CPU time 4.06 seconds
Started May 09 12:34:02 PM PDT 24
Finished May 09 12:34:15 PM PDT 24
Peak memory 208752 kb
Host smart-a2c581c0-316c-4662-b3b2-93258a89d64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991890127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.991890127
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.423114923
Short name T553
Test name
Test status
Simulation time 239086689 ps
CPU time 1.78 seconds
Started May 09 12:33:59 PM PDT 24
Finished May 09 12:34:09 PM PDT 24
Peak memory 214080 kb
Host smart-c3db6197-f41a-4886-a19d-52aa2ff13525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423114923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.423114923
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.2443098633
Short name T546
Test name
Test status
Simulation time 121453364 ps
CPU time 3.42 seconds
Started May 09 12:33:56 PM PDT 24
Finished May 09 12:34:12 PM PDT 24
Peak memory 219424 kb
Host smart-ab340f7d-5aaa-4b00-b76b-e0d246bb7437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443098633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.2443098633
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.387685397
Short name T752
Test name
Test status
Simulation time 353004248 ps
CPU time 3.46 seconds
Started May 09 12:33:38 PM PDT 24
Finished May 09 12:33:53 PM PDT 24
Peak memory 207980 kb
Host smart-0b020b5b-14d9-44bb-a965-5f0f0a1cb477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387685397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.387685397
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.877134441
Short name T908
Test name
Test status
Simulation time 188261965 ps
CPU time 5.24 seconds
Started May 09 12:33:50 PM PDT 24
Finished May 09 12:34:04 PM PDT 24
Peak memory 208396 kb
Host smart-a6ef76be-bc3c-4d00-a6e4-540bbd3a0eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877134441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.877134441
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.2827052604
Short name T824
Test name
Test status
Simulation time 143782149 ps
CPU time 2.63 seconds
Started May 09 12:33:40 PM PDT 24
Finished May 09 12:33:54 PM PDT 24
Peak memory 208332 kb
Host smart-1fa433ff-765b-42f3-8e65-f7f695210950
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827052604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.2827052604
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.3229293210
Short name T17
Test name
Test status
Simulation time 7348754279 ps
CPU time 61.47 seconds
Started May 09 12:34:02 PM PDT 24
Finished May 09 12:35:11 PM PDT 24
Peak memory 208540 kb
Host smart-3b0c315b-4f82-4b4a-8b45-ce9869ce929a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229293210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.3229293210
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.3898891261
Short name T331
Test name
Test status
Simulation time 417582815 ps
CPU time 6.11 seconds
Started May 09 12:34:03 PM PDT 24
Finished May 09 12:34:17 PM PDT 24
Peak memory 208528 kb
Host smart-a316f232-e674-4e6d-b064-fc851cf11eec
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898891261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.3898891261
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.3743470311
Short name T722
Test name
Test status
Simulation time 182483514 ps
CPU time 3.48 seconds
Started May 09 12:34:03 PM PDT 24
Finished May 09 12:34:15 PM PDT 24
Peak memory 209356 kb
Host smart-b3423f14-a162-4e6f-8f29-83c4d397023d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743470311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.3743470311
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.2728592551
Short name T539
Test name
Test status
Simulation time 489779313 ps
CPU time 5.68 seconds
Started May 09 12:33:39 PM PDT 24
Finished May 09 12:33:55 PM PDT 24
Peak memory 208372 kb
Host smart-24e561cc-19c7-4f2d-991c-458a7ceff7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728592551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.2728592551
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.1134667120
Short name T221
Test name
Test status
Simulation time 9343086114 ps
CPU time 91.13 seconds
Started May 09 12:33:43 PM PDT 24
Finished May 09 12:35:25 PM PDT 24
Peak memory 222508 kb
Host smart-7b859555-bfd9-45ba-9c8b-09641cb1b508
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134667120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.1134667120
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.1141623815
Short name T350
Test name
Test status
Simulation time 53990972 ps
CPU time 3.22 seconds
Started May 09 12:33:40 PM PDT 24
Finished May 09 12:33:55 PM PDT 24
Peak memory 208672 kb
Host smart-ed2bc580-0cab-4eb8-912e-fe6944a7fb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141623815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.1141623815
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.1374695759
Short name T508
Test name
Test status
Simulation time 196882973 ps
CPU time 3.95 seconds
Started May 09 12:34:01 PM PDT 24
Finished May 09 12:34:13 PM PDT 24
Peak memory 210612 kb
Host smart-db366cdd-65d4-49c1-9b59-ceec20864fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374695759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.1374695759
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.737170986
Short name T505
Test name
Test status
Simulation time 32016819 ps
CPU time 0.7 seconds
Started May 09 12:33:47 PM PDT 24
Finished May 09 12:33:57 PM PDT 24
Peak memory 205784 kb
Host smart-e6a9e205-c29c-409e-84d3-7069f88d7d98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737170986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.737170986
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.2119141348
Short name T276
Test name
Test status
Simulation time 103790121 ps
CPU time 3.82 seconds
Started May 09 12:33:47 PM PDT 24
Finished May 09 12:34:00 PM PDT 24
Peak memory 214460 kb
Host smart-4167e44a-b493-423d-8f3a-fa112650e0d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2119141348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.2119141348
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.3265792266
Short name T793
Test name
Test status
Simulation time 740589416 ps
CPU time 4.25 seconds
Started May 09 12:33:46 PM PDT 24
Finished May 09 12:34:00 PM PDT 24
Peak memory 209076 kb
Host smart-5acc2cec-dcba-41b1-a285-0533ad78cf5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265792266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.3265792266
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.2747076809
Short name T720
Test name
Test status
Simulation time 588630701 ps
CPU time 7.8 seconds
Started May 09 12:33:55 PM PDT 24
Finished May 09 12:34:09 PM PDT 24
Peak memory 214188 kb
Host smart-7308930c-ee89-4355-a502-836f203ae433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747076809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.2747076809
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.383556935
Short name T249
Test name
Test status
Simulation time 474079495 ps
CPU time 2.83 seconds
Started May 09 12:34:08 PM PDT 24
Finished May 09 12:34:20 PM PDT 24
Peak memory 211112 kb
Host smart-1ae8a8eb-308a-4c98-99fd-810cecd8c6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383556935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.383556935
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.3925254832
Short name T772
Test name
Test status
Simulation time 186816944 ps
CPU time 4.93 seconds
Started May 09 12:34:00 PM PDT 24
Finished May 09 12:34:13 PM PDT 24
Peak memory 220168 kb
Host smart-f3c44150-fbeb-4940-901e-d2ea8536c43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925254832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.3925254832
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.3049661014
Short name T822
Test name
Test status
Simulation time 656532373 ps
CPU time 3.38 seconds
Started May 09 12:33:40 PM PDT 24
Finished May 09 12:33:54 PM PDT 24
Peak memory 214060 kb
Host smart-df40511a-527f-4fa2-a2e3-4f6deab0a4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049661014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.3049661014
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.1608095526
Short name T607
Test name
Test status
Simulation time 133520874 ps
CPU time 4.53 seconds
Started May 09 12:34:03 PM PDT 24
Finished May 09 12:34:17 PM PDT 24
Peak memory 206512 kb
Host smart-9bcf6818-dc21-4c63-8514-045a8f6f1b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608095526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.1608095526
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.840351175
Short name T848
Test name
Test status
Simulation time 54199262 ps
CPU time 2.67 seconds
Started May 09 12:34:03 PM PDT 24
Finished May 09 12:34:15 PM PDT 24
Peak memory 207784 kb
Host smart-af9756d7-fe18-4452-9524-1c7d2dd7119a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840351175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.840351175
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.3334313127
Short name T544
Test name
Test status
Simulation time 48525368 ps
CPU time 2.46 seconds
Started May 09 12:33:42 PM PDT 24
Finished May 09 12:33:55 PM PDT 24
Peak memory 207796 kb
Host smart-65bcb114-2cd9-4ef7-bd67-08ec4b77e5b6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334313127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.3334313127
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.605034573
Short name T778
Test name
Test status
Simulation time 133346113 ps
CPU time 4.01 seconds
Started May 09 12:33:43 PM PDT 24
Finished May 09 12:33:57 PM PDT 24
Peak memory 208228 kb
Host smart-bec118d7-1563-42d3-bc9b-63e7ea18635a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605034573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.605034573
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.3278520091
Short name T261
Test name
Test status
Simulation time 954212131 ps
CPU time 3.68 seconds
Started May 09 12:33:56 PM PDT 24
Finished May 09 12:34:07 PM PDT 24
Peak memory 217996 kb
Host smart-59d97c1c-7051-49f9-ae0b-8049349ea953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278520091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.3278520091
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.2746357504
Short name T657
Test name
Test status
Simulation time 199544280 ps
CPU time 5.86 seconds
Started May 09 12:34:02 PM PDT 24
Finished May 09 12:34:16 PM PDT 24
Peak memory 206672 kb
Host smart-d093ce51-9a88-4d64-88f5-f5b561e3d2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746357504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.2746357504
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.2500714057
Short name T27
Test name
Test status
Simulation time 8511638097 ps
CPU time 149.67 seconds
Started May 09 12:33:40 PM PDT 24
Finished May 09 12:36:21 PM PDT 24
Peak memory 217516 kb
Host smart-07f34a32-a761-4a47-8c30-264cd41c0dfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500714057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.2500714057
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.1682437664
Short name T629
Test name
Test status
Simulation time 498498992 ps
CPU time 9.87 seconds
Started May 09 12:33:39 PM PDT 24
Finished May 09 12:34:00 PM PDT 24
Peak memory 222372 kb
Host smart-22553334-f49b-4419-841b-e2d46ef57cec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682437664 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.1682437664
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.2754574123
Short name T600
Test name
Test status
Simulation time 297106327 ps
CPU time 7.76 seconds
Started May 09 12:34:02 PM PDT 24
Finished May 09 12:34:19 PM PDT 24
Peak memory 208712 kb
Host smart-9a383289-5f3e-4265-a68e-1afc935c564e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754574123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.2754574123
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.1529228806
Short name T472
Test name
Test status
Simulation time 18897456 ps
CPU time 0.81 seconds
Started May 09 12:34:12 PM PDT 24
Finished May 09 12:34:21 PM PDT 24
Peak memory 205848 kb
Host smart-85d87a8b-f3b8-4376-a08e-389253e65a3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529228806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.1529228806
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.2994259767
Short name T215
Test name
Test status
Simulation time 395657456 ps
CPU time 11.68 seconds
Started May 09 12:34:05 PM PDT 24
Finished May 09 12:34:25 PM PDT 24
Peak memory 214424 kb
Host smart-fac84800-30fe-4b16-b88e-eacfa0110950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994259767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.2994259767
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.2444673053
Short name T532
Test name
Test status
Simulation time 57418382 ps
CPU time 2.55 seconds
Started May 09 12:34:03 PM PDT 24
Finished May 09 12:34:14 PM PDT 24
Peak memory 208644 kb
Host smart-f8fbae72-1cce-4edf-b617-7b44ea2acd45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444673053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.2444673053
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.476965971
Short name T231
Test name
Test status
Simulation time 29225574 ps
CPU time 1.73 seconds
Started May 09 12:34:05 PM PDT 24
Finished May 09 12:34:15 PM PDT 24
Peak memory 214156 kb
Host smart-7e9931b2-f80f-493e-92d3-bdcf31e604e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476965971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.476965971
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.2882148985
Short name T289
Test name
Test status
Simulation time 48649093 ps
CPU time 3.11 seconds
Started May 09 12:33:58 PM PDT 24
Finished May 09 12:34:09 PM PDT 24
Peak memory 214156 kb
Host smart-ce5f0df1-c9db-439a-9917-cbcc9522a671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882148985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.2882148985
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.2052796013
Short name T701
Test name
Test status
Simulation time 41218755 ps
CPU time 2.29 seconds
Started May 09 12:33:55 PM PDT 24
Finished May 09 12:34:04 PM PDT 24
Peak memory 215148 kb
Host smart-39690982-7ca3-4631-9828-ad1d32111d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052796013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.2052796013
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.651610236
Short name T873
Test name
Test status
Simulation time 2610370092 ps
CPU time 9.43 seconds
Started May 09 12:34:03 PM PDT 24
Finished May 09 12:34:20 PM PDT 24
Peak memory 214292 kb
Host smart-a490ecc7-09fe-4542-9bb1-c61241820071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651610236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.651610236
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.3501890245
Short name T656
Test name
Test status
Simulation time 798159002 ps
CPU time 7.26 seconds
Started May 09 12:33:40 PM PDT 24
Finished May 09 12:33:59 PM PDT 24
Peak memory 208288 kb
Host smart-104e7430-f04d-46f6-a1a1-1e5aea780c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501890245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.3501890245
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.415687678
Short name T526
Test name
Test status
Simulation time 66935533 ps
CPU time 2.9 seconds
Started May 09 12:34:19 PM PDT 24
Finished May 09 12:34:30 PM PDT 24
Peak memory 207812 kb
Host smart-cd800197-c06f-4e0f-8249-d8f895d5dc95
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415687678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.415687678
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.356692144
Short name T80
Test name
Test status
Simulation time 1068006479 ps
CPU time 3.69 seconds
Started May 09 12:34:03 PM PDT 24
Finished May 09 12:34:16 PM PDT 24
Peak memory 208508 kb
Host smart-86b9c7cf-df0d-4082-a56b-4760bdceb0e8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356692144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.356692144
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.3589048249
Short name T545
Test name
Test status
Simulation time 22944496 ps
CPU time 1.89 seconds
Started May 09 12:33:49 PM PDT 24
Finished May 09 12:33:59 PM PDT 24
Peak memory 206572 kb
Host smart-ee2b1fd8-eabd-45cd-834c-bd62dfd6f5d6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589048249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.3589048249
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.1663413688
Short name T199
Test name
Test status
Simulation time 162233079 ps
CPU time 2.59 seconds
Started May 09 12:34:03 PM PDT 24
Finished May 09 12:34:13 PM PDT 24
Peak memory 218384 kb
Host smart-95ec7ff2-04d4-4ca3-b519-6fd3ecd44173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663413688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.1663413688
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.3960337985
Short name T570
Test name
Test status
Simulation time 36817497 ps
CPU time 1.64 seconds
Started May 09 12:33:57 PM PDT 24
Finished May 09 12:34:05 PM PDT 24
Peak memory 206392 kb
Host smart-51832269-9705-42fd-9e33-86764595993e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960337985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.3960337985
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.2157381665
Short name T904
Test name
Test status
Simulation time 87351965 ps
CPU time 3.93 seconds
Started May 09 12:33:54 PM PDT 24
Finished May 09 12:34:05 PM PDT 24
Peak memory 214324 kb
Host smart-516834cf-7cb8-455a-9478-b237d090aa41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157381665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2157381665
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.2999933662
Short name T903
Test name
Test status
Simulation time 151989393 ps
CPU time 4.05 seconds
Started May 09 12:34:03 PM PDT 24
Finished May 09 12:34:16 PM PDT 24
Peak memory 210108 kb
Host smart-0f14f3d3-dfc2-4cb7-b692-86562ada4825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999933662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.2999933662
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.3937449890
Short name T618
Test name
Test status
Simulation time 25409454 ps
CPU time 0.88 seconds
Started May 09 12:34:06 PM PDT 24
Finished May 09 12:34:15 PM PDT 24
Peak memory 205968 kb
Host smart-708be9ef-04e0-4882-900f-28128ba5b0eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937449890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.3937449890
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.8315524
Short name T260
Test name
Test status
Simulation time 177657819 ps
CPU time 4.95 seconds
Started May 09 12:34:07 PM PDT 24
Finished May 09 12:34:20 PM PDT 24
Peak memory 214796 kb
Host smart-3f5d879e-51b8-416c-92ce-e98391b7412c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=8315524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.8315524
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.2704883220
Short name T212
Test name
Test status
Simulation time 230749648 ps
CPU time 2.85 seconds
Started May 09 12:33:55 PM PDT 24
Finished May 09 12:34:05 PM PDT 24
Peak memory 209740 kb
Host smart-97370082-402c-494c-aac2-0efe4b26351b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704883220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.2704883220
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.1637811356
Short name T705
Test name
Test status
Simulation time 79296842 ps
CPU time 2 seconds
Started May 09 12:33:46 PM PDT 24
Finished May 09 12:33:58 PM PDT 24
Peak memory 206656 kb
Host smart-b7868f8c-a6f9-4f48-a4fd-8e5cf3cb3da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637811356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.1637811356
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.199253624
Short name T305
Test name
Test status
Simulation time 36350798 ps
CPU time 2.82 seconds
Started May 09 12:33:56 PM PDT 24
Finished May 09 12:34:05 PM PDT 24
Peak memory 215704 kb
Host smart-0056dec2-d39b-4ed2-a2a6-702ef58f6a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199253624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.199253624
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.3231039393
Short name T738
Test name
Test status
Simulation time 30002850 ps
CPU time 1.7 seconds
Started May 09 12:34:02 PM PDT 24
Finished May 09 12:34:13 PM PDT 24
Peak memory 214100 kb
Host smart-aa0599f9-0733-4633-9b18-06707bc884e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231039393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.3231039393
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.813766897
Short name T172
Test name
Test status
Simulation time 197559273 ps
CPU time 3.92 seconds
Started May 09 12:33:52 PM PDT 24
Finished May 09 12:34:03 PM PDT 24
Peak memory 219924 kb
Host smart-a85c5643-c86b-4cde-80cb-d28f2c8cc971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813766897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.813766897
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.1368860274
Short name T550
Test name
Test status
Simulation time 1879738760 ps
CPU time 56.3 seconds
Started May 09 12:33:54 PM PDT 24
Finished May 09 12:34:57 PM PDT 24
Peak memory 209004 kb
Host smart-3bc29980-73f2-4195-87ed-00885b503327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368860274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.1368860274
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.3771618198
Short name T717
Test name
Test status
Simulation time 212259460 ps
CPU time 4.37 seconds
Started May 09 12:33:49 PM PDT 24
Finished May 09 12:34:02 PM PDT 24
Peak memory 206712 kb
Host smart-2dd3a13d-bba9-45e5-be13-60464aedbe7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771618198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.3771618198
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.3824348008
Short name T237
Test name
Test status
Simulation time 550017835 ps
CPU time 14.29 seconds
Started May 09 12:34:02 PM PDT 24
Finished May 09 12:34:24 PM PDT 24
Peak memory 208152 kb
Host smart-e9c158df-3f33-470e-8dfc-1a3ef368953a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824348008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.3824348008
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.3920937577
Short name T909
Test name
Test status
Simulation time 468503239 ps
CPU time 6.19 seconds
Started May 09 12:34:26 PM PDT 24
Finished May 09 12:34:38 PM PDT 24
Peak memory 207660 kb
Host smart-92e5288c-f560-4e81-a835-044dc827534a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920937577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.3920937577
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.3765329634
Short name T608
Test name
Test status
Simulation time 218987810 ps
CPU time 2.78 seconds
Started May 09 12:34:02 PM PDT 24
Finished May 09 12:34:12 PM PDT 24
Peak memory 206684 kb
Host smart-388e5f32-ef85-4ba0-9e0f-5559f830a56c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765329634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.3765329634
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.3165751092
Short name T658
Test name
Test status
Simulation time 132984782 ps
CPU time 1.95 seconds
Started May 09 12:33:59 PM PDT 24
Finished May 09 12:34:08 PM PDT 24
Peak memory 207988 kb
Host smart-e231f143-1880-4369-8a32-681a7eaad7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165751092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.3165751092
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.3883205318
Short name T897
Test name
Test status
Simulation time 78667228 ps
CPU time 2.11 seconds
Started May 09 12:33:43 PM PDT 24
Finished May 09 12:33:55 PM PDT 24
Peak memory 208436 kb
Host smart-34a52fce-7ed9-46d6-9737-8bc46760dae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883205318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.3883205318
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.2071533071
Short name T514
Test name
Test status
Simulation time 604958836 ps
CPU time 15.61 seconds
Started May 09 12:33:50 PM PDT 24
Finished May 09 12:34:14 PM PDT 24
Peak memory 214072 kb
Host smart-ee0b7133-2d44-450d-92e1-0487919aa681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071533071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.2071533071
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.3733167317
Short name T153
Test name
Test status
Simulation time 101942835 ps
CPU time 1.91 seconds
Started May 09 12:34:06 PM PDT 24
Finished May 09 12:34:16 PM PDT 24
Peak memory 209888 kb
Host smart-4bd1bf99-4105-4be5-9609-1ff217201aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733167317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.3733167317
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.4257359097
Short name T495
Test name
Test status
Simulation time 12407209 ps
CPU time 0.74 seconds
Started May 09 12:34:05 PM PDT 24
Finished May 09 12:34:15 PM PDT 24
Peak memory 205876 kb
Host smart-dfc1159e-8f3e-46b7-b394-0563f272595c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257359097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.4257359097
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.1790888629
Short name T28
Test name
Test status
Simulation time 144387250 ps
CPU time 2.97 seconds
Started May 09 12:34:06 PM PDT 24
Finished May 09 12:34:17 PM PDT 24
Peak memory 221488 kb
Host smart-fb8a3f2c-33f1-4696-9c87-07c470c972ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790888629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.1790888629
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.2061263737
Short name T301
Test name
Test status
Simulation time 520873770 ps
CPU time 5.25 seconds
Started May 09 12:33:58 PM PDT 24
Finished May 09 12:34:11 PM PDT 24
Peak memory 214208 kb
Host smart-ee06930a-67bd-4660-930b-ca72d8c94ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061263737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.2061263737
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.348967474
Short name T240
Test name
Test status
Simulation time 40104018 ps
CPU time 2.6 seconds
Started May 09 12:33:59 PM PDT 24
Finished May 09 12:34:09 PM PDT 24
Peak memory 208396 kb
Host smart-2243eddb-cc2e-4b32-b981-556607869afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348967474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.348967474
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.2250824027
Short name T792
Test name
Test status
Simulation time 111195612 ps
CPU time 3.5 seconds
Started May 09 12:33:51 PM PDT 24
Finished May 09 12:34:02 PM PDT 24
Peak memory 222148 kb
Host smart-ee7c7f74-f973-4114-bc00-f61a11794170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250824027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.2250824027
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.2384846206
Short name T653
Test name
Test status
Simulation time 693638977 ps
CPU time 4.61 seconds
Started May 09 12:34:03 PM PDT 24
Finished May 09 12:34:16 PM PDT 24
Peak memory 214528 kb
Host smart-640c0d0a-31b9-435c-9cf6-6f160a15fe5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384846206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.2384846206
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.1645422264
Short name T476
Test name
Test status
Simulation time 70718669 ps
CPU time 3.02 seconds
Started May 09 12:34:07 PM PDT 24
Finished May 09 12:34:19 PM PDT 24
Peak memory 214156 kb
Host smart-5e6e4245-5574-4268-8536-f42c58376c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645422264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.1645422264
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.4216733628
Short name T891
Test name
Test status
Simulation time 202087500 ps
CPU time 2.59 seconds
Started May 09 12:34:17 PM PDT 24
Finished May 09 12:34:28 PM PDT 24
Peak memory 206564 kb
Host smart-939c1e6a-ea4a-48cb-ae33-1786dbb73d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216733628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.4216733628
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.1615990533
Short name T851
Test name
Test status
Simulation time 121926189 ps
CPU time 2.37 seconds
Started May 09 12:33:59 PM PDT 24
Finished May 09 12:34:09 PM PDT 24
Peak memory 207264 kb
Host smart-588c59ff-e166-407f-982e-f4257acb3548
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615990533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.1615990533
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.2576424179
Short name T852
Test name
Test status
Simulation time 25397415 ps
CPU time 1.86 seconds
Started May 09 12:33:59 PM PDT 24
Finished May 09 12:34:09 PM PDT 24
Peak memory 206792 kb
Host smart-c4716394-2fab-420c-a63b-fe57ab0f5d68
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576424179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.2576424179
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.1129086020
Short name T636
Test name
Test status
Simulation time 195407419 ps
CPU time 5.67 seconds
Started May 09 12:34:06 PM PDT 24
Finished May 09 12:34:20 PM PDT 24
Peak memory 207876 kb
Host smart-b3ee019f-179a-4af6-b27a-8911711e7f6d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129086020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.1129086020
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.3782074960
Short name T850
Test name
Test status
Simulation time 65193709 ps
CPU time 3.2 seconds
Started May 09 12:34:02 PM PDT 24
Finished May 09 12:34:14 PM PDT 24
Peak memory 214128 kb
Host smart-80265e09-1804-4bca-9f19-42796d4d6638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782074960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.3782074960
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.3897487401
Short name T838
Test name
Test status
Simulation time 1043526545 ps
CPU time 5.47 seconds
Started May 09 12:33:45 PM PDT 24
Finished May 09 12:34:01 PM PDT 24
Peak memory 206596 kb
Host smart-5da10a18-b75c-4b47-8678-8f2df0cd0e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897487401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.3897487401
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.3932813332
Short name T291
Test name
Test status
Simulation time 3861275725 ps
CPU time 32.98 seconds
Started May 09 12:34:03 PM PDT 24
Finished May 09 12:34:45 PM PDT 24
Peak memory 220600 kb
Host smart-e43f276b-b564-460a-b171-87764ef3c9b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932813332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.3932813332
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.3903369835
Short name T288
Test name
Test status
Simulation time 161561871 ps
CPU time 4.26 seconds
Started May 09 12:34:07 PM PDT 24
Finished May 09 12:34:20 PM PDT 24
Peak memory 222548 kb
Host smart-da43186c-6818-4b6a-b4f9-57d266a21152
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903369835 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.3903369835
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.294027250
Short name T666
Test name
Test status
Simulation time 103511906 ps
CPU time 4.18 seconds
Started May 09 12:33:56 PM PDT 24
Finished May 09 12:34:08 PM PDT 24
Peak memory 210356 kb
Host smart-bef1cd26-3732-4fac-acf1-6c11979acaf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294027250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.294027250
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.2352965178
Short name T98
Test name
Test status
Simulation time 59347087 ps
CPU time 2 seconds
Started May 09 12:33:56 PM PDT 24
Finished May 09 12:34:05 PM PDT 24
Peak memory 209984 kb
Host smart-c9fdf762-5d81-49ff-b23a-3519ba2dbcf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352965178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.2352965178
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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