Summary for Variable op_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
5 |
1 |
4 |
80.00 |
Automatically Generated Bins for op_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
auto[OpDisable] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[OpAdvance] |
41 |
1 |
|
|
T4 |
1 |
|
T7 |
1 |
|
T44 |
1 |
auto[OpGenId] |
10 |
1 |
|
|
T56 |
1 |
|
T189 |
1 |
|
T190 |
1 |
auto[OpGenSwOut] |
17 |
1 |
|
|
T29 |
1 |
|
T58 |
1 |
|
T45 |
1 |
auto[OpGenHwOut] |
21 |
1 |
|
|
T31 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable state_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
7 |
0 |
7 |
100.00 |
Automatically Generated Bins for state_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[StReset] |
1758 |
1 |
|
|
T13 |
1 |
|
T9 |
90 |
|
T4 |
1 |
auto[StInit] |
84 |
1 |
|
|
T31 |
1 |
|
T51 |
1 |
|
T45 |
2 |
auto[StCreatorRootKey] |
63 |
1 |
|
|
T29 |
1 |
|
T42 |
1 |
|
T52 |
1 |
auto[StOwnerIntKey] |
36 |
1 |
|
|
T29 |
2 |
|
T4 |
1 |
|
T55 |
1 |
auto[StOwnerKey] |
40 |
1 |
|
|
T12 |
1 |
|
T16 |
1 |
|
T37 |
1 |
auto[StDisabled] |
495 |
1 |
|
|
T29 |
2 |
|
T4 |
15 |
|
T45 |
13 |
auto[StInvalid] |
50 |
1 |
|
|
T17 |
1 |
|
T38 |
1 |
|
T47 |
1 |
Summary for Variable wip_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wip_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
3523 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
auto[1] |
89 |
1 |
|
|
T31 |
1 |
|
T29 |
1 |
|
T4 |
2 |
Summary for Cross state_x_wip_cross
Samples crossed: state_cp wip_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
14 |
1 |
13 |
92.86 |
1 |
Automatically Generated Cross Bins for state_x_wip_cross
Uncovered bins
state_cp | wip_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[StInvalid]] |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
state_cp | wip_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[StReset] |
auto[0] |
1754 |
1 |
|
|
T13 |
1 |
|
T9 |
90 |
|
T4 |
1 |
auto[StReset] |
auto[1] |
4 |
1 |
|
|
T7 |
1 |
|
T33 |
1 |
|
T30 |
1 |
auto[StInit] |
auto[0] |
40 |
1 |
|
|
T51 |
1 |
|
T50 |
1 |
|
T32 |
1 |
auto[StInit] |
auto[1] |
44 |
1 |
|
|
T31 |
1 |
|
T45 |
2 |
|
T5 |
1 |
auto[StCreatorRootKey] |
auto[0] |
49 |
1 |
|
|
T42 |
1 |
|
T52 |
1 |
|
T191 |
1 |
auto[StCreatorRootKey] |
auto[1] |
14 |
1 |
|
|
T29 |
1 |
|
T53 |
1 |
|
T20 |
1 |
auto[StOwnerIntKey] |
auto[0] |
28 |
1 |
|
|
T29 |
2 |
|
T55 |
1 |
|
T6 |
1 |
auto[StOwnerIntKey] |
auto[1] |
8 |
1 |
|
|
T4 |
1 |
|
T44 |
1 |
|
T56 |
1 |
auto[StOwnerKey] |
auto[0] |
29 |
1 |
|
|
T12 |
1 |
|
T16 |
1 |
|
T37 |
1 |
auto[StOwnerKey] |
auto[1] |
11 |
1 |
|
|
T58 |
1 |
|
T59 |
1 |
|
T192 |
1 |
auto[StDisabled] |
auto[0] |
487 |
1 |
|
|
T29 |
2 |
|
T4 |
14 |
|
T45 |
13 |
auto[StDisabled] |
auto[1] |
8 |
1 |
|
|
T4 |
1 |
|
T64 |
1 |
|
T193 |
1 |
auto[StInvalid] |
auto[0] |
50 |
1 |
|
|
T17 |
1 |
|
T38 |
1 |
|
T47 |
1 |
Summary for Cross state_x_op_cross
Samples crossed: state_cp op_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
35 |
14 |
21 |
60.00 |
14 |
Automatically Generated Cross Bins for state_x_op_cross
Element holes
state_cp | op_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[StInvalid]] |
* |
-- |
-- |
5 |
|
Uncovered bins
state_cp | op_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[StReset]] |
[auto[OpGenId] , auto[OpGenSwOut]] |
-- |
-- |
2 |
|
[auto[StReset]] |
[auto[OpDisable]] |
0 |
1 |
1 |
|
[auto[StInit] , auto[StCreatorRootKey]] |
[auto[OpDisable]] |
-- |
-- |
2 |
|
[auto[StOwnerIntKey]] |
[auto[OpGenSwOut]] |
0 |
1 |
1 |
|
[auto[StOwnerIntKey]] |
[auto[OpDisable]] |
0 |
1 |
1 |
|
[auto[StOwnerKey] , auto[StDisabled]] |
[auto[OpDisable]] |
-- |
-- |
2 |
|
Covered bins
state_cp | op_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[StReset] |
auto[OpAdvance] |
3 |
1 |
|
|
T7 |
1 |
|
T33 |
1 |
|
T30 |
1 |
auto[StReset] |
auto[OpGenHwOut] |
1 |
1 |
|
|
T158 |
1 |
|
- |
- |
|
- |
- |
auto[StInit] |
auto[OpAdvance] |
19 |
1 |
|
|
T45 |
1 |
|
T192 |
1 |
|
T194 |
1 |
auto[StInit] |
auto[OpGenId] |
3 |
1 |
|
|
T189 |
1 |
|
T195 |
1 |
|
T196 |
1 |
auto[StInit] |
auto[OpGenSwOut] |
11 |
1 |
|
|
T45 |
1 |
|
T197 |
1 |
|
T76 |
2 |
auto[StInit] |
auto[OpGenHwOut] |
11 |
1 |
|
|
T31 |
1 |
|
T5 |
1 |
|
T76 |
1 |
auto[StCreatorRootKey] |
auto[OpAdvance] |
7 |
1 |
|
|
T53 |
1 |
|
T198 |
1 |
|
T180 |
1 |
auto[StCreatorRootKey] |
auto[OpGenId] |
2 |
1 |
|
|
T199 |
1 |
|
T200 |
1 |
|
- |
- |
auto[StCreatorRootKey] |
auto[OpGenSwOut] |
2 |
1 |
|
|
T29 |
1 |
|
T20 |
1 |
|
- |
- |
auto[StCreatorRootKey] |
auto[OpGenHwOut] |
3 |
1 |
|
|
T201 |
1 |
|
T202 |
1 |
|
T203 |
1 |
auto[StOwnerIntKey] |
auto[OpAdvance] |
4 |
1 |
|
|
T4 |
1 |
|
T44 |
1 |
|
T65 |
1 |
auto[StOwnerIntKey] |
auto[OpGenId] |
2 |
1 |
|
|
T56 |
1 |
|
T204 |
1 |
|
- |
- |
auto[StOwnerIntKey] |
auto[OpGenHwOut] |
2 |
1 |
|
|
T6 |
1 |
|
T205 |
1 |
|
- |
- |
auto[StOwnerKey] |
auto[OpAdvance] |
6 |
1 |
|
|
T192 |
1 |
|
T206 |
1 |
|
T75 |
1 |
auto[StOwnerKey] |
auto[OpGenId] |
1 |
1 |
|
|
T207 |
1 |
|
- |
- |
|
- |
- |
auto[StOwnerKey] |
auto[OpGenSwOut] |
2 |
1 |
|
|
T58 |
1 |
|
T59 |
1 |
|
- |
- |
auto[StOwnerKey] |
auto[OpGenHwOut] |
2 |
1 |
|
|
T208 |
1 |
|
T209 |
1 |
|
- |
- |
auto[StDisabled] |
auto[OpAdvance] |
2 |
1 |
|
|
T210 |
1 |
|
T211 |
1 |
|
- |
- |
auto[StDisabled] |
auto[OpGenId] |
2 |
1 |
|
|
T190 |
1 |
|
T212 |
1 |
|
- |
- |
auto[StDisabled] |
auto[OpGenSwOut] |
2 |
1 |
|
|
T64 |
1 |
|
T193 |
1 |
|
- |
- |
auto[StDisabled] |
auto[OpGenHwOut] |
2 |
1 |
|
|
T4 |
1 |
|
T166 |
1 |
|
- |
- |