Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11129

1

T1

4

T2

5

T3

7

auto[Attestation]

7946

1

T1

3

T2

6

T3

4

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2918	1			T1	3		T2	1		T3	2
auto[Aes]	3292	1			T2	2		T3	1		T12	3
auto[Kmac]	3362	1			T2	1		T12	4		T15	6
auto[Otbn]	3430	1			T1	2		T2	4		T3	6

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7938	1			T1	2		T2	4		T3	8
auto[OpGenId]	6073	1			T1	2		T2	3		T3	2
auto[OpGenSwOut]	6044	1			T1	1		T2	1		T3	5
auto[OpGenHwOut]	6958	1			T1	4		T2	7		T3	4
auto[OpDisable]	156	1			T1	1		T4	3		T46	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

11140

1

T1

7

T2

13

T3

8

auto[OpDoneFail]

16029

1

T1

3

T2

2

T3

11

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6279	1			T1	1		T2	1		T3	4
auto[StInit]	3803	1			T1	2		T2	3		T3	2
auto[StCreatorRootKey]	3341	1			T1	5		T2	2		T3	2
auto[StOwnerIntKey]	2965	1			T2	2		T3	2		T12	5
auto[StOwnerKey]	2572	1			T2	7		T3	2		T12	4
auto[StDisabled]	8209	1			T1	2		T3	7		T18	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	306	1			T3	1		T15	1		T28	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	99	1			T24	1		T45	1		T184	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	92	1			T42	1		T45	2		T50	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	72	1			T28	1		T4	1		T45	3
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	58	1			T12	1		T28	1		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	234	1			T1	1		T29	1		T4	7
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	305	1			T28	1		T31	2		T29	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	85	1			T16	1		T4	5		T79	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	82	1			T4	3		T45	1		T50	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	79	1			T28	1		T4	4		T108	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	51	1			T15	1		T4	1		T50	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	217	1			T28	1		T4	6		T45	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	300	1			T15	2		T28	1		T29	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	113	1			T28	1		T29	1		T4	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	92	1			T15	1		T29	1		T42	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	76	1			T12	1		T15	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	62	1			T28	1		T4	2		T45	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	281	1			T29	2		T4	7		T80	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	330	1			T31	4		T83	1		T4	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	115	1			T3	1		T4	2		T46	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	86	1			T12	1		T81	1		T45	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	86	1			T2	1		T37	1		T29	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	66	1			T3	1		T45	1		T108	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	215	1			T3	1		T29	1		T4	8
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	108	1			T38	1		T4	4		T45	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	92	1			T15	1		T4	1		T52	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	80	1			T38	1		T28	1		T4	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	103	1			T4	2		T46	1		T45	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	68	1			T16	1		T4	1		T50	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	216	1			T29	3		T4	1		T45	4
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	83	1			T38	3		T29	1		T4	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	81	1			T29	1		T42	1		T4	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	90	1			T29	1		T83	1		T4	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	80	1			T29	1		T4	2		T50	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	70	1			T37	1		T4	2		T45	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	223	1			T3	1		T28	1		T4	5
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	77	1			T38	1		T45	4		T50	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	80	1			T4	3		T24	3		T108	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	81	1			T29	1		T4	1		T185	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	81	1			T29	1		T4	1		T46	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	62	1			T12	1		T37	2		T29	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	214	1			T28	1		T4	5		T46	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	89	1			T38	1		T45	6		T50	4
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	110	1			T38	1		T4	1		T55	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	80	1			T38	1		T4	3		T119	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	73	1			T28	1		T4	2		T45	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	81	1			T28	1		T81	1		T45	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	220	1			T4	5		T186	1		T45	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	279	1			T37	1		T28	3		T83	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	109	1			T31	1		T79	1		T81	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	84	1			T12	1		T29	1		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	76	1			T29	1		T58	2		T45	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	66	1			T4	2		T50	3		T70	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	184	1			T1	1		T3	1		T29	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	418	1			T38	1		T28	1		T42	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	110	1			T12	1		T29	1		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	108	1			T15	1		T16	1		T29	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	97	1			T29	1		T71	1		T45	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	81	1			T2	2		T12	2		T4	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	271	1			T4	4		T45	1		T108	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	430	1			T29	1		T83	1		T84	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	114	1			T29	1		T4	1		T24	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	113	1			T29	1		T86	1		T71	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	94	1			T12	1		T15	1		T187	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	94	1			T84	1		T86	1		T4	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	291	1			T84	2		T86	3		T4	4
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	374	1			T3	1		T15	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	135	1			T18	1		T29	1		T85	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	109	1			T1	1		T85	1		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	95	1			T15	1		T85	1		T4	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	95	1			T85	1		T4	2		T188	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	290	1			T18	1		T29	1		T83	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	67	1			T38	1		T45	4		T50	5
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	91	1			T1	1		T4	1		T52	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	92	1			T42	1		T4	1		T81	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	82	1			T28	1		T46	1		T186	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	59	1			T2	1		T29	1		T4	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	201	1			T4	2		T80	2		T186	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	62	1			T38	1		T4	2		T45	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	110	1			T4	4		T50	1		T43	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	99	1			T16	1		T4	2		T55	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	95	1			T15	1		T45	3		T50	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	107	1			T16	1		T28	1		T79	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	288	1			T4	3		T80	2		T46	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	45	1			T38	2		T4	1		T45	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	110	1			T12	1		T31	1		T84	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	121	1			T84	1		T80	1		T81	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	98	1			T15	1		T16	1		T84	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	85	1			T2	1		T16	1		T29	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	248	1			T84	2		T86	1		T4	6
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	60	1			T38	1		T29	1		T45	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	119	1			T4	1		T55	1		T58	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	112	1			T1	1		T2	1		T3	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	103	1			T3	1		T18	1		T55	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	95	1			T2	2		T15	2		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	292	1			T18	3		T4	9		T81	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	202	1			T12	1		T28	1		T42	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	659	1			T1	1		T3	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	191	1			T15	1		T4	8		T45	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	628	1			T16	1		T28	3		T31	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	220	1			T12	1		T15	2		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	704	1			T15	2		T28	2		T29	4
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	227	1			T2	1		T3	1		T12	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	671	1			T3	2		T31	4		T29	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	236	1			T16	1		T38	1		T28	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	431	1			T15	1		T38	1		T29	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	222	1			T37	1		T29	2		T83	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	405	1			T3	1		T38	3		T28	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	209	1			T12	1		T37	2		T29	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	386	1			T38	1		T28	1		T4	8
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	213	1			T28	2		T4	5		T81	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	440	1			T38	3		T4	6		T55	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	200	1			T12	1		T29	2		T4	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	598	1			T1	1		T3	1		T37	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	271	1			T2	2		T12	2		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	814	1			T12	1		T38	1		T28	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	282	1			T12	1		T15	1		T29	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	854	1			T29	2		T83	1		T84	5
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	276	1			T1	1		T15	1		T85	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	822	1			T3	1		T15	1		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	215	1			T2	1		T29	1		T42	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	377	1			T1	1		T38	1		T28	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	285	1			T15	1		T16	2		T28	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	476	1			T38	1		T4	9		T80	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	291	1			T2	1		T15	1		T16	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	416	1			T12	1		T38	2		T31	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	293	1			T1	1		T2	3		T3	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	488	1			T18	3		T38	1		T29	1