Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33152

1

T1

12

T2

17

T3

22

auto[1]

328

1

T80

6

T108

8

T117

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	33162	1			T1	12		T2	17		T3	22
auto[134217728:268435455]	14	1			T118	2		T120	2		T264	1
auto[268435456:402653183]	11	1			T286	1		T215	1		T377	1
auto[402653184:536870911]	5	1			T121	2		T389	1		T320	1
auto[536870912:671088639]	10	1			T119	1		T264	1		T390	2
auto[671088640:805306367]	8	1			T118	2		T264	1		T332	1
auto[805306368:939524095]	9	1			T314	1		T391	1		T392	1
auto[939524096:1073741823]	12	1			T118	1		T286	1		T213	1
auto[1073741824:1207959551]	11	1			T108	1		T120	1		T242	1
auto[1207959552:1342177279]	13	1			T119	1		T120	3		T121	1
auto[1342177280:1476395007]	14	1			T108	1		T118	1		T119	1
auto[1476395008:1610612735]	10	1			T117	1		T118	1		T264	1
auto[1610612736:1744830463]	7	1			T264	1		T214	1		T393	1
auto[1744830464:1879048191]	11	1			T119	1		T120	1		T393	1
auto[1879048192:2013265919]	8	1			T120	3		T393	1		T314	1
auto[2013265920:2147483647]	13	1			T121	1		T242	1		T213	1
auto[2147483648:2281701375]	18	1			T108	1		T118	1		T120	1
auto[2281701376:2415919103]	9	1			T108	1		T264	1		T394	1
auto[2415919104:2550136831]	11	1			T108	1		T118	1		T120	2
auto[2550136832:2684354559]	11	1			T80	2		T118	1		T120	1
auto[2684354560:2818572287]	3	1			T80	1		T390	1		T235	1
auto[2818572288:2952790015]	5	1			T108	1		T120	1		T121	1
auto[2952790016:3087007743]	6	1			T213	1		T215	1		T378	1
auto[3087007744:3221225471]	21	1			T108	1		T242	1		T286	1
auto[3221225472:3355443199]	15	1			T118	2		T120	1		T121	1
auto[3355443200:3489660927]	4	1			T213	1		T327	1		T215	1
auto[3489660928:3623878655]	8	1			T108	1		T242	1		T286	1
auto[3623878656:3758096383]	9	1			T119	1		T121	1		T332	1
auto[3758096384:3892314111]	13	1			T80	1		T242	1		T390	1
auto[3892314112:4026531839]	11	1			T80	1		T119	1		T120	1
auto[4026531840:4160749567]	10	1			T118	1		T120	1		T121	1
auto[4160749568:4294967295]	8	1			T119	1		T121	1		T215	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	33152	1			T1	12		T2	17		T3	22
auto[0:134217727]	auto[1]	10	1			T80	1		T118	2		T264	1
auto[134217728:268435455]	auto[1]	14	1			T118	2		T120	2		T264	1
auto[268435456:402653183]	auto[1]	11	1			T286	1		T215	1		T377	1
auto[402653184:536870911]	auto[1]	5	1			T121	2		T389	1		T320	1
auto[536870912:671088639]	auto[1]	10	1			T119	1		T264	1		T390	2
auto[671088640:805306367]	auto[1]	8	1			T118	2		T264	1		T332	1
auto[805306368:939524095]	auto[1]	9	1			T314	1		T391	1		T392	1
auto[939524096:1073741823]	auto[1]	12	1			T118	1		T286	1		T213	1
auto[1073741824:1207959551]	auto[1]	11	1			T108	1		T120	1		T242	1
auto[1207959552:1342177279]	auto[1]	13	1			T119	1		T120	3		T121	1
auto[1342177280:1476395007]	auto[1]	14	1			T108	1		T118	1		T119	1
auto[1476395008:1610612735]	auto[1]	10	1			T117	1		T118	1		T264	1
auto[1610612736:1744830463]	auto[1]	7	1			T264	1		T214	1		T393	1
auto[1744830464:1879048191]	auto[1]	11	1			T119	1		T120	1		T393	1
auto[1879048192:2013265919]	auto[1]	8	1			T120	3		T393	1		T314	1
auto[2013265920:2147483647]	auto[1]	13	1			T121	1		T242	1		T213	1
auto[2147483648:2281701375]	auto[1]	18	1			T108	1		T118	1		T120	1
auto[2281701376:2415919103]	auto[1]	9	1			T108	1		T264	1		T394	1
auto[2415919104:2550136831]	auto[1]	11	1			T108	1		T118	1		T120	2
auto[2550136832:2684354559]	auto[1]	11	1			T80	2		T118	1		T120	1
auto[2684354560:2818572287]	auto[1]	3	1			T80	1		T390	1		T235	1
auto[2818572288:2952790015]	auto[1]	5	1			T108	1		T120	1		T121	1
auto[2952790016:3087007743]	auto[1]	6	1			T213	1		T215	1		T378	1
auto[3087007744:3221225471]	auto[1]	21	1			T108	1		T242	1		T286	1
auto[3221225472:3355443199]	auto[1]	15	1			T118	2		T120	1		T121	1
auto[3355443200:3489660927]	auto[1]	4	1			T213	1		T327	1		T215	1
auto[3489660928:3623878655]	auto[1]	8	1			T108	1		T242	1		T286	1
auto[3623878656:3758096383]	auto[1]	9	1			T119	1		T121	1		T332	1
auto[3758096384:3892314111]	auto[1]	13	1			T80	1		T242	1		T390	1
auto[3892314112:4026531839]	auto[1]	11	1			T80	1		T119	1		T120	1
auto[4026531840:4160749567]	auto[1]	10	1			T118	1		T120	1		T121	1
auto[4160749568:4294967295]	auto[1]	8	1			T119	1		T121	1		T215	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1523

1

T2

1

T15

5

T16

2

auto[1]

1808

1

T1

3

T2

2

T15

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	114	1			T17	1		T38	1		T4	1
auto[134217728:268435455]	108	1			T15	1		T80	1		T81	1
auto[268435456:402653183]	99	1			T4	2		T81	1		T303	1
auto[402653184:536870911]	97	1			T38	1		T46	1		T48	1
auto[536870912:671088639]	121	1			T15	1		T28	1		T4	1
auto[671088640:805306367]	88	1			T15	1		T4	2		T255	1
auto[805306368:939524095]	105	1			T15	1		T16	2		T4	3
auto[939524096:1073741823]	101	1			T1	2		T4	1		T45	1
auto[1073741824:1207959551]	105	1			T2	1		T28	1		T47	1
auto[1207959552:1342177279]	81	1			T38	1		T4	4		T79	1
auto[1342177280:1476395007]	109	1			T2	1		T50	1		T60	1
auto[1476395008:1610612735]	110	1			T15	1		T28	1		T29	2
auto[1610612736:1744830463]	101	1			T45	1		T108	1		T48	1
auto[1744830464:1879048191]	102	1			T2	1		T81	1		T45	1
auto[1879048192:2013265919]	110	1			T38	1		T28	1		T4	2
auto[2013265920:2147483647]	105	1			T17	1		T4	1		T58	1
auto[2147483648:2281701375]	94	1			T38	1		T47	1		T4	2
auto[2281701376:2415919103]	105	1			T38	1		T28	1		T4	5
auto[2415919104:2550136831]	123	1			T16	1		T17	1		T29	1
auto[2550136832:2684354559]	115	1			T29	1		T4	3		T81	1
auto[2684354560:2818572287]	107	1			T28	1		T31	1		T4	1
auto[2818572288:2952790015]	104	1			T1	1		T17	1		T80	1
auto[2952790016:3087007743]	93	1			T16	1		T4	3		T45	2
auto[3087007744:3221225471]	107	1			T4	1		T80	2		T24	1
auto[3221225472:3355443199]	123	1			T28	1		T29	1		T4	1
auto[3355443200:3489660927]	105	1			T15	2		T38	1		T28	1
auto[3489660928:3623878655]	86	1			T17	1		T4	2		T79	1
auto[3623878656:3758096383]	90	1			T4	3		T45	2		T50	1
auto[3758096384:3892314111]	105	1			T31	1		T79	1		T7	1
auto[3892314112:4026531839]	108	1			T47	1		T4	3		T44	1
auto[4026531840:4160749567]	101	1			T28	1		T29	1		T4	1
auto[4160749568:4294967295]	109	1			T47	1		T4	1		T55	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	54	1			T17	1		T38	1		T45	1
auto[0:134217727]	auto[1]	60	1			T4	1		T50	2		T358	1
auto[134217728:268435455]	auto[0]	51	1			T15	1		T80	1		T108	1
auto[134217728:268435455]	auto[1]	57	1			T81	1		T303	1		T59	1
auto[268435456:402653183]	auto[0]	40	1			T4	1		T81	1		T303	1
auto[268435456:402653183]	auto[1]	59	1			T4	1		T353	1		T61	1
auto[402653184:536870911]	auto[0]	33	1			T113	1		T192	3		T225	1
auto[402653184:536870911]	auto[1]	64	1			T38	1		T46	1		T48	1
auto[536870912:671088639]	auto[0]	65	1			T15	1		T28	1		T4	1
auto[536870912:671088639]	auto[1]	56	1			T45	1		T50	2		T117	1
auto[671088640:805306367]	auto[0]	45	1			T4	2		T255	1		T230	1
auto[671088640:805306367]	auto[1]	43	1			T15	1		T59	1		T70	1
auto[805306368:939524095]	auto[0]	53	1			T15	1		T16	1		T4	2
auto[805306368:939524095]	auto[1]	52	1			T16	1		T4	1		T44	1
auto[939524096:1073741823]	auto[0]	44	1			T45	1		T172	1		T192	2
auto[939524096:1073741823]	auto[1]	57	1			T1	2		T4	1		T48	1
auto[1073741824:1207959551]	auto[0]	49	1			T28	1		T47	1		T29	1
auto[1073741824:1207959551]	auto[1]	56	1			T2	1		T29	1		T4	2
auto[1207959552:1342177279]	auto[0]	45	1			T38	1		T4	2		T79	1
auto[1207959552:1342177279]	auto[1]	36	1			T4	2		T44	1		T186	1
auto[1342177280:1476395007]	auto[0]	54	1			T2	1		T241	1		T70	1
auto[1342177280:1476395007]	auto[1]	55	1			T50	1		T60	1		T230	1
auto[1476395008:1610612735]	auto[0]	42	1			T15	1		T28	1		T29	1
auto[1476395008:1610612735]	auto[1]	68	1			T29	1		T4	1		T80	1
auto[1610612736:1744830463]	auto[0]	42	1			T45	1		T48	1		T129	1
auto[1610612736:1744830463]	auto[1]	59	1			T108	1		T50	1		T49	1
auto[1744830464:1879048191]	auto[0]	44	1			T50	1		T379	1		T113	1
auto[1744830464:1879048191]	auto[1]	58	1			T2	1		T81	1		T45	1
auto[1879048192:2013265919]	auto[0]	49	1			T28	1		T45	1		T50	1
auto[1879048192:2013265919]	auto[1]	61	1			T38	1		T4	2		T44	1
auto[2013265920:2147483647]	auto[0]	53	1			T4	1		T7	1		T45	1
auto[2013265920:2147483647]	auto[1]	52	1			T17	1		T58	1		T44	1
auto[2147483648:2281701375]	auto[0]	47	1			T38	1		T47	1		T4	1
auto[2147483648:2281701375]	auto[1]	47	1			T4	1		T45	1		T108	1
auto[2281701376:2415919103]	auto[0]	45	1			T38	1		T28	1		T4	3
auto[2281701376:2415919103]	auto[1]	60	1			T4	2		T108	1		T49	1
auto[2415919104:2550136831]	auto[0]	61	1			T29	1		T4	2		T79	1
auto[2415919104:2550136831]	auto[1]	62	1			T16	1		T17	1		T4	1
auto[2550136832:2684354559]	auto[0]	51	1			T29	1		T4	1		T6	1
auto[2550136832:2684354559]	auto[1]	64	1			T4	2		T81	1		T50	1
auto[2684354560:2818572287]	auto[0]	46	1			T28	1		T50	1		T117	1
auto[2684354560:2818572287]	auto[1]	61	1			T31	1		T4	1		T50	1
auto[2818572288:2952790015]	auto[0]	44	1			T17	1		T216	1		T303	1
auto[2818572288:2952790015]	auto[1]	60	1			T1	1		T80	1		T81	1
auto[2952790016:3087007743]	auto[0]	36	1			T16	1		T4	2		T45	1
auto[2952790016:3087007743]	auto[1]	57	1			T4	1		T45	1		T50	1
auto[3087007744:3221225471]	auto[0]	57	1			T4	1		T24	1		T48	1
auto[3087007744:3221225471]	auto[1]	50	1			T80	2		T45	1		T129	1
auto[3221225472:3355443199]	auto[0]	48	1			T28	1		T29	1		T45	1
auto[3221225472:3355443199]	auto[1]	75	1			T4	1		T50	2		T119	1
auto[3355443200:3489660927]	auto[0]	55	1			T15	1		T38	1		T4	1
auto[3355443200:3489660927]	auto[1]	50	1			T15	1		T28	1		T58	1
auto[3489660928:3623878655]	auto[0]	34	1			T79	1		T45	1		T49	1
auto[3489660928:3623878655]	auto[1]	52	1			T17	1		T4	2		T81	1
auto[3623878656:3758096383]	auto[0]	37	1			T4	1		T45	1		T117	1
auto[3623878656:3758096383]	auto[1]	53	1			T4	2		T45	1		T50	1
auto[3758096384:3892314111]	auto[0]	55	1			T79	1		T7	1		T217	1
auto[3758096384:3892314111]	auto[1]	50	1			T31	1		T48	1		T50	1
auto[3892314112:4026531839]	auto[0]	48	1			T4	1		T44	1		T108	1
auto[3892314112:4026531839]	auto[1]	60	1			T47	1		T4	2		T45	1
auto[4026531840:4160749567]	auto[0]	48	1			T28	1		T4	1		T277	1
auto[4026531840:4160749567]	auto[1]	53	1			T29	1		T81	1		T358	1
auto[4160749568:4294967295]	auto[0]	48	1			T46	1		T45	1		T50	1
auto[4160749568:4294967295]	auto[1]	61	1			T47	1		T4	1		T55	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1514

1

T2

1

T15

4

T16

2

auto[1]

1817

1

T1

3

T2

2

T15

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	100	1			T29	1		T4	3		T81	1
auto[134217728:268435455]	108	1			T16	1		T38	1		T47	1
auto[268435456:402653183]	126	1			T38	1		T4	1		T24	1
auto[402653184:536870911]	116	1			T17	2		T4	1		T60	1
auto[536870912:671088639]	105	1			T15	1		T38	1		T29	1
auto[671088640:805306367]	108	1			T4	1		T58	1		T81	1
auto[805306368:939524095]	100	1			T17	1		T28	1		T4	3
auto[939524096:1073741823]	101	1			T1	1		T15	1		T16	1
auto[1073741824:1207959551]	103	1			T28	1		T47	1		T80	1
auto[1207959552:1342177279]	104	1			T4	2		T80	1		T81	1
auto[1342177280:1476395007]	101	1			T28	1		T29	1		T4	2
auto[1476395008:1610612735]	99	1			T4	2		T79	1		T24	1
auto[1610612736:1744830463]	124	1			T2	2		T15	1		T16	1
auto[1744830464:1879048191]	106	1			T29	1		T4	1		T48	1
auto[1879048192:2013265919]	98	1			T16	1		T28	2		T4	2
auto[2013265920:2147483647]	98	1			T4	1		T50	1		T255	1
auto[2147483648:2281701375]	117	1			T2	1		T38	1		T28	1
auto[2281701376:2415919103]	99	1			T15	1		T28	1		T4	2
auto[2415919104:2550136831]	97	1			T1	1		T47	1		T29	1
auto[2550136832:2684354559]	79	1			T15	1		T29	1		T4	3
auto[2684354560:2818572287]	95	1			T1	1		T31	1		T4	1
auto[2818572288:2952790015]	115	1			T55	1		T79	1		T81	1
auto[2952790016:3087007743]	96	1			T4	2		T50	1		T255	1
auto[3087007744:3221225471]	86	1			T7	1		T81	1		T45	2
auto[3221225472:3355443199]	105	1			T4	1		T80	2		T45	1
auto[3355443200:3489660927]	102	1			T38	1		T28	1		T47	1
auto[3489660928:3623878655]	101	1			T15	1		T4	1		T50	2
auto[3623878656:3758096383]	105	1			T28	1		T44	1		T45	1
auto[3758096384:3892314111]	104	1			T38	1		T31	1		T4	2
auto[3892314112:4026531839]	109	1			T38	1		T4	3		T79	1
auto[4026531840:4160749567]	112	1			T17	1		T4	3		T79	1
auto[4160749568:4294967295]	112	1			T15	1		T17	1		T4	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	49	1			T29	1		T4	1		T50	2
auto[0:134217727]	auto[1]	51	1			T4	2		T81	1		T44	1
auto[134217728:268435455]	auto[0]	52	1			T58	1		T50	1		T303	1
auto[134217728:268435455]	auto[1]	56	1			T16	1		T38	1		T47	1
auto[268435456:402653183]	auto[0]	59	1			T38	1		T24	1		T45	1
auto[268435456:402653183]	auto[1]	67	1			T4	1		T186	1		T69	2
auto[402653184:536870911]	auto[0]	48	1			T17	1		T91	1		T311	1
auto[402653184:536870911]	auto[1]	68	1			T17	1		T4	1		T60	1
auto[536870912:671088639]	auto[0]	47	1			T15	1		T4	1		T45	1
auto[536870912:671088639]	auto[1]	58	1			T38	1		T29	1		T45	1
auto[671088640:805306367]	auto[0]	47	1			T4	1		T58	1		T70	1
auto[671088640:805306367]	auto[1]	61	1			T81	1		T45	2		T108	1
auto[805306368:939524095]	auto[0]	40	1			T4	2		T132	1		T113	1
auto[805306368:939524095]	auto[1]	60	1			T17	1		T28	1		T4	1
auto[939524096:1073741823]	auto[0]	32	1			T15	1		T16	1		T7	1
auto[939524096:1073741823]	auto[1]	69	1			T1	1		T29	1		T4	1
auto[1073741824:1207959551]	auto[0]	49	1			T28	1		T47	1		T80	1
auto[1073741824:1207959551]	auto[1]	54	1			T50	1		T303	1		T56	1
auto[1207959552:1342177279]	auto[0]	51	1			T4	1		T81	1		T108	1
auto[1207959552:1342177279]	auto[1]	53	1			T4	1		T80	1		T50	1
auto[1342177280:1476395007]	auto[0]	40	1			T28	1		T216	1		T379	1
auto[1342177280:1476395007]	auto[1]	61	1			T29	1		T4	2		T45	2
auto[1476395008:1610612735]	auto[0]	43	1			T4	1		T79	1		T50	1
auto[1476395008:1610612735]	auto[1]	56	1			T4	1		T24	1		T45	1
auto[1610612736:1744830463]	auto[0]	60	1			T15	1		T16	1		T29	1
auto[1610612736:1744830463]	auto[1]	64	1			T2	2		T4	2		T71	1
auto[1744830464:1879048191]	auto[0]	51	1			T29	1		T4	1		T48	1
auto[1744830464:1879048191]	auto[1]	55	1			T119	1		T6	2		T113	1
auto[1879048192:2013265919]	auto[0]	41	1			T28	2		T4	1		T59	1
auto[1879048192:2013265919]	auto[1]	57	1			T16	1		T4	1		T48	1
auto[2013265920:2147483647]	auto[0]	46	1			T50	1		T277	2		T87	1
auto[2013265920:2147483647]	auto[1]	52	1			T4	1		T255	1		T113	1
auto[2147483648:2281701375]	auto[0]	59	1			T2	1		T38	1		T28	1
auto[2147483648:2281701375]	auto[1]	58	1			T4	2		T45	1		T49	1
auto[2281701376:2415919103]	auto[0]	50	1			T28	1		T4	2		T45	1
auto[2281701376:2415919103]	auto[1]	49	1			T15	1		T81	1		T50	2
auto[2415919104:2550136831]	auto[0]	37	1			T47	1		T359	1		T189	1
auto[2415919104:2550136831]	auto[1]	60	1			T1	1		T29	1		T4	2
auto[2550136832:2684354559]	auto[0]	29	1			T29	1		T4	1		T50	1
auto[2550136832:2684354559]	auto[1]	50	1			T15	1		T4	2		T45	1
auto[2684354560:2818572287]	auto[0]	43	1			T79	1		T44	1		T216	1
auto[2684354560:2818572287]	auto[1]	52	1			T1	1		T31	1		T4	1
auto[2818572288:2952790015]	auto[0]	57	1			T79	1		T45	2		T50	1
auto[2818572288:2952790015]	auto[1]	58	1			T55	1		T81	1		T117	2
auto[2952790016:3087007743]	auto[0]	40	1			T4	1		T70	1		T192	2
auto[2952790016:3087007743]	auto[1]	56	1			T4	1		T50	1		T255	1
auto[3087007744:3221225471]	auto[0]	37	1			T7	1		T45	1		T379	1
auto[3087007744:3221225471]	auto[1]	49	1			T81	1		T45	1		T353	1
auto[3221225472:3355443199]	auto[0]	45	1			T217	1		T379	1		T113	1
auto[3221225472:3355443199]	auto[1]	60	1			T4	1		T80	2		T45	1
auto[3355443200:3489660927]	auto[0]	57	1			T38	1		T4	1		T59	1
auto[3355443200:3489660927]	auto[1]	45	1			T28	1		T47	1		T4	1
auto[3489660928:3623878655]	auto[0]	44	1			T15	1		T117	1		T59	1
auto[3489660928:3623878655]	auto[1]	57	1			T4	1		T50	2		T328	1
auto[3623878656:3758096383]	auto[0]	52	1			T28	1		T45	1		T216	1
auto[3623878656:3758096383]	auto[1]	53	1			T44	1		T255	1		T118	1
auto[3758096384:3892314111]	auto[0]	48	1			T38	1		T4	1		T45	1
auto[3758096384:3892314111]	auto[1]	56	1			T31	1		T4	1		T81	1
auto[3892314112:4026531839]	auto[0]	59	1			T38	1		T4	3		T79	1
auto[3892314112:4026531839]	auto[1]	50	1			T50	1		T192	1		T64	2
auto[4026531840:4160749567]	auto[0]	49	1			T4	1		T79	1		T69	1
auto[4026531840:4160749567]	auto[1]	63	1			T17	1		T4	2		T45	1
auto[4160749568:4294967295]	auto[0]	53	1			T17	1		T4	2		T80	1
auto[4160749568:4294967295]	auto[1]	59	1			T15	1		T61	1		T70	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1511

1

T2

1

T15

4

T16

2

auto[1]

1820

1

T1

3

T2

2

T15

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	102	1			T29	1		T4	1		T79	1
auto[134217728:268435455]	110	1			T28	2		T29	1		T4	3
auto[268435456:402653183]	100	1			T17	1		T80	2		T45	3
auto[402653184:536870911]	120	1			T47	1		T29	1		T4	2
auto[536870912:671088639]	106	1			T15	1		T38	2		T4	1
auto[671088640:805306367]	104	1			T15	1		T16	1		T28	1
auto[805306368:939524095]	108	1			T4	1		T80	1		T7	1
auto[939524096:1073741823]	94	1			T2	1		T4	2		T117	1
auto[1073741824:1207959551]	121	1			T28	1		T29	1		T81	1
auto[1207959552:1342177279]	111	1			T1	1		T31	1		T186	1
auto[1342177280:1476395007]	120	1			T1	1		T16	1		T38	1
auto[1476395008:1610612735]	98	1			T47	1		T4	2		T44	1
auto[1610612736:1744830463]	82	1			T4	1		T7	1		T45	1
auto[1744830464:1879048191]	100	1			T4	3		T58	1		T44	1
auto[1879048192:2013265919]	98	1			T38	1		T4	5		T45	1
auto[2013265920:2147483647]	113	1			T28	1		T4	1		T80	1
auto[2147483648:2281701375]	97	1			T28	1		T4	2		T55	1
auto[2281701376:2415919103]	83	1			T28	1		T29	1		T4	1
auto[2415919104:2550136831]	107	1			T15	1		T28	1		T4	3
auto[2550136832:2684354559]	94	1			T17	1		T47	1		T4	1
auto[2684354560:2818572287]	117	1			T17	1		T4	2		T50	1
auto[2818572288:2952790015]	105	1			T16	1		T4	1		T81	1
auto[2952790016:3087007743]	114	1			T38	1		T4	5		T81	1
auto[3087007744:3221225471]	92	1			T15	1		T4	1		T24	1
auto[3221225472:3355443199]	115	1			T15	2		T28	1		T4	1
auto[3355443200:3489660927]	106	1			T15	1		T17	2		T4	2
auto[3489660928:3623878655]	105	1			T16	1		T45	3		T108	1
auto[3623878656:3758096383]	103	1			T1	1		T2	1		T29	1
auto[3758096384:3892314111]	106	1			T2	1		T31	1		T4	1
auto[3892314112:4026531839]	92	1			T38	1		T47	1		T4	1
auto[4026531840:4160749567]	102	1			T4	3		T79	1		T81	2
auto[4160749568:4294967295]	106	1			T38	1		T29	2		T4	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	48	1			T79	1		T255	1		T59	1
auto[0:134217727]	auto[1]	54	1			T29	1		T4	1		T44	1
auto[134217728:268435455]	auto[0]	46	1			T28	1		T29	1		T4	2
auto[134217728:268435455]	auto[1]	64	1			T28	1		T4	1		T50	2
auto[268435456:402653183]	auto[0]	44	1			T17	1		T80	1		T45	2
auto[268435456:402653183]	auto[1]	56	1			T80	1		T45	1		T50	1
auto[402653184:536870911]	auto[0]	56	1			T79	1		T69	1		T6	1
auto[402653184:536870911]	auto[1]	64	1			T47	1		T29	1		T4	2
auto[536870912:671088639]	auto[0]	50	1			T15	1		T38	2		T45	1
auto[536870912:671088639]	auto[1]	56	1			T4	1		T81	1		T71	1
auto[671088640:805306367]	auto[0]	58	1			T16	1		T28	1		T4	1
auto[671088640:805306367]	auto[1]	46	1			T15	1		T216	1		T217	1
auto[805306368:939524095]	auto[0]	49	1			T7	1		T50	2		T216	1
auto[805306368:939524095]	auto[1]	59	1			T4	1		T80	1		T45	1
auto[939524096:1073741823]	auto[0]	37	1			T358	1		T277	1		T70	1
auto[939524096:1073741823]	auto[1]	57	1			T2	1		T4	2		T117	1
auto[1073741824:1207959551]	auto[0]	62	1			T28	1		T29	1		T108	1
auto[1073741824:1207959551]	auto[1]	59	1			T81	1		T45	1		T50	1
auto[1207959552:1342177279]	auto[0]	59	1			T48	1		T54	1		T192	3
auto[1207959552:1342177279]	auto[1]	52	1			T1	1		T31	1		T186	1
auto[1342177280:1476395007]	auto[0]	62	1			T38	1		T4	1		T79	1
auto[1342177280:1476395007]	auto[1]	58	1			T1	1		T16	1		T108	1
auto[1476395008:1610612735]	auto[0]	46	1			T47	1		T4	1		T216	1
auto[1476395008:1610612735]	auto[1]	52	1			T4	1		T44	1		T45	1
auto[1610612736:1744830463]	auto[0]	38	1			T7	1		T54	1		T192	1
auto[1610612736:1744830463]	auto[1]	44	1			T4	1		T45	1		T108	1
auto[1744830464:1879048191]	auto[0]	51	1			T4	2		T58	1		T50	1
auto[1744830464:1879048191]	auto[1]	49	1			T4	1		T44	1		T186	1
auto[1879048192:2013265919]	auto[0]	45	1			T38	1		T4	2		T45	1
auto[1879048192:2013265919]	auto[1]	53	1			T4	3		T50	2		T303	1
auto[2013265920:2147483647]	auto[0]	41	1			T28	1		T4	1		T80	1
auto[2013265920:2147483647]	auto[1]	72	1			T45	1		T48	1		T50	1
auto[2147483648:2281701375]	auto[0]	51	1			T4	1		T46	1		T50	2
auto[2147483648:2281701375]	auto[1]	46	1			T28	1		T4	1		T55	1
auto[2281701376:2415919103]	auto[0]	31	1			T28	1		T45	1		T277	1
auto[2281701376:2415919103]	auto[1]	52	1			T29	1		T4	1		T80	1
auto[2415919104:2550136831]	auto[0]	43	1			T15	1		T28	1		T4	1
auto[2415919104:2550136831]	auto[1]	64	1			T4	2		T58	1		T69	1
auto[2550136832:2684354559]	auto[0]	53	1			T17	1		T4	1		T5	1
auto[2550136832:2684354559]	auto[1]	41	1			T47	1		T45	1		T129	1
auto[2684354560:2818572287]	auto[0]	49	1			T50	1		T216	1		T59	1
auto[2684354560:2818572287]	auto[1]	68	1			T17	1		T4	2		T49	1
auto[2818572288:2952790015]	auto[0]	43	1			T4	1		T50	1		T117	1
auto[2818572288:2952790015]	auto[1]	62	1			T16	1		T81	1		T45	1
auto[2952790016:3087007743]	auto[0]	46	1			T38	1		T4	2		T59	1
auto[2952790016:3087007743]	auto[1]	68	1			T4	3		T81	1		T48	1
auto[3087007744:3221225471]	auto[0]	35	1			T15	1		T24	1		T379	1
auto[3087007744:3221225471]	auto[1]	57	1			T4	1		T45	1		T117	1
auto[3221225472:3355443199]	auto[0]	53	1			T15	1		T28	1		T4	1
auto[3221225472:3355443199]	auto[1]	62	1			T15	1		T50	2		T277	1
auto[3355443200:3489660927]	auto[0]	52	1			T46	1		T50	1		T192	3
auto[3355443200:3489660927]	auto[1]	54	1			T15	1		T17	2		T4	2
auto[3489660928:3623878655]	auto[0]	32	1			T16	1		T45	2		T108	1
auto[3489660928:3623878655]	auto[1]	73	1			T45	1		T50	1		T255	1
auto[3623878656:3758096383]	auto[0]	46	1			T29	1		T108	1		T50	2
auto[3623878656:3758096383]	auto[1]	57	1			T1	1		T2	1		T4	1
auto[3758096384:3892314111]	auto[0]	50	1			T2	1		T4	1		T24	1
auto[3758096384:3892314111]	auto[1]	56	1			T31	1		T50	1		T358	1
auto[3892314112:4026531839]	auto[0]	37	1			T47	1		T245	1		T171	1
auto[3892314112:4026531839]	auto[1]	55	1			T38	1		T4	1		T44	1
auto[4026531840:4160749567]	auto[0]	50	1			T4	1		T79	1		T44	1
auto[4026531840:4160749567]	auto[1]	52	1			T4	2		T81	2		T45	1
auto[4160749568:4294967295]	auto[0]	48	1			T38	1		T29	2		T79	1
auto[4160749568:4294967295]	auto[1]	58	1			T4	2		T50	1		T60	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1538

1

T1

1

T2

1

T15

4

auto[1]

1793

1

T1

2

T2

2

T15

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	93	1			T50	2		T217	1		T87	1
auto[134217728:268435455]	107	1			T38	1		T28	1		T4	4
auto[268435456:402653183]	103	1			T15	1		T4	1		T45	1
auto[402653184:536870911]	102	1			T47	1		T79	1		T255	1
auto[536870912:671088639]	112	1			T17	2		T28	1		T4	2
auto[671088640:805306367]	109	1			T16	1		T28	1		T4	3
auto[805306368:939524095]	90	1			T2	1		T15	1		T31	1
auto[939524096:1073741823]	124	1			T16	1		T17	1		T38	2
auto[1073741824:1207959551]	106	1			T15	1		T4	2		T45	1
auto[1207959552:1342177279]	103	1			T29	1		T4	2		T44	1
auto[1342177280:1476395007]	101	1			T80	1		T108	1		T50	1
auto[1476395008:1610612735]	107	1			T28	1		T4	4		T186	1
auto[1610612736:1744830463]	112	1			T15	1		T4	1		T58	1
auto[1744830464:1879048191]	98	1			T38	1		T81	1		T44	1
auto[1879048192:2013265919]	118	1			T4	4		T79	2		T45	1
auto[2013265920:2147483647]	118	1			T38	1		T4	1		T81	1
auto[2147483648:2281701375]	90	1			T15	1		T4	1		T45	2
auto[2281701376:2415919103]	109	1			T28	1		T29	1		T4	2
auto[2415919104:2550136831]	86	1			T28	2		T29	1		T79	1
auto[2550136832:2684354559]	122	1			T16	1		T29	1		T4	2
auto[2684354560:2818572287]	108	1			T38	1		T4	1		T80	1
auto[2818572288:2952790015]	120	1			T2	1		T15	1		T29	1
auto[2952790016:3087007743]	106	1			T2	1		T80	1		T24	1
auto[3087007744:3221225471]	112	1			T15	1		T17	1		T47	1
auto[3221225472:3355443199]	85	1			T17	1		T31	1		T4	1
auto[3355443200:3489660927]	93	1			T1	1		T29	1		T4	1
auto[3489660928:3623878655]	96	1			T38	1		T47	1		T4	2
auto[3623878656:3758096383]	106	1			T1	2		T4	2		T45	2
auto[3758096384:3892314111]	103	1			T16	1		T28	2		T4	1
auto[3892314112:4026531839]	104	1			T45	2		T49	1		T277	1
auto[4026531840:4160749567]	95	1			T50	2		T358	1		T6	2
auto[4160749568:4294967295]	93	1			T4	2		T80	1		T81	1