Unified Coverage Report :: Group Instance : salt_6

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2949

1

T1

3

T2

3

T15

7

auto[1]

303

1

T80

12

T108

7

T117

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	98	1			T15	1		T17	1		T29	1
auto[134217728:268435455]	94	1			T79	1		T80	1		T46	1
auto[268435456:402653183]	97	1			T15	2		T4	2		T80	1
auto[402653184:536870911]	111	1			T38	1		T28	2		T79	1
auto[536870912:671088639]	102	1			T29	2		T4	1		T80	1
auto[671088640:805306367]	118	1			T1	1		T17	1		T38	1
auto[805306368:939524095]	123	1			T38	1		T29	1		T4	1
auto[939524096:1073741823]	100	1			T4	1		T80	1		T24	1
auto[1073741824:1207959551]	88	1			T28	1		T4	2		T48	1
auto[1207959552:1342177279]	118	1			T2	1		T38	1		T4	1
auto[1342177280:1476395007]	107	1			T47	1		T4	3		T81	1
auto[1476395008:1610612735]	93	1			T4	1		T80	2		T81	1
auto[1610612736:1744830463]	111	1			T31	1		T47	1		T58	1
auto[1744830464:1879048191]	94	1			T38	1		T4	2		T81	1
auto[1879048192:2013265919]	107	1			T4	1		T80	1		T81	1
auto[2013265920:2147483647]	101	1			T28	2		T4	1		T80	1
auto[2147483648:2281701375]	112	1			T81	1		T358	1		T255	1
auto[2281701376:2415919103]	84	1			T1	1		T15	3		T4	1
auto[2415919104:2550136831]	89	1			T31	1		T4	1		T45	1
auto[2550136832:2684354559]	93	1			T17	1		T28	1		T29	1
auto[2684354560:2818572287]	84	1			T28	1		T4	1		T80	1
auto[2818572288:2952790015]	104	1			T17	1		T4	2		T45	1
auto[2952790016:3087007743]	122	1			T2	1		T15	1		T38	1
auto[3087007744:3221225471]	102	1			T29	1		T4	6		T79	1
auto[3221225472:3355443199]	95	1			T44	1		T186	1		T45	1
auto[3355443200:3489660927]	117	1			T4	4		T44	1		T45	1
auto[3489660928:3623878655]	79	1			T29	1		T4	2		T50	1
auto[3623878656:3758096383]	96	1			T17	1		T28	1		T29	1
auto[3758096384:3892314111]	99	1			T45	2		T117	1		T49	1
auto[3892314112:4026531839]	111	1			T1	1		T2	1		T38	1
auto[4026531840:4160749567]	105	1			T80	1		T45	2		T108	2
auto[4160749568:4294967295]	98	1			T4	3		T79	1		T80	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	87	1			T15	1		T17	1		T29	1
auto[0:134217727]	auto[1]	11	1			T117	1		T121	1		T242	1
auto[134217728:268435455]	auto[0]	83	1			T79	1		T46	1		T50	2
auto[134217728:268435455]	auto[1]	11	1			T80	1		T118	2		T119	1
auto[268435456:402653183]	auto[0]	89	1			T15	2		T4	2		T7	1
auto[268435456:402653183]	auto[1]	8	1			T80	1		T242	1		T396	1
auto[402653184:536870911]	auto[0]	104	1			T38	1		T28	2		T79	1
auto[402653184:536870911]	auto[1]	7	1			T342	1		T396	1		T395	1
auto[536870912:671088639]	auto[0]	94	1			T29	2		T4	1		T48	1
auto[536870912:671088639]	auto[1]	8	1			T80	1		T119	2		T121	1
auto[671088640:805306367]	auto[0]	112	1			T1	1		T17	1		T38	1
auto[671088640:805306367]	auto[1]	6	1			T118	1		T119	1		T286	1
auto[805306368:939524095]	auto[0]	108	1			T38	1		T29	1		T4	1
auto[805306368:939524095]	auto[1]	15	1			T80	2		T117	1		T120	2
auto[939524096:1073741823]	auto[0]	92	1			T4	1		T24	1		T358	1
auto[939524096:1073741823]	auto[1]	8	1			T80	1		T119	1		T120	1
auto[1073741824:1207959551]	auto[0]	78	1			T28	1		T4	2		T48	1
auto[1073741824:1207959551]	auto[1]	10	1			T118	1		T119	1		T120	1
auto[1207959552:1342177279]	auto[0]	100	1			T2	1		T38	1		T4	1
auto[1207959552:1342177279]	auto[1]	18	1			T108	1		T118	1		T121	1
auto[1342177280:1476395007]	auto[0]	95	1			T47	1		T4	3		T81	1
auto[1342177280:1476395007]	auto[1]	12	1			T118	2		T119	1		T264	2
auto[1476395008:1610612735]	auto[0]	84	1			T4	1		T80	1		T81	1
auto[1476395008:1610612735]	auto[1]	9	1			T80	1		T108	1		T242	1
auto[1610612736:1744830463]	auto[0]	96	1			T31	1		T47	1		T58	1
auto[1610612736:1744830463]	auto[1]	15	1			T80	1		T108	1		T119	1
auto[1744830464:1879048191]	auto[0]	89	1			T38	1		T4	2		T81	1
auto[1744830464:1879048191]	auto[1]	5	1			T392	1		T278	1		T402	1
auto[1879048192:2013265919]	auto[0]	101	1			T4	1		T81	1		T186	1
auto[1879048192:2013265919]	auto[1]	6	1			T80	1		T119	1		T296	1
auto[2013265920:2147483647]	auto[0]	93	1			T28	2		T4	1		T81	1
auto[2013265920:2147483647]	auto[1]	8	1			T80	1		T118	1		T121	1
auto[2147483648:2281701375]	auto[0]	101	1			T81	1		T358	1		T255	1
auto[2147483648:2281701375]	auto[1]	11	1			T118	1		T242	1		T264	3
auto[2281701376:2415919103]	auto[0]	78	1			T1	1		T15	3		T4	1
auto[2281701376:2415919103]	auto[1]	6	1			T119	2		T377	1		T407	1
auto[2415919104:2550136831]	auto[0]	81	1			T31	1		T4	1		T45	1
auto[2415919104:2550136831]	auto[1]	8	1			T108	1		T120	1		T242	1
auto[2550136832:2684354559]	auto[0]	89	1			T17	1		T28	1		T29	1
auto[2550136832:2684354559]	auto[1]	4	1			T118	1		T120	1		T402	1
auto[2684354560:2818572287]	auto[0]	80	1			T28	1		T4	1		T80	1
auto[2684354560:2818572287]	auto[1]	4	1			T404	1		T405	1		T406	1
auto[2818572288:2952790015]	auto[0]	94	1			T17	1		T4	2		T45	1
auto[2818572288:2952790015]	auto[1]	10	1			T121	1		T332	1		T214	1
auto[2952790016:3087007743]	auto[0]	110	1			T2	1		T15	1		T38	1
auto[2952790016:3087007743]	auto[1]	12	1			T213	2		T214	1		T296	1
auto[3087007744:3221225471]	auto[0]	89	1			T29	1		T4	6		T79	1
auto[3087007744:3221225471]	auto[1]	13	1			T80	1		T108	1		T118	1
auto[3221225472:3355443199]	auto[0]	86	1			T44	1		T186	1		T45	1
auto[3221225472:3355443199]	auto[1]	9	1			T119	1		T121	1		T213	1
auto[3355443200:3489660927]	auto[0]	112	1			T4	4		T44	1		T45	1
auto[3355443200:3489660927]	auto[1]	5	1			T119	1		T120	1		T220	1
auto[3489660928:3623878655]	auto[0]	73	1			T29	1		T4	2		T50	1
auto[3489660928:3623878655]	auto[1]	6	1			T393	2		T390	1		T408	1
auto[3623878656:3758096383]	auto[0]	84	1			T17	1		T28	1		T29	1
auto[3623878656:3758096383]	auto[1]	12	1			T108	1		T118	1		T120	1
auto[3758096384:3892314111]	auto[0]	91	1			T45	2		T117	1		T49	1
auto[3758096384:3892314111]	auto[1]	8	1			T215	2		T296	1		T235	1
auto[3892314112:4026531839]	auto[0]	90	1			T1	1		T2	1		T38	1
auto[3892314112:4026531839]	auto[1]	21	1			T108	1		T118	2		T119	1
auto[4026531840:4160749567]	auto[0]	93	1			T45	2		T108	2		T129	1
auto[4026531840:4160749567]	auto[1]	12	1			T80	1		T118	1		T119	1
auto[4160749568:4294967295]	auto[0]	93	1			T4	3		T79	1		T80	2
auto[4160749568:4294967295]	auto[1]	5	1			T120	1		T121	1		T390	1