Unified Coverage Report :: Group Instance : max_owner_int_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4470

1

T1

4

T2

4

T15

8

auto[1]

2192

1

T1

2

T2

2

T15

6

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	194	1			T17	2		T38	2		T28	2
auto[134217728:268435455]	234	1			T17	2		T45	2		T108	2
auto[268435456:402653183]	236	1			T15	2		T28	2		T29	2
auto[402653184:536870911]	222	1			T4	4		T79	2		T353	2
auto[536870912:671088639]	202	1			T50	4		T117	2		T216	2
auto[671088640:805306367]	208	1			T15	2		T38	2		T29	2
auto[805306368:939524095]	234	1			T4	4		T44	2		T24	2
auto[939524096:1073741823]	230	1			T1	2		T15	2		T16	2
auto[1073741824:1207959551]	184	1			T4	2		T303	2		T230	2
auto[1207959552:1342177279]	196	1			T28	2		T4	2		T71	2
auto[1342177280:1476395007]	232	1			T17	2		T28	2		T47	2
auto[1476395008:1610612735]	210	1			T2	2		T38	2		T29	4
auto[1610612736:1744830463]	228	1			T45	2		T108	2		T48	2
auto[1744830464:1879048191]	208	1			T38	2		T47	2		T4	8
auto[1879048192:2013265919]	200	1			T17	2		T38	2		T4	2
auto[2013265920:2147483647]	198	1			T31	2		T4	4		T80	2
auto[2147483648:2281701375]	198	1			T16	2		T29	2		T4	2
auto[2281701376:2415919103]	224	1			T38	2		T28	2		T4	6
auto[2415919104:2550136831]	202	1			T16	2		T29	2		T4	2
auto[2550136832:2684354559]	194	1			T4	4		T44	2		T71	2
auto[2684354560:2818572287]	212	1			T47	2		T4	2		T80	2
auto[2818572288:2952790015]	196	1			T1	2		T15	2		T28	2
auto[2952790016:3087007743]	222	1			T15	2		T38	2		T29	2
auto[3087007744:3221225471]	178	1			T4	2		T81	2		T45	2
auto[3221225472:3355443199]	218	1			T29	2		T4	10		T81	2
auto[3355443200:3489660927]	218	1			T31	2		T47	2		T4	6
auto[3489660928:3623878655]	188	1			T2	2		T50	4		T117	2
auto[3623878656:3758096383]	188	1			T2	2		T4	2		T46	2
auto[3758096384:3892314111]	176	1			T15	2		T4	4		T80	2
auto[3892314112:4026531839]	220	1			T1	2		T28	4		T4	8
auto[4026531840:4160749567]	222	1			T15	2		T16	2		T4	4
auto[4160749568:4294967295]	190	1			T17	2		T28	2		T81	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	150	1			T17	2		T38	2		T28	2
auto[0:134217727]	auto[1]	44	1			T381	2		T226	2		T397	2
auto[134217728:268435455]	auto[0]	174	1			T17	2		T45	2		T108	2
auto[134217728:268435455]	auto[1]	60	1			T230	2		T70	2		T113	2
auto[268435456:402653183]	auto[0]	138	1			T28	2		T4	6		T108	2
auto[268435456:402653183]	auto[1]	98	1			T15	2		T29	2		T81	2
auto[402653184:536870911]	auto[0]	146	1			T4	4		T379	2		T61	2
auto[402653184:536870911]	auto[1]	76	1			T79	2		T353	2		T69	2
auto[536870912:671088639]	auto[0]	128	1			T50	2		T117	2		T216	2
auto[536870912:671088639]	auto[1]	74	1			T50	2		T176	2		T192	2
auto[671088640:805306367]	auto[0]	150	1			T15	2		T4	4		T45	4
auto[671088640:805306367]	auto[1]	58	1			T38	2		T29	2		T58	2
auto[805306368:939524095]	auto[0]	152	1			T4	2		T44	2		T24	2
auto[805306368:939524095]	auto[1]	82	1			T4	2		T132	2		T113	2
auto[939524096:1073741823]	auto[0]	142	1			T15	2		T16	2		T4	2
auto[939524096:1073741823]	auto[1]	88	1			T1	2		T7	2		T50	2
auto[1073741824:1207959551]	auto[0]	136	1			T303	2		T129	2		T192	4
auto[1073741824:1207959551]	auto[1]	48	1			T4	2		T230	2		T87	2
auto[1207959552:1342177279]	auto[0]	126	1			T28	2		T4	2		T71	2
auto[1207959552:1342177279]	auto[1]	70	1			T45	4		T60	2		T129	2
auto[1342177280:1476395007]	auto[0]	156	1			T17	2		T28	2		T47	2
auto[1342177280:1476395007]	auto[1]	76	1			T358	2		T61	2		T398	2
auto[1476395008:1610612735]	auto[0]	136	1			T2	2		T38	2		T29	2
auto[1476395008:1610612735]	auto[1]	74	1			T29	2		T4	2		T45	2
auto[1610612736:1744830463]	auto[0]	154	1			T45	2		T108	2		T48	2
auto[1610612736:1744830463]	auto[1]	74	1			T230	2		T132	2		T6	2
auto[1744830464:1879048191]	auto[0]	154	1			T38	2		T47	2		T4	8
auto[1744830464:1879048191]	auto[1]	54	1			T45	2		T129	2		T192	2
auto[1879048192:2013265919]	auto[0]	144	1			T58	2		T50	2		T5	2
auto[1879048192:2013265919]	auto[1]	56	1			T17	2		T38	2		T4	2
auto[2013265920:2147483647]	auto[0]	126	1			T4	2		T80	2		T379	2
auto[2013265920:2147483647]	auto[1]	72	1			T31	2		T4	2		T50	4
auto[2147483648:2281701375]	auto[0]	142	1			T16	2		T4	2		T55	2
auto[2147483648:2281701375]	auto[1]	56	1			T29	2		T81	2		T45	2
auto[2281701376:2415919103]	auto[0]	132	1			T38	2		T28	2		T4	4
auto[2281701376:2415919103]	auto[1]	92	1			T4	2		T81	2		T45	4
auto[2415919104:2550136831]	auto[0]	148	1			T16	2		T29	2		T4	2
auto[2415919104:2550136831]	auto[1]	54	1			T45	2		T50	2		T118	2
auto[2550136832:2684354559]	auto[0]	132	1			T4	4		T44	2		T71	2
auto[2550136832:2684354559]	auto[1]	62	1			T45	2		T113	2		T192	4
auto[2684354560:2818572287]	auto[0]	132	1			T47	2		T4	2		T80	2
auto[2684354560:2818572287]	auto[1]	80	1			T81	2		T45	2		T60	2
auto[2818572288:2952790015]	auto[0]	132	1			T1	2		T28	2		T4	2
auto[2818572288:2952790015]	auto[1]	64	1			T15	2		T4	2		T7	2
auto[2952790016:3087007743]	auto[0]	134	1			T29	2		T4	2		T80	2
auto[2952790016:3087007743]	auto[1]	88	1			T15	2		T38	2		T4	2
auto[3087007744:3221225471]	auto[0]	120	1			T4	2		T50	2		T358	2
auto[3087007744:3221225471]	auto[1]	58	1			T81	2		T45	2		T358	2
auto[3221225472:3355443199]	auto[0]	148	1			T4	6		T277	4		T379	2
auto[3221225472:3355443199]	auto[1]	70	1			T29	2		T4	4		T81	2
auto[3355443200:3489660927]	auto[0]	140	1			T31	2		T47	2		T4	6
auto[3355443200:3489660927]	auto[1]	78	1			T186	2		T50	2		T217	2
auto[3489660928:3623878655]	auto[0]	128	1			T50	4		T117	2		T303	2
auto[3489660928:3623878655]	auto[1]	60	1			T2	2		T54	2		T113	2
auto[3623878656:3758096383]	auto[0]	142	1			T2	2		T4	2		T5	2
auto[3623878656:3758096383]	auto[1]	46	1			T46	2		T216	2		T277	2
auto[3758096384:3892314111]	auto[0]	114	1			T15	2		T4	2		T44	2
auto[3758096384:3892314111]	auto[1]	62	1			T4	2		T80	2		T32	2
auto[3892314112:4026531839]	auto[0]	150	1			T1	2		T28	4		T4	2
auto[3892314112:4026531839]	auto[1]	70	1			T4	6		T241	2		T132	2
auto[4026531840:4160749567]	auto[0]	136	1			T15	2		T16	2		T4	2
auto[4026531840:4160749567]	auto[1]	86	1			T4	2		T81	2		T108	2
auto[4160749568:4294967295]	auto[0]	128	1			T28	2		T45	2		T50	2
auto[4160749568:4294967295]	auto[1]	62	1			T17	2		T81	2		T129	2