Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.74 99.03 97.99 98.57 100.00 99.02 98.41 91.19


Total test records in report: 1086
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T1006 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.1296229259 May 12 04:08:08 PM PDT 24 May 12 04:08:24 PM PDT 24 1503202469 ps
T1007 /workspace/coverage/cover_reg_top/20.keymgr_intr_test.362447384 May 12 04:08:33 PM PDT 24 May 12 04:08:35 PM PDT 24 11573860 ps
T1008 /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.122105841 May 12 04:08:23 PM PDT 24 May 12 04:08:25 PM PDT 24 152813878 ps
T1009 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.436758719 May 12 04:08:24 PM PDT 24 May 12 04:08:26 PM PDT 24 259220471 ps
T1010 /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.352492916 May 12 04:08:29 PM PDT 24 May 12 04:08:32 PM PDT 24 138504684 ps
T1011 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.737095670 May 12 04:08:15 PM PDT 24 May 12 04:08:23 PM PDT 24 1558525549 ps
T1012 /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.782387516 May 12 04:08:20 PM PDT 24 May 12 04:08:24 PM PDT 24 177367022 ps
T1013 /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.2552391742 May 12 04:08:03 PM PDT 24 May 12 04:08:06 PM PDT 24 115178385 ps
T1014 /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.660902731 May 12 04:08:03 PM PDT 24 May 12 04:08:05 PM PDT 24 23339367 ps
T1015 /workspace/coverage/cover_reg_top/32.keymgr_intr_test.1406796471 May 12 04:08:33 PM PDT 24 May 12 04:08:35 PM PDT 24 25057583 ps
T1016 /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.3083204166 May 12 04:08:28 PM PDT 24 May 12 04:08:29 PM PDT 24 34364331 ps
T1017 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.1664078244 May 12 04:08:19 PM PDT 24 May 12 04:08:21 PM PDT 24 70509068 ps
T148 /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.3924383983 May 12 04:08:02 PM PDT 24 May 12 04:08:07 PM PDT 24 296067245 ps
T1018 /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.3216573144 May 12 04:08:12 PM PDT 24 May 12 04:08:19 PM PDT 24 1448687246 ps
T1019 /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.3947616433 May 12 04:08:22 PM PDT 24 May 12 04:08:25 PM PDT 24 172486673 ps
T1020 /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1800619463 May 12 04:08:15 PM PDT 24 May 12 04:08:19 PM PDT 24 66812064 ps
T1021 /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.3622605708 May 12 04:08:34 PM PDT 24 May 12 04:08:37 PM PDT 24 23015526 ps
T1022 /workspace/coverage/cover_reg_top/25.keymgr_intr_test.3033231123 May 12 04:08:35 PM PDT 24 May 12 04:08:37 PM PDT 24 26729148 ps
T1023 /workspace/coverage/cover_reg_top/36.keymgr_intr_test.2855884583 May 12 04:08:33 PM PDT 24 May 12 04:08:35 PM PDT 24 127564078 ps
T1024 /workspace/coverage/cover_reg_top/7.keymgr_intr_test.2558552452 May 12 04:08:16 PM PDT 24 May 12 04:08:17 PM PDT 24 55021001 ps
T1025 /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.2570834654 May 12 04:08:04 PM PDT 24 May 12 04:08:09 PM PDT 24 446714240 ps
T1026 /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.274276506 May 12 04:08:24 PM PDT 24 May 12 04:08:27 PM PDT 24 77148438 ps
T1027 /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.3684365254 May 12 04:08:29 PM PDT 24 May 12 04:08:31 PM PDT 24 118748640 ps
T1028 /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.4258264333 May 12 04:08:05 PM PDT 24 May 12 04:08:08 PM PDT 24 256869296 ps
T146 /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.680829771 May 12 04:08:29 PM PDT 24 May 12 04:08:34 PM PDT 24 528458639 ps
T1029 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.3780226409 May 12 04:08:22 PM PDT 24 May 12 04:08:29 PM PDT 24 643345099 ps
T1030 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.561874171 May 12 04:08:15 PM PDT 24 May 12 04:08:18 PM PDT 24 327116457 ps
T1031 /workspace/coverage/cover_reg_top/15.keymgr_intr_test.2272800628 May 12 04:08:24 PM PDT 24 May 12 04:08:26 PM PDT 24 25572022 ps
T1032 /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.3120135286 May 12 04:08:15 PM PDT 24 May 12 04:08:20 PM PDT 24 424631891 ps
T1033 /workspace/coverage/cover_reg_top/27.keymgr_intr_test.3381850250 May 12 04:08:30 PM PDT 24 May 12 04:08:32 PM PDT 24 12592322 ps
T1034 /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.1037162434 May 12 04:08:04 PM PDT 24 May 12 04:08:05 PM PDT 24 20672172 ps
T1035 /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.2362013510 May 12 04:08:19 PM PDT 24 May 12 04:08:22 PM PDT 24 24411096 ps
T1036 /workspace/coverage/cover_reg_top/29.keymgr_intr_test.1710282234 May 12 04:08:32 PM PDT 24 May 12 04:08:34 PM PDT 24 18495533 ps
T1037 /workspace/coverage/cover_reg_top/47.keymgr_intr_test.2822083814 May 12 04:08:37 PM PDT 24 May 12 04:08:38 PM PDT 24 33605429 ps
T1038 /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3472936623 May 12 04:08:26 PM PDT 24 May 12 04:08:27 PM PDT 24 32935065 ps
T1039 /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.1260368621 May 12 04:08:15 PM PDT 24 May 12 04:08:19 PM PDT 24 68836894 ps
T1040 /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.920313629 May 12 04:08:04 PM PDT 24 May 12 04:08:09 PM PDT 24 135269898 ps
T1041 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.2043985828 May 12 04:08:23 PM PDT 24 May 12 04:08:26 PM PDT 24 133902739 ps
T1042 /workspace/coverage/cover_reg_top/38.keymgr_intr_test.1418876199 May 12 04:08:34 PM PDT 24 May 12 04:08:36 PM PDT 24 12233134 ps
T1043 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.1403471938 May 12 04:08:12 PM PDT 24 May 12 04:08:14 PM PDT 24 320049799 ps
T1044 /workspace/coverage/cover_reg_top/35.keymgr_intr_test.582274493 May 12 04:08:34 PM PDT 24 May 12 04:08:36 PM PDT 24 59146199 ps
T1045 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.450004748 May 12 04:08:10 PM PDT 24 May 12 04:08:23 PM PDT 24 1769307426 ps
T1046 /workspace/coverage/cover_reg_top/8.keymgr_intr_test.43073374 May 12 04:08:20 PM PDT 24 May 12 04:08:22 PM PDT 24 10027611 ps
T1047 /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.1966228954 May 12 04:08:04 PM PDT 24 May 12 04:08:21 PM PDT 24 676926261 ps
T1048 /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.247888295 May 12 04:08:20 PM PDT 24 May 12 04:08:24 PM PDT 24 190174389 ps
T1049 /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.4026109659 May 12 04:08:19 PM PDT 24 May 12 04:08:21 PM PDT 24 96729641 ps
T1050 /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.2711901787 May 12 04:08:14 PM PDT 24 May 12 04:08:15 PM PDT 24 63752527 ps
T1051 /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.3812391362 May 12 04:08:13 PM PDT 24 May 12 04:08:15 PM PDT 24 33663639 ps
T1052 /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.2555604014 May 12 04:08:00 PM PDT 24 May 12 04:08:02 PM PDT 24 46588447 ps
T1053 /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.651153324 May 12 04:08:33 PM PDT 24 May 12 04:08:36 PM PDT 24 225908223 ps
T145 /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.1676961776 May 12 04:08:18 PM PDT 24 May 12 04:08:21 PM PDT 24 73904345 ps
T1054 /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1740989054 May 12 04:07:59 PM PDT 24 May 12 04:08:03 PM PDT 24 265251988 ps
T1055 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2405654918 May 12 04:08:28 PM PDT 24 May 12 04:08:36 PM PDT 24 153619054 ps
T150 /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.1479454052 May 12 04:08:11 PM PDT 24 May 12 04:08:15 PM PDT 24 203949319 ps
T1056 /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.187141449 May 12 04:08:26 PM PDT 24 May 12 04:08:28 PM PDT 24 76043532 ps
T1057 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3277995413 May 12 04:08:20 PM PDT 24 May 12 04:08:27 PM PDT 24 634514769 ps
T1058 /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.133853714 May 12 04:08:03 PM PDT 24 May 12 04:08:05 PM PDT 24 21770268 ps
T1059 /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2317282982 May 12 04:08:19 PM PDT 24 May 12 04:08:22 PM PDT 24 248868875 ps
T1060 /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.525377497 May 12 04:08:26 PM PDT 24 May 12 04:08:30 PM PDT 24 1635547020 ps
T147 /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.2135587768 May 12 04:08:28 PM PDT 24 May 12 04:08:33 PM PDT 24 689791777 ps
T1061 /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.3252742367 May 12 04:08:24 PM PDT 24 May 12 04:08:28 PM PDT 24 403455725 ps
T1062 /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.1059863644 May 12 04:08:30 PM PDT 24 May 12 04:08:32 PM PDT 24 419553982 ps
T1063 /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.2524955397 May 12 04:08:02 PM PDT 24 May 12 04:08:09 PM PDT 24 539542401 ps
T1064 /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.3325664740 May 12 04:08:21 PM PDT 24 May 12 04:08:24 PM PDT 24 142084468 ps
T1065 /workspace/coverage/cover_reg_top/12.keymgr_intr_test.2522401853 May 12 04:08:22 PM PDT 24 May 12 04:08:23 PM PDT 24 187372348 ps
T1066 /workspace/coverage/cover_reg_top/1.keymgr_intr_test.239696045 May 12 04:08:02 PM PDT 24 May 12 04:08:03 PM PDT 24 15111224 ps
T1067 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.2211661810 May 12 04:08:11 PM PDT 24 May 12 04:08:13 PM PDT 24 478794171 ps
T1068 /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.1971398208 May 12 04:08:02 PM PDT 24 May 12 04:08:18 PM PDT 24 555758029 ps
T1069 /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.378607693 May 12 04:08:19 PM PDT 24 May 12 04:08:21 PM PDT 24 28068729 ps
T1070 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1196907151 May 12 04:08:08 PM PDT 24 May 12 04:08:12 PM PDT 24 165989429 ps
T1071 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.3755242624 May 12 04:08:23 PM PDT 24 May 12 04:08:30 PM PDT 24 246238880 ps
T1072 /workspace/coverage/cover_reg_top/26.keymgr_intr_test.3975999925 May 12 04:08:34 PM PDT 24 May 12 04:08:36 PM PDT 24 12178028 ps
T1073 /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.3432724722 May 12 04:08:05 PM PDT 24 May 12 04:08:07 PM PDT 24 71726538 ps
T1074 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3519092807 May 12 04:08:34 PM PDT 24 May 12 04:08:40 PM PDT 24 315905337 ps
T1075 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.2063576074 May 12 04:07:56 PM PDT 24 May 12 04:07:59 PM PDT 24 252178856 ps
T1076 /workspace/coverage/cover_reg_top/49.keymgr_intr_test.4048511416 May 12 04:08:36 PM PDT 24 May 12 04:08:38 PM PDT 24 35929806 ps
T1077 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1991087053 May 12 04:08:32 PM PDT 24 May 12 04:08:33 PM PDT 24 53308040 ps
T1078 /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.198289405 May 12 04:08:04 PM PDT 24 May 12 04:08:06 PM PDT 24 20232277 ps
T1079 /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.1779571811 May 12 04:08:09 PM PDT 24 May 12 04:08:11 PM PDT 24 33719151 ps
T1080 /workspace/coverage/cover_reg_top/24.keymgr_intr_test.1391947558 May 12 04:08:32 PM PDT 24 May 12 04:08:34 PM PDT 24 14140520 ps
T1081 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1264307104 May 12 04:08:05 PM PDT 24 May 12 04:08:10 PM PDT 24 199439063 ps
T1082 /workspace/coverage/cover_reg_top/23.keymgr_intr_test.493515392 May 12 04:08:31 PM PDT 24 May 12 04:08:33 PM PDT 24 11669270 ps
T1083 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.4069713856 May 12 04:08:14 PM PDT 24 May 12 04:08:23 PM PDT 24 306960308 ps
T1084 /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.3029710168 May 12 04:08:34 PM PDT 24 May 12 04:08:37 PM PDT 24 79870689 ps
T1085 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.3935042867 May 12 04:08:22 PM PDT 24 May 12 04:08:26 PM PDT 24 322891641 ps
T1086 /workspace/coverage/cover_reg_top/31.keymgr_intr_test.1994840989 May 12 04:08:33 PM PDT 24 May 12 04:08:35 PM PDT 24 30036528 ps

Test location /workspace/coverage/default/19.keymgr_sideload_protect.1794950743
Short name T15
Test name
Test status
Simulation time 409746989 ps
CPU time 9.64 seconds
Started May 12 03:47:22 PM PDT 24
Finished May 12 03:47:32 PM PDT 24
Peak memory 218264 kb
Host smart-f12e3840-661f-4b38-b3a6-72577fd6d645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794950743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.1794950743
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.2345667497
Short name T4
Test name
Test status
Simulation time 4370448413 ps
CPU time 45.75 seconds
Started May 12 03:47:46 PM PDT 24
Finished May 12 03:48:33 PM PDT 24
Peak memory 215548 kb
Host smart-abe73f3c-24c6-4245-9c36-4af942a61786
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345667497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.2345667497
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.3831850430
Short name T29
Test name
Test status
Simulation time 359016715 ps
CPU time 18 seconds
Started May 12 03:47:38 PM PDT 24
Finished May 12 03:47:56 PM PDT 24
Peak memory 222572 kb
Host smart-6e8d4fb8-d4bd-4c65-9fd7-3685b57c3f71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831850430 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.3831850430
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.768648929
Short name T9
Test name
Test status
Simulation time 719932008 ps
CPU time 7.96 seconds
Started May 12 03:45:01 PM PDT 24
Finished May 12 03:45:10 PM PDT 24
Peak memory 233640 kb
Host smart-0707e579-2693-43f6-a6ec-2bb3f599bcc4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768648929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.768648929
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.4169292539
Short name T50
Test name
Test status
Simulation time 5352335942 ps
CPU time 39.79 seconds
Started May 12 03:46:00 PM PDT 24
Finished May 12 03:46:40 PM PDT 24
Peak memory 216076 kb
Host smart-ecb8a527-7bca-4128-80f9-f1f16a4f7ef4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169292539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.4169292539
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.317719870
Short name T113
Test name
Test status
Simulation time 1138184140 ps
CPU time 11.76 seconds
Started May 12 03:48:04 PM PDT 24
Finished May 12 03:48:16 PM PDT 24
Peak memory 222548 kb
Host smart-9546b482-bddd-4931-98ca-03990a986f01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317719870 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.317719870
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.1069427858
Short name T12
Test name
Test status
Simulation time 430247559 ps
CPU time 3.27 seconds
Started May 12 03:49:35 PM PDT 24
Finished May 12 03:49:39 PM PDT 24
Peak memory 210260 kb
Host smart-cbd151aa-5617-4467-877a-569f8605f353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069427858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.1069427858
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.3823311929
Short name T118
Test name
Test status
Simulation time 286221676 ps
CPU time 15.5 seconds
Started May 12 03:46:50 PM PDT 24
Finished May 12 03:47:06 PM PDT 24
Peak memory 214756 kb
Host smart-c3d3aa07-03b2-4a01-b156-9dd36cfe5511
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3823311929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.3823311929
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.172448672
Short name T192
Test name
Test status
Simulation time 1768090242 ps
CPU time 52.8 seconds
Started May 12 03:46:19 PM PDT 24
Finished May 12 03:47:12 PM PDT 24
Peak memory 216720 kb
Host smart-ecaff1cb-37d7-4010-b86f-12834766101f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172448672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.172448672
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.3329981337
Short name T7
Test name
Test status
Simulation time 155232714 ps
CPU time 4.91 seconds
Started May 12 03:48:05 PM PDT 24
Finished May 12 03:48:11 PM PDT 24
Peak memory 222588 kb
Host smart-96857387-c592-4ea9-b02c-1cea56a61cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329981337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.3329981337
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2169309502
Short name T103
Test name
Test status
Simulation time 184476348 ps
CPU time 5.08 seconds
Started May 12 04:08:33 PM PDT 24
Finished May 12 04:08:39 PM PDT 24
Peak memory 214260 kb
Host smart-59d0ef4c-efa7-44b3-97d5-dc4909814aa2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169309502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.2169309502
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.3015010542
Short name T48
Test name
Test status
Simulation time 79209454 ps
CPU time 2.13 seconds
Started May 12 03:47:50 PM PDT 24
Finished May 12 03:47:52 PM PDT 24
Peak memory 214284 kb
Host smart-1189b245-7bf9-46a2-8a04-e43aeaed7e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015010542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.3015010542
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.1108204913
Short name T119
Test name
Test status
Simulation time 3009675594 ps
CPU time 134.43 seconds
Started May 12 03:48:40 PM PDT 24
Finished May 12 03:50:55 PM PDT 24
Peak memory 215224 kb
Host smart-43a8e6cc-5fa2-4173-ba1b-468a5fc878ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1108204913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.1108204913
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.3986822957
Short name T120
Test name
Test status
Simulation time 10793283368 ps
CPU time 132.98 seconds
Started May 12 03:48:02 PM PDT 24
Finished May 12 03:50:16 PM PDT 24
Peak memory 215240 kb
Host smart-264fd455-ed70-4b02-aefb-a333597b3551
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3986822957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.3986822957
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.2465592343
Short name T24
Test name
Test status
Simulation time 650020799 ps
CPU time 4.71 seconds
Started May 12 03:47:49 PM PDT 24
Finished May 12 03:47:54 PM PDT 24
Peak memory 208952 kb
Host smart-3992ab95-3c76-4dc6-b0e8-2a2275c39418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465592343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.2465592343
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.3464732566
Short name T45
Test name
Test status
Simulation time 21261767393 ps
CPU time 664.85 seconds
Started May 12 03:49:25 PM PDT 24
Finished May 12 04:00:30 PM PDT 24
Peak memory 222668 kb
Host smart-b682867c-2bf8-4907-9a02-608f8dd82ff9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464732566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.3464732566
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.253642629
Short name T213
Test name
Test status
Simulation time 2108911041 ps
CPU time 31.14 seconds
Started May 12 03:49:38 PM PDT 24
Finished May 12 03:50:10 PM PDT 24
Peak memory 214856 kb
Host smart-7dc170a5-7369-4c3b-9710-775256d3c4ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=253642629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.253642629
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.1628408052
Short name T80
Test name
Test status
Simulation time 315151767 ps
CPU time 17.41 seconds
Started May 12 03:45:09 PM PDT 24
Finished May 12 03:45:27 PM PDT 24
Peak memory 214300 kb
Host smart-bb7818b1-b3a4-4d03-8075-9d056e00a112
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1628408052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.1628408052
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3100243601
Short name T111
Test name
Test status
Simulation time 183946096 ps
CPU time 3.37 seconds
Started May 12 04:08:03 PM PDT 24
Finished May 12 04:08:07 PM PDT 24
Peak memory 214220 kb
Host smart-45ca8863-22d7-42ff-9c59-ec8387867a07
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100243601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.3100243601
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.409511051
Short name T22
Test name
Test status
Simulation time 167728422 ps
CPU time 2.24 seconds
Started May 12 03:45:21 PM PDT 24
Finished May 12 03:45:26 PM PDT 24
Peak memory 215452 kb
Host smart-24a410f5-d72f-4f4b-9285-4cbf88990716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409511051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.409511051
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.1796238169
Short name T76
Test name
Test status
Simulation time 9628250014 ps
CPU time 272.6 seconds
Started May 12 03:48:08 PM PDT 24
Finished May 12 03:52:41 PM PDT 24
Peak memory 217724 kb
Host smart-d8c3bb68-b46d-49a2-b92e-9008a107b4c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796238169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.1796238169
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.165585887
Short name T56
Test name
Test status
Simulation time 55495664 ps
CPU time 3.71 seconds
Started May 12 03:48:25 PM PDT 24
Finished May 12 03:48:29 PM PDT 24
Peak memory 218364 kb
Host smart-a45fec24-eb0a-4ef8-94c7-8529b8db8a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165585887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.165585887
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.2040641398
Short name T64
Test name
Test status
Simulation time 2536382681 ps
CPU time 24.7 seconds
Started May 12 03:44:47 PM PDT 24
Finished May 12 03:45:13 PM PDT 24
Peak memory 222772 kb
Host smart-6987561b-de61-46da-9f95-c160e4e32ad1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040641398 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.2040641398
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.2380626037
Short name T402
Test name
Test status
Simulation time 1357313455 ps
CPU time 74.29 seconds
Started May 12 03:44:17 PM PDT 24
Finished May 12 03:45:32 PM PDT 24
Peak memory 215012 kb
Host smart-3db96b81-d54f-46fc-949a-8f38f0f24f65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2380626037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.2380626037
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.3251450535
Short name T39
Test name
Test status
Simulation time 257979137 ps
CPU time 3.24 seconds
Started May 12 03:47:58 PM PDT 24
Finished May 12 03:48:01 PM PDT 24
Peak memory 216880 kb
Host smart-de1db97e-1577-4ca5-afac-57d6fe6547b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251450535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.3251450535
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.1366689275
Short name T23
Test name
Test status
Simulation time 2437845665 ps
CPU time 16.99 seconds
Started May 12 03:46:05 PM PDT 24
Finished May 12 03:46:23 PM PDT 24
Peak memory 214416 kb
Host smart-6fa07f5d-a60a-4816-80de-78b5c46e5dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366689275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.1366689275
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.55917044
Short name T314
Test name
Test status
Simulation time 135641242 ps
CPU time 6.5 seconds
Started May 12 03:46:01 PM PDT 24
Finished May 12 03:46:08 PM PDT 24
Peak memory 215248 kb
Host smart-b8eba27b-0b52-42e7-b4ff-08fa1ad69277
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=55917044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.55917044
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.3230335562
Short name T31
Test name
Test status
Simulation time 233730533 ps
CPU time 3.6 seconds
Started May 12 03:49:37 PM PDT 24
Finished May 12 03:49:41 PM PDT 24
Peak memory 220364 kb
Host smart-bfcfa693-16f8-4e43-b9c6-838653d70778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230335562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.3230335562
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.2212434130
Short name T134
Test name
Test status
Simulation time 436916898 ps
CPU time 6.74 seconds
Started May 12 04:08:17 PM PDT 24
Finished May 12 04:08:24 PM PDT 24
Peak memory 205516 kb
Host smart-5fdf9c6b-a81b-4376-be01-43156b7d636e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212434130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.2212434130
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.2192774169
Short name T121
Test name
Test status
Simulation time 734768195 ps
CPU time 9.14 seconds
Started May 12 03:48:23 PM PDT 24
Finished May 12 03:48:32 PM PDT 24
Peak memory 214332 kb
Host smart-4e30f33b-e4f5-4efb-887d-04bd7beddd46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2192774169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.2192774169
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.2674037900
Short name T38
Test name
Test status
Simulation time 294235679 ps
CPU time 11.82 seconds
Started May 12 03:48:31 PM PDT 24
Finished May 12 03:48:43 PM PDT 24
Peak memory 214188 kb
Host smart-43eaf735-222e-439f-ae4d-83fc38a5a5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674037900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.2674037900
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.2031056586
Short name T75
Test name
Test status
Simulation time 4130614056 ps
CPU time 48.92 seconds
Started May 12 03:46:37 PM PDT 24
Finished May 12 03:47:26 PM PDT 24
Peak memory 216148 kb
Host smart-4443cb24-7123-4c43-b94f-83886e625cdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031056586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.2031056586
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.3150171972
Short name T417
Test name
Test status
Simulation time 10999716 ps
CPU time 0.78 seconds
Started May 12 03:44:10 PM PDT 24
Finished May 12 03:44:11 PM PDT 24
Peak memory 205940 kb
Host smart-a22145f3-a1da-495b-b9b5-5d19ff41dea6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150171972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.3150171972
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.3438719969
Short name T225
Test name
Test status
Simulation time 65466147 ps
CPU time 3.05 seconds
Started May 12 03:47:52 PM PDT 24
Finished May 12 03:47:56 PM PDT 24
Peak memory 216312 kb
Host smart-58da834b-4c4e-46be-a2f7-ab268f6bb2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438719969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.3438719969
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.481547927
Short name T248
Test name
Test status
Simulation time 7772049988 ps
CPU time 29.63 seconds
Started May 12 03:47:33 PM PDT 24
Finished May 12 03:48:03 PM PDT 24
Peak memory 222592 kb
Host smart-c09e85ee-6873-41de-830d-7350a4d47785
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481547927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.481547927
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.3760763157
Short name T278
Test name
Test status
Simulation time 498152704 ps
CPU time 14.08 seconds
Started May 12 03:49:35 PM PDT 24
Finished May 12 03:49:49 PM PDT 24
Peak memory 215804 kb
Host smart-6d24c7ba-d9ce-407b-83e4-4dadbb0cc1ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3760763157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.3760763157
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.3705596167
Short name T144
Test name
Test status
Simulation time 733773217 ps
CPU time 8.29 seconds
Started May 12 04:08:29 PM PDT 24
Finished May 12 04:08:38 PM PDT 24
Peak memory 213880 kb
Host smart-3f2f8329-54c2-4a8f-8847-8774d40cb12c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705596167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.3705596167
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.2432106361
Short name T93
Test name
Test status
Simulation time 9933387727 ps
CPU time 89.27 seconds
Started May 12 03:48:31 PM PDT 24
Finished May 12 03:50:00 PM PDT 24
Peak memory 214432 kb
Host smart-1bbee84b-d3d5-44cd-9b04-d11e781a2f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432106361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2432106361
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.1581718453
Short name T25
Test name
Test status
Simulation time 944149468 ps
CPU time 7.66 seconds
Started May 12 03:49:20 PM PDT 24
Finished May 12 03:49:28 PM PDT 24
Peak memory 220720 kb
Host smart-d6c762eb-56d6-4c04-a08c-3df9321f428e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581718453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.1581718453
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.3938717959
Short name T214
Test name
Test status
Simulation time 197762150 ps
CPU time 4.01 seconds
Started May 12 03:43:51 PM PDT 24
Finished May 12 03:43:55 PM PDT 24
Peak memory 214284 kb
Host smart-9a4c302b-f5ff-456e-a5e4-5995eae71bcb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3938717959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.3938717959
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.1273604976
Short name T227
Test name
Test status
Simulation time 124763560 ps
CPU time 5.01 seconds
Started May 12 03:44:59 PM PDT 24
Finished May 12 03:45:04 PM PDT 24
Peak memory 214200 kb
Host smart-64b763d6-3bb9-4f7c-8305-c08dc8839839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273604976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.1273604976
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.214801853
Short name T130
Test name
Test status
Simulation time 947415245 ps
CPU time 8.26 seconds
Started May 12 04:08:22 PM PDT 24
Finished May 12 04:08:31 PM PDT 24
Peak memory 214092 kb
Host smart-0bc4e27a-a21e-4b37-8f82-1e2fe70be3bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214801853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err
.214801853
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.1546507870
Short name T208
Test name
Test status
Simulation time 1500979335 ps
CPU time 62.44 seconds
Started May 12 03:48:25 PM PDT 24
Finished May 12 03:49:28 PM PDT 24
Peak memory 222456 kb
Host smart-052d6854-0a8e-441d-8a3a-168aa5c54c81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546507870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.1546507870
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.635999430
Short name T163
Test name
Test status
Simulation time 191741726 ps
CPU time 4.36 seconds
Started May 12 03:48:39 PM PDT 24
Finished May 12 03:48:44 PM PDT 24
Peak memory 222540 kb
Host smart-96beeb4e-4964-4145-8a40-962c16ab50f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635999430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.635999430
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.3922045629
Short name T55
Test name
Test status
Simulation time 60404488 ps
CPU time 3.04 seconds
Started May 12 03:49:11 PM PDT 24
Finished May 12 03:49:15 PM PDT 24
Peak memory 222544 kb
Host smart-87875b73-afc3-4401-8033-3ca5fdf53f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922045629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.3922045629
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.337732307
Short name T157
Test name
Test status
Simulation time 739836155 ps
CPU time 3.84 seconds
Started May 12 03:46:17 PM PDT 24
Finished May 12 03:46:21 PM PDT 24
Peak memory 222612 kb
Host smart-aa8893ad-4b85-4ed9-9b4b-1fcf51ee19b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337732307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.337732307
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.1821343053
Short name T259
Test name
Test status
Simulation time 905377838 ps
CPU time 13.76 seconds
Started May 12 03:47:07 PM PDT 24
Finished May 12 03:47:21 PM PDT 24
Peak memory 208920 kb
Host smart-0358a383-5830-4726-a8fd-4537bb67fccd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821343053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.1821343053
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.1952186163
Short name T6
Test name
Test status
Simulation time 3191321358 ps
CPU time 24.4 seconds
Started May 12 03:50:12 PM PDT 24
Finished May 12 03:50:37 PM PDT 24
Peak memory 222740 kb
Host smart-20775274-18f5-4b15-8acc-36607431577c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952186163 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.1952186163
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.1185952037
Short name T321
Test name
Test status
Simulation time 213764332 ps
CPU time 3.34 seconds
Started May 12 03:45:40 PM PDT 24
Finished May 12 03:45:45 PM PDT 24
Peak memory 214260 kb
Host smart-80dec554-db34-425c-9a14-b21aed1ae01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185952037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.1185952037
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.3519704029
Short name T191
Test name
Test status
Simulation time 92824089 ps
CPU time 3.37 seconds
Started May 12 03:43:59 PM PDT 24
Finished May 12 03:44:03 PM PDT 24
Peak memory 210816 kb
Host smart-8a77036d-ab09-4e1f-9650-53b5a9849492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519704029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.3519704029
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.2135587768
Short name T147
Test name
Test status
Simulation time 689791777 ps
CPU time 4.8 seconds
Started May 12 04:08:28 PM PDT 24
Finished May 12 04:08:33 PM PDT 24
Peak memory 205712 kb
Host smart-c7b0fd13-7bd7-4e74-af3b-4e96a08b9a85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135587768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.2135587768
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.3703219327
Short name T140
Test name
Test status
Simulation time 142818010 ps
CPU time 5.83 seconds
Started May 12 04:08:15 PM PDT 24
Finished May 12 04:08:21 PM PDT 24
Peak memory 205692 kb
Host smart-087a73b5-6819-4443-a137-10e7cfb2b15b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703219327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.3703219327
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.419783806
Short name T21
Test name
Test status
Simulation time 42756000 ps
CPU time 1.74 seconds
Started May 12 03:49:21 PM PDT 24
Finished May 12 03:49:24 PM PDT 24
Peak memory 214536 kb
Host smart-63badc2f-8122-49d7-9900-aa89d00c52ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419783806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.419783806
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.3966404818
Short name T158
Test name
Test status
Simulation time 37005358 ps
CPU time 2.22 seconds
Started May 12 03:47:18 PM PDT 24
Finished May 12 03:47:20 PM PDT 24
Peak memory 215844 kb
Host smart-629cc7d4-2523-43d1-8c2f-520e0c97b25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966404818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.3966404818
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.3797239155
Short name T362
Test name
Test status
Simulation time 383550823 ps
CPU time 4.47 seconds
Started May 12 03:43:32 PM PDT 24
Finished May 12 03:43:37 PM PDT 24
Peak memory 214224 kb
Host smart-e6bf799c-b6c2-479e-8b06-c10befc56330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797239155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.3797239155
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.3303146514
Short name T179
Test name
Test status
Simulation time 2662103267 ps
CPU time 40.47 seconds
Started May 12 03:46:29 PM PDT 24
Finished May 12 03:47:10 PM PDT 24
Peak memory 215264 kb
Host smart-fbe2465c-4de4-400c-bd40-108cd2f1a13c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303146514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.3303146514
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.3168203638
Short name T891
Test name
Test status
Simulation time 1000366430 ps
CPU time 17.28 seconds
Started May 12 03:47:26 PM PDT 24
Finished May 12 03:47:44 PM PDT 24
Peak memory 214232 kb
Host smart-2c2ae701-a041-4d9a-843b-b869f72e6e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168203638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.3168203638
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.282273452
Short name T293
Test name
Test status
Simulation time 277685338 ps
CPU time 8.08 seconds
Started May 12 03:47:43 PM PDT 24
Finished May 12 03:47:51 PM PDT 24
Peak memory 214316 kb
Host smart-f95a284c-e7d1-409c-a834-f3a64daf2221
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=282273452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.282273452
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.2763454923
Short name T74
Test name
Test status
Simulation time 506564773 ps
CPU time 20.7 seconds
Started May 12 03:48:02 PM PDT 24
Finished May 12 03:48:23 PM PDT 24
Peak memory 220096 kb
Host smart-2f1cc07f-78c3-4e55-86be-71fe48664fcb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763454923 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.2763454923
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.1390033359
Short name T65
Test name
Test status
Simulation time 159650659 ps
CPU time 11.88 seconds
Started May 12 03:48:32 PM PDT 24
Finished May 12 03:48:44 PM PDT 24
Peak memory 222516 kb
Host smart-e16fa1e2-cef7-4021-8fad-a6d4e4c1c103
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390033359 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.1390033359
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.3836632482
Short name T160
Test name
Test status
Simulation time 33349656 ps
CPU time 2.15 seconds
Started May 12 03:44:57 PM PDT 24
Finished May 12 03:45:00 PM PDT 24
Peak memory 216764 kb
Host smart-96e8095b-68e0-4219-bf19-73e7b969e0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836632482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.3836632482
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.2165932004
Short name T13
Test name
Test status
Simulation time 44592723 ps
CPU time 3.07 seconds
Started May 12 03:49:34 PM PDT 24
Finished May 12 03:49:38 PM PDT 24
Peak memory 214676 kb
Host smart-b04a4b00-3358-4bf3-a7b1-9ed376f056d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165932004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.2165932004
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.3254186410
Short name T159
Test name
Test status
Simulation time 66870435 ps
CPU time 3.76 seconds
Started May 12 03:49:44 PM PDT 24
Finished May 12 03:49:48 PM PDT 24
Peak memory 222504 kb
Host smart-6a30328b-0516-4c19-8efb-c108552e0a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254186410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.3254186410
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.3583775958
Short name T59
Test name
Test status
Simulation time 75483156 ps
CPU time 2.91 seconds
Started May 12 03:43:23 PM PDT 24
Finished May 12 03:43:26 PM PDT 24
Peak memory 208108 kb
Host smart-8f1c3c30-5f00-4deb-b801-d7ff217849a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583775958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.3583775958
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.3700287661
Short name T308
Test name
Test status
Simulation time 489322482 ps
CPU time 4.26 seconds
Started May 12 03:46:37 PM PDT 24
Finished May 12 03:46:42 PM PDT 24
Peak memory 214220 kb
Host smart-79421eac-600d-45d2-bbe3-52816f4ec0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700287661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.3700287661
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.1880236757
Short name T375
Test name
Test status
Simulation time 111790626 ps
CPU time 2.9 seconds
Started May 12 03:47:08 PM PDT 24
Finished May 12 03:47:11 PM PDT 24
Peak memory 210564 kb
Host smart-43ecb501-b12e-4dbb-8c22-100ac90bb5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880236757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.1880236757
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.562735558
Short name T888
Test name
Test status
Simulation time 774401848 ps
CPU time 10.89 seconds
Started May 12 03:47:22 PM PDT 24
Finished May 12 03:47:33 PM PDT 24
Peak memory 215444 kb
Host smart-14d09a35-de8d-40cb-a7f4-e7f485d65339
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=562735558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.562735558
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.476143914
Short name T277
Test name
Test status
Simulation time 147187234 ps
CPU time 3.72 seconds
Started May 12 03:48:05 PM PDT 24
Finished May 12 03:48:09 PM PDT 24
Peak memory 214464 kb
Host smart-01586bed-6225-4066-93fa-a8b316c0c850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476143914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.476143914
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.1323783115
Short name T271
Test name
Test status
Simulation time 106960427 ps
CPU time 2.77 seconds
Started May 12 03:48:22 PM PDT 24
Finished May 12 03:48:26 PM PDT 24
Peak memory 220464 kb
Host smart-f618c58a-a798-4529-92fe-83ba0b443d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323783115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.1323783115
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.1836890332
Short name T297
Test name
Test status
Simulation time 19899972365 ps
CPU time 503.57 seconds
Started May 12 03:49:05 PM PDT 24
Finished May 12 03:57:29 PM PDT 24
Peak memory 221796 kb
Host smart-8fff3972-0b04-4081-8b54-4ccd997d860f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836890332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.1836890332
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.4007098145
Short name T203
Test name
Test status
Simulation time 7785652085 ps
CPU time 64.61 seconds
Started May 12 03:49:51 PM PDT 24
Finished May 12 03:50:56 PM PDT 24
Peak memory 222492 kb
Host smart-6d81556a-95e3-44da-a273-bcbe756062d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007098145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.4007098145
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.4091666116
Short name T143
Test name
Test status
Simulation time 197209875 ps
CPU time 3.57 seconds
Started May 12 04:08:08 PM PDT 24
Finished May 12 04:08:12 PM PDT 24
Peak memory 213780 kb
Host smart-4aa19c73-bccb-4168-9a81-4797915de17a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091666116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.4091666116
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.680829771
Short name T146
Test name
Test status
Simulation time 528458639 ps
CPU time 4.38 seconds
Started May 12 04:08:29 PM PDT 24
Finished May 12 04:08:34 PM PDT 24
Peak memory 213876 kb
Host smart-508656ae-fca6-47c3-a7b7-b590910d0c87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680829771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_err
.680829771
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.1044482872
Short name T153
Test name
Test status
Simulation time 456488978 ps
CPU time 5.2 seconds
Started May 12 04:08:30 PM PDT 24
Finished May 12 04:08:36 PM PDT 24
Peak memory 213852 kb
Host smart-b7363cdb-4bc7-4859-8d20-41459659caf4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044482872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.1044482872
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.1479454052
Short name T150
Test name
Test status
Simulation time 203949319 ps
CPU time 3.06 seconds
Started May 12 04:08:11 PM PDT 24
Finished May 12 04:08:15 PM PDT 24
Peak memory 213884 kb
Host smart-306e37c2-569f-4ccd-8369-57129a94a5eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479454052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.1479454052
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.2073519683
Short name T135
Test name
Test status
Simulation time 325663062 ps
CPU time 4.1 seconds
Started May 12 03:46:54 PM PDT 24
Finished May 12 03:46:58 PM PDT 24
Peak memory 210376 kb
Host smart-b6d790a3-4506-43f7-8c6e-c9d56b35cc33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073519683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.2073519683
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.3270519380
Short name T162
Test name
Test status
Simulation time 221241755 ps
CPU time 3.88 seconds
Started May 12 03:47:52 PM PDT 24
Finished May 12 03:47:57 PM PDT 24
Peak memory 216456 kb
Host smart-33aac0f5-0dc5-46cc-b44d-56048452cda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270519380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.3270519380
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.3451370924
Short name T506
Test name
Test status
Simulation time 187849806 ps
CPU time 3.13 seconds
Started May 12 03:43:08 PM PDT 24
Finished May 12 03:43:11 PM PDT 24
Peak memory 208252 kb
Host smart-492dca01-f200-474b-9000-d61ec38f22f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451370924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.3451370924
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.1473002930
Short name T207
Test name
Test status
Simulation time 808183176 ps
CPU time 4.66 seconds
Started May 12 03:44:02 PM PDT 24
Finished May 12 03:44:07 PM PDT 24
Peak memory 221412 kb
Host smart-4848c921-b205-4d6e-b9a1-ddbc6cda00b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473002930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.1473002930
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.799062704
Short name T339
Test name
Test status
Simulation time 101807887 ps
CPU time 3.29 seconds
Started May 12 03:43:56 PM PDT 24
Finished May 12 03:44:00 PM PDT 24
Peak memory 214260 kb
Host smart-53de4bea-7b46-46c8-a7cc-0a0d475cc921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799062704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.799062704
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.4054700398
Short name T211
Test name
Test status
Simulation time 741367623 ps
CPU time 29.98 seconds
Started May 12 03:43:59 PM PDT 24
Finished May 12 03:44:30 PM PDT 24
Peak memory 216876 kb
Host smart-c798b5ea-0c96-4626-8d20-8cc802bc9b25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054700398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.4054700398
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.218257851
Short name T359
Test name
Test status
Simulation time 52748396 ps
CPU time 3.07 seconds
Started May 12 03:46:16 PM PDT 24
Finished May 12 03:46:20 PM PDT 24
Peak memory 219404 kb
Host smart-a81489ff-b058-47d6-ad64-31ed490f02f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218257851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.218257851
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.684813422
Short name T300
Test name
Test status
Simulation time 85331778 ps
CPU time 3.21 seconds
Started May 12 03:46:10 PM PDT 24
Finished May 12 03:46:14 PM PDT 24
Peak memory 207056 kb
Host smart-17864936-08c2-4985-af40-41b8abdd46fa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684813422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.684813422
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.4211160236
Short name T406
Test name
Test status
Simulation time 1248125569 ps
CPU time 35.67 seconds
Started May 12 03:46:22 PM PDT 24
Finished May 12 03:46:58 PM PDT 24
Peak memory 215332 kb
Host smart-a8c86907-a10b-4748-a21b-cfe6af1019d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4211160236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.4211160236
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.376472824
Short name T521
Test name
Test status
Simulation time 157303910 ps
CPU time 3.36 seconds
Started May 12 03:46:37 PM PDT 24
Finished May 12 03:46:40 PM PDT 24
Peak memory 210044 kb
Host smart-90841408-d556-4bfe-8e83-4eeddfcb7471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376472824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.376472824
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.1633966470
Short name T284
Test name
Test status
Simulation time 2775336718 ps
CPU time 18.27 seconds
Started May 12 03:46:39 PM PDT 24
Finished May 12 03:46:57 PM PDT 24
Peak memory 209184 kb
Host smart-1fd905c8-cbb0-4cb0-88c3-59d77b1667ba
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633966470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.1633966470
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.768549839
Short name T195
Test name
Test status
Simulation time 1315137867 ps
CPU time 28.73 seconds
Started May 12 03:47:08 PM PDT 24
Finished May 12 03:47:37 PM PDT 24
Peak memory 222468 kb
Host smart-ea9ced5d-ac34-4178-ac5e-49f7e51d4360
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768549839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.768549839
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.1493892774
Short name T366
Test name
Test status
Simulation time 399935450 ps
CPU time 5.32 seconds
Started May 12 03:47:14 PM PDT 24
Finished May 12 03:47:20 PM PDT 24
Peak memory 214300 kb
Host smart-23336306-4d12-4d7e-821b-d16f70c23979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493892774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.1493892774
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.1732979445
Short name T199
Test name
Test status
Simulation time 350037403 ps
CPU time 3.04 seconds
Started May 12 03:44:25 PM PDT 24
Finished May 12 03:44:28 PM PDT 24
Peak memory 222624 kb
Host smart-d8e5cade-fa3a-4aa8-ad5b-213bfdb821b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732979445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.1732979445
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.4115142760
Short name T305
Test name
Test status
Simulation time 24495721 ps
CPU time 2.01 seconds
Started May 12 03:47:42 PM PDT 24
Finished May 12 03:47:44 PM PDT 24
Peak memory 214304 kb
Host smart-db8048f0-5ee0-49f6-8608-600cda44820b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115142760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.4115142760
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.3307891484
Short name T329
Test name
Test status
Simulation time 3746920963 ps
CPU time 14.88 seconds
Started May 12 03:48:22 PM PDT 24
Finished May 12 03:48:38 PM PDT 24
Peak memory 222656 kb
Host smart-f21cd7b1-4bc8-4856-88ac-5ac75223dcaf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307891484 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.3307891484
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.294809774
Short name T276
Test name
Test status
Simulation time 87352847 ps
CPU time 3.69 seconds
Started May 12 03:48:21 PM PDT 24
Finished May 12 03:48:25 PM PDT 24
Peak memory 215344 kb
Host smart-38f52551-4f49-4c87-8fd4-35ea2ec9f524
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=294809774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.294809774
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.799947304
Short name T215
Test name
Test status
Simulation time 117927908 ps
CPU time 6.55 seconds
Started May 12 03:48:33 PM PDT 24
Finished May 12 03:48:40 PM PDT 24
Peak memory 214588 kb
Host smart-23109577-54b8-4592-96b5-721a2871c470
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=799947304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.799947304
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.964756241
Short name T352
Test name
Test status
Simulation time 152487536 ps
CPU time 4.18 seconds
Started May 12 03:49:00 PM PDT 24
Finished May 12 03:49:05 PM PDT 24
Peak memory 214472 kb
Host smart-85341bc7-53c3-493d-84d7-c0b3ce589013
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=964756241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.964756241
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.768677415
Short name T326
Test name
Test status
Simulation time 91673403 ps
CPU time 4.38 seconds
Started May 12 03:49:20 PM PDT 24
Finished May 12 03:49:25 PM PDT 24
Peak memory 214236 kb
Host smart-4356b1b5-0008-45d2-a932-26173dd34965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768677415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.768677415
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.397592410
Short name T115
Test name
Test status
Simulation time 2668149189 ps
CPU time 29.1 seconds
Started May 12 03:49:18 PM PDT 24
Finished May 12 03:49:48 PM PDT 24
Peak memory 222704 kb
Host smart-e4ecac6e-28f2-455b-b455-7fdf7fe03dbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397592410 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.397592410
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.1029559365
Short name T190
Test name
Test status
Simulation time 2558909010 ps
CPU time 51.33 seconds
Started May 12 03:45:03 PM PDT 24
Finished May 12 03:45:55 PM PDT 24
Peak memory 222568 kb
Host smart-94310072-a9f2-4357-9e45-f60a4755e00c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029559365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.1029559365
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.3807533761
Short name T258
Test name
Test status
Simulation time 43393158 ps
CPU time 2.61 seconds
Started May 12 03:49:21 PM PDT 24
Finished May 12 03:49:25 PM PDT 24
Peak memory 209716 kb
Host smart-e578f13a-9bba-4ef4-9d4b-916a63f15822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807533761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.3807533761
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.1217940112
Short name T164
Test name
Test status
Simulation time 274134031 ps
CPU time 4.93 seconds
Started May 12 03:50:02 PM PDT 24
Finished May 12 03:50:08 PM PDT 24
Peak memory 222480 kb
Host smart-19d69cc7-555b-4746-8ab7-81716c925310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217940112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.1217940112
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.3505366095
Short name T962
Test name
Test status
Simulation time 590491385 ps
CPU time 3.87 seconds
Started May 12 04:08:02 PM PDT 24
Finished May 12 04:08:07 PM PDT 24
Peak memory 205620 kb
Host smart-58088366-f561-499e-8f83-1044058b6d42
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505366095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.3
505366095
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.1971398208
Short name T1068
Test name
Test status
Simulation time 555758029 ps
CPU time 15.81 seconds
Started May 12 04:08:02 PM PDT 24
Finished May 12 04:08:18 PM PDT 24
Peak memory 205716 kb
Host smart-39940a6b-2e57-4721-86d9-f573a0151b90
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971398208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.1
971398208
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.848197529
Short name T990
Test name
Test status
Simulation time 56225011 ps
CPU time 1.23 seconds
Started May 12 04:08:01 PM PDT 24
Finished May 12 04:08:02 PM PDT 24
Peak memory 205692 kb
Host smart-e328ca61-8eff-49ed-8d04-207741d79e9c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848197529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.848197529
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2887625035
Short name T983
Test name
Test status
Simulation time 60196891 ps
CPU time 1.5 seconds
Started May 12 04:08:08 PM PDT 24
Finished May 12 04:08:10 PM PDT 24
Peak memory 213780 kb
Host smart-a2d24430-229c-4060-b5ae-9d0b7e52d617
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887625035 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.2887625035
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.133853714
Short name T1058
Test name
Test status
Simulation time 21770268 ps
CPU time 1.06 seconds
Started May 12 04:08:03 PM PDT 24
Finished May 12 04:08:05 PM PDT 24
Peak memory 205332 kb
Host smart-4161792c-1e7f-46f1-a9e0-a0e675551916
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133853714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.133853714
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.3819764263
Short name T931
Test name
Test status
Simulation time 50041178 ps
CPU time 0.97 seconds
Started May 12 04:08:01 PM PDT 24
Finished May 12 04:08:02 PM PDT 24
Peak memory 205612 kb
Host smart-c8e45bdd-478d-4c46-8f76-41c4dd17160d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819764263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.3819764263
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.198289405
Short name T1078
Test name
Test status
Simulation time 20232277 ps
CPU time 1.49 seconds
Started May 12 04:08:04 PM PDT 24
Finished May 12 04:08:06 PM PDT 24
Peak memory 205744 kb
Host smart-d31c32ae-3074-4bd5-9063-791c4864a3aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198289405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sam
e_csr_outstanding.198289405
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.2063576074
Short name T1075
Test name
Test status
Simulation time 252178856 ps
CPU time 1.94 seconds
Started May 12 04:07:56 PM PDT 24
Finished May 12 04:07:59 PM PDT 24
Peak memory 214320 kb
Host smart-6bc34bb4-5a68-4b72-9e3e-d693d6e92b58
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063576074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.2063576074
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.3979728572
Short name T964
Test name
Test status
Simulation time 594016983 ps
CPU time 8.69 seconds
Started May 12 04:07:56 PM PDT 24
Finished May 12 04:08:06 PM PDT 24
Peak memory 214188 kb
Host smart-f8482df1-c2a1-4a2e-a63f-5647a10cc49c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979728572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.3979728572
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1740989054
Short name T1054
Test name
Test status
Simulation time 265251988 ps
CPU time 3.04 seconds
Started May 12 04:07:59 PM PDT 24
Finished May 12 04:08:03 PM PDT 24
Peak memory 215988 kb
Host smart-98dd5151-a9d9-415c-8ded-1a00fe33360a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740989054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.1740989054
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.3924383983
Short name T148
Test name
Test status
Simulation time 296067245 ps
CPU time 4.92 seconds
Started May 12 04:08:02 PM PDT 24
Finished May 12 04:08:07 PM PDT 24
Peak memory 215116 kb
Host smart-d9e472e0-d754-40e7-abc2-70480ca27115
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924383983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.3924383983
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.582826576
Short name T122
Test name
Test status
Simulation time 177589616 ps
CPU time 4.6 seconds
Started May 12 04:08:02 PM PDT 24
Finished May 12 04:08:07 PM PDT 24
Peak memory 205728 kb
Host smart-7b7e718b-ec7b-4065-b8c3-729dcbb05486
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582826576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.582826576
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.2524955397
Short name T1063
Test name
Test status
Simulation time 539542401 ps
CPU time 6.6 seconds
Started May 12 04:08:02 PM PDT 24
Finished May 12 04:08:09 PM PDT 24
Peak memory 205736 kb
Host smart-7e556314-5d19-45ca-b4eb-9412c1ae7c2d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524955397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.2
524955397
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.1037162434
Short name T1034
Test name
Test status
Simulation time 20672172 ps
CPU time 1.16 seconds
Started May 12 04:08:04 PM PDT 24
Finished May 12 04:08:05 PM PDT 24
Peak memory 205676 kb
Host smart-99ee530e-4d6f-486d-aed5-cf17fd6d1289
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037162434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.1
037162434
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.3432724722
Short name T1073
Test name
Test status
Simulation time 71726538 ps
CPU time 1.56 seconds
Started May 12 04:08:05 PM PDT 24
Finished May 12 04:08:07 PM PDT 24
Peak memory 213944 kb
Host smart-80ecfd7d-eea7-4fad-870a-c4f7cfd29f5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432724722 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.3432724722
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.3441356188
Short name T982
Test name
Test status
Simulation time 87597800 ps
CPU time 1.21 seconds
Started May 12 04:08:06 PM PDT 24
Finished May 12 04:08:08 PM PDT 24
Peak memory 205584 kb
Host smart-a43597cb-011e-4f5d-affd-1aba5426b901
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441356188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.3441356188
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.239696045
Short name T1066
Test name
Test status
Simulation time 15111224 ps
CPU time 0.78 seconds
Started May 12 04:08:02 PM PDT 24
Finished May 12 04:08:03 PM PDT 24
Peak memory 205284 kb
Host smart-9d85b017-3a65-4c3a-99b2-ff650cf6c1ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239696045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.239696045
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.2555604014
Short name T1052
Test name
Test status
Simulation time 46588447 ps
CPU time 1.39 seconds
Started May 12 04:08:00 PM PDT 24
Finished May 12 04:08:02 PM PDT 24
Peak memory 213984 kb
Host smart-1c9b521c-6625-496d-986b-ff2dc7c0f19b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555604014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.2555604014
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.1296229259
Short name T1006
Test name
Test status
Simulation time 1503202469 ps
CPU time 15.39 seconds
Started May 12 04:08:08 PM PDT 24
Finished May 12 04:08:24 PM PDT 24
Peak memory 214284 kb
Host smart-4ff890db-e19e-4551-acdb-8bcd4accf496
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296229259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.1296229259
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.2552391742
Short name T1013
Test name
Test status
Simulation time 115178385 ps
CPU time 2.41 seconds
Started May 12 04:08:03 PM PDT 24
Finished May 12 04:08:06 PM PDT 24
Peak memory 213904 kb
Host smart-b56e2f4d-58f3-4cf4-9ab3-4b8d120d3ff1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552391742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.2552391742
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.2709825494
Short name T923
Test name
Test status
Simulation time 100430998 ps
CPU time 1.43 seconds
Started May 12 04:08:23 PM PDT 24
Finished May 12 04:08:25 PM PDT 24
Peak memory 213952 kb
Host smart-74f3a0fd-71f9-4e8a-9b4e-e28d1d0b7289
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709825494 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.2709825494
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.1675710544
Short name T1000
Test name
Test status
Simulation time 44509978 ps
CPU time 1 seconds
Started May 12 04:08:23 PM PDT 24
Finished May 12 04:08:24 PM PDT 24
Peak memory 205520 kb
Host smart-2e645f94-e0ae-443a-9047-4e66dab15099
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675710544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.1675710544
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1820016912
Short name T933
Test name
Test status
Simulation time 137804930 ps
CPU time 0.96 seconds
Started May 12 04:08:18 PM PDT 24
Finished May 12 04:08:19 PM PDT 24
Peak memory 205472 kb
Host smart-cb580ce2-7a49-4250-a4ce-0951928872bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820016912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.1820016912
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.880202733
Short name T125
Test name
Test status
Simulation time 52623953 ps
CPU time 1.94 seconds
Started May 12 04:08:17 PM PDT 24
Finished May 12 04:08:20 PM PDT 24
Peak memory 205624 kb
Host smart-ac698c69-3566-45d4-9185-56444fd74d15
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880202733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_sa
me_csr_outstanding.880202733
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.3750798121
Short name T963
Test name
Test status
Simulation time 78813639 ps
CPU time 1.93 seconds
Started May 12 04:08:18 PM PDT 24
Finished May 12 04:08:21 PM PDT 24
Peak memory 214260 kb
Host smart-7720cf13-ef28-42aa-a685-1463cd056bac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750798121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.3750798121
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3277995413
Short name T1057
Test name
Test status
Simulation time 634514769 ps
CPU time 5.48 seconds
Started May 12 04:08:20 PM PDT 24
Finished May 12 04:08:27 PM PDT 24
Peak memory 214128 kb
Host smart-749aade9-e94c-4868-a54c-1d28a524054e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277995413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.3277995413
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.3058536045
Short name T957
Test name
Test status
Simulation time 257457654 ps
CPU time 2.73 seconds
Started May 12 04:08:20 PM PDT 24
Finished May 12 04:08:24 PM PDT 24
Peak memory 213956 kb
Host smart-23949c88-e937-4d72-abe6-543a60277cd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058536045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.3058536045
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.2362013510
Short name T1035
Test name
Test status
Simulation time 24411096 ps
CPU time 1.47 seconds
Started May 12 04:08:19 PM PDT 24
Finished May 12 04:08:22 PM PDT 24
Peak memory 213900 kb
Host smart-06b7e065-3fd4-471f-ae93-14d1c47f9531
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362013510 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.2362013510
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.4026109659
Short name T1049
Test name
Test status
Simulation time 96729641 ps
CPU time 1.15 seconds
Started May 12 04:08:19 PM PDT 24
Finished May 12 04:08:21 PM PDT 24
Peak memory 205680 kb
Host smart-0caeefaa-73e0-4a91-880b-7de09c767dd9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026109659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.4026109659
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.2481265527
Short name T928
Test name
Test status
Simulation time 57238331 ps
CPU time 0.81 seconds
Started May 12 04:08:22 PM PDT 24
Finished May 12 04:08:24 PM PDT 24
Peak memory 205384 kb
Host smart-b2381d48-fc59-4874-9779-b5d92f3b5528
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481265527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.2481265527
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.1088105190
Short name T985
Test name
Test status
Simulation time 195981842 ps
CPU time 2.12 seconds
Started May 12 04:08:20 PM PDT 24
Finished May 12 04:08:23 PM PDT 24
Peak memory 205616 kb
Host smart-791faaea-e89f-4cfe-b42f-5c732a167808
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088105190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.1088105190
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.1055541431
Short name T109
Test name
Test status
Simulation time 487665231 ps
CPU time 3.97 seconds
Started May 12 04:08:19 PM PDT 24
Finished May 12 04:08:24 PM PDT 24
Peak memory 214192 kb
Host smart-b80f5fa8-22ad-401a-8f91-f5592afeb381
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055541431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.1055541431
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.1078009185
Short name T988
Test name
Test status
Simulation time 581209760 ps
CPU time 6.8 seconds
Started May 12 04:08:20 PM PDT 24
Finished May 12 04:08:28 PM PDT 24
Peak memory 220940 kb
Host smart-550915a0-1221-4a77-9b25-77ab495fd464
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078009185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.1078009185
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.274276506
Short name T1026
Test name
Test status
Simulation time 77148438 ps
CPU time 2.29 seconds
Started May 12 04:08:24 PM PDT 24
Finished May 12 04:08:27 PM PDT 24
Peak memory 213820 kb
Host smart-4a6280e5-0540-4802-9bf6-899a85a8dbaf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274276506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.274276506
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2293674602
Short name T1005
Test name
Test status
Simulation time 164245513 ps
CPU time 5.97 seconds
Started May 12 04:08:21 PM PDT 24
Finished May 12 04:08:28 PM PDT 24
Peak memory 205732 kb
Host smart-bfdb4a1d-957c-4427-a710-2a3f738e730d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293674602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.2293674602
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.782387516
Short name T1012
Test name
Test status
Simulation time 177367022 ps
CPU time 2.35 seconds
Started May 12 04:08:20 PM PDT 24
Finished May 12 04:08:24 PM PDT 24
Peak memory 213908 kb
Host smart-abf8f0f9-5101-4018-aa0d-72973096d372
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782387516 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.782387516
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.378607693
Short name T1069
Test name
Test status
Simulation time 28068729 ps
CPU time 1.51 seconds
Started May 12 04:08:19 PM PDT 24
Finished May 12 04:08:21 PM PDT 24
Peak memory 205748 kb
Host smart-d29920f2-9f56-4a6c-bca9-3b63e5b6ae06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378607693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.378607693
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.2522401853
Short name T1065
Test name
Test status
Simulation time 187372348 ps
CPU time 0.88 seconds
Started May 12 04:08:22 PM PDT 24
Finished May 12 04:08:23 PM PDT 24
Peak memory 205360 kb
Host smart-635ebc95-2aa2-4c36-a1af-ecb0a6f1ec37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522401853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.2522401853
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.4109046370
Short name T947
Test name
Test status
Simulation time 437191762 ps
CPU time 2.56 seconds
Started May 12 04:08:20 PM PDT 24
Finished May 12 04:08:24 PM PDT 24
Peak memory 205588 kb
Host smart-69e51b32-c4e8-4f73-a2c3-d24db24afea8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109046370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.4109046370
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.3935042867
Short name T1085
Test name
Test status
Simulation time 322891641 ps
CPU time 3.26 seconds
Started May 12 04:08:22 PM PDT 24
Finished May 12 04:08:26 PM PDT 24
Peak memory 214300 kb
Host smart-cb4eca08-ce2d-447d-a6c0-171775b61f05
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935042867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.3935042867
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.837765709
Short name T940
Test name
Test status
Simulation time 1373807996 ps
CPU time 11.17 seconds
Started May 12 04:08:21 PM PDT 24
Finished May 12 04:08:33 PM PDT 24
Peak memory 214176 kb
Host smart-f1c5c12f-6d7d-40a5-bd98-a385458a2573
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837765709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
keymgr_shadow_reg_errors_with_csr_rw.837765709
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.247888295
Short name T1048
Test name
Test status
Simulation time 190174389 ps
CPU time 3.44 seconds
Started May 12 04:08:20 PM PDT 24
Finished May 12 04:08:24 PM PDT 24
Peak memory 213976 kb
Host smart-82b283b8-abee-4a28-bc88-f5bf908cb81b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247888295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.247888295
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.1705620510
Short name T149
Test name
Test status
Simulation time 959539599 ps
CPU time 7.41 seconds
Started May 12 04:08:20 PM PDT 24
Finished May 12 04:08:29 PM PDT 24
Peak memory 205656 kb
Host smart-34d02b84-72e9-4cce-9906-8059cd3794c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705620510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.1705620510
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.352492916
Short name T1010
Test name
Test status
Simulation time 138504684 ps
CPU time 2.8 seconds
Started May 12 04:08:29 PM PDT 24
Finished May 12 04:08:32 PM PDT 24
Peak memory 213932 kb
Host smart-7e1265f0-82ef-49b6-9881-9f37c6ec3173
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352492916 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.352492916
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.3825109604
Short name T979
Test name
Test status
Simulation time 22453886 ps
CPU time 0.94 seconds
Started May 12 04:08:24 PM PDT 24
Finished May 12 04:08:26 PM PDT 24
Peak memory 205424 kb
Host smart-53d74b17-b71e-40ad-9f10-05ac449f110d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825109604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.3825109604
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3472936623
Short name T1038
Test name
Test status
Simulation time 32935065 ps
CPU time 0.85 seconds
Started May 12 04:08:26 PM PDT 24
Finished May 12 04:08:27 PM PDT 24
Peak memory 205244 kb
Host smart-2677ed56-81b7-4766-a0b5-26e1013453f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472936623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.3472936623
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.187141449
Short name T1056
Test name
Test status
Simulation time 76043532 ps
CPU time 1.36 seconds
Started May 12 04:08:26 PM PDT 24
Finished May 12 04:08:28 PM PDT 24
Peak memory 205592 kb
Host smart-f3ee12e0-c1b9-472b-9779-85878fb46e9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187141449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_sa
me_csr_outstanding.187141449
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1805743749
Short name T953
Test name
Test status
Simulation time 191285033 ps
CPU time 4.51 seconds
Started May 12 04:08:23 PM PDT 24
Finished May 12 04:08:29 PM PDT 24
Peak memory 214252 kb
Host smart-f8474d17-5da4-4927-85bf-0c43582df62c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805743749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.1805743749
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.798941308
Short name T966
Test name
Test status
Simulation time 941452737 ps
CPU time 5.41 seconds
Started May 12 04:08:25 PM PDT 24
Finished May 12 04:08:31 PM PDT 24
Peak memory 214172 kb
Host smart-50fd9577-61a4-4891-ba19-4d10bb0213d8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798941308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
keymgr_shadow_reg_errors_with_csr_rw.798941308
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.3252742367
Short name T1061
Test name
Test status
Simulation time 403455725 ps
CPU time 3.09 seconds
Started May 12 04:08:24 PM PDT 24
Finished May 12 04:08:28 PM PDT 24
Peak memory 222084 kb
Host smart-f1c143b6-68bd-49d6-b008-6444628d2ab9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252742367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.3252742367
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.3452871064
Short name T924
Test name
Test status
Simulation time 103428033 ps
CPU time 4.76 seconds
Started May 12 04:08:23 PM PDT 24
Finished May 12 04:08:29 PM PDT 24
Peak memory 213776 kb
Host smart-7c93afa1-63d1-41bc-9eb9-942e89777e6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452871064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.3452871064
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.4140222775
Short name T948
Test name
Test status
Simulation time 184817780 ps
CPU time 2.22 seconds
Started May 12 04:08:30 PM PDT 24
Finished May 12 04:08:33 PM PDT 24
Peak memory 213936 kb
Host smart-12130151-f8eb-4e2f-9eb3-cf411e1d2c09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140222775 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.4140222775
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.3561682017
Short name T932
Test name
Test status
Simulation time 31315842 ps
CPU time 0.94 seconds
Started May 12 04:08:30 PM PDT 24
Finished May 12 04:08:31 PM PDT 24
Peak memory 205500 kb
Host smart-675c04bc-67e6-4ac5-80e5-edeac0106e89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561682017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.3561682017
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.1129070358
Short name T926
Test name
Test status
Simulation time 13644102 ps
CPU time 0.75 seconds
Started May 12 04:08:25 PM PDT 24
Finished May 12 04:08:26 PM PDT 24
Peak memory 205288 kb
Host smart-41eb5b7c-9d74-4906-8aff-640111256004
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129070358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.1129070358
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.3947616433
Short name T1019
Test name
Test status
Simulation time 172486673 ps
CPU time 2.12 seconds
Started May 12 04:08:22 PM PDT 24
Finished May 12 04:08:25 PM PDT 24
Peak memory 205732 kb
Host smart-6caf5979-9b6e-4604-b096-f3ca8a9c7c84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947616433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.3947616433
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3975054226
Short name T110
Test name
Test status
Simulation time 239957203 ps
CPU time 1.95 seconds
Started May 12 04:08:22 PM PDT 24
Finished May 12 04:08:25 PM PDT 24
Peak memory 214204 kb
Host smart-07f53aa6-257d-40a5-86cd-6d4759990175
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975054226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.3975054226
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.3780226409
Short name T1029
Test name
Test status
Simulation time 643345099 ps
CPU time 6.34 seconds
Started May 12 04:08:22 PM PDT 24
Finished May 12 04:08:29 PM PDT 24
Peak memory 214100 kb
Host smart-d880fb2c-d127-483c-9dce-c753b0274446
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780226409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.3780226409
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.3325664740
Short name T1064
Test name
Test status
Simulation time 142084468 ps
CPU time 1.71 seconds
Started May 12 04:08:21 PM PDT 24
Finished May 12 04:08:24 PM PDT 24
Peak memory 215596 kb
Host smart-74fb2a46-1db3-4002-b093-26bfd062d9a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325664740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.3325664740
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.2673273627
Short name T977
Test name
Test status
Simulation time 69761659 ps
CPU time 2.31 seconds
Started May 12 04:08:27 PM PDT 24
Finished May 12 04:08:29 PM PDT 24
Peak memory 213860 kb
Host smart-3adaf18d-bce6-438f-b10c-aaa8c53b8332
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673273627 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.2673273627
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.3684365254
Short name T1027
Test name
Test status
Simulation time 118748640 ps
CPU time 1.02 seconds
Started May 12 04:08:29 PM PDT 24
Finished May 12 04:08:31 PM PDT 24
Peak memory 205604 kb
Host smart-1fc5224c-b06a-47fc-878f-6b9c02446f3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684365254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.3684365254
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.2272800628
Short name T1031
Test name
Test status
Simulation time 25572022 ps
CPU time 0.76 seconds
Started May 12 04:08:24 PM PDT 24
Finished May 12 04:08:26 PM PDT 24
Peak memory 205260 kb
Host smart-9aabcab2-b995-4ac5-8062-484d1fe0b096
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272800628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.2272800628
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.525377497
Short name T1060
Test name
Test status
Simulation time 1635547020 ps
CPU time 2.71 seconds
Started May 12 04:08:26 PM PDT 24
Finished May 12 04:08:30 PM PDT 24
Peak memory 205732 kb
Host smart-44b9af37-e306-4ff5-b6a2-6ecb1f89b7d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525377497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_sa
me_csr_outstanding.525377497
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.2676268693
Short name T992
Test name
Test status
Simulation time 189277270 ps
CPU time 2.23 seconds
Started May 12 04:08:26 PM PDT 24
Finished May 12 04:08:29 PM PDT 24
Peak memory 214300 kb
Host smart-5ca9dca2-beed-40db-a712-95717a7de498
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676268693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.2676268693
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.3755242624
Short name T1071
Test name
Test status
Simulation time 246238880 ps
CPU time 5.68 seconds
Started May 12 04:08:23 PM PDT 24
Finished May 12 04:08:30 PM PDT 24
Peak memory 221108 kb
Host smart-28fe9ee5-3e8a-48d1-b3fc-24fc78e4edbd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755242624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.3755242624
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.1796472847
Short name T935
Test name
Test status
Simulation time 144162230 ps
CPU time 3.48 seconds
Started May 12 04:08:25 PM PDT 24
Finished May 12 04:08:29 PM PDT 24
Peak memory 213800 kb
Host smart-e1196be2-4607-4112-99e2-37a8edc6e4b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796472847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.1796472847
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.3972132343
Short name T987
Test name
Test status
Simulation time 27148621 ps
CPU time 1.12 seconds
Started May 12 04:08:34 PM PDT 24
Finished May 12 04:08:36 PM PDT 24
Peak memory 205716 kb
Host smart-8b238e2d-370a-4e38-bd20-45886d920fff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972132343 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.3972132343
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.2314314531
Short name T1003
Test name
Test status
Simulation time 141713084 ps
CPU time 1.49 seconds
Started May 12 04:08:33 PM PDT 24
Finished May 12 04:08:36 PM PDT 24
Peak memory 205716 kb
Host smart-20a4c134-bee3-41c3-90d5-8aff5032a094
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314314531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.2314314531
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3988013098
Short name T955
Test name
Test status
Simulation time 14569574 ps
CPU time 0.81 seconds
Started May 12 04:08:28 PM PDT 24
Finished May 12 04:08:30 PM PDT 24
Peak memory 205300 kb
Host smart-9f99123a-dab0-45dc-9a27-7bf2461c4b49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988013098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.3988013098
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.404933969
Short name T975
Test name
Test status
Simulation time 111300750 ps
CPU time 1.45 seconds
Started May 12 04:08:34 PM PDT 24
Finished May 12 04:08:36 PM PDT 24
Peak memory 205652 kb
Host smart-d554d02d-b2a0-4a9d-849d-41adbf17cca5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404933969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_sa
me_csr_outstanding.404933969
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.2043985828
Short name T1041
Test name
Test status
Simulation time 133902739 ps
CPU time 2.17 seconds
Started May 12 04:08:23 PM PDT 24
Finished May 12 04:08:26 PM PDT 24
Peak memory 214336 kb
Host smart-7a301c1b-25c0-4b7e-b397-9a58317e84eb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043985828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.2043985828
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.1812073299
Short name T112
Test name
Test status
Simulation time 339187308 ps
CPU time 9.28 seconds
Started May 12 04:08:24 PM PDT 24
Finished May 12 04:08:34 PM PDT 24
Peak memory 214464 kb
Host smart-8b51dd63-1094-492c-b971-0a2b4b320cb3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812073299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.1812073299
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.369684547
Short name T972
Test name
Test status
Simulation time 159656999 ps
CPU time 3.09 seconds
Started May 12 04:08:29 PM PDT 24
Finished May 12 04:08:33 PM PDT 24
Peak memory 213848 kb
Host smart-7b63b783-3f24-4b67-9783-1bdb255fd4a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369684547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.369684547
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.3381509573
Short name T142
Test name
Test status
Simulation time 54454374 ps
CPU time 2.72 seconds
Started May 12 04:08:29 PM PDT 24
Finished May 12 04:08:33 PM PDT 24
Peak memory 213892 kb
Host smart-dc52237a-122e-4ca3-90f1-0920d3229f42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381509573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.3381509573
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.651153324
Short name T1053
Test name
Test status
Simulation time 225908223 ps
CPU time 1.66 seconds
Started May 12 04:08:33 PM PDT 24
Finished May 12 04:08:36 PM PDT 24
Peak memory 213880 kb
Host smart-ebd8068e-6f5c-4527-ac04-50e7eb098b27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651153324 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.651153324
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.3083204166
Short name T1016
Test name
Test status
Simulation time 34364331 ps
CPU time 0.81 seconds
Started May 12 04:08:28 PM PDT 24
Finished May 12 04:08:29 PM PDT 24
Peak memory 205500 kb
Host smart-7aaaa446-e47d-4966-8e95-af0639f2074b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083204166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.3083204166
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.2770058540
Short name T946
Test name
Test status
Simulation time 29460737 ps
CPU time 0.72 seconds
Started May 12 04:08:32 PM PDT 24
Finished May 12 04:08:33 PM PDT 24
Peak memory 205364 kb
Host smart-10bfe296-c9b3-4009-baf1-303d96eb0df3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770058540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.2770058540
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.2388294762
Short name T124
Test name
Test status
Simulation time 87484703 ps
CPU time 1.81 seconds
Started May 12 04:08:29 PM PDT 24
Finished May 12 04:08:32 PM PDT 24
Peak memory 205604 kb
Host smart-5b5c0524-d4c2-4581-8493-eda754756502
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388294762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.2388294762
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.2876340914
Short name T939
Test name
Test status
Simulation time 412949879 ps
CPU time 2.81 seconds
Started May 12 04:08:34 PM PDT 24
Finished May 12 04:08:38 PM PDT 24
Peak memory 214232 kb
Host smart-0d1440e4-a2b5-476f-8aa8-909f5e15dc3c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876340914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.2876340914
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2405654918
Short name T1055
Test name
Test status
Simulation time 153619054 ps
CPU time 7.6 seconds
Started May 12 04:08:28 PM PDT 24
Finished May 12 04:08:36 PM PDT 24
Peak memory 214316 kb
Host smart-00d09e97-01ee-40d4-9c9c-ed696c04142a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405654918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.2405654918
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.3105752873
Short name T919
Test name
Test status
Simulation time 31682015 ps
CPU time 2.4 seconds
Started May 12 04:08:28 PM PDT 24
Finished May 12 04:08:31 PM PDT 24
Peak memory 213872 kb
Host smart-508ff856-95c3-4576-83b0-75edbe04989f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105752873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.3105752873
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.3256175047
Short name T374
Test name
Test status
Simulation time 401908581 ps
CPU time 5.77 seconds
Started May 12 04:08:33 PM PDT 24
Finished May 12 04:08:40 PM PDT 24
Peak memory 205588 kb
Host smart-6cc2ffc4-ccbb-434f-b842-e3b4f1c40f49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256175047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.3256175047
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.378270428
Short name T936
Test name
Test status
Simulation time 102067430 ps
CPU time 1.51 seconds
Started May 12 04:08:34 PM PDT 24
Finished May 12 04:08:37 PM PDT 24
Peak memory 213920 kb
Host smart-9967ecda-13f2-40b2-889f-8c22719fa2f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378270428 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.378270428
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.1059863644
Short name T1062
Test name
Test status
Simulation time 419553982 ps
CPU time 1.36 seconds
Started May 12 04:08:30 PM PDT 24
Finished May 12 04:08:32 PM PDT 24
Peak memory 205676 kb
Host smart-1fe6ec39-21e5-4c3c-887b-b0ed3feab65a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059863644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.1059863644
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.2240558323
Short name T984
Test name
Test status
Simulation time 12800527 ps
CPU time 0.87 seconds
Started May 12 04:08:28 PM PDT 24
Finished May 12 04:08:30 PM PDT 24
Peak memory 205288 kb
Host smart-aad29ca5-d64a-4819-bd3a-53dae85f543f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240558323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.2240558323
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.352753597
Short name T986
Test name
Test status
Simulation time 57424183 ps
CPU time 1.48 seconds
Started May 12 04:08:29 PM PDT 24
Finished May 12 04:08:31 PM PDT 24
Peak memory 205624 kb
Host smart-323d242b-59e5-4eb3-9b21-77016a4b3e86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352753597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_sa
me_csr_outstanding.352753597
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3519092807
Short name T1074
Test name
Test status
Simulation time 315905337 ps
CPU time 4.63 seconds
Started May 12 04:08:34 PM PDT 24
Finished May 12 04:08:40 PM PDT 24
Peak memory 218960 kb
Host smart-9aa7ceab-248e-4ea6-a750-9a0da96e3e7c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519092807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.3519092807
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.1224354717
Short name T937
Test name
Test status
Simulation time 273318901 ps
CPU time 5.29 seconds
Started May 12 04:08:27 PM PDT 24
Finished May 12 04:08:33 PM PDT 24
Peak memory 213868 kb
Host smart-0c90bdd7-2678-4ad1-88a3-cb5fcfdf2b18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224354717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.1224354717
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1439432821
Short name T997
Test name
Test status
Simulation time 31178662 ps
CPU time 1.27 seconds
Started May 12 04:08:30 PM PDT 24
Finished May 12 04:08:32 PM PDT 24
Peak memory 213996 kb
Host smart-61457ac8-9a50-4a4e-83f2-a10581148b75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439432821 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.1439432821
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.3622605708
Short name T1021
Test name
Test status
Simulation time 23015526 ps
CPU time 1.16 seconds
Started May 12 04:08:34 PM PDT 24
Finished May 12 04:08:37 PM PDT 24
Peak memory 205656 kb
Host smart-fb6f963c-4d69-4ba3-971e-39de601de3b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622605708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.3622605708
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.1138926233
Short name T1002
Test name
Test status
Simulation time 24314941 ps
CPU time 0.79 seconds
Started May 12 04:08:29 PM PDT 24
Finished May 12 04:08:31 PM PDT 24
Peak memory 205368 kb
Host smart-f66b7114-067b-470b-a443-5137ee4944b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138926233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.1138926233
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.845753587
Short name T942
Test name
Test status
Simulation time 22907240 ps
CPU time 1.58 seconds
Started May 12 04:08:33 PM PDT 24
Finished May 12 04:08:36 PM PDT 24
Peak memory 205796 kb
Host smart-f60aab5d-2151-43ee-aafa-329ea6c560a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845753587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_sa
me_csr_outstanding.845753587
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.1106209776
Short name T967
Test name
Test status
Simulation time 255617165 ps
CPU time 3.02 seconds
Started May 12 04:08:30 PM PDT 24
Finished May 12 04:08:34 PM PDT 24
Peak memory 214236 kb
Host smart-69574444-13b9-4184-80ab-90ae6590cb07
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106209776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.1106209776
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.4143606020
Short name T958
Test name
Test status
Simulation time 92741583 ps
CPU time 5.17 seconds
Started May 12 04:08:33 PM PDT 24
Finished May 12 04:08:39 PM PDT 24
Peak memory 214188 kb
Host smart-864d0073-c2a0-42a9-9032-504863598223
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143606020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.4143606020
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.3029710168
Short name T1084
Test name
Test status
Simulation time 79870689 ps
CPU time 1.96 seconds
Started May 12 04:08:34 PM PDT 24
Finished May 12 04:08:37 PM PDT 24
Peak memory 216044 kb
Host smart-ff6056d1-071c-472e-b824-cd14e776af2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029710168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.3029710168
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3420340033
Short name T960
Test name
Test status
Simulation time 758510919 ps
CPU time 7.02 seconds
Started May 12 04:08:07 PM PDT 24
Finished May 12 04:08:15 PM PDT 24
Peak memory 205696 kb
Host smart-d4c7bc71-ee5c-47d9-9bcf-8135173e781d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420340033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.3
420340033
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.1966228954
Short name T1047
Test name
Test status
Simulation time 676926261 ps
CPU time 16.11 seconds
Started May 12 04:08:04 PM PDT 24
Finished May 12 04:08:21 PM PDT 24
Peak memory 205736 kb
Host smart-fd49fdbc-946a-45bf-b299-699dc17297b8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966228954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.1
966228954
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.660902731
Short name T1014
Test name
Test status
Simulation time 23339367 ps
CPU time 0.88 seconds
Started May 12 04:08:03 PM PDT 24
Finished May 12 04:08:05 PM PDT 24
Peak memory 205504 kb
Host smart-e6789bfe-51cb-4fc9-9124-9b242b23e70e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660902731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.660902731
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.4258264333
Short name T1028
Test name
Test status
Simulation time 256869296 ps
CPU time 1.72 seconds
Started May 12 04:08:05 PM PDT 24
Finished May 12 04:08:08 PM PDT 24
Peak memory 214028 kb
Host smart-5ad85e62-0cee-49bd-98d3-2ffd53894ed8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258264333 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.4258264333
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.2062313737
Short name T952
Test name
Test status
Simulation time 60601822 ps
CPU time 1.16 seconds
Started May 12 04:08:04 PM PDT 24
Finished May 12 04:08:06 PM PDT 24
Peak memory 205616 kb
Host smart-662e529c-145f-4eb0-b050-3e10c8015669
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062313737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.2062313737
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.4022883663
Short name T969
Test name
Test status
Simulation time 22402918 ps
CPU time 0.76 seconds
Started May 12 04:08:06 PM PDT 24
Finished May 12 04:08:07 PM PDT 24
Peak memory 205312 kb
Host smart-7f17ab3d-73a6-46d9-8d85-58173dd7328f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022883663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.4022883663
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.1779424319
Short name T994
Test name
Test status
Simulation time 37649738 ps
CPU time 1.52 seconds
Started May 12 04:08:03 PM PDT 24
Finished May 12 04:08:05 PM PDT 24
Peak memory 205716 kb
Host smart-8249b883-b2d3-477f-b8ba-06fe21d76ae4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779424319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.1779424319
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.3873470294
Short name T998
Test name
Test status
Simulation time 1001539274 ps
CPU time 3.78 seconds
Started May 12 04:08:04 PM PDT 24
Finished May 12 04:08:09 PM PDT 24
Peak memory 214244 kb
Host smart-36681602-5d63-4ba1-a591-d773aa593281
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873470294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.3873470294
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.853629636
Short name T995
Test name
Test status
Simulation time 260870866 ps
CPU time 4.03 seconds
Started May 12 04:08:06 PM PDT 24
Finished May 12 04:08:11 PM PDT 24
Peak memory 214280 kb
Host smart-38e90e7e-f3bc-4c4b-a786-6479671f3f64
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853629636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.k
eymgr_shadow_reg_errors_with_csr_rw.853629636
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.920313629
Short name T1040
Test name
Test status
Simulation time 135269898 ps
CPU time 4.83 seconds
Started May 12 04:08:04 PM PDT 24
Finished May 12 04:08:09 PM PDT 24
Peak memory 217100 kb
Host smart-f785e8fb-5402-4709-98d4-8f801c9cc551
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920313629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.920313629
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.1257716925
Short name T980
Test name
Test status
Simulation time 209527618 ps
CPU time 3.84 seconds
Started May 12 04:08:08 PM PDT 24
Finished May 12 04:08:13 PM PDT 24
Peak memory 205796 kb
Host smart-2950795a-dc27-4795-9a98-f41bd7082dba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257716925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.1257716925
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.362447384
Short name T1007
Test name
Test status
Simulation time 11573860 ps
CPU time 0.73 seconds
Started May 12 04:08:33 PM PDT 24
Finished May 12 04:08:35 PM PDT 24
Peak memory 205320 kb
Host smart-5975000a-25f2-485f-8c74-2e2ca3532ede
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362447384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.362447384
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.2858282124
Short name T971
Test name
Test status
Simulation time 13419141 ps
CPU time 0.91 seconds
Started May 12 04:08:31 PM PDT 24
Finished May 12 04:08:33 PM PDT 24
Peak memory 205464 kb
Host smart-f60c5054-3c60-40a5-92bd-2fa46a2584e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858282124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.2858282124
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.3026665767
Short name T999
Test name
Test status
Simulation time 10389075 ps
CPU time 0.8 seconds
Started May 12 04:08:30 PM PDT 24
Finished May 12 04:08:32 PM PDT 24
Peak memory 205316 kb
Host smart-b62f66c4-05c4-4e54-a2b9-968e21d90ea2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026665767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.3026665767
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.493515392
Short name T1082
Test name
Test status
Simulation time 11669270 ps
CPU time 0.76 seconds
Started May 12 04:08:31 PM PDT 24
Finished May 12 04:08:33 PM PDT 24
Peak memory 205324 kb
Host smart-b8315178-ff83-4121-af61-7d4be4e08cb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493515392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.493515392
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.1391947558
Short name T1080
Test name
Test status
Simulation time 14140520 ps
CPU time 0.92 seconds
Started May 12 04:08:32 PM PDT 24
Finished May 12 04:08:34 PM PDT 24
Peak memory 205536 kb
Host smart-d4e01cfd-88e2-476b-9707-3a0fdc6e4a9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391947558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.1391947558
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.3033231123
Short name T1022
Test name
Test status
Simulation time 26729148 ps
CPU time 0.75 seconds
Started May 12 04:08:35 PM PDT 24
Finished May 12 04:08:37 PM PDT 24
Peak memory 205340 kb
Host smart-812cfc91-a1f2-45ae-86fc-9e447fd4f339
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033231123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.3033231123
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.3975999925
Short name T1072
Test name
Test status
Simulation time 12178028 ps
CPU time 0.87 seconds
Started May 12 04:08:34 PM PDT 24
Finished May 12 04:08:36 PM PDT 24
Peak memory 205348 kb
Host smart-a28003f8-a46d-46b4-bdad-9e0b45898b9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975999925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.3975999925
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.3381850250
Short name T1033
Test name
Test status
Simulation time 12592322 ps
CPU time 0.77 seconds
Started May 12 04:08:30 PM PDT 24
Finished May 12 04:08:32 PM PDT 24
Peak memory 205284 kb
Host smart-8270db39-2630-4aff-9076-10db4cbc11aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381850250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.3381850250
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.2914083657
Short name T978
Test name
Test status
Simulation time 41576710 ps
CPU time 0.81 seconds
Started May 12 04:08:32 PM PDT 24
Finished May 12 04:08:34 PM PDT 24
Peak memory 205388 kb
Host smart-c0ab840c-7520-47f1-9e09-9a8a3b526927
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914083657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.2914083657
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.1710282234
Short name T1036
Test name
Test status
Simulation time 18495533 ps
CPU time 0.84 seconds
Started May 12 04:08:32 PM PDT 24
Finished May 12 04:08:34 PM PDT 24
Peak memory 205396 kb
Host smart-26d9ed4f-41a7-4639-a585-816123afb4cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710282234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.1710282234
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.737095670
Short name T1011
Test name
Test status
Simulation time 1558525549 ps
CPU time 7.5 seconds
Started May 12 04:08:15 PM PDT 24
Finished May 12 04:08:23 PM PDT 24
Peak memory 205696 kb
Host smart-b966ded5-3858-4255-b3be-bac8305d9d9b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737095670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.737095670
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.3216573144
Short name T1018
Test name
Test status
Simulation time 1448687246 ps
CPU time 6.77 seconds
Started May 12 04:08:12 PM PDT 24
Finished May 12 04:08:19 PM PDT 24
Peak memory 205744 kb
Host smart-bcb77f34-a936-470d-8abb-c2c78dcd017b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216573144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.3
216573144
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.4072296630
Short name T951
Test name
Test status
Simulation time 24845973 ps
CPU time 0.91 seconds
Started May 12 04:08:08 PM PDT 24
Finished May 12 04:08:10 PM PDT 24
Peak memory 205492 kb
Host smart-f27f6ff8-0cca-4b26-ae81-ecc3cc10a3fe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072296630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.4
072296630
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.3582710564
Short name T925
Test name
Test status
Simulation time 113303011 ps
CPU time 2.05 seconds
Started May 12 04:08:09 PM PDT 24
Finished May 12 04:08:11 PM PDT 24
Peak memory 214008 kb
Host smart-73a34654-1f91-4bf6-a0a9-b3b9bff2520c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582710564 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.3582710564
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.2970146915
Short name T126
Test name
Test status
Simulation time 40580680 ps
CPU time 0.99 seconds
Started May 12 04:08:08 PM PDT 24
Finished May 12 04:08:10 PM PDT 24
Peak memory 205492 kb
Host smart-000fcaca-86a6-4505-b195-cc1483a407af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970146915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.2970146915
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.2796328752
Short name T970
Test name
Test status
Simulation time 30459988 ps
CPU time 0.76 seconds
Started May 12 04:08:14 PM PDT 24
Finished May 12 04:08:16 PM PDT 24
Peak memory 205388 kb
Host smart-500497ab-fee2-48db-936b-48211b75d348
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796328752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.2796328752
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.2126798547
Short name T973
Test name
Test status
Simulation time 630483613 ps
CPU time 2.46 seconds
Started May 12 04:08:10 PM PDT 24
Finished May 12 04:08:13 PM PDT 24
Peak memory 205684 kb
Host smart-c938905e-0f73-4ee8-901c-157839553843
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126798547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.2126798547
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1196907151
Short name T1070
Test name
Test status
Simulation time 165989429 ps
CPU time 3.37 seconds
Started May 12 04:08:08 PM PDT 24
Finished May 12 04:08:12 PM PDT 24
Peak memory 214248 kb
Host smart-03a846c2-f39c-4d8f-9fa1-d4f6b9e0cd8f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196907151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.1196907151
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1264307104
Short name T1081
Test name
Test status
Simulation time 199439063 ps
CPU time 4.82 seconds
Started May 12 04:08:05 PM PDT 24
Finished May 12 04:08:10 PM PDT 24
Peak memory 214220 kb
Host smart-bbaf31c4-8a29-4703-ad11-7d5d58ad2caa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264307104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.1264307104
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.4179752359
Short name T917
Test name
Test status
Simulation time 28328039 ps
CPU time 1.65 seconds
Started May 12 04:08:04 PM PDT 24
Finished May 12 04:08:06 PM PDT 24
Peak memory 213848 kb
Host smart-fffa3ae9-8093-4608-9e5d-0e4c9367d574
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179752359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.4179752359
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.2570834654
Short name T1025
Test name
Test status
Simulation time 446714240 ps
CPU time 3.6 seconds
Started May 12 04:08:04 PM PDT 24
Finished May 12 04:08:09 PM PDT 24
Peak memory 215124 kb
Host smart-0ca68451-d058-4316-887a-b8f3352d62b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570834654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.2570834654
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.2310042575
Short name T956
Test name
Test status
Simulation time 15227991 ps
CPU time 0.75 seconds
Started May 12 04:08:33 PM PDT 24
Finished May 12 04:08:35 PM PDT 24
Peak memory 205372 kb
Host smart-ff68435c-9568-43b4-a439-ec6b03c08b76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310042575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.2310042575
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.1994840989
Short name T1086
Test name
Test status
Simulation time 30036528 ps
CPU time 0.75 seconds
Started May 12 04:08:33 PM PDT 24
Finished May 12 04:08:35 PM PDT 24
Peak memory 205364 kb
Host smart-ec70b6ec-8b60-476d-8934-1aa2de1de1e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994840989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.1994840989
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.1406796471
Short name T1015
Test name
Test status
Simulation time 25057583 ps
CPU time 0.72 seconds
Started May 12 04:08:33 PM PDT 24
Finished May 12 04:08:35 PM PDT 24
Peak memory 205284 kb
Host smart-2293bfcf-407f-4a2c-89ea-2e0fb5b2f75e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406796471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.1406796471
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.758143017
Short name T914
Test name
Test status
Simulation time 17351897 ps
CPU time 0.86 seconds
Started May 12 04:08:34 PM PDT 24
Finished May 12 04:08:36 PM PDT 24
Peak memory 205320 kb
Host smart-30b92d3f-ccaa-443b-ab18-478e8f8bd1a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758143017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.758143017
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1991087053
Short name T1077
Test name
Test status
Simulation time 53308040 ps
CPU time 0.74 seconds
Started May 12 04:08:32 PM PDT 24
Finished May 12 04:08:33 PM PDT 24
Peak memory 205364 kb
Host smart-cc105b56-a4d2-4f44-881c-e9bc781d53c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991087053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.1991087053
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.582274493
Short name T1044
Test name
Test status
Simulation time 59146199 ps
CPU time 0.75 seconds
Started May 12 04:08:34 PM PDT 24
Finished May 12 04:08:36 PM PDT 24
Peak memory 205376 kb
Host smart-b720d90e-86a9-4995-81a9-351a0252f8ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582274493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.582274493
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.2855884583
Short name T1023
Test name
Test status
Simulation time 127564078 ps
CPU time 0.82 seconds
Started May 12 04:08:33 PM PDT 24
Finished May 12 04:08:35 PM PDT 24
Peak memory 205388 kb
Host smart-1fc28573-5994-4070-965e-9b904fef4813
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855884583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.2855884583
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.2805002779
Short name T968
Test name
Test status
Simulation time 39603973 ps
CPU time 0.74 seconds
Started May 12 04:08:33 PM PDT 24
Finished May 12 04:08:35 PM PDT 24
Peak memory 205400 kb
Host smart-080db8aa-15d2-4a81-a684-2121968a7ea7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805002779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.2805002779
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.1418876199
Short name T1042
Test name
Test status
Simulation time 12233134 ps
CPU time 0.76 seconds
Started May 12 04:08:34 PM PDT 24
Finished May 12 04:08:36 PM PDT 24
Peak memory 205364 kb
Host smart-f2270309-5d34-48b8-86f7-a1695c921368
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418876199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.1418876199
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.1573544265
Short name T941
Test name
Test status
Simulation time 7331089 ps
CPU time 0.7 seconds
Started May 12 04:08:33 PM PDT 24
Finished May 12 04:08:35 PM PDT 24
Peak memory 205340 kb
Host smart-6179a2aa-b93d-4d74-999b-db78aa4647b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573544265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.1573544265
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.3508120060
Short name T944
Test name
Test status
Simulation time 964685809 ps
CPU time 6.41 seconds
Started May 12 04:08:11 PM PDT 24
Finished May 12 04:08:18 PM PDT 24
Peak memory 205676 kb
Host smart-3021aa2b-9313-49e8-a384-9774699a13b5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508120060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.3
508120060
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2588626354
Short name T959
Test name
Test status
Simulation time 12217028755 ps
CPU time 15.87 seconds
Started May 12 04:08:08 PM PDT 24
Finished May 12 04:08:24 PM PDT 24
Peak memory 205716 kb
Host smart-cbc0a366-cbf8-4659-ba5e-c260773722bf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588626354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.2
588626354
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.754216530
Short name T961
Test name
Test status
Simulation time 126629890 ps
CPU time 1.63 seconds
Started May 12 04:08:12 PM PDT 24
Finished May 12 04:08:14 PM PDT 24
Peak memory 205648 kb
Host smart-3cf6a2c6-edde-4ae0-abe2-dad4843826a4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754216530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.754216530
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.1403471938
Short name T1043
Test name
Test status
Simulation time 320049799 ps
CPU time 1.57 seconds
Started May 12 04:08:12 PM PDT 24
Finished May 12 04:08:14 PM PDT 24
Peak memory 213916 kb
Host smart-e0df5f9c-b313-4193-9be4-145a730ac21d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403471938 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.1403471938
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.1779571811
Short name T1079
Test name
Test status
Simulation time 33719151 ps
CPU time 0.91 seconds
Started May 12 04:08:09 PM PDT 24
Finished May 12 04:08:11 PM PDT 24
Peak memory 205452 kb
Host smart-9844144f-0197-4d11-aab9-2878cceff30d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779571811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.1779571811
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.2916498528
Short name T1004
Test name
Test status
Simulation time 8538355 ps
CPU time 0.78 seconds
Started May 12 04:08:08 PM PDT 24
Finished May 12 04:08:09 PM PDT 24
Peak memory 205304 kb
Host smart-116e744f-277c-4c24-a139-1a58f49bb3b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916498528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.2916498528
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.3382440260
Short name T981
Test name
Test status
Simulation time 40281424 ps
CPU time 2.45 seconds
Started May 12 04:08:09 PM PDT 24
Finished May 12 04:08:12 PM PDT 24
Peak memory 205688 kb
Host smart-e777f941-72a9-4100-abb3-8ccfb9f5b2ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382440260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.3382440260
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.522782410
Short name T991
Test name
Test status
Simulation time 77504175 ps
CPU time 1.78 seconds
Started May 12 04:08:07 PM PDT 24
Finished May 12 04:08:09 PM PDT 24
Peak memory 214272 kb
Host smart-a13de2b4-7616-40fe-b9bc-cab631339780
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522782410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow
_reg_errors.522782410
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.901195359
Short name T104
Test name
Test status
Simulation time 228719897 ps
CPU time 5.01 seconds
Started May 12 04:08:15 PM PDT 24
Finished May 12 04:08:20 PM PDT 24
Peak memory 214188 kb
Host smart-d3126dd2-58e6-4275-812b-1dd938ea0555
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901195359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.k
eymgr_shadow_reg_errors_with_csr_rw.901195359
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.2571448053
Short name T974
Test name
Test status
Simulation time 170903778 ps
CPU time 3.59 seconds
Started May 12 04:08:08 PM PDT 24
Finished May 12 04:08:12 PM PDT 24
Peak memory 216388 kb
Host smart-23934a80-7327-40da-96ea-39600e482f34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571448053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.2571448053
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.2906303607
Short name T141
Test name
Test status
Simulation time 201377899 ps
CPU time 4.47 seconds
Started May 12 04:08:09 PM PDT 24
Finished May 12 04:08:14 PM PDT 24
Peak memory 205700 kb
Host smart-773bddf4-a32b-4563-b235-31d0427c6a01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906303607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.2906303607
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.1752370864
Short name T920
Test name
Test status
Simulation time 39530943 ps
CPU time 0.84 seconds
Started May 12 04:08:33 PM PDT 24
Finished May 12 04:08:34 PM PDT 24
Peak memory 205312 kb
Host smart-e1acb1b1-a59c-472d-8c76-15dc0948a731
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752370864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.1752370864
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.2983174784
Short name T993
Test name
Test status
Simulation time 26578565 ps
CPU time 0.75 seconds
Started May 12 04:08:34 PM PDT 24
Finished May 12 04:08:36 PM PDT 24
Peak memory 205344 kb
Host smart-b3bd5fd5-f6c4-4964-98b5-a15cc426c1d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983174784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.2983174784
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.193062944
Short name T921
Test name
Test status
Simulation time 14738344 ps
CPU time 0.8 seconds
Started May 12 04:08:34 PM PDT 24
Finished May 12 04:08:36 PM PDT 24
Peak memory 205392 kb
Host smart-fa6da1f9-ce6e-4e7a-8228-2e5401acec1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193062944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.193062944
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.3862730236
Short name T918
Test name
Test status
Simulation time 11080692 ps
CPU time 0.75 seconds
Started May 12 04:08:36 PM PDT 24
Finished May 12 04:08:37 PM PDT 24
Peak memory 205312 kb
Host smart-dad9a63e-32a5-49d8-a9d1-a18c6939a8b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862730236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.3862730236
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.660392868
Short name T915
Test name
Test status
Simulation time 26718150 ps
CPU time 0.71 seconds
Started May 12 04:08:35 PM PDT 24
Finished May 12 04:08:37 PM PDT 24
Peak memory 205324 kb
Host smart-cda55446-bcf1-43ee-922e-126782833f7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660392868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.660392868
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.4056378337
Short name T929
Test name
Test status
Simulation time 13451476 ps
CPU time 0.94 seconds
Started May 12 04:08:35 PM PDT 24
Finished May 12 04:08:37 PM PDT 24
Peak memory 205564 kb
Host smart-f676cc7d-e554-4ec7-a1df-e9e2e4c9ba82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056378337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.4056378337
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.3316722658
Short name T930
Test name
Test status
Simulation time 15201266 ps
CPU time 0.74 seconds
Started May 12 04:08:35 PM PDT 24
Finished May 12 04:08:37 PM PDT 24
Peak memory 205296 kb
Host smart-992c8221-69e4-4bbe-8468-ad11e03a1e80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316722658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.3316722658
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.2822083814
Short name T1037
Test name
Test status
Simulation time 33605429 ps
CPU time 0.75 seconds
Started May 12 04:08:37 PM PDT 24
Finished May 12 04:08:38 PM PDT 24
Peak memory 205352 kb
Host smart-ccd710c3-bb7e-4f75-919b-61a27b2d724f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822083814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.2822083814
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.4041325687
Short name T1001
Test name
Test status
Simulation time 10065600 ps
CPU time 0.82 seconds
Started May 12 04:08:35 PM PDT 24
Finished May 12 04:08:37 PM PDT 24
Peak memory 205324 kb
Host smart-b037a937-91e3-4f7f-a8ca-255042ac4437
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041325687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.4041325687
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.4048511416
Short name T1076
Test name
Test status
Simulation time 35929806 ps
CPU time 0.71 seconds
Started May 12 04:08:36 PM PDT 24
Finished May 12 04:08:38 PM PDT 24
Peak memory 205356 kb
Host smart-568bd093-17d5-45f2-b52e-e2fe64726e71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048511416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.4048511416
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3989042778
Short name T945
Test name
Test status
Simulation time 132507238 ps
CPU time 2.01 seconds
Started May 12 04:08:15 PM PDT 24
Finished May 12 04:08:18 PM PDT 24
Peak memory 213880 kb
Host smart-bb18dcb2-a0cc-49de-af66-12cbb6b6935b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989042778 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.3989042778
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.1579048582
Short name T996
Test name
Test status
Simulation time 28289762 ps
CPU time 1.55 seconds
Started May 12 04:08:10 PM PDT 24
Finished May 12 04:08:12 PM PDT 24
Peak memory 205624 kb
Host smart-89643911-0dba-4328-92d7-6866c1bb05d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579048582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.1579048582
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.3399919864
Short name T943
Test name
Test status
Simulation time 25000244 ps
CPU time 1.04 seconds
Started May 12 04:08:11 PM PDT 24
Finished May 12 04:08:13 PM PDT 24
Peak memory 205548 kb
Host smart-9c59189d-578b-487e-9708-56cbfc659e35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399919864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.3399919864
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.3929192255
Short name T127
Test name
Test status
Simulation time 220182690 ps
CPU time 4.86 seconds
Started May 12 04:08:10 PM PDT 24
Finished May 12 04:08:15 PM PDT 24
Peak memory 205716 kb
Host smart-ca767b13-b64d-45df-826c-9693e1feb245
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929192255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.3929192255
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.100151124
Short name T106
Test name
Test status
Simulation time 113286491 ps
CPU time 2.2 seconds
Started May 12 04:08:13 PM PDT 24
Finished May 12 04:08:15 PM PDT 24
Peak memory 214228 kb
Host smart-ee4bdcd1-8a06-455d-bf47-c1d384215b54
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100151124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow
_reg_errors.100151124
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.450004748
Short name T1045
Test name
Test status
Simulation time 1769307426 ps
CPU time 12.09 seconds
Started May 12 04:08:10 PM PDT 24
Finished May 12 04:08:23 PM PDT 24
Peak memory 220596 kb
Host smart-1a61cf4b-2966-4683-ac6f-18748c893265
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450004748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.k
eymgr_shadow_reg_errors_with_csr_rw.450004748
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.335305385
Short name T916
Test name
Test status
Simulation time 167708844 ps
CPU time 3.19 seconds
Started May 12 04:08:09 PM PDT 24
Finished May 12 04:08:13 PM PDT 24
Peak memory 213980 kb
Host smart-29283366-e8ea-435e-b774-5f2fe29d047a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335305385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.335305385
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.3563291641
Short name T131
Test name
Test status
Simulation time 222187576 ps
CPU time 3.74 seconds
Started May 12 04:08:10 PM PDT 24
Finished May 12 04:08:14 PM PDT 24
Peak memory 213804 kb
Host smart-4ae62f8d-2479-42a7-aafa-d769b213b5cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563291641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.3563291641
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.3812391362
Short name T1051
Test name
Test status
Simulation time 33663639 ps
CPU time 1.61 seconds
Started May 12 04:08:13 PM PDT 24
Finished May 12 04:08:15 PM PDT 24
Peak memory 214040 kb
Host smart-abe72243-7757-4838-809c-d12cdf41833b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812391362 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.3812391362
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.2711901787
Short name T1050
Test name
Test status
Simulation time 63752527 ps
CPU time 0.96 seconds
Started May 12 04:08:14 PM PDT 24
Finished May 12 04:08:15 PM PDT 24
Peak memory 205520 kb
Host smart-3d368240-95bf-448c-a661-d00b0d0e23c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711901787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.2711901787
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.4276965692
Short name T938
Test name
Test status
Simulation time 54936828 ps
CPU time 0.84 seconds
Started May 12 04:08:15 PM PDT 24
Finished May 12 04:08:17 PM PDT 24
Peak memory 205276 kb
Host smart-332f5c06-94d7-462f-b568-9933cc5123c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276965692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.4276965692
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1800619463
Short name T1020
Test name
Test status
Simulation time 66812064 ps
CPU time 2.45 seconds
Started May 12 04:08:15 PM PDT 24
Finished May 12 04:08:19 PM PDT 24
Peak memory 205704 kb
Host smart-9e5975b8-2b44-4793-9e56-15553e780273
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800619463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.1800619463
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.2211661810
Short name T1067
Test name
Test status
Simulation time 478794171 ps
CPU time 1.41 seconds
Started May 12 04:08:11 PM PDT 24
Finished May 12 04:08:13 PM PDT 24
Peak memory 214136 kb
Host smart-110fadcd-d57f-4bc1-8d1f-4ba53dd13acd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211661810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.2211661810
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.2735281901
Short name T949
Test name
Test status
Simulation time 252448487 ps
CPU time 8.55 seconds
Started May 12 04:08:11 PM PDT 24
Finished May 12 04:08:20 PM PDT 24
Peak memory 214356 kb
Host smart-fc45ab1a-a5fc-40d1-a615-312a1a9b75b2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735281901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.2735281901
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.3120135286
Short name T1032
Test name
Test status
Simulation time 424631891 ps
CPU time 4.15 seconds
Started May 12 04:08:15 PM PDT 24
Finished May 12 04:08:20 PM PDT 24
Peak memory 216016 kb
Host smart-66af54ad-aa46-458a-a689-59d9c6c3e0a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120135286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.3120135286
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2907288072
Short name T922
Test name
Test status
Simulation time 114456930 ps
CPU time 1.59 seconds
Started May 12 04:08:14 PM PDT 24
Finished May 12 04:08:16 PM PDT 24
Peak memory 213912 kb
Host smart-23077754-a472-46ca-865e-13e5c21462be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907288072 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.2907288072
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.436758719
Short name T1009
Test name
Test status
Simulation time 259220471 ps
CPU time 1.16 seconds
Started May 12 04:08:24 PM PDT 24
Finished May 12 04:08:26 PM PDT 24
Peak memory 205796 kb
Host smart-1a724c30-2cc9-46ba-aa71-27d672a41b13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436758719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.436758719
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.2558552452
Short name T1024
Test name
Test status
Simulation time 55021001 ps
CPU time 0.77 seconds
Started May 12 04:08:16 PM PDT 24
Finished May 12 04:08:17 PM PDT 24
Peak memory 205380 kb
Host smart-e7f9f5ef-e5ff-4137-96dd-3f04e9b0b4d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558552452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.2558552452
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.1260368621
Short name T1039
Test name
Test status
Simulation time 68836894 ps
CPU time 2.56 seconds
Started May 12 04:08:15 PM PDT 24
Finished May 12 04:08:19 PM PDT 24
Peak memory 205680 kb
Host smart-1c2e692b-e3ea-4469-83ea-2a0be957d38f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260368621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.1260368621
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.2377468560
Short name T976
Test name
Test status
Simulation time 266464656 ps
CPU time 2.08 seconds
Started May 12 04:08:20 PM PDT 24
Finished May 12 04:08:23 PM PDT 24
Peak memory 214288 kb
Host smart-91443af0-e25a-43af-8ef4-e96184fa99ac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377468560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.2377468560
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.116400840
Short name T989
Test name
Test status
Simulation time 226967679 ps
CPU time 5.72 seconds
Started May 12 04:08:15 PM PDT 24
Finished May 12 04:08:22 PM PDT 24
Peak memory 214288 kb
Host smart-d345f991-a6bb-4c73-aa5e-2b1efd895af8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116400840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.k
eymgr_shadow_reg_errors_with_csr_rw.116400840
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.3590907399
Short name T954
Test name
Test status
Simulation time 42136244 ps
CPU time 2.09 seconds
Started May 12 04:08:13 PM PDT 24
Finished May 12 04:08:16 PM PDT 24
Peak memory 205712 kb
Host smart-60ade340-276b-4560-885e-473fa882b5c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590907399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.3590907399
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.2023527773
Short name T934
Test name
Test status
Simulation time 96178622 ps
CPU time 1.75 seconds
Started May 12 04:08:17 PM PDT 24
Finished May 12 04:08:19 PM PDT 24
Peak memory 213804 kb
Host smart-fa8c49e3-f5ea-41b0-bac7-8e0ff076ec51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023527773 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.2023527773
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.1922471495
Short name T927
Test name
Test status
Simulation time 93740077 ps
CPU time 1.45 seconds
Started May 12 04:08:21 PM PDT 24
Finished May 12 04:08:23 PM PDT 24
Peak memory 205644 kb
Host smart-66b1ee64-d73e-411a-8ef4-170403241932
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922471495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.1922471495
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.43073374
Short name T1046
Test name
Test status
Simulation time 10027611 ps
CPU time 0.75 seconds
Started May 12 04:08:20 PM PDT 24
Finished May 12 04:08:22 PM PDT 24
Peak memory 205336 kb
Host smart-097b969a-5290-491c-9852-14d7f173fb27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43073374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.43073374
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.3528732011
Short name T123
Test name
Test status
Simulation time 50291498 ps
CPU time 1.63 seconds
Started May 12 04:08:19 PM PDT 24
Finished May 12 04:08:21 PM PDT 24
Peak memory 205556 kb
Host smart-734bb713-61b3-4d08-a0fb-91a3acffba51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528732011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.3528732011
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.561874171
Short name T1030
Test name
Test status
Simulation time 327116457 ps
CPU time 2.05 seconds
Started May 12 04:08:15 PM PDT 24
Finished May 12 04:08:18 PM PDT 24
Peak memory 214260 kb
Host smart-c41e0a46-5168-4f95-9c00-194bf461d969
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561874171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow
_reg_errors.561874171
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.4069713856
Short name T1083
Test name
Test status
Simulation time 306960308 ps
CPU time 8.77 seconds
Started May 12 04:08:14 PM PDT 24
Finished May 12 04:08:23 PM PDT 24
Peak memory 220388 kb
Host smart-f17515ff-d96a-45ea-9bf4-fac610b2517a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069713856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.4069713856
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.122105841
Short name T1008
Test name
Test status
Simulation time 152813878 ps
CPU time 2.1 seconds
Started May 12 04:08:23 PM PDT 24
Finished May 12 04:08:25 PM PDT 24
Peak memory 213876 kb
Host smart-37875fa0-f192-44c4-93ce-233f056e7a03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122105841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.122105841
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2317282982
Short name T1059
Test name
Test status
Simulation time 248868875 ps
CPU time 2.42 seconds
Started May 12 04:08:19 PM PDT 24
Finished May 12 04:08:22 PM PDT 24
Peak memory 213896 kb
Host smart-14f4295a-b6b6-4423-824a-9058fe4d95d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317282982 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.2317282982
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.1664078244
Short name T1017
Test name
Test status
Simulation time 70509068 ps
CPU time 0.94 seconds
Started May 12 04:08:19 PM PDT 24
Finished May 12 04:08:21 PM PDT 24
Peak memory 205476 kb
Host smart-c3bbff2a-cfff-45f7-ada8-354bcd0a6dd3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664078244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.1664078244
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.2026426993
Short name T965
Test name
Test status
Simulation time 15582351 ps
CPU time 0.91 seconds
Started May 12 04:08:19 PM PDT 24
Finished May 12 04:08:21 PM PDT 24
Peak memory 205468 kb
Host smart-0f4bb80e-861b-4de1-ad9e-c9b4a7123a45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026426993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.2026426993
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.622419940
Short name T128
Test name
Test status
Simulation time 73720857 ps
CPU time 2.28 seconds
Started May 12 04:08:19 PM PDT 24
Finished May 12 04:08:22 PM PDT 24
Peak memory 205648 kb
Host smart-1310472a-6906-43fb-89a2-81c603963dab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622419940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sam
e_csr_outstanding.622419940
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.3086447676
Short name T107
Test name
Test status
Simulation time 46324572 ps
CPU time 2.06 seconds
Started May 12 04:08:17 PM PDT 24
Finished May 12 04:08:19 PM PDT 24
Peak memory 214284 kb
Host smart-37192aed-89e7-4544-8385-82cc23c2d28d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086447676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.3086447676
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2537762400
Short name T105
Test name
Test status
Simulation time 179717437 ps
CPU time 3.79 seconds
Started May 12 04:08:17 PM PDT 24
Finished May 12 04:08:21 PM PDT 24
Peak memory 214264 kb
Host smart-53b54b49-4fa0-4f62-b925-b1ba10c7fb19
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537762400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.2537762400
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.856248642
Short name T950
Test name
Test status
Simulation time 221131360 ps
CPU time 1.85 seconds
Started May 12 04:08:21 PM PDT 24
Finished May 12 04:08:24 PM PDT 24
Peak memory 213776 kb
Host smart-0230a1d4-a4bb-4acd-8f66-b26f4dbbb28d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856248642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.856248642
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.1676961776
Short name T145
Test name
Test status
Simulation time 73904345 ps
CPU time 2.87 seconds
Started May 12 04:08:18 PM PDT 24
Finished May 12 04:08:21 PM PDT 24
Peak memory 213968 kb
Host smart-2101708e-dd22-4868-9636-a7ec5ff66b59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676961776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.1676961776
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.4191051899
Short name T820
Test name
Test status
Simulation time 42908047 ps
CPU time 0.88 seconds
Started May 12 03:43:41 PM PDT 24
Finished May 12 03:43:42 PM PDT 24
Peak memory 205912 kb
Host smart-fc2a697e-bcd8-4750-b1e8-42fac59be76b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191051899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.4191051899
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.3100525488
Short name T378
Test name
Test status
Simulation time 370676896 ps
CPU time 4.12 seconds
Started May 12 03:43:14 PM PDT 24
Finished May 12 03:43:19 PM PDT 24
Peak memory 215208 kb
Host smart-efdb0199-e1a0-476b-943f-3787e3918370
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3100525488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.3100525488
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.1650583378
Short name T34
Test name
Test status
Simulation time 167479656 ps
CPU time 2.58 seconds
Started May 12 03:43:32 PM PDT 24
Finished May 12 03:43:35 PM PDT 24
Peak memory 207908 kb
Host smart-e4df8d72-7640-493a-b352-6cd60727eb42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650583378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.1650583378
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.1600903383
Short name T510
Test name
Test status
Simulation time 394226636 ps
CPU time 4.83 seconds
Started May 12 03:43:18 PM PDT 24
Finished May 12 03:43:23 PM PDT 24
Peak memory 218364 kb
Host smart-847be33e-551f-4536-933a-e8b64a4aa466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600903383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.1600903383
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.2313489874
Short name T767
Test name
Test status
Simulation time 30024554 ps
CPU time 2.44 seconds
Started May 12 03:43:23 PM PDT 24
Finished May 12 03:43:26 PM PDT 24
Peak memory 214300 kb
Host smart-955d3e7c-7e5a-4147-90e5-0064aac99385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313489874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.2313489874
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_random.729504146
Short name T444
Test name
Test status
Simulation time 259341595 ps
CPU time 5.94 seconds
Started May 12 03:43:19 PM PDT 24
Finished May 12 03:43:25 PM PDT 24
Peak memory 208984 kb
Host smart-1dba825c-9d75-494c-b5d0-8c0c20dbbb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729504146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.729504146
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.1495611723
Short name T11
Test name
Test status
Simulation time 831524152 ps
CPU time 14.04 seconds
Started May 12 03:43:40 PM PDT 24
Finished May 12 03:43:55 PM PDT 24
Peak memory 238188 kb
Host smart-dff95c11-f3d6-42ce-9731-29ceec2a510e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495611723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.1495611723
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.408451668
Short name T638
Test name
Test status
Simulation time 910524103 ps
CPU time 35.61 seconds
Started May 12 03:43:14 PM PDT 24
Finished May 12 03:43:50 PM PDT 24
Peak memory 208764 kb
Host smart-c39f8c88-42e9-482c-ac69-c43dd29e23cc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408451668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.408451668
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.887607840
Short name T436
Test name
Test status
Simulation time 58497129 ps
CPU time 2.96 seconds
Started May 12 03:43:10 PM PDT 24
Finished May 12 03:43:13 PM PDT 24
Peak memory 208072 kb
Host smart-cb2d6a68-a155-41af-be3f-89022c216970
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887607840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.887607840
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.3692498613
Short name T485
Test name
Test status
Simulation time 363001733 ps
CPU time 5.21 seconds
Started May 12 03:43:14 PM PDT 24
Finished May 12 03:43:19 PM PDT 24
Peak memory 206888 kb
Host smart-6a1376e0-b277-404c-99e1-7f99456927f2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692498613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.3692498613
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.2323328088
Short name T416
Test name
Test status
Simulation time 356578755 ps
CPU time 3.1 seconds
Started May 12 03:43:34 PM PDT 24
Finished May 12 03:43:37 PM PDT 24
Peak memory 207532 kb
Host smart-834534ad-c138-41aa-b45b-029dbd6a8d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323328088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.2323328088
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.1724645696
Short name T561
Test name
Test status
Simulation time 156278091 ps
CPU time 5.31 seconds
Started May 12 03:43:08 PM PDT 24
Finished May 12 03:43:13 PM PDT 24
Peak memory 208572 kb
Host smart-b5472684-cb99-477f-840d-aa181b7463dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724645696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.1724645696
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.1834003824
Short name T747
Test name
Test status
Simulation time 9767502573 ps
CPU time 110.14 seconds
Started May 12 03:43:39 PM PDT 24
Finished May 12 03:45:29 PM PDT 24
Peak memory 222716 kb
Host smart-a643c0b5-2f1e-4f9f-8a40-bd73922c3721
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834003824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.1834003824
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.2573412382
Short name T481
Test name
Test status
Simulation time 163485501 ps
CPU time 5.39 seconds
Started May 12 03:43:20 PM PDT 24
Finished May 12 03:43:26 PM PDT 24
Peak memory 207912 kb
Host smart-56499074-33d6-41c5-a58d-a7f1f7357b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573412382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.2573412382
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.1154002299
Short name T577
Test name
Test status
Simulation time 223611121 ps
CPU time 2.87 seconds
Started May 12 03:44:25 PM PDT 24
Finished May 12 03:44:29 PM PDT 24
Peak memory 214720 kb
Host smart-a743c4db-5517-4f2e-ae58-8a04a00fd7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154002299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.1154002299
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.3829063560
Short name T531
Test name
Test status
Simulation time 1634556185 ps
CPU time 4.61 seconds
Started May 12 03:43:55 PM PDT 24
Finished May 12 03:44:00 PM PDT 24
Peak memory 214288 kb
Host smart-01293b5b-d100-45c7-bc90-5c4fc7bdfb01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829063560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.3829063560
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.126283925
Short name T205
Test name
Test status
Simulation time 128182636 ps
CPU time 4.56 seconds
Started May 12 03:43:53 PM PDT 24
Finished May 12 03:43:58 PM PDT 24
Peak memory 209708 kb
Host smart-d2374f40-f440-4ab5-bc1e-607628aec4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126283925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.126283925
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.3175207156
Short name T908
Test name
Test status
Simulation time 109890028 ps
CPU time 5.49 seconds
Started May 12 03:43:48 PM PDT 24
Finished May 12 03:43:54 PM PDT 24
Peak memory 218152 kb
Host smart-1ab4b853-ba35-4c19-822d-ccb77a293cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175207156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.3175207156
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.3455916726
Short name T102
Test name
Test status
Simulation time 1712601758 ps
CPU time 17.13 seconds
Started May 12 03:44:09 PM PDT 24
Finished May 12 03:44:26 PM PDT 24
Peak memory 232648 kb
Host smart-83e3a4b3-a024-4d69-8bcb-664c3176f124
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455916726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.3455916726
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.981076682
Short name T356
Test name
Test status
Simulation time 5494496706 ps
CPU time 25.39 seconds
Started May 12 03:43:46 PM PDT 24
Finished May 12 03:44:11 PM PDT 24
Peak memory 208224 kb
Host smart-8c20db72-11be-4262-837b-101a26ea0e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981076682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.981076682
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.1828887072
Short name T783
Test name
Test status
Simulation time 144627356 ps
CPU time 5.64 seconds
Started May 12 03:43:47 PM PDT 24
Finished May 12 03:43:53 PM PDT 24
Peak memory 208520 kb
Host smart-d4060351-5a92-4640-9809-720ac4247bbe
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828887072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.1828887072
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.1127494725
Short name T187
Test name
Test status
Simulation time 33767866 ps
CPU time 2.43 seconds
Started May 12 03:43:47 PM PDT 24
Finished May 12 03:43:50 PM PDT 24
Peak memory 206864 kb
Host smart-8f1fe3f8-980a-4c1b-82e3-aef0e79f19d6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127494725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.1127494725
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.1950547467
Short name T455
Test name
Test status
Simulation time 1674778723 ps
CPU time 5.79 seconds
Started May 12 03:43:48 PM PDT 24
Finished May 12 03:43:55 PM PDT 24
Peak memory 206928 kb
Host smart-8f19eb37-2162-4613-b315-ca335e7b0a33
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950547467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.1950547467
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.417900382
Short name T624
Test name
Test status
Simulation time 278055755 ps
CPU time 3.97 seconds
Started May 12 03:43:57 PM PDT 24
Finished May 12 03:44:01 PM PDT 24
Peak memory 209340 kb
Host smart-e9f9ae29-f412-4dfd-89eb-136372575ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417900382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.417900382
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.2686037093
Short name T659
Test name
Test status
Simulation time 317937087 ps
CPU time 3.01 seconds
Started May 12 03:43:53 PM PDT 24
Finished May 12 03:43:56 PM PDT 24
Peak memory 206720 kb
Host smart-98ee02ce-1999-4fbc-ad21-29d7becef286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686037093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.2686037093
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.2103162171
Short name T818
Test name
Test status
Simulation time 648320901 ps
CPU time 5.78 seconds
Started May 12 03:43:54 PM PDT 24
Finished May 12 03:44:00 PM PDT 24
Peak memory 209380 kb
Host smart-cbcc2805-e06a-435b-b30f-af4cd332af9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103162171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.2103162171
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.1446774203
Short name T660
Test name
Test status
Simulation time 41163751 ps
CPU time 1.74 seconds
Started May 12 03:44:04 PM PDT 24
Finished May 12 03:44:06 PM PDT 24
Peak memory 209916 kb
Host smart-96cbda72-2c04-4e5a-a586-95b5e77b3cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446774203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.1446774203
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.1695644543
Short name T583
Test name
Test status
Simulation time 24433179 ps
CPU time 0.84 seconds
Started May 12 03:46:08 PM PDT 24
Finished May 12 03:46:09 PM PDT 24
Peak memory 205880 kb
Host smart-0cc322a3-3052-4f33-958c-fc9a2eb38b76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695644543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.1695644543
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.279883259
Short name T389
Test name
Test status
Simulation time 114532649 ps
CPU time 6.11 seconds
Started May 12 03:46:01 PM PDT 24
Finished May 12 03:46:07 PM PDT 24
Peak memory 222324 kb
Host smart-763f885f-3d34-4acd-8679-f9236ed2a3c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=279883259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.279883259
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.896782265
Short name T648
Test name
Test status
Simulation time 855141569 ps
CPU time 7.46 seconds
Started May 12 03:46:14 PM PDT 24
Finished May 12 03:46:22 PM PDT 24
Peak memory 210360 kb
Host smart-0bc00552-25a4-441a-8d3d-444ca8134b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896782265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.896782265
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.2130733873
Short name T630
Test name
Test status
Simulation time 435452002 ps
CPU time 3.46 seconds
Started May 12 03:46:02 PM PDT 24
Finished May 12 03:46:06 PM PDT 24
Peak memory 210116 kb
Host smart-e0b9b655-86b0-43cd-a778-44bc9eb534fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130733873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.2130733873
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.787199943
Short name T787
Test name
Test status
Simulation time 360215486 ps
CPU time 3.37 seconds
Started May 12 03:46:07 PM PDT 24
Finished May 12 03:46:11 PM PDT 24
Peak memory 222020 kb
Host smart-ce8a02e2-55d0-4295-8815-8b3b3b336850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787199943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.787199943
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.1036517595
Short name T680
Test name
Test status
Simulation time 126828455 ps
CPU time 2.84 seconds
Started May 12 03:46:05 PM PDT 24
Finished May 12 03:46:08 PM PDT 24
Peak memory 207512 kb
Host smart-e37113b5-088d-46d1-88d3-66bfd26b021e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036517595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.1036517595
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.2820972851
Short name T812
Test name
Test status
Simulation time 339607524 ps
CPU time 10.91 seconds
Started May 12 03:46:09 PM PDT 24
Finished May 12 03:46:21 PM PDT 24
Peak memory 210076 kb
Host smart-4684d6cd-aa67-48bb-ae4f-b612796e845a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820972851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.2820972851
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.266293650
Short name T411
Test name
Test status
Simulation time 90267497 ps
CPU time 2.86 seconds
Started May 12 03:46:01 PM PDT 24
Finished May 12 03:46:04 PM PDT 24
Peak memory 208472 kb
Host smart-52afde35-9c75-4b5a-a7ba-385929404f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266293650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.266293650
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.1224730856
Short name T239
Test name
Test status
Simulation time 332521727 ps
CPU time 5.97 seconds
Started May 12 03:46:04 PM PDT 24
Finished May 12 03:46:10 PM PDT 24
Peak memory 208532 kb
Host smart-600c2ed4-a2d2-4dbe-ba26-41dd1c2f7a61
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224730856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.1224730856
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.3156254732
Short name T791
Test name
Test status
Simulation time 82765800 ps
CPU time 1.95 seconds
Started May 12 03:46:01 PM PDT 24
Finished May 12 03:46:03 PM PDT 24
Peak memory 206976 kb
Host smart-b738444f-8f90-4b57-a5fb-f97c078e0502
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156254732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.3156254732
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.4127271507
Short name T913
Test name
Test status
Simulation time 1860317133 ps
CPU time 4.82 seconds
Started May 12 03:46:03 PM PDT 24
Finished May 12 03:46:08 PM PDT 24
Peak memory 206908 kb
Host smart-99b94a37-5501-4d1d-8a54-ad68fe92e7d8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127271507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.4127271507
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.2483767781
Short name T691
Test name
Test status
Simulation time 278625636 ps
CPU time 5.53 seconds
Started May 12 03:46:08 PM PDT 24
Finished May 12 03:46:14 PM PDT 24
Peak memory 209524 kb
Host smart-11d6fc23-97c2-417a-aa34-93644d71c7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483767781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.2483767781
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.3702787109
Short name T382
Test name
Test status
Simulation time 322790925 ps
CPU time 3.32 seconds
Started May 12 03:45:59 PM PDT 24
Finished May 12 03:46:03 PM PDT 24
Peak memory 208568 kb
Host smart-a738122d-c1da-4ed2-916d-b42d7f9ba78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702787109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.3702787109
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.2307224199
Short name T879
Test name
Test status
Simulation time 996395974 ps
CPU time 26.22 seconds
Started May 12 03:46:11 PM PDT 24
Finished May 12 03:46:38 PM PDT 24
Peak memory 220208 kb
Host smart-0ad59843-0879-4a02-a48e-e9a9fbbf1499
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307224199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.2307224199
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.1808079025
Short name T344
Test name
Test status
Simulation time 575121802 ps
CPU time 19.96 seconds
Started May 12 03:46:13 PM PDT 24
Finished May 12 03:46:33 PM PDT 24
Peak memory 222512 kb
Host smart-a00e8e57-8010-4f71-99ff-e2b70cec97fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808079025 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.1808079025
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.3591734212
Short name T81
Test name
Test status
Simulation time 66344711 ps
CPU time 4.26 seconds
Started May 12 03:46:07 PM PDT 24
Finished May 12 03:46:12 PM PDT 24
Peak memory 214256 kb
Host smart-8e72944f-0936-4f30-ba9f-247641125914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591734212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.3591734212
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.1228749703
Short name T152
Test name
Test status
Simulation time 154276187 ps
CPU time 3.12 seconds
Started May 12 03:46:10 PM PDT 24
Finished May 12 03:46:14 PM PDT 24
Peak memory 210240 kb
Host smart-f197c0dd-9217-49ce-b4d0-e26f41982010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228749703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.1228749703
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.319088401
Short name T478
Test name
Test status
Simulation time 12522361 ps
CPU time 0.85 seconds
Started May 12 03:46:19 PM PDT 24
Finished May 12 03:46:20 PM PDT 24
Peak memory 205924 kb
Host smart-2cda91a7-c6c6-4fe9-9f53-c8b59ace702d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319088401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.319088401
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.3631765409
Short name T396
Test name
Test status
Simulation time 48036760 ps
CPU time 3.51 seconds
Started May 12 03:46:15 PM PDT 24
Finished May 12 03:46:19 PM PDT 24
Peak memory 214300 kb
Host smart-df7df674-99fa-4ca5-b1f4-72d79c010635
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3631765409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.3631765409
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.710911149
Short name T498
Test name
Test status
Simulation time 63990838 ps
CPU time 3.38 seconds
Started May 12 03:46:13 PM PDT 24
Finished May 12 03:46:17 PM PDT 24
Peak memory 210344 kb
Host smart-42a21dc6-6d92-4c31-9baf-4697a01d7669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710911149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.710911149
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.984187003
Short name T341
Test name
Test status
Simulation time 102801854 ps
CPU time 3.52 seconds
Started May 12 03:46:13 PM PDT 24
Finished May 12 03:46:17 PM PDT 24
Peak memory 214272 kb
Host smart-539943cc-c52f-4cb2-ba2a-0cd16cbf1ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984187003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.984187003
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.1374143570
Short name T651
Test name
Test status
Simulation time 435075406 ps
CPU time 4.88 seconds
Started May 12 03:46:11 PM PDT 24
Finished May 12 03:46:16 PM PDT 24
Peak memory 210296 kb
Host smart-5593df70-dbcc-42a7-8050-17427b1729dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374143570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.1374143570
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.2142505117
Short name T729
Test name
Test status
Simulation time 1251421150 ps
CPU time 8.69 seconds
Started May 12 03:46:10 PM PDT 24
Finished May 12 03:46:19 PM PDT 24
Peak memory 207988 kb
Host smart-ef4c1c61-3274-4854-bd19-dc37247891d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142505117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.2142505117
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.3424048480
Short name T456
Test name
Test status
Simulation time 71077205 ps
CPU time 3.34 seconds
Started May 12 03:46:12 PM PDT 24
Finished May 12 03:46:16 PM PDT 24
Peak memory 208596 kb
Host smart-b7cf501b-3d90-410a-a5ef-3ed5d6831a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424048480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.3424048480
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.244167513
Short name T824
Test name
Test status
Simulation time 250196582 ps
CPU time 3.31 seconds
Started May 12 03:46:10 PM PDT 24
Finished May 12 03:46:14 PM PDT 24
Peak memory 206920 kb
Host smart-db46ba14-1928-4c7a-815f-634753b265eb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244167513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.244167513
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.624658043
Short name T863
Test name
Test status
Simulation time 221448126 ps
CPU time 7.26 seconds
Started May 12 03:46:09 PM PDT 24
Finished May 12 03:46:16 PM PDT 24
Peak memory 208436 kb
Host smart-b58932f1-5588-459f-a523-a16307b8d818
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624658043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.624658043
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.1931568930
Short name T311
Test name
Test status
Simulation time 240728118 ps
CPU time 2.54 seconds
Started May 12 03:46:18 PM PDT 24
Finished May 12 03:46:20 PM PDT 24
Peak memory 209600 kb
Host smart-21b5f7a8-6e70-4124-b6fa-a3e93a70253d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931568930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.1931568930
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.3038888368
Short name T449
Test name
Test status
Simulation time 42438970 ps
CPU time 1.9 seconds
Started May 12 03:46:10 PM PDT 24
Finished May 12 03:46:12 PM PDT 24
Peak memory 207000 kb
Host smart-584a1c19-97d0-4634-91aa-7c93d155f273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038888368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.3038888368
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.225362387
Short name T839
Test name
Test status
Simulation time 206688401 ps
CPU time 7.21 seconds
Started May 12 03:46:21 PM PDT 24
Finished May 12 03:46:29 PM PDT 24
Peak memory 222524 kb
Host smart-02705378-0075-4702-a7ab-260e7b80d4a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225362387 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.225362387
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.1414603580
Short name T524
Test name
Test status
Simulation time 334327573 ps
CPU time 4.27 seconds
Started May 12 03:46:17 PM PDT 24
Finished May 12 03:46:22 PM PDT 24
Peak memory 209660 kb
Host smart-96864cc8-5d2d-44ce-9275-1af343aa657d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414603580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.1414603580
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.3237556980
Short name T57
Test name
Test status
Simulation time 450454488 ps
CPU time 8.65 seconds
Started May 12 03:46:17 PM PDT 24
Finished May 12 03:46:26 PM PDT 24
Peak memory 210228 kb
Host smart-7a0247d8-e1c2-41c1-8896-40115056e8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237556980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.3237556980
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.1982886458
Short name T441
Test name
Test status
Simulation time 16427622 ps
CPU time 0.87 seconds
Started May 12 03:46:32 PM PDT 24
Finished May 12 03:46:33 PM PDT 24
Peak memory 205572 kb
Host smart-11ed6ece-e0f6-42bb-86bb-aa4f9adc86a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982886458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.1982886458
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.4078740781
Short name T67
Test name
Test status
Simulation time 58205738 ps
CPU time 2.86 seconds
Started May 12 03:46:24 PM PDT 24
Finished May 12 03:46:27 PM PDT 24
Peak memory 210016 kb
Host smart-22ed02a7-2c93-4463-91c2-e8a6949b3599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078740781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.4078740781
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.4055717972
Short name T757
Test name
Test status
Simulation time 199031937 ps
CPU time 2.73 seconds
Started May 12 03:46:23 PM PDT 24
Finished May 12 03:46:26 PM PDT 24
Peak memory 208716 kb
Host smart-eedd6938-dcc0-48ad-b163-9143bf8fed52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055717972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.4055717972
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.2229559537
Short name T26
Test name
Test status
Simulation time 294390385 ps
CPU time 4.15 seconds
Started May 12 03:46:24 PM PDT 24
Finished May 12 03:46:28 PM PDT 24
Peak memory 209528 kb
Host smart-5087740e-5472-4f58-9c8f-7787f258070c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229559537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.2229559537
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.3167972633
Short name T745
Test name
Test status
Simulation time 159976208 ps
CPU time 4.34 seconds
Started May 12 03:46:28 PM PDT 24
Finished May 12 03:46:32 PM PDT 24
Peak memory 214220 kb
Host smart-ac411e43-939c-4fd9-a6cd-1dd147b636f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167972633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.3167972633
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.1441231835
Short name T883
Test name
Test status
Simulation time 238373605 ps
CPU time 3.55 seconds
Started May 12 03:46:25 PM PDT 24
Finished May 12 03:46:29 PM PDT 24
Peak memory 209768 kb
Host smart-08cd5e4f-21b6-48e1-87c5-8226bb10ff8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441231835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.1441231835
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.2360425799
Short name T606
Test name
Test status
Simulation time 214408441 ps
CPU time 6.57 seconds
Started May 12 03:46:24 PM PDT 24
Finished May 12 03:46:31 PM PDT 24
Peak memory 218412 kb
Host smart-ebc9ff58-d563-4b3e-b90f-db6bdfc8c127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360425799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.2360425799
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.1363295114
Short name T813
Test name
Test status
Simulation time 575045858 ps
CPU time 2.77 seconds
Started May 12 03:46:18 PM PDT 24
Finished May 12 03:46:21 PM PDT 24
Peak memory 206640 kb
Host smart-e008fe7f-77c9-40c8-b029-5a79012393ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363295114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.1363295114
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.3674586370
Short name T431
Test name
Test status
Simulation time 1524017632 ps
CPU time 23.74 seconds
Started May 12 03:46:20 PM PDT 24
Finished May 12 03:46:44 PM PDT 24
Peak memory 208100 kb
Host smart-e5e7a72e-21f3-44f6-9493-e14b32b32999
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674586370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.3674586370
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.981211534
Short name T591
Test name
Test status
Simulation time 152964858 ps
CPU time 2.44 seconds
Started May 12 03:46:21 PM PDT 24
Finished May 12 03:46:24 PM PDT 24
Peak memory 206892 kb
Host smart-f3ca793e-aa23-4099-8b07-81407903fb9e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981211534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.981211534
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.1506257565
Short name T626
Test name
Test status
Simulation time 60392317 ps
CPU time 3.19 seconds
Started May 12 03:46:19 PM PDT 24
Finished May 12 03:46:22 PM PDT 24
Peak memory 206932 kb
Host smart-a0bcecc2-d57e-46ba-9f14-b284508a0143
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506257565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.1506257565
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.497811014
Short name T772
Test name
Test status
Simulation time 196191405 ps
CPU time 2.4 seconds
Started May 12 03:46:23 PM PDT 24
Finished May 12 03:46:26 PM PDT 24
Peak memory 209000 kb
Host smart-064b49d7-733c-4c9a-bde4-b2ea412c41f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497811014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.497811014
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.670233266
Short name T185
Test name
Test status
Simulation time 32348292 ps
CPU time 2.33 seconds
Started May 12 03:46:18 PM PDT 24
Finished May 12 03:46:21 PM PDT 24
Peak memory 206796 kb
Host smart-7ad702a2-6b8a-4df8-be17-72ddfcf026c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670233266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.670233266
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.473651686
Short name T355
Test name
Test status
Simulation time 94749308 ps
CPU time 3.62 seconds
Started May 12 03:46:27 PM PDT 24
Finished May 12 03:46:31 PM PDT 24
Peak memory 210204 kb
Host smart-7a489aff-a9bc-4275-b576-f5bf7fe2b1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473651686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.473651686
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.3412324242
Short name T609
Test name
Test status
Simulation time 146072597 ps
CPU time 2.46 seconds
Started May 12 03:46:32 PM PDT 24
Finished May 12 03:46:34 PM PDT 24
Peak memory 209796 kb
Host smart-dba2a825-f7e2-495d-bd5f-fbd5c3bf6ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412324242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.3412324242
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.2614652371
Short name T461
Test name
Test status
Simulation time 14358782 ps
CPU time 0.8 seconds
Started May 12 03:46:34 PM PDT 24
Finished May 12 03:46:35 PM PDT 24
Peak memory 205908 kb
Host smart-d4908470-ed92-4846-a4bb-76d378fd0398
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614652371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.2614652371
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.3332826093
Short name T320
Test name
Test status
Simulation time 384705902 ps
CPU time 11.24 seconds
Started May 12 03:46:32 PM PDT 24
Finished May 12 03:46:44 PM PDT 24
Peak memory 215816 kb
Host smart-c7aefea5-ff2f-49c5-a7cf-a75115565b50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3332826093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.3332826093
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.1915248978
Short name T821
Test name
Test status
Simulation time 181358485 ps
CPU time 3.69 seconds
Started May 12 03:46:34 PM PDT 24
Finished May 12 03:46:38 PM PDT 24
Peak memory 214220 kb
Host smart-ae7dd654-3ea2-4bfe-bf63-e1fe51d03dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915248978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.1915248978
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.1866039949
Short name T717
Test name
Test status
Simulation time 148288406 ps
CPU time 4.68 seconds
Started May 12 03:46:32 PM PDT 24
Finished May 12 03:46:37 PM PDT 24
Peak memory 208240 kb
Host smart-5c1f93b7-ae81-4413-ac69-b8a4f8146a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866039949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.1866039949
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.3375885422
Short name T768
Test name
Test status
Simulation time 236810125 ps
CPU time 5.89 seconds
Started May 12 03:46:35 PM PDT 24
Finished May 12 03:46:41 PM PDT 24
Peak memory 219076 kb
Host smart-46dc43fd-437b-43b2-9a0b-da123f2a3e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375885422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.3375885422
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.645179841
Short name T176
Test name
Test status
Simulation time 576807293 ps
CPU time 3.11 seconds
Started May 12 03:46:34 PM PDT 24
Finished May 12 03:46:37 PM PDT 24
Peak memory 206340 kb
Host smart-23879970-a462-4dc4-afaa-a51120d9f7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645179841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.645179841
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.360773854
Short name T503
Test name
Test status
Simulation time 757840042 ps
CPU time 7.75 seconds
Started May 12 03:46:33 PM PDT 24
Finished May 12 03:46:41 PM PDT 24
Peak memory 209424 kb
Host smart-2398ce18-9215-4089-ab39-7aed9983a879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360773854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.360773854
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.2923700619
Short name T546
Test name
Test status
Simulation time 46282155 ps
CPU time 2.62 seconds
Started May 12 03:46:31 PM PDT 24
Finished May 12 03:46:34 PM PDT 24
Peak memory 208176 kb
Host smart-04c71511-06c1-43db-990e-1f9bd2b173a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923700619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.2923700619
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.3265972237
Short name T487
Test name
Test status
Simulation time 101260287 ps
CPU time 4.64 seconds
Started May 12 03:46:30 PM PDT 24
Finished May 12 03:46:35 PM PDT 24
Peak memory 208668 kb
Host smart-e49fe7cd-b157-4984-983c-60e28e9c44bb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265972237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.3265972237
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.3312195726
Short name T223
Test name
Test status
Simulation time 540177114 ps
CPU time 4.25 seconds
Started May 12 03:46:31 PM PDT 24
Finished May 12 03:46:35 PM PDT 24
Peak memory 207892 kb
Host smart-3258eac4-417e-431e-b83e-d7e27f46b12b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312195726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.3312195726
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.2122356853
Short name T445
Test name
Test status
Simulation time 429341718 ps
CPU time 5.07 seconds
Started May 12 03:46:30 PM PDT 24
Finished May 12 03:46:36 PM PDT 24
Peak memory 208600 kb
Host smart-9a202a18-fac0-48aa-8fc9-55afc4f05e3c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122356853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.2122356853
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.2498665879
Short name T770
Test name
Test status
Simulation time 49108025 ps
CPU time 2.02 seconds
Started May 12 03:46:37 PM PDT 24
Finished May 12 03:46:39 PM PDT 24
Peak memory 207232 kb
Host smart-75bb2f55-3d5d-4276-b3d5-dca20dc87653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498665879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.2498665879
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.1022220415
Short name T763
Test name
Test status
Simulation time 3375561828 ps
CPU time 8.47 seconds
Started May 12 03:46:31 PM PDT 24
Finished May 12 03:46:40 PM PDT 24
Peak memory 208644 kb
Host smart-c583d3ac-fcb4-4338-bcf6-686e942bebc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022220415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.1022220415
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.3878348321
Short name T550
Test name
Test status
Simulation time 856126755 ps
CPU time 3.86 seconds
Started May 12 03:46:37 PM PDT 24
Finished May 12 03:46:41 PM PDT 24
Peak memory 207220 kb
Host smart-7cdcf3fd-351d-4272-aa5a-b425f5201e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878348321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.3878348321
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.3303376965
Short name T728
Test name
Test status
Simulation time 11595376 ps
CPU time 1.02 seconds
Started May 12 03:46:44 PM PDT 24
Finished May 12 03:46:45 PM PDT 24
Peak memory 205920 kb
Host smart-c44fbbe5-95ec-451b-a444-6b986522a6b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303376965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.3303376965
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.2346100503
Short name T408
Test name
Test status
Simulation time 177184573 ps
CPU time 3.83 seconds
Started May 12 03:46:46 PM PDT 24
Finished May 12 03:46:50 PM PDT 24
Peak memory 215504 kb
Host smart-546a3de0-0f1c-4ac8-82b0-3ec9a7c468cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2346100503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.2346100503
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.3406130851
Short name T32
Test name
Test status
Simulation time 226415588 ps
CPU time 4.39 seconds
Started May 12 03:46:42 PM PDT 24
Finished May 12 03:46:47 PM PDT 24
Peak memory 220080 kb
Host smart-bca21ca0-5d31-4e89-a31c-c79539ce1d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406130851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.3406130851
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.3478698902
Short name T313
Test name
Test status
Simulation time 319301283 ps
CPU time 2.7 seconds
Started May 12 03:46:46 PM PDT 24
Finished May 12 03:46:50 PM PDT 24
Peak memory 214336 kb
Host smart-2b891697-860e-45e9-aee3-0a34afa7c742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478698902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.3478698902
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.3364950851
Short name T869
Test name
Test status
Simulation time 1767139995 ps
CPU time 22.89 seconds
Started May 12 03:46:46 PM PDT 24
Finished May 12 03:47:09 PM PDT 24
Peak memory 220908 kb
Host smart-67f4c6a1-e514-4c35-b294-cb3d1265bfbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364950851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.3364950851
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.3296378086
Short name T572
Test name
Test status
Simulation time 73864269 ps
CPU time 2.5 seconds
Started May 12 03:46:42 PM PDT 24
Finished May 12 03:46:45 PM PDT 24
Peak memory 214236 kb
Host smart-0d0e746b-afae-4909-a49e-613e01b5904f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296378086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.3296378086
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.1490093854
Short name T592
Test name
Test status
Simulation time 903025400 ps
CPU time 3.11 seconds
Started May 12 03:46:45 PM PDT 24
Finished May 12 03:46:48 PM PDT 24
Peak memory 220104 kb
Host smart-abe2c9fd-9e06-4620-accb-5c5201d7fc35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490093854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.1490093854
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.1690364128
Short name T500
Test name
Test status
Simulation time 268284556 ps
CPU time 6.54 seconds
Started May 12 03:46:46 PM PDT 24
Finished May 12 03:46:53 PM PDT 24
Peak memory 207420 kb
Host smart-88104e61-f6e0-46ba-8a05-0643ac2ee966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690364128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.1690364128
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.4142431037
Short name T493
Test name
Test status
Simulation time 649549624 ps
CPU time 3.32 seconds
Started May 12 03:46:36 PM PDT 24
Finished May 12 03:46:40 PM PDT 24
Peak memory 206876 kb
Host smart-79fe289f-8f18-4589-bb09-d47b4c3409ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142431037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.4142431037
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.107452896
Short name T346
Test name
Test status
Simulation time 109054497 ps
CPU time 3.92 seconds
Started May 12 03:46:50 PM PDT 24
Finished May 12 03:46:54 PM PDT 24
Peak memory 208756 kb
Host smart-fad8b233-e4aa-4f3b-a8cb-0aa8c37fb5d6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107452896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.107452896
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.3109338943
Short name T18
Test name
Test status
Simulation time 375826725 ps
CPU time 6.59 seconds
Started May 12 03:46:37 PM PDT 24
Finished May 12 03:46:44 PM PDT 24
Peak memory 207916 kb
Host smart-c4e991da-6249-4d3c-98d1-e76396e211c1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109338943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.3109338943
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.2812062733
Short name T808
Test name
Test status
Simulation time 204256111 ps
CPU time 3.62 seconds
Started May 12 03:46:46 PM PDT 24
Finished May 12 03:46:50 PM PDT 24
Peak memory 208892 kb
Host smart-51f0bff4-b205-49ba-9bf0-e031d35eb01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812062733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.2812062733
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.2152977809
Short name T425
Test name
Test status
Simulation time 641956661 ps
CPU time 4.76 seconds
Started May 12 03:46:36 PM PDT 24
Finished May 12 03:46:42 PM PDT 24
Peak memory 208316 kb
Host smart-ab9f86dc-ed31-441c-976f-bbb723517410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152977809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.2152977809
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.2724959352
Short name T262
Test name
Test status
Simulation time 9497623340 ps
CPU time 90.69 seconds
Started May 12 03:46:43 PM PDT 24
Finished May 12 03:48:14 PM PDT 24
Peak memory 221316 kb
Host smart-2f23700e-36bc-40ae-aa1e-c943337f7313
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724959352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.2724959352
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.913111241
Short name T620
Test name
Test status
Simulation time 45926964 ps
CPU time 2.97 seconds
Started May 12 03:46:44 PM PDT 24
Finished May 12 03:46:48 PM PDT 24
Peak memory 208124 kb
Host smart-0404f20c-5bc9-490a-bba6-553612bef3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913111241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.913111241
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.3354086985
Short name T593
Test name
Test status
Simulation time 138320017 ps
CPU time 4.69 seconds
Started May 12 03:46:43 PM PDT 24
Finished May 12 03:46:48 PM PDT 24
Peak memory 209764 kb
Host smart-53479e80-be72-4e0b-8fdf-a721cd8c2a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354086985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.3354086985
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.130432431
Short name T860
Test name
Test status
Simulation time 16216578 ps
CPU time 1.01 seconds
Started May 12 03:46:53 PM PDT 24
Finished May 12 03:46:55 PM PDT 24
Peak memory 205904 kb
Host smart-f12e75ba-a081-4024-9fc2-2c69fcc13a83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130432431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.130432431
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.3962946233
Short name T242
Test name
Test status
Simulation time 81011325 ps
CPU time 5.92 seconds
Started May 12 03:46:46 PM PDT 24
Finished May 12 03:46:53 PM PDT 24
Peak memory 215584 kb
Host smart-c4b899f3-6904-4985-856f-7bfac7c350e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3962946233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.3962946233
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.1439830394
Short name T35
Test name
Test status
Simulation time 110045194 ps
CPU time 4.77 seconds
Started May 12 03:46:50 PM PDT 24
Finished May 12 03:46:55 PM PDT 24
Peak memory 219296 kb
Host smart-b7252beb-8734-40ba-bb95-09729e1b0b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439830394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.1439830394
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.638716333
Short name T640
Test name
Test status
Simulation time 216172759 ps
CPU time 5.32 seconds
Started May 12 03:47:08 PM PDT 24
Finished May 12 03:47:14 PM PDT 24
Peak memory 207276 kb
Host smart-4b8ea9fa-c00d-4448-aa51-656ac49117cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638716333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.638716333
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.2141076526
Short name T363
Test name
Test status
Simulation time 86191534 ps
CPU time 2.48 seconds
Started May 12 03:46:48 PM PDT 24
Finished May 12 03:46:51 PM PDT 24
Peak memory 214688 kb
Host smart-ec79b28c-92dd-4932-b3a2-cc9ed6945052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141076526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.2141076526
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.618543059
Short name T864
Test name
Test status
Simulation time 139415486 ps
CPU time 4.21 seconds
Started May 12 03:46:49 PM PDT 24
Finished May 12 03:46:53 PM PDT 24
Peak memory 214312 kb
Host smart-6e63757d-2951-48fe-8926-99aa31f2bef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618543059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.618543059
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.99594215
Short name T260
Test name
Test status
Simulation time 77013921 ps
CPU time 3.53 seconds
Started May 12 03:46:51 PM PDT 24
Finished May 12 03:46:55 PM PDT 24
Peak memory 214228 kb
Host smart-a24d7317-275a-4154-902e-5f5914769af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99594215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.99594215
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.1978404349
Short name T397
Test name
Test status
Simulation time 688493024 ps
CPU time 6.74 seconds
Started May 12 03:46:47 PM PDT 24
Finished May 12 03:46:55 PM PDT 24
Peak memory 209616 kb
Host smart-d2916578-94e0-4115-a082-8ce5c0bae24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978404349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.1978404349
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.664550301
Short name T3
Test name
Test status
Simulation time 185605552 ps
CPU time 3.77 seconds
Started May 12 03:46:45 PM PDT 24
Finished May 12 03:46:50 PM PDT 24
Peak memory 208452 kb
Host smart-964faaa2-4839-4f76-a3ea-0c0dc80f73f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664550301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.664550301
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.2528636962
Short name T874
Test name
Test status
Simulation time 68019056 ps
CPU time 3.5 seconds
Started May 12 03:46:51 PM PDT 24
Finished May 12 03:46:55 PM PDT 24
Peak memory 206992 kb
Host smart-3c9b4e38-9acd-4e41-8eef-0a6562aa4a18
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528636962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.2528636962
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.1548007258
Short name T657
Test name
Test status
Simulation time 161570948 ps
CPU time 3.42 seconds
Started May 12 03:46:49 PM PDT 24
Finished May 12 03:46:53 PM PDT 24
Peak memory 208812 kb
Host smart-5d9e2f8a-f88c-4a49-ab6c-d93d617c3f36
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548007258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.1548007258
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.1520115702
Short name T430
Test name
Test status
Simulation time 812144945 ps
CPU time 30.83 seconds
Started May 12 03:46:47 PM PDT 24
Finished May 12 03:47:19 PM PDT 24
Peak memory 207900 kb
Host smart-4dea8d27-a418-4b12-880c-792dde449e8f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520115702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.1520115702
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.2393567824
Short name T599
Test name
Test status
Simulation time 82336631 ps
CPU time 4.17 seconds
Started May 12 03:46:52 PM PDT 24
Finished May 12 03:46:56 PM PDT 24
Peak memory 218204 kb
Host smart-4199f3f3-8d19-4f3f-ba58-2e80ea294d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393567824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.2393567824
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.3352255558
Short name T850
Test name
Test status
Simulation time 153289940 ps
CPU time 3.22 seconds
Started May 12 03:46:46 PM PDT 24
Finished May 12 03:46:50 PM PDT 24
Peak memory 208176 kb
Host smart-1cd4f843-b426-4e14-9d4c-30a249889451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352255558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.3352255558
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.427139678
Short name T280
Test name
Test status
Simulation time 366999908 ps
CPU time 4.32 seconds
Started May 12 03:46:48 PM PDT 24
Finished May 12 03:46:53 PM PDT 24
Peak memory 208384 kb
Host smart-9d680541-2510-4db3-a9aa-d35aed5ca45d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427139678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.427139678
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.4127240549
Short name T753
Test name
Test status
Simulation time 251070663 ps
CPU time 12.99 seconds
Started May 12 03:46:54 PM PDT 24
Finished May 12 03:47:08 PM PDT 24
Peak memory 222440 kb
Host smart-7902cd54-2558-4b10-bb54-cda2d293c88e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127240549 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.4127240549
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.1190549173
Short name T354
Test name
Test status
Simulation time 1210205960 ps
CPU time 14.15 seconds
Started May 12 03:46:46 PM PDT 24
Finished May 12 03:47:01 PM PDT 24
Peak memory 208044 kb
Host smart-5970de69-776b-42d6-8e42-27374cb9a123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190549173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.1190549173
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.2328439305
Short name T805
Test name
Test status
Simulation time 32589004 ps
CPU time 2 seconds
Started May 12 03:46:47 PM PDT 24
Finished May 12 03:46:50 PM PDT 24
Peak memory 210088 kb
Host smart-06a5add9-842e-4cb7-8c63-62a3bd2e03f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328439305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.2328439305
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.4031588705
Short name T601
Test name
Test status
Simulation time 10530773 ps
CPU time 0.97 seconds
Started May 12 03:47:14 PM PDT 24
Finished May 12 03:47:16 PM PDT 24
Peak memory 205940 kb
Host smart-563a12e5-11e1-4788-9e7a-4b0bf47455a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031588705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.4031588705
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.1758167054
Short name T773
Test name
Test status
Simulation time 448792804 ps
CPU time 2.99 seconds
Started May 12 03:46:54 PM PDT 24
Finished May 12 03:46:58 PM PDT 24
Peak memory 214532 kb
Host smart-8d118add-1301-4c38-b04a-30f32197778b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758167054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.1758167054
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.170109127
Short name T72
Test name
Test status
Simulation time 274706472 ps
CPU time 3.85 seconds
Started May 12 03:46:54 PM PDT 24
Finished May 12 03:46:59 PM PDT 24
Peak memory 210012 kb
Host smart-ec2952ff-6b07-47d0-89d7-d7abf75dcad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170109127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.170109127
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.167316326
Short name T91
Test name
Test status
Simulation time 125892142 ps
CPU time 2.62 seconds
Started May 12 03:46:55 PM PDT 24
Finished May 12 03:46:58 PM PDT 24
Peak memory 214352 kb
Host smart-b96bf457-bfba-4694-b6a8-9cb9ebf00ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167316326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.167316326
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.3580000689
Short name T274
Test name
Test status
Simulation time 510940429 ps
CPU time 5.23 seconds
Started May 12 03:46:53 PM PDT 24
Finished May 12 03:46:59 PM PDT 24
Peak memory 222412 kb
Host smart-1480078b-ad5b-4450-8aac-0078f3255ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580000689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.3580000689
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.3681606600
Short name T58
Test name
Test status
Simulation time 2229215463 ps
CPU time 19.77 seconds
Started May 12 03:46:54 PM PDT 24
Finished May 12 03:47:14 PM PDT 24
Peak memory 209688 kb
Host smart-abd8daa1-1875-4cd7-ade8-c16e17ec9def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681606600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.3681606600
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.3473691347
Short name T256
Test name
Test status
Simulation time 3828998387 ps
CPU time 67.28 seconds
Started May 12 03:46:52 PM PDT 24
Finished May 12 03:47:59 PM PDT 24
Peak memory 210520 kb
Host smart-34217e6c-3827-45a1-b7d8-d191fcca4a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473691347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.3473691347
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.3331247835
Short name T319
Test name
Test status
Simulation time 507638690 ps
CPU time 3.05 seconds
Started May 12 03:46:54 PM PDT 24
Finished May 12 03:46:57 PM PDT 24
Peak memory 206912 kb
Host smart-e0063154-dce5-4b27-8746-345cdc961a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331247835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.3331247835
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.953576570
Short name T756
Test name
Test status
Simulation time 86655569 ps
CPU time 4.28 seconds
Started May 12 03:46:53 PM PDT 24
Finished May 12 03:46:58 PM PDT 24
Peak memory 208552 kb
Host smart-674cfa2b-b6cc-4e36-bc7e-a788c8741efb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953576570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.953576570
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.2780566628
Short name T316
Test name
Test status
Simulation time 58809757 ps
CPU time 3.49 seconds
Started May 12 03:46:52 PM PDT 24
Finished May 12 03:46:56 PM PDT 24
Peak memory 208532 kb
Host smart-7c4eab02-2a28-4638-a960-98b1bdef61dd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780566628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.2780566628
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.707514060
Short name T85
Test name
Test status
Simulation time 97546278 ps
CPU time 4.11 seconds
Started May 12 03:46:52 PM PDT 24
Finished May 12 03:46:57 PM PDT 24
Peak memory 208316 kb
Host smart-64f983b8-5506-4afb-a159-eac0cd6feb7a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707514060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.707514060
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.1666827853
Short name T175
Test name
Test status
Simulation time 500417655 ps
CPU time 10.05 seconds
Started May 12 03:46:55 PM PDT 24
Finished May 12 03:47:05 PM PDT 24
Peak memory 208720 kb
Host smart-f84ee58e-e1f2-4320-aca8-dec45fd09d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666827853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.1666827853
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.558952686
Short name T471
Test name
Test status
Simulation time 70528992 ps
CPU time 2.27 seconds
Started May 12 03:46:50 PM PDT 24
Finished May 12 03:46:53 PM PDT 24
Peak memory 206612 kb
Host smart-eea0323d-7270-41f0-8c00-6bf877a7f322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558952686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.558952686
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.579234887
Short name T132
Test name
Test status
Simulation time 351573943 ps
CPU time 12.65 seconds
Started May 12 03:46:56 PM PDT 24
Finished May 12 03:47:09 PM PDT 24
Peak memory 216492 kb
Host smart-792e9193-a0c6-4a9c-868d-24bce8ca7483
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579234887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.579234887
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.3097636239
Short name T871
Test name
Test status
Simulation time 964174715 ps
CPU time 7.96 seconds
Started May 12 03:47:00 PM PDT 24
Finished May 12 03:47:08 PM PDT 24
Peak memory 222432 kb
Host smart-a98d244f-33ae-4476-b383-4f54a894c480
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097636239 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.3097636239
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.3951838031
Short name T422
Test name
Test status
Simulation time 1015443813 ps
CPU time 33.47 seconds
Started May 12 03:47:01 PM PDT 24
Finished May 12 03:47:35 PM PDT 24
Peak memory 208992 kb
Host smart-bb90524f-0053-4474-9abb-7525a97ef5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951838031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.3951838031
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.4003305816
Short name T432
Test name
Test status
Simulation time 28661131 ps
CPU time 0.76 seconds
Started May 12 03:47:07 PM PDT 24
Finished May 12 03:47:09 PM PDT 24
Peak memory 205924 kb
Host smart-daa5c68c-8e47-4b7d-84bd-b4f6e6b5129c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003305816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.4003305816
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.1188060768
Short name T391
Test name
Test status
Simulation time 22452307229 ps
CPU time 137.3 seconds
Started May 12 03:47:00 PM PDT 24
Finished May 12 03:49:18 PM PDT 24
Peak memory 222476 kb
Host smart-c4ffcf34-e92f-494a-8bac-da24a0b90324
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1188060768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.1188060768
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.903938440
Short name T666
Test name
Test status
Simulation time 84370195 ps
CPU time 3.2 seconds
Started May 12 03:47:09 PM PDT 24
Finished May 12 03:47:13 PM PDT 24
Peak memory 207960 kb
Host smart-c1e26f7d-74ac-4579-b14b-82d1960953c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903938440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.903938440
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.837019438
Short name T707
Test name
Test status
Simulation time 239029497 ps
CPU time 6.41 seconds
Started May 12 03:47:03 PM PDT 24
Finished May 12 03:47:10 PM PDT 24
Peak memory 210248 kb
Host smart-9df3331f-9070-43a1-8a02-eacbda09386d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837019438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.837019438
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.2107923700
Short name T798
Test name
Test status
Simulation time 295371595 ps
CPU time 3.08 seconds
Started May 12 03:47:03 PM PDT 24
Finished May 12 03:47:06 PM PDT 24
Peak memory 214316 kb
Host smart-0830ad0d-3b27-4b96-a0b0-7cad3aa22c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107923700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.2107923700
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.1142207572
Short name T340
Test name
Test status
Simulation time 279451413 ps
CPU time 2.74 seconds
Started May 12 03:47:04 PM PDT 24
Finished May 12 03:47:07 PM PDT 24
Peak memory 214244 kb
Host smart-52d0aeb0-7f32-40b5-9525-b339e0ca8817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142207572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.1142207572
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.1317290667
Short name T854
Test name
Test status
Simulation time 283403602 ps
CPU time 3.78 seconds
Started May 12 03:47:04 PM PDT 24
Finished May 12 03:47:09 PM PDT 24
Peak memory 206084 kb
Host smart-7a509417-95cd-4f68-b33c-6313173c9e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317290667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.1317290667
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.1052881425
Short name T713
Test name
Test status
Simulation time 239459235 ps
CPU time 5.9 seconds
Started May 12 03:47:07 PM PDT 24
Finished May 12 03:47:13 PM PDT 24
Peak memory 214344 kb
Host smart-c7ce16a4-ed35-4d76-aa0c-7a2080aa4a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052881425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.1052881425
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.2105320278
Short name T822
Test name
Test status
Simulation time 562323860 ps
CPU time 17.76 seconds
Started May 12 03:46:57 PM PDT 24
Finished May 12 03:47:16 PM PDT 24
Peak memory 207816 kb
Host smart-99d830e9-efa4-46de-93e2-00e5cf79b3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105320278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.2105320278
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.3995402960
Short name T232
Test name
Test status
Simulation time 92298291 ps
CPU time 4.83 seconds
Started May 12 03:47:02 PM PDT 24
Finished May 12 03:47:07 PM PDT 24
Peak memory 208860 kb
Host smart-fc0b7803-6518-453a-a80b-a0e25e6b91f6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995402960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.3995402960
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.2194957792
Short name T541
Test name
Test status
Simulation time 202855098 ps
CPU time 3.16 seconds
Started May 12 03:46:57 PM PDT 24
Finished May 12 03:47:01 PM PDT 24
Peak memory 206728 kb
Host smart-f76959c5-285c-4928-b21f-67abc6aefc18
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194957792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.2194957792
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.2270322825
Short name T873
Test name
Test status
Simulation time 241398072 ps
CPU time 3.33 seconds
Started May 12 03:47:05 PM PDT 24
Finished May 12 03:47:08 PM PDT 24
Peak memory 206912 kb
Host smart-55216e67-c047-4a32-bbea-3a0f531c3a49
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270322825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.2270322825
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.3961755022
Short name T712
Test name
Test status
Simulation time 84394063 ps
CPU time 2.62 seconds
Started May 12 03:47:05 PM PDT 24
Finished May 12 03:47:08 PM PDT 24
Peak memory 208104 kb
Host smart-b3df4c00-19fe-477e-9ac3-901d62e38716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961755022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.3961755022
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.890168341
Short name T639
Test name
Test status
Simulation time 261274554 ps
CPU time 6.72 seconds
Started May 12 03:46:57 PM PDT 24
Finished May 12 03:47:04 PM PDT 24
Peak memory 208684 kb
Host smart-4b6221f1-f8b9-48b3-b32c-6ac95630a61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890168341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.890168341
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.4063954171
Short name T171
Test name
Test status
Simulation time 219551944 ps
CPU time 5.45 seconds
Started May 12 03:47:05 PM PDT 24
Finished May 12 03:47:11 PM PDT 24
Peak memory 214352 kb
Host smart-4c121875-006d-4433-8239-ea1a38c25d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063954171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.4063954171
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.153475466
Short name T418
Test name
Test status
Simulation time 69846148 ps
CPU time 0.84 seconds
Started May 12 03:47:13 PM PDT 24
Finished May 12 03:47:14 PM PDT 24
Peak memory 205920 kb
Host smart-c2308c55-bc50-40a2-82e5-a9d8ebfc1354
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153475466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.153475466
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.1932754901
Short name T117
Test name
Test status
Simulation time 31307716 ps
CPU time 2.63 seconds
Started May 12 03:47:13 PM PDT 24
Finished May 12 03:47:16 PM PDT 24
Peak memory 214280 kb
Host smart-d291b754-7792-4b07-b622-9e455bc9ddbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1932754901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.1932754901
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.4172429867
Short name T63
Test name
Test status
Simulation time 1074478576 ps
CPU time 19.33 seconds
Started May 12 03:47:15 PM PDT 24
Finished May 12 03:47:35 PM PDT 24
Peak memory 222696 kb
Host smart-c9fea41d-a7a9-41fa-8d1e-a7af028d14c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172429867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.4172429867
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.3213051311
Short name T698
Test name
Test status
Simulation time 37137997 ps
CPU time 2.07 seconds
Started May 12 03:47:11 PM PDT 24
Finished May 12 03:47:14 PM PDT 24
Peak memory 208620 kb
Host smart-7740ac5c-4ae0-4760-ba63-95c8a85da68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213051311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.3213051311
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.2301484110
Short name T849
Test name
Test status
Simulation time 97853573 ps
CPU time 3.2 seconds
Started May 12 03:47:15 PM PDT 24
Finished May 12 03:47:19 PM PDT 24
Peak memory 214236 kb
Host smart-d74c55fe-b67e-4fe3-84b5-2fb44e1c7aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301484110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.2301484110
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.3821437020
Short name T845
Test name
Test status
Simulation time 902698476 ps
CPU time 5.33 seconds
Started May 12 03:47:10 PM PDT 24
Finished May 12 03:47:15 PM PDT 24
Peak memory 218448 kb
Host smart-91bdfebb-1fd6-4237-a9e2-fc794e402fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821437020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.3821437020
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.777746336
Short name T527
Test name
Test status
Simulation time 180661973 ps
CPU time 8.1 seconds
Started May 12 03:47:16 PM PDT 24
Finished May 12 03:47:25 PM PDT 24
Peak memory 218488 kb
Host smart-dc394e5d-863f-42ca-8194-1e5b880128ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777746336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.777746336
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.1419684130
Short name T440
Test name
Test status
Simulation time 403741239 ps
CPU time 9.06 seconds
Started May 12 03:47:09 PM PDT 24
Finished May 12 03:47:18 PM PDT 24
Peak memory 208472 kb
Host smart-e5607aa2-e4d1-4d43-abcb-2a92d9321007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419684130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.1419684130
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.4186165506
Short name T816
Test name
Test status
Simulation time 287794076 ps
CPU time 4.46 seconds
Started May 12 03:47:12 PM PDT 24
Finished May 12 03:47:16 PM PDT 24
Peak memory 208624 kb
Host smart-1ac40eb6-495c-433c-a11e-1fc3e4ba5f50
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186165506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.4186165506
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.1987182807
Short name T623
Test name
Test status
Simulation time 5377185039 ps
CPU time 46.17 seconds
Started May 12 03:47:19 PM PDT 24
Finished May 12 03:48:05 PM PDT 24
Peak memory 208648 kb
Host smart-f0a4fb0d-d6c2-4207-b5ff-91d733022a30
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987182807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.1987182807
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.2624090587
Short name T848
Test name
Test status
Simulation time 58390926 ps
CPU time 2.79 seconds
Started May 12 03:47:13 PM PDT 24
Finished May 12 03:47:16 PM PDT 24
Peak memory 209480 kb
Host smart-89a62622-ef00-4c22-860b-467d7f170a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624090587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.2624090587
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.3405470251
Short name T507
Test name
Test status
Simulation time 236000792 ps
CPU time 5.85 seconds
Started May 12 03:47:07 PM PDT 24
Finished May 12 03:47:14 PM PDT 24
Peak memory 206672 kb
Host smart-7e63e0a4-fbf4-4ebf-95c4-1cb197cf978a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405470251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.3405470251
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.1920392731
Short name T279
Test name
Test status
Simulation time 6838418201 ps
CPU time 220.58 seconds
Started May 12 03:47:12 PM PDT 24
Finished May 12 03:50:53 PM PDT 24
Peak memory 222664 kb
Host smart-d2b1ea2b-413f-4878-b3bd-dcab696dc5e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920392731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.1920392731
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.2706118203
Short name T607
Test name
Test status
Simulation time 605720141 ps
CPU time 7.91 seconds
Started May 12 03:47:12 PM PDT 24
Finished May 12 03:47:20 PM PDT 24
Peak memory 218244 kb
Host smart-a556156d-d752-4e0e-a7a2-0ec9d46197b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706118203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.2706118203
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.3526302905
Short name T674
Test name
Test status
Simulation time 620525854 ps
CPU time 2.84 seconds
Started May 12 03:47:12 PM PDT 24
Finished May 12 03:47:15 PM PDT 24
Peak memory 210276 kb
Host smart-1535398c-c113-42a7-9e3a-9e9667c6c8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526302905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.3526302905
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.3732184061
Short name T649
Test name
Test status
Simulation time 43189493 ps
CPU time 0.85 seconds
Started May 12 03:47:22 PM PDT 24
Finished May 12 03:47:23 PM PDT 24
Peak memory 205860 kb
Host smart-f05ca0db-b307-4c59-baac-827350e99427
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732184061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.3732184061
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.1519923447
Short name T229
Test name
Test status
Simulation time 419655338 ps
CPU time 3.33 seconds
Started May 12 03:47:16 PM PDT 24
Finished May 12 03:47:20 PM PDT 24
Peak memory 209964 kb
Host smart-1fda6b05-8ce5-4135-82b9-81871d15a789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519923447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.1519923447
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.767343205
Short name T875
Test name
Test status
Simulation time 240784807 ps
CPU time 4.86 seconds
Started May 12 03:47:20 PM PDT 24
Finished May 12 03:47:25 PM PDT 24
Peak memory 220004 kb
Host smart-25d5d4c6-383a-403c-9059-222e3f820b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767343205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.767343205
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.3569712539
Short name T90
Test name
Test status
Simulation time 318734899 ps
CPU time 1.83 seconds
Started May 12 03:47:18 PM PDT 24
Finished May 12 03:47:21 PM PDT 24
Peak memory 214260 kb
Host smart-afcf37b6-dfa7-4658-aa9d-2b5703e6576c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569712539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.3569712539
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.3902757652
Short name T528
Test name
Test status
Simulation time 655084195 ps
CPU time 3.5 seconds
Started May 12 03:47:21 PM PDT 24
Finished May 12 03:47:25 PM PDT 24
Peak memory 214308 kb
Host smart-a5cff1cb-b523-4a5e-99e5-8ed81f448848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902757652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.3902757652
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.3090177354
Short name T579
Test name
Test status
Simulation time 3372801977 ps
CPU time 6.91 seconds
Started May 12 03:47:21 PM PDT 24
Finished May 12 03:47:29 PM PDT 24
Peak memory 207900 kb
Host smart-f2cb90ee-88ef-4171-945c-2c1b32b856eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090177354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.3090177354
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.2414186556
Short name T519
Test name
Test status
Simulation time 986683757 ps
CPU time 17.51 seconds
Started May 12 03:47:13 PM PDT 24
Finished May 12 03:47:31 PM PDT 24
Peak memory 207964 kb
Host smart-40c97f06-5c98-4893-b304-7fb1035ce00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414186556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.2414186556
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.3238783520
Short name T831
Test name
Test status
Simulation time 142654403 ps
CPU time 2.51 seconds
Started May 12 03:47:17 PM PDT 24
Finished May 12 03:47:20 PM PDT 24
Peak memory 206880 kb
Host smart-b636243a-e6ed-4f69-b065-af6c6385e49e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238783520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.3238783520
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.3833247445
Short name T589
Test name
Test status
Simulation time 46449361 ps
CPU time 2.07 seconds
Started May 12 03:47:16 PM PDT 24
Finished May 12 03:47:18 PM PDT 24
Peak memory 208596 kb
Host smart-0b05c886-9d2a-42b4-b64b-28fdb5acf119
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833247445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.3833247445
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.1400850071
Short name T295
Test name
Test status
Simulation time 300312663 ps
CPU time 3.33 seconds
Started May 12 03:47:21 PM PDT 24
Finished May 12 03:47:25 PM PDT 24
Peak memory 206788 kb
Host smart-cbe2b6b0-c28b-4bc7-9091-70b8bfecd4b7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400850071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.1400850071
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_smoke.75618713
Short name T865
Test name
Test status
Simulation time 76299120 ps
CPU time 3.4 seconds
Started May 12 03:47:14 PM PDT 24
Finished May 12 03:47:18 PM PDT 24
Peak memory 208624 kb
Host smart-c029331e-c061-4dd4-818a-5c02cabe090f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75618713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.75618713
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.3430201003
Short name T633
Test name
Test status
Simulation time 91697446593 ps
CPU time 448.75 seconds
Started May 12 03:47:18 PM PDT 24
Finished May 12 03:54:47 PM PDT 24
Peak memory 222548 kb
Host smart-fd0ed425-b371-4398-85f6-3491143d50c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430201003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.3430201003
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.961294546
Short name T165
Test name
Test status
Simulation time 711494786 ps
CPU time 15.69 seconds
Started May 12 03:47:20 PM PDT 24
Finished May 12 03:47:36 PM PDT 24
Peak memory 222592 kb
Host smart-eb1d1eca-e9c3-48eb-a796-3afd4c8ed5cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961294546 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.961294546
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.2406147017
Short name T281
Test name
Test status
Simulation time 126276484 ps
CPU time 6.3 seconds
Started May 12 03:47:15 PM PDT 24
Finished May 12 03:47:22 PM PDT 24
Peak memory 209348 kb
Host smart-5a3d81a4-f9f4-4302-8dc8-4f4d364f32ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406147017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.2406147017
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.2985816383
Short name T796
Test name
Test status
Simulation time 280617754 ps
CPU time 6.55 seconds
Started May 12 03:47:21 PM PDT 24
Finished May 12 03:47:28 PM PDT 24
Peak memory 211016 kb
Host smart-287febcf-f36c-4fa2-876a-95e1ed77e08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985816383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.2985816383
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.2873206739
Short name T82
Test name
Test status
Simulation time 13315852 ps
CPU time 0.79 seconds
Started May 12 03:44:31 PM PDT 24
Finished May 12 03:44:32 PM PDT 24
Peak memory 205900 kb
Host smart-c86ba9d3-4edd-4c51-996d-a62b9e39fb70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873206739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.2873206739
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.2905018257
Short name T61
Test name
Test status
Simulation time 61492604 ps
CPU time 3.9 seconds
Started May 12 03:44:36 PM PDT 24
Finished May 12 03:44:40 PM PDT 24
Peak memory 209068 kb
Host smart-741f73a6-1003-4430-973f-ebed84eaeb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905018257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.2905018257
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.2055727749
Short name T610
Test name
Test status
Simulation time 589330813 ps
CPU time 8.07 seconds
Started May 12 03:44:26 PM PDT 24
Finished May 12 03:44:35 PM PDT 24
Peak memory 222436 kb
Host smart-bfbb3692-62d7-4b9b-94a8-fe4e68b8bf5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055727749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.2055727749
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.1818095481
Short name T851
Test name
Test status
Simulation time 262724355 ps
CPU time 3.85 seconds
Started May 12 03:44:26 PM PDT 24
Finished May 12 03:44:31 PM PDT 24
Peak memory 214248 kb
Host smart-7ce145ba-fd2f-4d36-a10a-e6678067cd01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818095481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.1818095481
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.2942355372
Short name T204
Test name
Test status
Simulation time 183119710 ps
CPU time 4.73 seconds
Started May 12 03:44:20 PM PDT 24
Finished May 12 03:44:25 PM PDT 24
Peak memory 210828 kb
Host smart-d3cefabb-0a66-49e9-971d-2df245eee3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942355372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.2942355372
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.3150619677
Short name T379
Test name
Test status
Simulation time 303936875 ps
CPU time 6.13 seconds
Started May 12 03:44:47 PM PDT 24
Finished May 12 03:44:54 PM PDT 24
Peak memory 208944 kb
Host smart-ea193b90-10ed-4821-88b4-ffd887a0b29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150619677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.3150619677
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.3826947965
Short name T10
Test name
Test status
Simulation time 1137434041 ps
CPU time 19.02 seconds
Started May 12 03:44:31 PM PDT 24
Finished May 12 03:44:50 PM PDT 24
Peak memory 230684 kb
Host smart-f7aa6ecf-5057-446e-a078-ef3dd31b5cbf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826947965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.3826947965
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.3168211135
Short name T565
Test name
Test status
Simulation time 553983331 ps
CPU time 5.36 seconds
Started May 12 03:44:15 PM PDT 24
Finished May 12 03:44:21 PM PDT 24
Peak memory 206788 kb
Host smart-96ef6b3e-c51d-4728-b4d4-d067ca099fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168211135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.3168211135
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.1940298750
Short name T899
Test name
Test status
Simulation time 105127969 ps
CPU time 4.33 seconds
Started May 12 03:44:11 PM PDT 24
Finished May 12 03:44:16 PM PDT 24
Peak memory 206760 kb
Host smart-4ab6b03d-3c47-428f-a05e-ab10013070f7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940298750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.1940298750
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.1264686241
Short name T637
Test name
Test status
Simulation time 176623498 ps
CPU time 3.86 seconds
Started May 12 03:44:11 PM PDT 24
Finished May 12 03:44:15 PM PDT 24
Peak memory 206952 kb
Host smart-d0c11d8e-40ee-4644-bcb3-fc9bf5f60890
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264686241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.1264686241
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.588537748
Short name T789
Test name
Test status
Simulation time 136429740 ps
CPU time 3.34 seconds
Started May 12 03:44:38 PM PDT 24
Finished May 12 03:44:42 PM PDT 24
Peak memory 206764 kb
Host smart-761024ff-a03c-486a-8bfe-ada4fe9031d4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588537748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.588537748
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.2624996605
Short name T2
Test name
Test status
Simulation time 85290843 ps
CPU time 3.51 seconds
Started May 12 03:44:28 PM PDT 24
Finished May 12 03:44:32 PM PDT 24
Peak memory 215720 kb
Host smart-6ec43ae1-f075-43c6-a3e6-dcabe10b3e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624996605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.2624996605
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.3624043998
Short name T388
Test name
Test status
Simulation time 53252289 ps
CPU time 2.3 seconds
Started May 12 03:44:11 PM PDT 24
Finished May 12 03:44:14 PM PDT 24
Peak memory 208472 kb
Host smart-c25d2ded-2d55-4cc5-aafb-78df580a1720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624043998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.3624043998
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.3612506056
Short name T136
Test name
Test status
Simulation time 212507377 ps
CPU time 13.58 seconds
Started May 12 03:44:49 PM PDT 24
Finished May 12 03:45:03 PM PDT 24
Peak memory 222628 kb
Host smart-371e8eb7-1f0c-4ccc-bff1-9d428e505eea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612506056 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.3612506056
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.2714313031
Short name T254
Test name
Test status
Simulation time 193575795 ps
CPU time 5.38 seconds
Started May 12 03:44:25 PM PDT 24
Finished May 12 03:44:31 PM PDT 24
Peak memory 210272 kb
Host smart-988f8015-cd30-494f-ba7b-e218c2964cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714313031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.2714313031
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.3476423279
Short name T833
Test name
Test status
Simulation time 251891769 ps
CPU time 3.5 seconds
Started May 12 03:44:30 PM PDT 24
Finished May 12 03:44:34 PM PDT 24
Peak memory 210468 kb
Host smart-4acf7932-c731-49f0-a639-f889573507ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476423279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.3476423279
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.2515217354
Short name T792
Test name
Test status
Simulation time 112146743 ps
CPU time 0.8 seconds
Started May 12 03:47:27 PM PDT 24
Finished May 12 03:47:28 PM PDT 24
Peak memory 205880 kb
Host smart-2145cb4b-30b7-4b99-94ca-5e427542a298
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515217354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.2515217354
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.830532610
Short name T377
Test name
Test status
Simulation time 184588468 ps
CPU time 4.51 seconds
Started May 12 03:47:36 PM PDT 24
Finished May 12 03:47:41 PM PDT 24
Peak memory 214260 kb
Host smart-397c959a-3a4a-4f7f-ae2f-57d3d77f7ca6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=830532610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.830532610
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.1132675362
Short name T20
Test name
Test status
Simulation time 110343995 ps
CPU time 3.62 seconds
Started May 12 03:47:25 PM PDT 24
Finished May 12 03:47:29 PM PDT 24
Peak memory 209416 kb
Host smart-43f573f1-c127-45e3-91d7-bb98babeae2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132675362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.1132675362
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.4035736476
Short name T830
Test name
Test status
Simulation time 83520324 ps
CPU time 4.39 seconds
Started May 12 03:47:24 PM PDT 24
Finished May 12 03:47:29 PM PDT 24
Peak memory 218360 kb
Host smart-bdc90e29-2b15-4cbe-880e-3f961d97fe23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035736476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.4035736476
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.3839001519
Short name T98
Test name
Test status
Simulation time 1145382779 ps
CPU time 7.52 seconds
Started May 12 03:47:23 PM PDT 24
Finished May 12 03:47:31 PM PDT 24
Peak memory 214272 kb
Host smart-c16888e7-dda9-4bc5-b450-930dd57c7d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839001519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.3839001519
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.2128880459
Short name T889
Test name
Test status
Simulation time 796440849 ps
CPU time 5.98 seconds
Started May 12 03:47:24 PM PDT 24
Finished May 12 03:47:30 PM PDT 24
Peak memory 215976 kb
Host smart-f115a094-15ae-4c15-9955-f1b3525ad091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128880459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.2128880459
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.90740753
Short name T472
Test name
Test status
Simulation time 7022241931 ps
CPU time 17.08 seconds
Started May 12 03:47:22 PM PDT 24
Finished May 12 03:47:40 PM PDT 24
Peak memory 207664 kb
Host smart-5f4f7c6e-b87f-47c9-8dff-de9bf40142ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90740753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.90740753
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.1636713087
Short name T509
Test name
Test status
Simulation time 481598817 ps
CPU time 3.31 seconds
Started May 12 03:47:23 PM PDT 24
Finished May 12 03:47:27 PM PDT 24
Peak memory 206812 kb
Host smart-176d1f4b-7402-4491-8b40-664f482c9d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636713087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.1636713087
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.2248128054
Short name T643
Test name
Test status
Simulation time 108627915 ps
CPU time 3.91 seconds
Started May 12 03:47:25 PM PDT 24
Finished May 12 03:47:29 PM PDT 24
Peak memory 206892 kb
Host smart-26a0814f-4f91-4d6b-99da-85373cc5e05c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248128054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.2248128054
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.3784045430
Short name T451
Test name
Test status
Simulation time 72823944 ps
CPU time 2.61 seconds
Started May 12 03:47:23 PM PDT 24
Finished May 12 03:47:26 PM PDT 24
Peak memory 208816 kb
Host smart-2bbc9969-6187-42a4-9061-c98bcf996591
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784045430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.3784045430
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.1131417864
Short name T795
Test name
Test status
Simulation time 868379875 ps
CPU time 6.62 seconds
Started May 12 03:47:23 PM PDT 24
Finished May 12 03:47:30 PM PDT 24
Peak memory 208104 kb
Host smart-94f8f05d-d9a4-4443-b6e9-23bc5d7130ce
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131417864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.1131417864
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.3960533036
Short name T801
Test name
Test status
Simulation time 365718667 ps
CPU time 3.83 seconds
Started May 12 03:47:24 PM PDT 24
Finished May 12 03:47:28 PM PDT 24
Peak memory 222428 kb
Host smart-c6b0fea5-3c03-432f-bc15-026c7df935ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960533036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.3960533036
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.2456089334
Short name T608
Test name
Test status
Simulation time 268270976 ps
CPU time 6.89 seconds
Started May 12 03:47:25 PM PDT 24
Finished May 12 03:47:32 PM PDT 24
Peak memory 208240 kb
Host smart-1a3f78a1-226d-4ac9-8ee8-cd5e9ddeb8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456089334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.2456089334
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.2229116149
Short name T177
Test name
Test status
Simulation time 6398279796 ps
CPU time 22.95 seconds
Started May 12 03:47:27 PM PDT 24
Finished May 12 03:47:50 PM PDT 24
Peak memory 216932 kb
Host smart-fd2cd399-1a7f-48f2-ae45-e2a598248986
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229116149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.2229116149
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.2952466878
Short name T54
Test name
Test status
Simulation time 1790006940 ps
CPU time 10.1 seconds
Started May 12 03:47:29 PM PDT 24
Finished May 12 03:47:39 PM PDT 24
Peak memory 222568 kb
Host smart-6949a217-7121-450f-9f67-71ce01158f84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952466878 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.2952466878
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.4108938160
Short name T554
Test name
Test status
Simulation time 316479934 ps
CPU time 9.49 seconds
Started May 12 03:47:27 PM PDT 24
Finished May 12 03:47:37 PM PDT 24
Peak memory 218300 kb
Host smart-5e790f6e-493f-45ff-8aff-42b11186d0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108938160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.4108938160
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.234010386
Short name T731
Test name
Test status
Simulation time 80471739 ps
CPU time 2.52 seconds
Started May 12 03:47:26 PM PDT 24
Finished May 12 03:47:29 PM PDT 24
Peak memory 210860 kb
Host smart-dd9e0b40-ff3a-474b-952c-123bd3f1da76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234010386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.234010386
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.1122745520
Short name T551
Test name
Test status
Simulation time 39558430 ps
CPU time 0.77 seconds
Started May 12 03:47:31 PM PDT 24
Finished May 12 03:47:32 PM PDT 24
Peak memory 205908 kb
Host smart-3926ecfe-4f44-4fa4-9468-c3ee08453d00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122745520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.1122745520
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.4020267329
Short name T904
Test name
Test status
Simulation time 689284157 ps
CPU time 10.56 seconds
Started May 12 03:47:30 PM PDT 24
Finished May 12 03:47:41 PM PDT 24
Peak memory 215644 kb
Host smart-abd7ad37-89f4-4497-9931-55e40aaa9526
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4020267329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.4020267329
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.933553929
Short name T594
Test name
Test status
Simulation time 172843954 ps
CPU time 3.02 seconds
Started May 12 03:47:29 PM PDT 24
Finished May 12 03:47:33 PM PDT 24
Peak memory 218412 kb
Host smart-77681114-291f-4fe3-9d11-dc525ab78777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933553929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.933553929
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.80309662
Short name T288
Test name
Test status
Simulation time 6566208702 ps
CPU time 29.73 seconds
Started May 12 03:47:31 PM PDT 24
Finished May 12 03:48:02 PM PDT 24
Peak memory 222400 kb
Host smart-d66ffe4e-ca57-4156-bbb7-d84743ba5b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80309662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.80309662
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.3907735935
Short name T334
Test name
Test status
Simulation time 214641792 ps
CPU time 4.08 seconds
Started May 12 03:47:28 PM PDT 24
Finished May 12 03:47:32 PM PDT 24
Peak memory 207828 kb
Host smart-ff241ba3-14cf-4ba9-9ff5-c9bf9cb762dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907735935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.3907735935
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.4149368831
Short name T750
Test name
Test status
Simulation time 334433275 ps
CPU time 7.53 seconds
Started May 12 03:47:28 PM PDT 24
Finished May 12 03:47:37 PM PDT 24
Peak memory 218120 kb
Host smart-e39b6a6f-d018-4204-91c1-8cc82894a9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149368831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.4149368831
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.2311347879
Short name T491
Test name
Test status
Simulation time 228695548 ps
CPU time 6.58 seconds
Started May 12 03:47:29 PM PDT 24
Finished May 12 03:47:36 PM PDT 24
Peak memory 208252 kb
Host smart-f565f1b5-93ab-45e7-adb2-451b9f6bb964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311347879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.2311347879
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.3621421685
Short name T537
Test name
Test status
Simulation time 630808591 ps
CPU time 7.99 seconds
Started May 12 03:47:31 PM PDT 24
Finished May 12 03:47:39 PM PDT 24
Peak memory 208964 kb
Host smart-653d312f-19d3-4183-b36a-41da9c09f863
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621421685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.3621421685
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.3544758760
Short name T748
Test name
Test status
Simulation time 1468440336 ps
CPU time 8.34 seconds
Started May 12 03:47:28 PM PDT 24
Finished May 12 03:47:37 PM PDT 24
Peak memory 208212 kb
Host smart-2d723fd2-387e-4833-b38b-5ec2c7382d89
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544758760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.3544758760
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.1613464907
Short name T218
Test name
Test status
Simulation time 10401110364 ps
CPU time 62.75 seconds
Started May 12 03:47:29 PM PDT 24
Finished May 12 03:48:32 PM PDT 24
Peak memory 206836 kb
Host smart-d094dfff-6323-4241-a53d-68261e65226e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613464907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.1613464907
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.2492527880
Short name T559
Test name
Test status
Simulation time 1557025386 ps
CPU time 28.43 seconds
Started May 12 03:47:31 PM PDT 24
Finished May 12 03:47:59 PM PDT 24
Peak memory 208908 kb
Host smart-b0618119-b1be-4a7a-9aa3-f1028ace0a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492527880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.2492527880
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.3648728594
Short name T423
Test name
Test status
Simulation time 40837005 ps
CPU time 2.74 seconds
Started May 12 03:47:31 PM PDT 24
Finished May 12 03:47:34 PM PDT 24
Peak memory 208500 kb
Host smart-0e2bfc3f-74fb-46ac-a988-ddf62f10a94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648728594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.3648728594
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.102302398
Short name T138
Test name
Test status
Simulation time 1071563563 ps
CPU time 13.66 seconds
Started May 12 03:47:33 PM PDT 24
Finished May 12 03:47:47 PM PDT 24
Peak memory 222256 kb
Host smart-d586bc94-3be2-42f0-bf6e-ae7547b55441
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102302398 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.102302398
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.1178014987
Short name T28
Test name
Test status
Simulation time 559652084 ps
CPU time 5.61 seconds
Started May 12 03:47:27 PM PDT 24
Finished May 12 03:47:33 PM PDT 24
Peak memory 214292 kb
Host smart-9a657cd5-b9fd-4fab-96b0-e055da0ad1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178014987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.1178014987
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.4201323610
Short name T42
Test name
Test status
Simulation time 155712315 ps
CPU time 2.28 seconds
Started May 12 03:47:31 PM PDT 24
Finished May 12 03:47:34 PM PDT 24
Peak memory 209836 kb
Host smart-7c6effd7-ebf6-493a-9719-e06308117614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201323610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.4201323610
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.1993982311
Short name T14
Test name
Test status
Simulation time 34403691 ps
CPU time 0.92 seconds
Started May 12 03:47:49 PM PDT 24
Finished May 12 03:47:50 PM PDT 24
Peak memory 206036 kb
Host smart-8da27439-9d5b-42a8-94d9-acd5b6b8e32a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993982311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.1993982311
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.1805948798
Short name T400
Test name
Test status
Simulation time 58807135 ps
CPU time 2.6 seconds
Started May 12 03:47:37 PM PDT 24
Finished May 12 03:47:40 PM PDT 24
Peak memory 214284 kb
Host smart-108609fd-dfdb-48d3-b168-28088d2d42a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1805948798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.1805948798
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.696118844
Short name T807
Test name
Test status
Simulation time 614634998 ps
CPU time 8.14 seconds
Started May 12 03:47:42 PM PDT 24
Finished May 12 03:47:50 PM PDT 24
Peak memory 221280 kb
Host smart-2383c90e-3838-4ba9-97f1-da729edd3c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696118844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.696118844
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.2406203352
Short name T742
Test name
Test status
Simulation time 241616285 ps
CPU time 1.97 seconds
Started May 12 03:47:39 PM PDT 24
Finished May 12 03:47:41 PM PDT 24
Peak memory 207444 kb
Host smart-61fccfd2-d465-4028-90a7-1c3b0a69b032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406203352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.2406203352
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.2751936254
Short name T269
Test name
Test status
Simulation time 39263080 ps
CPU time 2.43 seconds
Started May 12 03:47:41 PM PDT 24
Finished May 12 03:47:43 PM PDT 24
Peak memory 206616 kb
Host smart-38e498f3-66fe-4911-89ce-2c871f863dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751936254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.2751936254
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.862688468
Short name T194
Test name
Test status
Simulation time 107107978 ps
CPU time 3.49 seconds
Started May 12 03:47:36 PM PDT 24
Finished May 12 03:47:40 PM PDT 24
Peak memory 214768 kb
Host smart-2fbb277c-7a22-4a83-be02-c341507a44f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862688468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.862688468
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.3383647762
Short name T222
Test name
Test status
Simulation time 1083878876 ps
CPU time 20.46 seconds
Started May 12 03:47:50 PM PDT 24
Finished May 12 03:48:11 PM PDT 24
Peak memory 209072 kb
Host smart-a2bd796f-573a-426d-b4cd-9fe4bbf55b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383647762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.3383647762
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.561926791
Short name T636
Test name
Test status
Simulation time 5190856061 ps
CPU time 34.02 seconds
Started May 12 03:47:33 PM PDT 24
Finished May 12 03:48:08 PM PDT 24
Peak memory 207952 kb
Host smart-0b1d6447-53b9-4005-b709-5aa862e37cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561926791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.561926791
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.747219967
Short name T670
Test name
Test status
Simulation time 66655000 ps
CPU time 3.49 seconds
Started May 12 03:47:34 PM PDT 24
Finished May 12 03:47:38 PM PDT 24
Peak memory 207096 kb
Host smart-83502418-5d5e-4c3b-94da-68a0b721ab2f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747219967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.747219967
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.884399761
Short name T690
Test name
Test status
Simulation time 676519474 ps
CPU time 18.95 seconds
Started May 12 03:47:34 PM PDT 24
Finished May 12 03:47:54 PM PDT 24
Peak memory 208724 kb
Host smart-ead2e93a-f707-4e24-887a-c21ef530f5bf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884399761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.884399761
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.521746591
Short name T562
Test name
Test status
Simulation time 164922428 ps
CPU time 3.6 seconds
Started May 12 03:47:36 PM PDT 24
Finished May 12 03:47:40 PM PDT 24
Peak memory 208996 kb
Host smart-6b68fbd9-c8f8-4020-8a6e-218ef6c7a1ea
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521746591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.521746591
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.2999976184
Short name T420
Test name
Test status
Simulation time 229740485 ps
CPU time 3.24 seconds
Started May 12 03:47:53 PM PDT 24
Finished May 12 03:47:57 PM PDT 24
Peak memory 218336 kb
Host smart-c1f26186-6c1e-4d57-87ef-f035ca1b05e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999976184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.2999976184
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.1931740407
Short name T790
Test name
Test status
Simulation time 168869092 ps
CPU time 2.7 seconds
Started May 12 03:47:52 PM PDT 24
Finished May 12 03:47:56 PM PDT 24
Peak memory 207360 kb
Host smart-17eddbcc-2006-4ead-a5ed-32067f58f087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931740407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.1931740407
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.4134278923
Short name T345
Test name
Test status
Simulation time 99035500 ps
CPU time 3.46 seconds
Started May 12 03:47:52 PM PDT 24
Finished May 12 03:47:56 PM PDT 24
Peak memory 208484 kb
Host smart-8d1cb266-225f-4f08-96ff-6789d6886e7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134278923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.4134278923
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.1073275824
Short name T246
Test name
Test status
Simulation time 163034074 ps
CPU time 7.37 seconds
Started May 12 03:47:35 PM PDT 24
Finished May 12 03:47:42 PM PDT 24
Peak memory 208408 kb
Host smart-f5204c9d-5e73-4748-ae3b-bb51ff166dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073275824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.1073275824
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.2506685608
Short name T183
Test name
Test status
Simulation time 129821386 ps
CPU time 2.85 seconds
Started May 12 03:47:40 PM PDT 24
Finished May 12 03:47:43 PM PDT 24
Peak memory 210088 kb
Host smart-ef7f2914-221a-4e2c-9bb3-21f3e3453d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506685608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.2506685608
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.1123637341
Short name T827
Test name
Test status
Simulation time 21701722 ps
CPU time 0.78 seconds
Started May 12 03:47:45 PM PDT 24
Finished May 12 03:47:46 PM PDT 24
Peak memory 205948 kb
Host smart-0a8dedde-09fc-434c-a5de-8d745fb0e848
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123637341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.1123637341
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.1851934989
Short name T523
Test name
Test status
Simulation time 181920387 ps
CPU time 3.87 seconds
Started May 12 03:47:48 PM PDT 24
Finished May 12 03:47:52 PM PDT 24
Peak memory 222784 kb
Host smart-3a8ccbdf-fe69-45fa-b154-561d8f1e6bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851934989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.1851934989
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.2145913144
Short name T457
Test name
Test status
Simulation time 300717331 ps
CPU time 2.03 seconds
Started May 12 03:47:43 PM PDT 24
Finished May 12 03:47:46 PM PDT 24
Peak memory 209116 kb
Host smart-1ee94854-a0af-432f-bc99-21ab5ea49d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145913144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.2145913144
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.463174167
Short name T47
Test name
Test status
Simulation time 213622928 ps
CPU time 3.31 seconds
Started May 12 03:47:46 PM PDT 24
Finished May 12 03:47:50 PM PDT 24
Peak memory 214312 kb
Host smart-55a4f8a2-2ed6-454e-b59e-ae394c175c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463174167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.463174167
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.949212290
Short name T843
Test name
Test status
Simulation time 246300759 ps
CPU time 4.35 seconds
Started May 12 03:47:42 PM PDT 24
Finished May 12 03:47:47 PM PDT 24
Peak memory 209356 kb
Host smart-a088183e-f419-4bd6-8a54-381bf574e755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949212290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.949212290
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.2445583828
Short name T257
Test name
Test status
Simulation time 794104785 ps
CPU time 7.2 seconds
Started May 12 03:47:44 PM PDT 24
Finished May 12 03:47:52 PM PDT 24
Peak memory 214348 kb
Host smart-f5720c20-6007-45e9-9d31-3a96360d839f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445583828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.2445583828
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.2310127666
Short name T759
Test name
Test status
Simulation time 962338735 ps
CPU time 8.55 seconds
Started May 12 03:47:43 PM PDT 24
Finished May 12 03:47:52 PM PDT 24
Peak memory 208568 kb
Host smart-2bc9ba49-ad63-4fa6-a120-66644005e06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310127666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.2310127666
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.1279800475
Short name T781
Test name
Test status
Simulation time 67936201 ps
CPU time 1.99 seconds
Started May 12 03:47:42 PM PDT 24
Finished May 12 03:47:45 PM PDT 24
Peak memory 206876 kb
Host smart-157562be-8725-40eb-8092-781590cd8957
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279800475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1279800475
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.4207277570
Short name T522
Test name
Test status
Simulation time 226241182 ps
CPU time 3.43 seconds
Started May 12 03:47:42 PM PDT 24
Finished May 12 03:47:45 PM PDT 24
Peak memory 208572 kb
Host smart-ad649afc-842e-497a-9a22-5a39ba5f9697
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207277570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.4207277570
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.2964446420
Short name T433
Test name
Test status
Simulation time 4101562265 ps
CPU time 23.61 seconds
Started May 12 03:47:43 PM PDT 24
Finished May 12 03:48:07 PM PDT 24
Peak memory 208044 kb
Host smart-4e67385a-bc22-4d3f-94ee-b191b6720b02
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964446420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.2964446420
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.2150598394
Short name T79
Test name
Test status
Simulation time 209864301 ps
CPU time 3.33 seconds
Started May 12 03:47:48 PM PDT 24
Finished May 12 03:47:51 PM PDT 24
Peak memory 209616 kb
Host smart-3841fa56-efbe-47dd-9c95-79ca25bccd4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150598394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.2150598394
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.877794799
Short name T463
Test name
Test status
Simulation time 7412675213 ps
CPU time 70.17 seconds
Started May 12 03:47:46 PM PDT 24
Finished May 12 03:48:56 PM PDT 24
Peak memory 208840 kb
Host smart-7afe0373-49e3-41b1-a3a9-fd2525e5bbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877794799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.877794799
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.3825287277
Short name T861
Test name
Test status
Simulation time 167356431 ps
CPU time 11.27 seconds
Started May 12 03:47:49 PM PDT 24
Finished May 12 03:48:01 PM PDT 24
Peak memory 222588 kb
Host smart-0fc36991-07f2-46c3-92dd-61dbffaef622
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825287277 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.3825287277
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.4224291401
Short name T569
Test name
Test status
Simulation time 984445434 ps
CPU time 10.01 seconds
Started May 12 03:47:45 PM PDT 24
Finished May 12 03:47:56 PM PDT 24
Peak memory 209452 kb
Host smart-185c6ac7-39a7-44d1-a61d-0cc0663f354b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224291401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.4224291401
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.2393509775
Short name T37
Test name
Test status
Simulation time 281682993 ps
CPU time 3.51 seconds
Started May 12 03:47:48 PM PDT 24
Finished May 12 03:47:52 PM PDT 24
Peak memory 210104 kb
Host smart-27b12f43-4f6f-4ec3-b3c4-3a5f1fd3a07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393509775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.2393509775
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.3723001111
Short name T413
Test name
Test status
Simulation time 19540352 ps
CPU time 1 seconds
Started May 12 03:48:00 PM PDT 24
Finished May 12 03:48:01 PM PDT 24
Peak memory 206076 kb
Host smart-0e4aea85-3161-4d21-a271-4ce43915b642
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723001111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.3723001111
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.2405423371
Short name T390
Test name
Test status
Simulation time 1243425647 ps
CPU time 65.34 seconds
Started May 12 03:47:50 PM PDT 24
Finished May 12 03:48:56 PM PDT 24
Peak memory 215444 kb
Host smart-6201e1c5-de81-400d-a3fd-4f6b0881d5bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2405423371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.2405423371
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.1575479401
Short name T161
Test name
Test status
Simulation time 75112655 ps
CPU time 3.8 seconds
Started May 12 03:47:54 PM PDT 24
Finished May 12 03:47:58 PM PDT 24
Peak memory 216580 kb
Host smart-d2560862-ab2a-4d4e-b395-59fa33fe7efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575479401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.1575479401
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.468755150
Short name T380
Test name
Test status
Simulation time 2220951621 ps
CPU time 20.52 seconds
Started May 12 03:47:49 PM PDT 24
Finished May 12 03:48:10 PM PDT 24
Peak memory 210604 kb
Host smart-bfccb32c-0d3a-4dbf-a57a-7809cc42ed59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468755150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.468755150
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.4036025002
Short name T87
Test name
Test status
Simulation time 91901659 ps
CPU time 2.14 seconds
Started May 12 03:47:50 PM PDT 24
Finished May 12 03:47:52 PM PDT 24
Peak memory 214228 kb
Host smart-9f156cb4-5fd0-4498-b1ee-aa48526b138b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036025002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.4036025002
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.699240012
Short name T234
Test name
Test status
Simulation time 312958354 ps
CPU time 2.91 seconds
Started May 12 03:47:50 PM PDT 24
Finished May 12 03:47:53 PM PDT 24
Peak memory 220304 kb
Host smart-468a8948-50ce-4e9d-b7a8-8c5ff31903d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699240012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.699240012
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.3293997357
Short name T719
Test name
Test status
Simulation time 1157968608 ps
CPU time 12.12 seconds
Started May 12 03:47:52 PM PDT 24
Finished May 12 03:48:05 PM PDT 24
Peak memory 207804 kb
Host smart-8f551413-c579-4f16-8fba-2572072a6fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293997357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.3293997357
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.2570210963
Short name T428
Test name
Test status
Simulation time 49589243 ps
CPU time 3.05 seconds
Started May 12 03:47:54 PM PDT 24
Finished May 12 03:47:57 PM PDT 24
Peak memory 206848 kb
Host smart-4d12fb8c-f2e9-42fa-a609-f97ec454063a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570210963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.2570210963
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.1649272251
Short name T291
Test name
Test status
Simulation time 121567646 ps
CPU time 3.35 seconds
Started May 12 03:47:45 PM PDT 24
Finished May 12 03:47:49 PM PDT 24
Peak memory 208488 kb
Host smart-bd3d16dd-d34e-4e86-8d68-7ae9792e89cf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649272251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.1649272251
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.3547281146
Short name T568
Test name
Test status
Simulation time 271047589 ps
CPU time 3.65 seconds
Started May 12 03:47:48 PM PDT 24
Finished May 12 03:47:52 PM PDT 24
Peak memory 206892 kb
Host smart-247a5c1d-089e-40da-9035-f45ba7a9735e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547281146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.3547281146
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.34850218
Short name T505
Test name
Test status
Simulation time 144669946 ps
CPU time 2.49 seconds
Started May 12 03:47:46 PM PDT 24
Finished May 12 03:47:49 PM PDT 24
Peak memory 206688 kb
Host smart-80bba22a-376e-4324-b643-8986d744a35e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34850218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.34850218
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.3346359896
Short name T421
Test name
Test status
Simulation time 64702324 ps
CPU time 1.75 seconds
Started May 12 03:47:53 PM PDT 24
Finished May 12 03:47:55 PM PDT 24
Peak memory 207964 kb
Host smart-0d1d27fa-a632-4564-8d4a-68dbbdcd29fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346359896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.3346359896
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.3196211653
Short name T494
Test name
Test status
Simulation time 469223971 ps
CPU time 6.4 seconds
Started May 12 03:47:46 PM PDT 24
Finished May 12 03:47:53 PM PDT 24
Peak memory 208276 kb
Host smart-fb22ca5b-04ed-4f9e-bb92-1fecbc4efce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196211653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.3196211653
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.110724921
Short name T348
Test name
Test status
Simulation time 1226340498 ps
CPU time 50.07 seconds
Started May 12 03:48:10 PM PDT 24
Finished May 12 03:49:01 PM PDT 24
Peak memory 222472 kb
Host smart-40bce17b-18d3-433a-aed5-a5c69a3157d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110724921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.110724921
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.509283593
Short name T268
Test name
Test status
Simulation time 344991372 ps
CPU time 12.34 seconds
Started May 12 03:48:10 PM PDT 24
Finished May 12 03:48:23 PM PDT 24
Peak memory 222616 kb
Host smart-46e968f8-31be-4c1e-b309-4b6023b34870
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509283593 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.509283593
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.1717463988
Short name T815
Test name
Test status
Simulation time 2072398938 ps
CPU time 50.84 seconds
Started May 12 03:47:50 PM PDT 24
Finished May 12 03:48:41 PM PDT 24
Peak memory 207780 kb
Host smart-da90c48a-db0a-4471-8a39-2ab4d93e47e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717463988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.1717463988
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.10266645
Short name T517
Test name
Test status
Simulation time 175201205 ps
CPU time 2.46 seconds
Started May 12 03:47:52 PM PDT 24
Finished May 12 03:47:55 PM PDT 24
Peak memory 210200 kb
Host smart-c0aef861-3f2a-4dac-a6d3-d4c673e6af12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10266645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.10266645
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.2458619720
Short name T585
Test name
Test status
Simulation time 34352452 ps
CPU time 0.92 seconds
Started May 12 03:48:02 PM PDT 24
Finished May 12 03:48:04 PM PDT 24
Peak memory 205912 kb
Host smart-8b59f92a-7052-49c7-81af-81cbbeab81d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458619720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.2458619720
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.3618236898
Short name T405
Test name
Test status
Simulation time 178558448 ps
CPU time 4.04 seconds
Started May 12 03:47:58 PM PDT 24
Finished May 12 03:48:03 PM PDT 24
Peak memory 214272 kb
Host smart-90ea939d-5bea-4cfd-9694-d1bc6658c98f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3618236898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.3618236898
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.1646941466
Short name T882
Test name
Test status
Simulation time 38272988 ps
CPU time 1.67 seconds
Started May 12 03:47:55 PM PDT 24
Finished May 12 03:47:57 PM PDT 24
Peak memory 214212 kb
Host smart-b0eb3fb6-1df5-4484-b412-530ad737d804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646941466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.1646941466
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.2705520792
Short name T251
Test name
Test status
Simulation time 131598050 ps
CPU time 3.28 seconds
Started May 12 03:47:57 PM PDT 24
Finished May 12 03:48:01 PM PDT 24
Peak memory 214244 kb
Host smart-986d7a76-5cb2-4988-91c6-01ab1cc9f3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705520792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.2705520792
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.901315615
Short name T741
Test name
Test status
Simulation time 775501875 ps
CPU time 4.05 seconds
Started May 12 03:47:58 PM PDT 24
Finished May 12 03:48:02 PM PDT 24
Peak memory 211992 kb
Host smart-24206486-903e-4f23-b781-ccc6c50982e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901315615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.901315615
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.4031703354
Short name T44
Test name
Test status
Simulation time 377348336 ps
CPU time 3.98 seconds
Started May 12 03:47:54 PM PDT 24
Finished May 12 03:47:59 PM PDT 24
Peak memory 209672 kb
Host smart-2be8cec2-de6e-4e12-b4a5-93e7449aee59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031703354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.4031703354
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.1526862206
Short name T216
Test name
Test status
Simulation time 1527007936 ps
CPU time 39.71 seconds
Started May 12 03:47:54 PM PDT 24
Finished May 12 03:48:34 PM PDT 24
Peak memory 219912 kb
Host smart-01bcc528-751f-49ff-b86e-221b8a98020a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526862206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.1526862206
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.2962211733
Short name T357
Test name
Test status
Simulation time 73384481 ps
CPU time 3.61 seconds
Started May 12 03:47:52 PM PDT 24
Finished May 12 03:47:56 PM PDT 24
Peak memory 208728 kb
Host smart-f9b7610f-1da5-4017-b99e-76f47686898c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962211733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.2962211733
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.741465443
Short name T538
Test name
Test status
Simulation time 35726875 ps
CPU time 2.72 seconds
Started May 12 03:47:52 PM PDT 24
Finished May 12 03:47:55 PM PDT 24
Peak memory 206724 kb
Host smart-5eb7296a-dbd0-48fb-94c2-fd3bbebbe557
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741465443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.741465443
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.312732882
Short name T480
Test name
Test status
Simulation time 796057668 ps
CPU time 9.42 seconds
Started May 12 03:47:54 PM PDT 24
Finished May 12 03:48:04 PM PDT 24
Peak memory 208268 kb
Host smart-a554cd44-0b43-4ad2-add9-f7647440cf4e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312732882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.312732882
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.3002164820
Short name T673
Test name
Test status
Simulation time 86749235 ps
CPU time 2.12 seconds
Started May 12 03:47:53 PM PDT 24
Finished May 12 03:47:56 PM PDT 24
Peak memory 206924 kb
Host smart-618b0ae2-eda1-4377-a4ad-ba83609fa8dc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002164820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.3002164820
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.3923670471
Short name T629
Test name
Test status
Simulation time 361023209 ps
CPU time 3 seconds
Started May 12 03:48:02 PM PDT 24
Finished May 12 03:48:06 PM PDT 24
Peak memory 215244 kb
Host smart-b8cbec2d-adf1-4646-9eb0-c914144d3261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923670471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.3923670471
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.2087219634
Short name T697
Test name
Test status
Simulation time 10376672808 ps
CPU time 42.47 seconds
Started May 12 03:47:53 PM PDT 24
Finished May 12 03:48:36 PM PDT 24
Peak memory 207924 kb
Host smart-e669c007-ada0-4717-9acf-f6256fc605e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087219634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.2087219634
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.1376983255
Short name T877
Test name
Test status
Simulation time 311418641 ps
CPU time 8.42 seconds
Started May 12 03:48:00 PM PDT 24
Finished May 12 03:48:09 PM PDT 24
Peak memory 208076 kb
Host smart-bd68f9d9-f3f3-4f1f-b7c3-333a0b1fe18d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376983255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.1376983255
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.162083636
Short name T350
Test name
Test status
Simulation time 64475477 ps
CPU time 3.77 seconds
Started May 12 03:47:56 PM PDT 24
Finished May 12 03:48:00 PM PDT 24
Peak memory 207624 kb
Host smart-0948ef3b-83b0-4070-9e9d-7ac1e66cda19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162083636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.162083636
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.3715421359
Short name T495
Test name
Test status
Simulation time 134659042 ps
CPU time 2.14 seconds
Started May 12 03:47:58 PM PDT 24
Finished May 12 03:48:00 PM PDT 24
Peak memory 209888 kb
Host smart-d6e485a5-ff6c-4c19-bb8b-9db71d0cd5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715421359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.3715421359
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.1433293749
Short name T415
Test name
Test status
Simulation time 36931312 ps
CPU time 0.88 seconds
Started May 12 03:48:07 PM PDT 24
Finished May 12 03:48:08 PM PDT 24
Peak memory 205908 kb
Host smart-25ac00c7-2cab-4726-ba4d-cd4d1c236a8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433293749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.1433293749
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.2729875730
Short name T468
Test name
Test status
Simulation time 156522263 ps
CPU time 2.98 seconds
Started May 12 03:48:02 PM PDT 24
Finished May 12 03:48:05 PM PDT 24
Peak memory 209256 kb
Host smart-319ea224-8e61-4e3d-88b6-dadc42f61d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729875730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.2729875730
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.2392334627
Short name T252
Test name
Test status
Simulation time 120351313 ps
CPU time 2.21 seconds
Started May 12 03:48:02 PM PDT 24
Finished May 12 03:48:05 PM PDT 24
Peak memory 214296 kb
Host smart-79c00a8c-a85d-445b-a85e-6cd5c4a729c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392334627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.2392334627
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.2455425642
Short name T17
Test name
Test status
Simulation time 74727825 ps
CPU time 2.56 seconds
Started May 12 03:48:07 PM PDT 24
Finished May 12 03:48:10 PM PDT 24
Peak memory 222372 kb
Host smart-1a403ac0-ade3-422a-b7b4-2b8ada73ddff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455425642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.2455425642
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.2337479374
Short name T732
Test name
Test status
Simulation time 336774826 ps
CPU time 2.82 seconds
Started May 12 03:48:05 PM PDT 24
Finished May 12 03:48:08 PM PDT 24
Peak memory 218988 kb
Host smart-8617a0cc-0669-4bc3-b86a-dc8e0b1e9a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337479374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.2337479374
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.1745087472
Short name T536
Test name
Test status
Simulation time 2792591508 ps
CPU time 22.55 seconds
Started May 12 03:48:02 PM PDT 24
Finished May 12 03:48:25 PM PDT 24
Peak memory 207120 kb
Host smart-0ed09906-3da6-45f5-97de-11b6d439b90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745087472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.1745087472
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.3569503464
Short name T661
Test name
Test status
Simulation time 1454858989 ps
CPU time 15.6 seconds
Started May 12 03:48:01 PM PDT 24
Finished May 12 03:48:17 PM PDT 24
Peak memory 208376 kb
Host smart-95f2eea0-8de0-4c47-b942-5fe4a01d44cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569503464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.3569503464
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.449513405
Short name T426
Test name
Test status
Simulation time 123919269 ps
CPU time 2.66 seconds
Started May 12 03:48:02 PM PDT 24
Finished May 12 03:48:05 PM PDT 24
Peak memory 206884 kb
Host smart-b4e97fae-8eb3-4b6e-b251-7d49d7529adc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449513405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.449513405
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.1455304130
Short name T687
Test name
Test status
Simulation time 114730992 ps
CPU time 4.34 seconds
Started May 12 03:48:01 PM PDT 24
Finished May 12 03:48:06 PM PDT 24
Peak memory 208736 kb
Host smart-1f687367-0211-4314-8d47-300b71ca3767
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455304130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.1455304130
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.3013517952
Short name T188
Test name
Test status
Simulation time 1301946936 ps
CPU time 9.05 seconds
Started May 12 03:48:04 PM PDT 24
Finished May 12 03:48:14 PM PDT 24
Peak memory 207908 kb
Host smart-8e364ef5-56bf-4187-aca7-af1649f20b81
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013517952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.3013517952
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.2002965147
Short name T238
Test name
Test status
Simulation time 91900623 ps
CPU time 2.35 seconds
Started May 12 03:48:03 PM PDT 24
Finished May 12 03:48:05 PM PDT 24
Peak memory 217976 kb
Host smart-4fd81c8b-b9b9-4f04-a878-b578808346bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002965147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.2002965147
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.1615186160
Short name T841
Test name
Test status
Simulation time 885156292 ps
CPU time 21 seconds
Started May 12 03:48:02 PM PDT 24
Finished May 12 03:48:23 PM PDT 24
Peak memory 207932 kb
Host smart-3725fa99-bdb2-4098-94bb-ccde50474624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615186160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.1615186160
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.94401866
Short name T236
Test name
Test status
Simulation time 838023929 ps
CPU time 33.23 seconds
Started May 12 03:48:01 PM PDT 24
Finished May 12 03:48:35 PM PDT 24
Peak memory 216312 kb
Host smart-36b6f41b-2c99-43e3-81b0-7214efebf560
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94401866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.94401866
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.2930905074
Short name T452
Test name
Test status
Simulation time 148238649 ps
CPU time 2.05 seconds
Started May 12 03:48:07 PM PDT 24
Finished May 12 03:48:10 PM PDT 24
Peak memory 214376 kb
Host smart-23a02d1d-c10c-404a-8e39-13dc00f1180b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930905074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.2930905074
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.2210939375
Short name T699
Test name
Test status
Simulation time 49980171 ps
CPU time 0.75 seconds
Started May 12 03:48:23 PM PDT 24
Finished May 12 03:48:24 PM PDT 24
Peak memory 205860 kb
Host smart-54012651-18ec-4cdc-a38a-5ffed92dc8c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210939375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.2210939375
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.3108283412
Short name T650
Test name
Test status
Simulation time 31882961 ps
CPU time 2.8 seconds
Started May 12 03:48:09 PM PDT 24
Finished May 12 03:48:12 PM PDT 24
Peak memory 214316 kb
Host smart-5a13f2d7-b80c-4af9-b9ff-6b710ea81441
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3108283412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.3108283412
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.1149472092
Short name T655
Test name
Test status
Simulation time 6797463607 ps
CPU time 12.53 seconds
Started May 12 03:48:22 PM PDT 24
Finished May 12 03:48:35 PM PDT 24
Peak memory 222192 kb
Host smart-123a1354-4054-4ec6-8ba8-1c2c2dd79cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149472092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.1149472092
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.750423584
Short name T46
Test name
Test status
Simulation time 1541012531 ps
CPU time 6.86 seconds
Started May 12 03:48:22 PM PDT 24
Finished May 12 03:48:30 PM PDT 24
Peak memory 209528 kb
Host smart-e81f8ee7-a99c-4bfa-9fd7-234c790a1357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750423584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.750423584
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.1003774705
Short name T778
Test name
Test status
Simulation time 193576907 ps
CPU time 3.64 seconds
Started May 12 03:48:09 PM PDT 24
Finished May 12 03:48:13 PM PDT 24
Peak memory 209368 kb
Host smart-fae764a5-7ad6-4c79-9f96-8d7d03344fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003774705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.1003774705
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.1039756729
Short name T364
Test name
Test status
Simulation time 248918955 ps
CPU time 4.14 seconds
Started May 12 03:48:10 PM PDT 24
Finished May 12 03:48:14 PM PDT 24
Peak memory 214212 kb
Host smart-94634ec6-a5fc-45fe-86ba-081a9830cf37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039756729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.1039756729
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.1899470038
Short name T343
Test name
Test status
Simulation time 116092083 ps
CPU time 5.85 seconds
Started May 12 03:48:07 PM PDT 24
Finished May 12 03:48:13 PM PDT 24
Peak memory 222464 kb
Host smart-02050158-b296-438b-a854-67b110d8a19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899470038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.1899470038
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.1944502588
Short name T788
Test name
Test status
Simulation time 57033144 ps
CPU time 3.53 seconds
Started May 12 03:48:08 PM PDT 24
Finished May 12 03:48:12 PM PDT 24
Peak memory 207484 kb
Host smart-38899ed1-5cab-4af3-92a0-902ffec29d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944502588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.1944502588
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.2307253961
Short name T575
Test name
Test status
Simulation time 59538993 ps
CPU time 2.29 seconds
Started May 12 03:48:22 PM PDT 24
Finished May 12 03:48:25 PM PDT 24
Peak memory 206732 kb
Host smart-16045548-6457-411f-9405-412b0967edd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307253961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.2307253961
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.3492103339
Short name T335
Test name
Test status
Simulation time 743467753 ps
CPU time 6.6 seconds
Started May 12 03:48:22 PM PDT 24
Finished May 12 03:48:29 PM PDT 24
Peak memory 208508 kb
Host smart-0b9f29ba-fd3c-404f-8f7a-4a8cdd3a48da
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492103339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.3492103339
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.4068752786
Short name T555
Test name
Test status
Simulation time 710701787 ps
CPU time 6.34 seconds
Started May 12 03:48:08 PM PDT 24
Finished May 12 03:48:15 PM PDT 24
Peak memory 208864 kb
Host smart-1e70e1f9-db11-4c70-be09-e0a7a6cd46aa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068752786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.4068752786
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.2785492544
Short name T880
Test name
Test status
Simulation time 275412872 ps
CPU time 3.99 seconds
Started May 12 03:48:09 PM PDT 24
Finished May 12 03:48:13 PM PDT 24
Peak memory 209104 kb
Host smart-55b25f97-2536-475a-aff5-069e91b67046
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785492544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.2785492544
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.1757197592
Short name T881
Test name
Test status
Simulation time 273657466 ps
CPU time 3.64 seconds
Started May 12 03:48:22 PM PDT 24
Finished May 12 03:48:26 PM PDT 24
Peak memory 206832 kb
Host smart-5a697bfe-3697-44bb-adc8-efdc4013ff30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757197592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.1757197592
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.2285474727
Short name T901
Test name
Test status
Simulation time 60382644 ps
CPU time 3.25 seconds
Started May 12 03:48:07 PM PDT 24
Finished May 12 03:48:11 PM PDT 24
Peak memory 208664 kb
Host smart-af8b51f9-1013-4778-8189-47b18b5259c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285474727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.2285474727
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.4156960106
Short name T299
Test name
Test status
Simulation time 1099536812 ps
CPU time 7.44 seconds
Started May 12 03:48:07 PM PDT 24
Finished May 12 03:48:15 PM PDT 24
Peak memory 214284 kb
Host smart-4d18784c-e453-43a3-98f0-7124aa21163d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156960106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.4156960106
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.3667127588
Short name T182
Test name
Test status
Simulation time 879707885 ps
CPU time 5.64 seconds
Started May 12 03:48:09 PM PDT 24
Finished May 12 03:48:15 PM PDT 24
Peak memory 210436 kb
Host smart-b1dce4d4-6eff-4d22-aa88-de26d8441195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667127588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.3667127588
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.719219216
Short name T439
Test name
Test status
Simulation time 26257678 ps
CPU time 0.88 seconds
Started May 12 03:48:19 PM PDT 24
Finished May 12 03:48:21 PM PDT 24
Peak memory 205952 kb
Host smart-fbbf1c75-cf82-42e5-9478-8f9a2c235042
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719219216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.719219216
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.3250337293
Short name T68
Test name
Test status
Simulation time 61508214 ps
CPU time 2.65 seconds
Started May 12 03:48:17 PM PDT 24
Finished May 12 03:48:20 PM PDT 24
Peak memory 214516 kb
Host smart-0a1d99ba-e0c3-49dd-a0d1-6247658344d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250337293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.3250337293
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.4203366137
Short name T337
Test name
Test status
Simulation time 146756549 ps
CPU time 2.55 seconds
Started May 12 03:48:13 PM PDT 24
Finished May 12 03:48:16 PM PDT 24
Peak memory 209540 kb
Host smart-3d063c5d-6c84-4565-89c6-30dada3e6a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203366137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.4203366137
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.2225399032
Short name T368
Test name
Test status
Simulation time 96482801 ps
CPU time 4.29 seconds
Started May 12 03:48:18 PM PDT 24
Finished May 12 03:48:22 PM PDT 24
Peak memory 221516 kb
Host smart-c2457b8e-ae06-4cb0-9ca6-62921b34f557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225399032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.2225399032
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.200222635
Short name T618
Test name
Test status
Simulation time 50525321 ps
CPU time 3.22 seconds
Started May 12 03:48:19 PM PDT 24
Finished May 12 03:48:22 PM PDT 24
Peak memory 220024 kb
Host smart-3210d856-f048-4980-b232-fa9da15a3961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200222635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.200222635
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.2209645699
Short name T761
Test name
Test status
Simulation time 97182670 ps
CPU time 3.71 seconds
Started May 12 03:48:13 PM PDT 24
Finished May 12 03:48:17 PM PDT 24
Peak memory 222432 kb
Host smart-64c9d873-f20d-4a76-b907-6990ad87ff9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209645699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.2209645699
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.167078197
Short name T353
Test name
Test status
Simulation time 81067681 ps
CPU time 4.25 seconds
Started May 12 03:48:15 PM PDT 24
Finished May 12 03:48:20 PM PDT 24
Peak memory 208896 kb
Host smart-6c0728ea-bec9-4e07-b927-8401d2994e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167078197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.167078197
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.3884044399
Short name T435
Test name
Test status
Simulation time 284456428 ps
CPU time 2.75 seconds
Started May 12 03:48:12 PM PDT 24
Finished May 12 03:48:15 PM PDT 24
Peak memory 206832 kb
Host smart-3b6b62ac-02f5-438c-a108-965acfae0a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884044399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.3884044399
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.4124823215
Short name T658
Test name
Test status
Simulation time 332255750 ps
CPU time 4.16 seconds
Started May 12 03:48:22 PM PDT 24
Finished May 12 03:48:27 PM PDT 24
Peak memory 208964 kb
Host smart-fd6b4465-36e0-47ca-b0db-99beefcaf389
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124823215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.4124823215
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.537165654
Short name T764
Test name
Test status
Simulation time 30043611 ps
CPU time 2.37 seconds
Started May 12 03:48:11 PM PDT 24
Finished May 12 03:48:13 PM PDT 24
Peak memory 206900 kb
Host smart-e42ca352-9c9d-4f87-ab1d-93eb67ec3cb9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537165654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.537165654
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.1168600960
Short name T477
Test name
Test status
Simulation time 53362860 ps
CPU time 3.41 seconds
Started May 12 03:48:16 PM PDT 24
Finished May 12 03:48:19 PM PDT 24
Peak memory 206976 kb
Host smart-4e13de40-20f2-455c-96b5-30bba19f4df8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168600960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.1168600960
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.1134472940
Short name T241
Test name
Test status
Simulation time 15305125 ps
CPU time 1.52 seconds
Started May 12 03:48:18 PM PDT 24
Finished May 12 03:48:20 PM PDT 24
Peak memory 208628 kb
Host smart-e057640e-e5d4-41e4-aa33-ff7a6e9988e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134472940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.1134472940
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.450177704
Short name T424
Test name
Test status
Simulation time 695740910 ps
CPU time 8.4 seconds
Started May 12 03:48:13 PM PDT 24
Finished May 12 03:48:22 PM PDT 24
Peak memory 208432 kb
Host smart-6676db78-37b3-4201-a855-f4e6c2d42614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450177704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.450177704
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.2917135996
Short name T499
Test name
Test status
Simulation time 163911351 ps
CPU time 4.18 seconds
Started May 12 03:48:16 PM PDT 24
Finished May 12 03:48:21 PM PDT 24
Peak memory 208328 kb
Host smart-815d44a6-d955-45ff-9b69-f472ae8817e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917135996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.2917135996
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.1174984265
Short name T51
Test name
Test status
Simulation time 130430246 ps
CPU time 1.81 seconds
Started May 12 03:48:16 PM PDT 24
Finished May 12 03:48:18 PM PDT 24
Peak memory 210184 kb
Host smart-6ab04f27-d393-4b24-9b4d-76b009dacb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174984265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.1174984265
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.504300289
Short name T696
Test name
Test status
Simulation time 23727893 ps
CPU time 0.76 seconds
Started May 12 03:48:28 PM PDT 24
Finished May 12 03:48:29 PM PDT 24
Peak memory 205920 kb
Host smart-b24f3f8e-1665-48a7-a20e-b0a1d18ab462
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504300289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.504300289
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.2741911777
Short name T560
Test name
Test status
Simulation time 111144746 ps
CPU time 4.89 seconds
Started May 12 03:48:27 PM PDT 24
Finished May 12 03:48:32 PM PDT 24
Peak memory 222456 kb
Host smart-06d45271-018f-462e-a445-d6a19578e2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741911777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.2741911777
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.3255568884
Short name T289
Test name
Test status
Simulation time 623892782 ps
CPU time 3.29 seconds
Started May 12 03:48:24 PM PDT 24
Finished May 12 03:48:27 PM PDT 24
Peak memory 214448 kb
Host smart-aaf86ea2-d59f-474d-ab3b-0d07731fe356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255568884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.3255568884
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.1162304018
Short name T596
Test name
Test status
Simulation time 418280352 ps
CPU time 2.84 seconds
Started May 12 03:48:26 PM PDT 24
Finished May 12 03:48:29 PM PDT 24
Peak memory 214364 kb
Host smart-3d9b54a1-6f19-4c0f-94e4-ab85b59ff041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162304018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.1162304018
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.3160066296
Short name T785
Test name
Test status
Simulation time 136407445 ps
CPU time 5.96 seconds
Started May 12 03:48:23 PM PDT 24
Finished May 12 03:48:29 PM PDT 24
Peak memory 208396 kb
Host smart-f57c3a74-95c3-4505-8373-ab3a0f5384f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160066296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.3160066296
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.2492293102
Short name T829
Test name
Test status
Simulation time 206347619 ps
CPU time 3.11 seconds
Started May 12 03:48:19 PM PDT 24
Finished May 12 03:48:23 PM PDT 24
Peak memory 206812 kb
Host smart-cece9f5a-df02-476e-9cc4-3dd1d84427ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492293102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.2492293102
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.3823403052
Short name T617
Test name
Test status
Simulation time 32713300 ps
CPU time 2.74 seconds
Started May 12 03:48:25 PM PDT 24
Finished May 12 03:48:28 PM PDT 24
Peak memory 206660 kb
Host smart-c3f2f1ea-29a7-484b-9c27-4bab4c26c567
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823403052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.3823403052
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.2150018287
Short name T434
Test name
Test status
Simulation time 452707214 ps
CPU time 6.44 seconds
Started May 12 03:48:19 PM PDT 24
Finished May 12 03:48:26 PM PDT 24
Peak memory 208092 kb
Host smart-494b84a8-0436-48e7-b71c-1874660660f3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150018287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.2150018287
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.511718999
Short name T893
Test name
Test status
Simulation time 1007032704 ps
CPU time 20.27 seconds
Started May 12 03:48:25 PM PDT 24
Finished May 12 03:48:46 PM PDT 24
Peak memory 207916 kb
Host smart-2a1207e2-846f-4814-893a-7dbc38d0c4fb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511718999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.511718999
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.3033915979
Short name T586
Test name
Test status
Simulation time 18511766 ps
CPU time 1.87 seconds
Started May 12 03:48:27 PM PDT 24
Finished May 12 03:48:30 PM PDT 24
Peak memory 215788 kb
Host smart-3049e319-0156-4a4d-84bd-eff3d5521cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033915979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.3033915979
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.2107057924
Short name T427
Test name
Test status
Simulation time 130794667 ps
CPU time 2.74 seconds
Started May 12 03:48:24 PM PDT 24
Finished May 12 03:48:27 PM PDT 24
Peak memory 208528 kb
Host smart-0c9ada75-403e-4a9f-9e42-b54c6cd61e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107057924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.2107057924
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.273954789
Short name T137
Test name
Test status
Simulation time 344293014 ps
CPU time 20.28 seconds
Started May 12 03:48:27 PM PDT 24
Finished May 12 03:48:48 PM PDT 24
Peak memory 222552 kb
Host smart-22371810-7862-4a58-8a51-fe3269ce4d06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273954789 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.273954789
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.2118395481
Short name T765
Test name
Test status
Simulation time 31526348 ps
CPU time 2.49 seconds
Started May 12 03:48:23 PM PDT 24
Finished May 12 03:48:26 PM PDT 24
Peak memory 207728 kb
Host smart-f36c24ee-f6a7-4580-9f91-f9311b188e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118395481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.2118395481
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.2267664881
Short name T133
Test name
Test status
Simulation time 1410006525 ps
CPU time 3.03 seconds
Started May 12 03:48:28 PM PDT 24
Finished May 12 03:48:32 PM PDT 24
Peak memory 210416 kb
Host smart-77f61cf6-6337-4412-b448-4f4f6fdaf12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267664881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.2267664881
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.2549673298
Short name T766
Test name
Test status
Simulation time 13493480 ps
CPU time 0.81 seconds
Started May 12 03:44:44 PM PDT 24
Finished May 12 03:44:45 PM PDT 24
Peak memory 205924 kb
Host smart-c2a8bcfe-e70f-4080-ab19-3e226f89c3c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549673298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.2549673298
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.3900462293
Short name T403
Test name
Test status
Simulation time 396368491 ps
CPU time 4.26 seconds
Started May 12 03:44:39 PM PDT 24
Finished May 12 03:44:44 PM PDT 24
Peak memory 214572 kb
Host smart-c7d7bb4d-f882-4e21-84c6-1e61336abd1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3900462293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.3900462293
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.1959449672
Short name T570
Test name
Test status
Simulation time 326195554 ps
CPU time 4.21 seconds
Started May 12 03:44:43 PM PDT 24
Finished May 12 03:44:47 PM PDT 24
Peak memory 210428 kb
Host smart-274a9d7a-babf-4807-81c3-c0192f895363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959449672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.1959449672
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.2306887926
Short name T458
Test name
Test status
Simulation time 77163740 ps
CPU time 2.36 seconds
Started May 12 03:44:35 PM PDT 24
Finished May 12 03:44:37 PM PDT 24
Peak memory 207912 kb
Host smart-804f12a7-20fc-4ddc-a141-1f6d2e8a3444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306887926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.2306887926
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.3606064970
Short name T89
Test name
Test status
Simulation time 280554569 ps
CPU time 2.29 seconds
Started May 12 03:44:51 PM PDT 24
Finished May 12 03:44:54 PM PDT 24
Peak memory 215360 kb
Host smart-5bbd5e00-b6c9-4b7b-95b6-22e2ea0137e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606064970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.3606064970
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.2511982074
Short name T228
Test name
Test status
Simulation time 384159134 ps
CPU time 5.05 seconds
Started May 12 03:44:54 PM PDT 24
Finished May 12 03:45:00 PM PDT 24
Peak memory 214236 kb
Host smart-80a05496-3eec-41c6-946a-323f0f852b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511982074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.2511982074
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.1956007564
Short name T206
Test name
Test status
Simulation time 189615680 ps
CPU time 3.83 seconds
Started May 12 03:44:36 PM PDT 24
Finished May 12 03:44:40 PM PDT 24
Peak memory 214308 kb
Host smart-65d2882f-6540-4122-8d19-b19f6986b00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956007564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.1956007564
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.2741342826
Short name T725
Test name
Test status
Simulation time 103536120 ps
CPU time 5.04 seconds
Started May 12 03:44:39 PM PDT 24
Finished May 12 03:44:44 PM PDT 24
Peak memory 218348 kb
Host smart-374743e2-c5e0-4bb5-a406-994b6482e796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741342826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.2741342826
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.4239064589
Short name T101
Test name
Test status
Simulation time 10059997517 ps
CPU time 15.81 seconds
Started May 12 03:44:57 PM PDT 24
Finished May 12 03:45:13 PM PDT 24
Peak memory 232964 kb
Host smart-6e34f7fc-2ac8-4cc8-9903-dcef3965a4e0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239064589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.4239064589
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.2852426060
Short name T619
Test name
Test status
Simulation time 287269123 ps
CPU time 5.31 seconds
Started May 12 03:44:30 PM PDT 24
Finished May 12 03:44:36 PM PDT 24
Peak memory 208068 kb
Host smart-9240e5bf-9705-43d6-9dcc-68308436b083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852426060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.2852426060
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.3270660554
Short name T782
Test name
Test status
Simulation time 266216822 ps
CPU time 3.63 seconds
Started May 12 03:44:37 PM PDT 24
Finished May 12 03:44:41 PM PDT 24
Peak memory 207992 kb
Host smart-2172ecca-fa19-45da-9b0a-d31166cd6631
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270660554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.3270660554
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.2975729428
Short name T611
Test name
Test status
Simulation time 136862476 ps
CPU time 2.61 seconds
Started May 12 03:44:29 PM PDT 24
Finished May 12 03:44:32 PM PDT 24
Peak memory 206872 kb
Host smart-70ce4830-8b31-40e5-a580-14645e078fa0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975729428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.2975729428
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.3650210032
Short name T475
Test name
Test status
Simulation time 558640407 ps
CPU time 5 seconds
Started May 12 03:44:48 PM PDT 24
Finished May 12 03:44:53 PM PDT 24
Peak memory 206788 kb
Host smart-aa63947f-64b2-481c-8e04-34223f4d8616
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650210032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.3650210032
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.3912419627
Short name T907
Test name
Test status
Simulation time 33797319 ps
CPU time 2.83 seconds
Started May 12 03:44:46 PM PDT 24
Finished May 12 03:44:49 PM PDT 24
Peak memory 218260 kb
Host smart-bcced305-dc64-4f3f-a426-9168068d1a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912419627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.3912419627
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.3583001014
Short name T409
Test name
Test status
Simulation time 397828254 ps
CPU time 4.84 seconds
Started May 12 03:44:38 PM PDT 24
Finished May 12 03:44:44 PM PDT 24
Peak memory 206940 kb
Host smart-7ae80f0e-8f0c-4df7-b414-8d37f1a60277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583001014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.3583001014
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.1077110765
Short name T653
Test name
Test status
Simulation time 12212711122 ps
CPU time 87.32 seconds
Started May 12 03:44:46 PM PDT 24
Finished May 12 03:46:14 PM PDT 24
Peak memory 222460 kb
Host smart-084a01e7-2cae-4b1d-b1d4-282a27199515
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077110765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.1077110765
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.3710141043
Short name T294
Test name
Test status
Simulation time 915303027 ps
CPU time 32.67 seconds
Started May 12 03:45:21 PM PDT 24
Finished May 12 03:45:56 PM PDT 24
Peak memory 214372 kb
Host smart-96a96bbe-60e4-4ab9-a2cc-37575828456a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710141043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.3710141043
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.714133473
Short name T371
Test name
Test status
Simulation time 814722329 ps
CPU time 2.55 seconds
Started May 12 03:44:42 PM PDT 24
Finished May 12 03:44:44 PM PDT 24
Peak memory 209852 kb
Host smart-6649f675-344e-467b-ace8-7ec1d096625b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714133473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.714133473
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.4057276738
Short name T769
Test name
Test status
Simulation time 12347869 ps
CPU time 0.8 seconds
Started May 12 03:48:29 PM PDT 24
Finished May 12 03:48:31 PM PDT 24
Peak memory 205884 kb
Host smart-8e4a3730-fa47-43e3-bf79-1f43cb0640c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057276738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.4057276738
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.4015313171
Short name T404
Test name
Test status
Simulation time 122573655 ps
CPU time 7.38 seconds
Started May 12 03:48:28 PM PDT 24
Finished May 12 03:48:37 PM PDT 24
Peak memory 214912 kb
Host smart-2b00e480-9264-4dbf-9f72-9c7cfcc27421
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4015313171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.4015313171
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.2572873078
Short name T66
Test name
Test status
Simulation time 346372683 ps
CPU time 10.09 seconds
Started May 12 03:48:28 PM PDT 24
Finished May 12 03:48:39 PM PDT 24
Peak memory 214524 kb
Host smart-3d94dc18-a6bc-4419-a605-a9735139a44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572873078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.2572873078
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.433643367
Short name T683
Test name
Test status
Simulation time 50245910 ps
CPU time 1.95 seconds
Started May 12 03:48:28 PM PDT 24
Finished May 12 03:48:31 PM PDT 24
Peak memory 207920 kb
Host smart-55ed70b6-73c1-46b8-a0a8-f23d4e4ffcdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433643367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.433643367
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.2110833521
Short name T365
Test name
Test status
Simulation time 90479204 ps
CPU time 3.66 seconds
Started May 12 03:48:29 PM PDT 24
Finished May 12 03:48:34 PM PDT 24
Peak memory 214404 kb
Host smart-db2fd1d0-f7a8-4f37-a7a5-a043d7b943d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110833521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.2110833521
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.1266190723
Short name T542
Test name
Test status
Simulation time 27521179 ps
CPU time 1.73 seconds
Started May 12 03:48:29 PM PDT 24
Finished May 12 03:48:31 PM PDT 24
Peak memory 214224 kb
Host smart-44cab6f3-8d45-4c01-a399-cd40d311cb7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266190723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.1266190723
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.848256677
Short name T645
Test name
Test status
Simulation time 66941859 ps
CPU time 3.58 seconds
Started May 12 03:48:27 PM PDT 24
Finished May 12 03:48:31 PM PDT 24
Peak memory 209552 kb
Host smart-deb8109a-b548-41e9-986c-a34bd1f46bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848256677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.848256677
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.3293372755
Short name T172
Test name
Test status
Simulation time 94404906 ps
CPU time 5.01 seconds
Started May 12 03:48:28 PM PDT 24
Finished May 12 03:48:34 PM PDT 24
Peak memory 214276 kb
Host smart-ae4ad0a0-c30a-4ee1-9a1a-4f3f44434eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293372755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.3293372755
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.2195905410
Short name T679
Test name
Test status
Simulation time 89553375 ps
CPU time 2.59 seconds
Started May 12 03:48:28 PM PDT 24
Finished May 12 03:48:32 PM PDT 24
Peak memory 206848 kb
Host smart-06e7029d-0655-46e5-ad82-21852df21996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195905410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.2195905410
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.3864774034
Short name T301
Test name
Test status
Simulation time 179537542 ps
CPU time 2.75 seconds
Started May 12 03:48:24 PM PDT 24
Finished May 12 03:48:28 PM PDT 24
Peak memory 208520 kb
Host smart-98e6d479-93c7-4747-a34d-751e45dccf88
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864774034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.3864774034
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.995594521
Short name T511
Test name
Test status
Simulation time 99962365 ps
CPU time 2.78 seconds
Started May 12 03:48:23 PM PDT 24
Finished May 12 03:48:26 PM PDT 24
Peak memory 206968 kb
Host smart-4a2f82c6-924f-4835-9001-74e4c6789b23
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995594521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.995594521
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.2335357607
Short name T602
Test name
Test status
Simulation time 3330829627 ps
CPU time 33.86 seconds
Started May 12 03:48:29 PM PDT 24
Finished May 12 03:49:03 PM PDT 24
Peak memory 209064 kb
Host smart-d3ec0093-be9e-4787-98f2-ea1429be88c4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335357607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.2335357607
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.3610979596
Short name T734
Test name
Test status
Simulation time 2162729606 ps
CPU time 10.85 seconds
Started May 12 03:48:29 PM PDT 24
Finished May 12 03:48:41 PM PDT 24
Peak memory 208968 kb
Host smart-5d64acdb-7360-4c40-a970-7a2fefb9c687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610979596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.3610979596
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.390543050
Short name T628
Test name
Test status
Simulation time 387280442 ps
CPU time 3.21 seconds
Started May 12 03:48:26 PM PDT 24
Finished May 12 03:48:30 PM PDT 24
Peak memory 207380 kb
Host smart-ab577b3f-e36e-4e8d-b7cf-88a5b47b7514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390543050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.390543050
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.819968439
Short name T383
Test name
Test status
Simulation time 201039717 ps
CPU time 4.24 seconds
Started May 12 03:48:28 PM PDT 24
Finished May 12 03:48:33 PM PDT 24
Peak memory 208564 kb
Host smart-e73bc234-9f3f-46ac-9d2c-064eb5e010e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819968439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.819968439
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.43335907
Short name T695
Test name
Test status
Simulation time 39568761 ps
CPU time 3.18 seconds
Started May 12 03:48:29 PM PDT 24
Finished May 12 03:48:33 PM PDT 24
Peak memory 207532 kb
Host smart-7f2491be-9bc0-43eb-9b4d-b06730db8369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43335907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.43335907
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.2887324250
Short name T139
Test name
Test status
Simulation time 261705343 ps
CPU time 1.93 seconds
Started May 12 03:48:30 PM PDT 24
Finished May 12 03:48:32 PM PDT 24
Peak memory 209788 kb
Host smart-49881ed1-6e38-4942-a4b2-a807d0d7bd18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887324250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.2887324250
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.994748995
Short name T605
Test name
Test status
Simulation time 13029087 ps
CPU time 0.77 seconds
Started May 12 03:48:35 PM PDT 24
Finished May 12 03:48:37 PM PDT 24
Peak memory 205908 kb
Host smart-eb489747-2ded-434e-bfad-3519745cea6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994748995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.994748995
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.489447251
Short name T793
Test name
Test status
Simulation time 66030705 ps
CPU time 2.97 seconds
Started May 12 03:48:35 PM PDT 24
Finished May 12 03:48:39 PM PDT 24
Peak memory 209184 kb
Host smart-39a8b8e3-310b-45f3-9a34-4533a7028964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489447251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.489447251
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.459309238
Short name T518
Test name
Test status
Simulation time 672027791 ps
CPU time 10.01 seconds
Started May 12 03:48:31 PM PDT 24
Finished May 12 03:48:41 PM PDT 24
Peak memory 218336 kb
Host smart-89850783-649e-4748-9723-fd35a62d4735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459309238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.459309238
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.3868613400
Short name T349
Test name
Test status
Simulation time 53204786 ps
CPU time 3.56 seconds
Started May 12 03:48:30 PM PDT 24
Finished May 12 03:48:34 PM PDT 24
Peak memory 214256 kb
Host smart-c6da9bd7-4b11-43da-8cc6-abe3bc33ad07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868613400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.3868613400
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.321526671
Short name T243
Test name
Test status
Simulation time 323047057 ps
CPU time 4.45 seconds
Started May 12 03:48:32 PM PDT 24
Finished May 12 03:48:37 PM PDT 24
Peak memory 209272 kb
Host smart-d37eb839-120b-40a3-af6f-24e5e5de4eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321526671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.321526671
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.1449957319
Short name T587
Test name
Test status
Simulation time 981002095 ps
CPU time 29.29 seconds
Started May 12 03:48:32 PM PDT 24
Finished May 12 03:49:02 PM PDT 24
Peak memory 208704 kb
Host smart-0493c767-b09a-49de-be6f-672ba54ee6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449957319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.1449957319
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.4228269411
Short name T571
Test name
Test status
Simulation time 55908173 ps
CPU time 2.76 seconds
Started May 12 03:48:31 PM PDT 24
Finished May 12 03:48:35 PM PDT 24
Peak memory 206820 kb
Host smart-9873b85d-1c89-45c2-ada7-1371ebc27a83
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228269411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.4228269411
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.1685826454
Short name T512
Test name
Test status
Simulation time 787705932 ps
CPU time 6.81 seconds
Started May 12 03:48:33 PM PDT 24
Finished May 12 03:48:40 PM PDT 24
Peak memory 208636 kb
Host smart-fa7dcf1c-4364-4005-b5a7-419d3831dfb4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685826454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.1685826454
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.433353547
Short name T685
Test name
Test status
Simulation time 431908684 ps
CPU time 2.05 seconds
Started May 12 03:48:32 PM PDT 24
Finished May 12 03:48:34 PM PDT 24
Peak memory 207572 kb
Host smart-ae3cc70b-8724-45ff-a451-59a5b99eb259
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433353547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.433353547
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.4077207216
Short name T878
Test name
Test status
Simulation time 67931641 ps
CPU time 2.98 seconds
Started May 12 03:48:36 PM PDT 24
Finished May 12 03:48:39 PM PDT 24
Peak memory 208656 kb
Host smart-51b944f3-5e72-459c-819e-0255e145b5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077207216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.4077207216
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.2821839705
Short name T384
Test name
Test status
Simulation time 208711800 ps
CPU time 5.55 seconds
Started May 12 03:48:28 PM PDT 24
Finished May 12 03:48:34 PM PDT 24
Peak memory 207824 kb
Host smart-eeec3079-5dc3-4671-b570-a635606d025a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821839705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.2821839705
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.3244248533
Short name T217
Test name
Test status
Simulation time 273575140 ps
CPU time 3.3 seconds
Started May 12 03:48:49 PM PDT 24
Finished May 12 03:48:54 PM PDT 24
Peak memory 210300 kb
Host smart-20936ff3-bcd7-4990-9156-77dea9d8b326
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244248533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.3244248533
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.3723916564
Short name T70
Test name
Test status
Simulation time 1465734192 ps
CPU time 21.6 seconds
Started May 12 03:48:48 PM PDT 24
Finished May 12 03:49:10 PM PDT 24
Peak memory 222604 kb
Host smart-2217abc6-f21b-4870-8d0b-51eddb8c1c73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723916564 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.3723916564
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.1662142631
Short name T578
Test name
Test status
Simulation time 7614862517 ps
CPU time 40.53 seconds
Started May 12 03:48:33 PM PDT 24
Finished May 12 03:49:14 PM PDT 24
Peak memory 218420 kb
Host smart-cc2fd16f-03f5-490f-8438-f9a5a871661a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662142631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.1662142631
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.472591038
Short name T151
Test name
Test status
Simulation time 73495395 ps
CPU time 2.02 seconds
Started May 12 03:48:36 PM PDT 24
Finished May 12 03:48:38 PM PDT 24
Peak memory 209928 kb
Host smart-6af1da4b-b457-487a-8135-ca411dc3a886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472591038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.472591038
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.4276295012
Short name T588
Test name
Test status
Simulation time 9946069 ps
CPU time 0.92 seconds
Started May 12 03:48:40 PM PDT 24
Finished May 12 03:48:42 PM PDT 24
Peak memory 205908 kb
Host smart-22231fc9-3056-47d5-850f-c6f04fc9f935
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276295012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.4276295012
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.3934833022
Short name T474
Test name
Test status
Simulation time 1832887934 ps
CPU time 15.07 seconds
Started May 12 03:48:40 PM PDT 24
Finished May 12 03:48:55 PM PDT 24
Peak memory 209368 kb
Host smart-839c6674-0098-42a6-9f74-8fca23f58277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934833022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.3934833022
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.1467181106
Short name T325
Test name
Test status
Simulation time 413949176 ps
CPU time 3.36 seconds
Started May 12 03:48:38 PM PDT 24
Finished May 12 03:48:41 PM PDT 24
Peak memory 206112 kb
Host smart-2f023f46-73b1-43c0-ab1d-fa4e36e3a3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467181106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.1467181106
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.2503731638
Short name T360
Test name
Test status
Simulation time 83112251 ps
CPU time 2.1 seconds
Started May 12 03:48:39 PM PDT 24
Finished May 12 03:48:41 PM PDT 24
Peak memory 214248 kb
Host smart-140b0033-2bc8-4f1e-89f3-65925ade1770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503731638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.2503731638
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.618114013
Short name T525
Test name
Test status
Simulation time 85088707 ps
CPU time 4.52 seconds
Started May 12 03:48:39 PM PDT 24
Finished May 12 03:48:44 PM PDT 24
Peak memory 222400 kb
Host smart-07e17a62-cccd-41ec-b93d-18d960a9808c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618114013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.618114013
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.1919738094
Short name T447
Test name
Test status
Simulation time 243741199 ps
CPU time 5.81 seconds
Started May 12 03:48:38 PM PDT 24
Finished May 12 03:48:44 PM PDT 24
Peak memory 207024 kb
Host smart-69cc2793-26c5-4327-b1be-f68de31f2540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919738094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.1919738094
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.1287147493
Short name T462
Test name
Test status
Simulation time 513372000 ps
CPU time 4.14 seconds
Started May 12 03:49:01 PM PDT 24
Finished May 12 03:49:05 PM PDT 24
Peak memory 208380 kb
Host smart-87efd39d-534b-4f9e-9d95-a4310332a44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287147493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.1287147493
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.2695364452
Short name T727
Test name
Test status
Simulation time 1047917964 ps
CPU time 7.88 seconds
Started May 12 03:48:36 PM PDT 24
Finished May 12 03:48:45 PM PDT 24
Peak memory 208672 kb
Host smart-5d309181-d0f1-47a1-926a-ee871418149e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695364452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.2695364452
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.2584174299
Short name T285
Test name
Test status
Simulation time 401191700 ps
CPU time 6.19 seconds
Started May 12 03:48:38 PM PDT 24
Finished May 12 03:48:45 PM PDT 24
Peak memory 208684 kb
Host smart-7474a88d-b326-406d-9785-202bad54a8a9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584174299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.2584174299
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.4240537957
Short name T173
Test name
Test status
Simulation time 68340427 ps
CPU time 3.32 seconds
Started May 12 03:48:37 PM PDT 24
Finished May 12 03:48:41 PM PDT 24
Peak memory 208616 kb
Host smart-cb06994a-1367-49c7-811e-9f52d4501986
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240537957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.4240537957
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.3757893145
Short name T547
Test name
Test status
Simulation time 81994457 ps
CPU time 2.05 seconds
Started May 12 03:48:39 PM PDT 24
Finished May 12 03:48:42 PM PDT 24
Peak memory 214316 kb
Host smart-fa21b3de-04bd-4268-815a-568fcc2af822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757893145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.3757893145
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.2987873165
Short name T414
Test name
Test status
Simulation time 96725300 ps
CPU time 2.45 seconds
Started May 12 03:48:38 PM PDT 24
Finished May 12 03:48:41 PM PDT 24
Peak memory 208768 kb
Host smart-9f8bd263-a562-4049-a54e-04d3b7874368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987873165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.2987873165
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.1664596690
Short name T814
Test name
Test status
Simulation time 764868844 ps
CPU time 20.55 seconds
Started May 12 03:48:43 PM PDT 24
Finished May 12 03:49:04 PM PDT 24
Peak memory 222440 kb
Host smart-481f3235-5247-4d63-abef-70e7d47fd0c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664596690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.1664596690
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.3739025642
Short name T794
Test name
Test status
Simulation time 38914498 ps
CPU time 3.23 seconds
Started May 12 03:48:42 PM PDT 24
Finished May 12 03:48:45 PM PDT 24
Peak memory 214332 kb
Host smart-6ebf017a-f2bb-40b1-8bfc-89dcde0d415a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739025642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.3739025642
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.2405519939
Short name T543
Test name
Test status
Simulation time 46668465 ps
CPU time 2.55 seconds
Started May 12 03:48:41 PM PDT 24
Finished May 12 03:48:44 PM PDT 24
Peak memory 210120 kb
Host smart-ed332eeb-8a9f-475b-a771-f603bf5c69b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405519939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.2405519939
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.1965042664
Short name T867
Test name
Test status
Simulation time 163905225 ps
CPU time 0.87 seconds
Started May 12 03:48:51 PM PDT 24
Finished May 12 03:48:52 PM PDT 24
Peak memory 205912 kb
Host smart-ce0b9d17-624d-408a-b0cb-3ee5f5b6d572
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965042664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.1965042664
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.2498143668
Short name T393
Test name
Test status
Simulation time 4648891427 ps
CPU time 62.89 seconds
Started May 12 03:48:44 PM PDT 24
Finished May 12 03:49:47 PM PDT 24
Peak memory 214852 kb
Host smart-088e5860-fa05-4d7b-8c55-cb253c5208e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2498143668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.2498143668
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.2769125906
Short name T779
Test name
Test status
Simulation time 290850334 ps
CPU time 1.49 seconds
Started May 12 03:48:44 PM PDT 24
Finished May 12 03:48:46 PM PDT 24
Peak memory 214228 kb
Host smart-10bd6673-0825-4ea0-b0c4-836986e0c971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769125906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.2769125906
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.2009770524
Short name T552
Test name
Test status
Simulation time 185483338 ps
CPU time 3.36 seconds
Started May 12 03:48:45 PM PDT 24
Finished May 12 03:48:49 PM PDT 24
Peak memory 214288 kb
Host smart-cabd2148-ebf6-40bf-bca5-72f054676724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009770524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.2009770524
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.2852123855
Short name T358
Test name
Test status
Simulation time 353249968 ps
CPU time 12.93 seconds
Started May 12 03:48:47 PM PDT 24
Finished May 12 03:49:01 PM PDT 24
Peak memory 214256 kb
Host smart-ce5af8dc-21f4-4463-b96d-b347a8be0477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852123855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.2852123855
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.2633063660
Short name T887
Test name
Test status
Simulation time 127674782 ps
CPU time 5.36 seconds
Started May 12 03:48:44 PM PDT 24
Finished May 12 03:48:50 PM PDT 24
Peak memory 214224 kb
Host smart-5492a427-1ccf-43e6-834e-5174e06112af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633063660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.2633063660
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.2019423115
Short name T464
Test name
Test status
Simulation time 64750470 ps
CPU time 3.62 seconds
Started May 12 03:48:43 PM PDT 24
Finished May 12 03:48:47 PM PDT 24
Peak memory 220168 kb
Host smart-00b206dc-626b-4d2b-a2b2-db5293fe2eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019423115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.2019423115
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.803960810
Short name T549
Test name
Test status
Simulation time 223222488 ps
CPU time 5.58 seconds
Started May 12 03:48:44 PM PDT 24
Finished May 12 03:48:50 PM PDT 24
Peak memory 209408 kb
Host smart-86608074-4724-4ab8-9ff9-a8ea55a98c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803960810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.803960810
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.477620539
Short name T224
Test name
Test status
Simulation time 220102785 ps
CPU time 3.3 seconds
Started May 12 03:48:43 PM PDT 24
Finished May 12 03:48:46 PM PDT 24
Peak memory 206784 kb
Host smart-7386daf3-3faa-4d2c-88fa-bdd1bf9f1516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477620539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.477620539
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.4032614647
Short name T249
Test name
Test status
Simulation time 125040352 ps
CPU time 5.86 seconds
Started May 12 03:48:47 PM PDT 24
Finished May 12 03:48:53 PM PDT 24
Peak memory 206920 kb
Host smart-40c6a7ee-4c79-4661-81ca-332c6736317e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032614647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.4032614647
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.3453634471
Short name T318
Test name
Test status
Simulation time 45962049 ps
CPU time 2.08 seconds
Started May 12 03:48:42 PM PDT 24
Finished May 12 03:48:44 PM PDT 24
Peak memory 206892 kb
Host smart-25e43792-6cb4-40ca-8451-3b620f43231e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453634471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.3453634471
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.905778970
Short name T490
Test name
Test status
Simulation time 333694565 ps
CPU time 3.09 seconds
Started May 12 03:48:45 PM PDT 24
Finished May 12 03:48:49 PM PDT 24
Peak memory 207016 kb
Host smart-f53a70e1-a0cb-475b-8eae-c65e22a76229
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905778970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.905778970
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.784670605
Short name T647
Test name
Test status
Simulation time 449274732 ps
CPU time 3.69 seconds
Started May 12 03:48:45 PM PDT 24
Finished May 12 03:48:49 PM PDT 24
Peak memory 218132 kb
Host smart-46e31693-326d-43ae-97cb-9dd871a1847e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784670605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.784670605
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.3894452192
Short name T662
Test name
Test status
Simulation time 1298781759 ps
CPU time 11.78 seconds
Started May 12 03:48:42 PM PDT 24
Finished May 12 03:48:54 PM PDT 24
Peak memory 207856 kb
Host smart-422d5622-a42c-4358-a6b6-3e0e26b6f994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894452192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.3894452192
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.3698261773
Short name T722
Test name
Test status
Simulation time 120689647 ps
CPU time 8.63 seconds
Started May 12 03:48:47 PM PDT 24
Finished May 12 03:48:56 PM PDT 24
Peak memory 219796 kb
Host smart-f40b3156-4d49-4077-b4cc-220c1f3983f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698261773 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.3698261773
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.1301835135
Short name T859
Test name
Test status
Simulation time 51433273 ps
CPU time 3.67 seconds
Started May 12 03:48:43 PM PDT 24
Finished May 12 03:48:47 PM PDT 24
Peak memory 208996 kb
Host smart-0583db88-e618-4d36-b13e-5f2379caaa6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301835135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.1301835135
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.1032918091
Short name T890
Test name
Test status
Simulation time 183717762 ps
CPU time 5.81 seconds
Started May 12 03:48:59 PM PDT 24
Finished May 12 03:49:06 PM PDT 24
Peak memory 210372 kb
Host smart-31ecce2a-d8a4-4e1a-a19c-9f4723cef511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032918091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.1032918091
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.3564826718
Short name T733
Test name
Test status
Simulation time 8510662 ps
CPU time 0.82 seconds
Started May 12 03:48:55 PM PDT 24
Finished May 12 03:48:57 PM PDT 24
Peak memory 205900 kb
Host smart-b6e37f1e-3625-4017-9170-da8965982a04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564826718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.3564826718
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.3457834589
Short name T327
Test name
Test status
Simulation time 781414311 ps
CPU time 10.5 seconds
Started May 12 03:48:48 PM PDT 24
Finished May 12 03:48:59 PM PDT 24
Peak memory 214784 kb
Host smart-9da8993d-04de-4f90-bc3b-638b189e8f26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3457834589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.3457834589
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.3366045765
Short name T40
Test name
Test status
Simulation time 76068377 ps
CPU time 3.3 seconds
Started May 12 03:48:55 PM PDT 24
Finished May 12 03:48:59 PM PDT 24
Peak memory 208824 kb
Host smart-ff3d64f0-52a7-47b3-b4b4-40887fb99038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366045765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.3366045765
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.992924614
Short name T338
Test name
Test status
Simulation time 46224329 ps
CPU time 2.45 seconds
Started May 12 03:49:01 PM PDT 24
Finished May 12 03:49:04 PM PDT 24
Peak memory 207668 kb
Host smart-cbf96aac-0fa8-4fb3-9383-c485795f2b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992924614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.992924614
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.2965110933
Short name T694
Test name
Test status
Simulation time 216633006 ps
CPU time 5.52 seconds
Started May 12 03:48:51 PM PDT 24
Finished May 12 03:48:57 PM PDT 24
Peak memory 222356 kb
Host smart-eaba8441-bb0a-4d23-a5e8-5a2938695a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965110933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.2965110933
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.2334929697
Short name T625
Test name
Test status
Simulation time 86246627 ps
CPU time 2.13 seconds
Started May 12 03:48:53 PM PDT 24
Finished May 12 03:48:55 PM PDT 24
Peak memory 214588 kb
Host smart-4dce68a5-9758-435e-82a6-0b60158aa6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334929697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.2334929697
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.1424207740
Short name T200
Test name
Test status
Simulation time 253928203 ps
CPU time 4.28 seconds
Started May 12 03:48:52 PM PDT 24
Finished May 12 03:48:57 PM PDT 24
Peak memory 220144 kb
Host smart-da7572a9-000b-47e8-8345-42677bcfebc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424207740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.1424207740
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.4206628838
Short name T553
Test name
Test status
Simulation time 1010488243 ps
CPU time 11.71 seconds
Started May 12 03:48:51 PM PDT 24
Finished May 12 03:49:03 PM PDT 24
Peak memory 214360 kb
Host smart-d797a6fd-9af1-4015-9c8c-0a9b1f7aa50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206628838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.4206628838
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.3132234851
Short name T83
Test name
Test status
Simulation time 145352266 ps
CPU time 3.97 seconds
Started May 12 03:48:47 PM PDT 24
Finished May 12 03:48:52 PM PDT 24
Peak memory 208680 kb
Host smart-e3cdab7a-0484-4cb3-a9fc-1f2ae143274e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132234851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.3132234851
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.1267339770
Short name T615
Test name
Test status
Simulation time 207299432 ps
CPU time 3.34 seconds
Started May 12 03:48:53 PM PDT 24
Finished May 12 03:48:57 PM PDT 24
Peak memory 207320 kb
Host smart-4e78d545-58ac-47e4-91bd-38c8c3e0f867
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267339770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.1267339770
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.3476350879
Short name T170
Test name
Test status
Simulation time 126806181 ps
CPU time 4.06 seconds
Started May 12 03:48:46 PM PDT 24
Finished May 12 03:48:51 PM PDT 24
Peak memory 206732 kb
Host smart-3dd20c08-d4fc-4bd6-9449-5babdfa20fe5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476350879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.3476350879
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.2750824885
Short name T721
Test name
Test status
Simulation time 127532837 ps
CPU time 4.05 seconds
Started May 12 03:48:51 PM PDT 24
Finished May 12 03:48:56 PM PDT 24
Peak memory 208616 kb
Host smart-c9df4bb7-ac33-4b61-b9b4-2f0c326388cc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750824885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.2750824885
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.1274179187
Short name T799
Test name
Test status
Simulation time 1106906320 ps
CPU time 20.79 seconds
Started May 12 03:48:56 PM PDT 24
Finished May 12 03:49:18 PM PDT 24
Peak memory 209208 kb
Host smart-1d24f96a-b9a8-4872-89b0-7ab83da895f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274179187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.1274179187
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.886606146
Short name T496
Test name
Test status
Simulation time 143215472 ps
CPU time 2.69 seconds
Started May 12 03:48:48 PM PDT 24
Finished May 12 03:48:51 PM PDT 24
Peak memory 208516 kb
Host smart-a132840e-8fb1-4db7-9735-288b4bed9b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886606146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.886606146
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.1331880011
Short name T347
Test name
Test status
Simulation time 17394159819 ps
CPU time 50.24 seconds
Started May 12 03:48:54 PM PDT 24
Finished May 12 03:49:44 PM PDT 24
Peak memory 216100 kb
Host smart-c1914772-a826-4134-be03-7ecfe7983b80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331880011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.1331880011
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.4183113229
Short name T709
Test name
Test status
Simulation time 255977449 ps
CPU time 6.67 seconds
Started May 12 03:48:51 PM PDT 24
Finished May 12 03:48:59 PM PDT 24
Peak memory 218184 kb
Host smart-943f98ec-d502-4799-ac54-d757d49a07da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183113229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.4183113229
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.1770137845
Short name T370
Test name
Test status
Simulation time 4625795067 ps
CPU time 7.82 seconds
Started May 12 03:48:55 PM PDT 24
Finished May 12 03:49:03 PM PDT 24
Peak memory 211968 kb
Host smart-15072db1-f035-49af-b211-6ae719e232a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770137845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.1770137845
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.1031619079
Short name T454
Test name
Test status
Simulation time 419596310 ps
CPU time 1.22 seconds
Started May 12 03:49:00 PM PDT 24
Finished May 12 03:49:02 PM PDT 24
Peak memory 206076 kb
Host smart-5bca58ed-a636-4380-9cb9-49021eb71acb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031619079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.1031619079
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.2925697830
Short name T407
Test name
Test status
Simulation time 90581149 ps
CPU time 3.52 seconds
Started May 12 03:48:57 PM PDT 24
Finished May 12 03:49:01 PM PDT 24
Peak memory 214736 kb
Host smart-f11adfd6-ef68-40ad-8613-464261e601e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2925697830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.2925697830
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.2620090418
Short name T27
Test name
Test status
Simulation time 72474050 ps
CPU time 2.86 seconds
Started May 12 03:48:55 PM PDT 24
Finished May 12 03:48:59 PM PDT 24
Peak memory 209988 kb
Host smart-ec896625-c3de-4e31-b38d-a979efebeefd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620090418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.2620090418
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.25570634
Short name T73
Test name
Test status
Simulation time 4715369346 ps
CPU time 35.14 seconds
Started May 12 03:48:55 PM PDT 24
Finished May 12 03:49:31 PM PDT 24
Peak memory 218916 kb
Host smart-61eda5cc-919f-4d86-bddc-e31383dfe28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25570634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.25570634
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.695595268
Short name T94
Test name
Test status
Simulation time 1000086557 ps
CPU time 31.14 seconds
Started May 12 03:48:58 PM PDT 24
Finished May 12 03:49:30 PM PDT 24
Peak memory 214296 kb
Host smart-4d458be2-a3c8-42af-a119-d11c19db83c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695595268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.695595268
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.3794466593
Short name T817
Test name
Test status
Simulation time 66616663 ps
CPU time 3.8 seconds
Started May 12 03:49:00 PM PDT 24
Finished May 12 03:49:05 PM PDT 24
Peak memory 214304 kb
Host smart-913a794d-9954-498e-b0e0-923a25f2ea3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794466593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.3794466593
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.3514254411
Short name T197
Test name
Test status
Simulation time 81098659 ps
CPU time 4.14 seconds
Started May 12 03:48:57 PM PDT 24
Finished May 12 03:49:02 PM PDT 24
Peak memory 214248 kb
Host smart-a274e54d-15e5-42e3-b898-57ae71145c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514254411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.3514254411
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.1012924357
Short name T823
Test name
Test status
Simulation time 1868862339 ps
CPU time 14.12 seconds
Started May 12 03:48:58 PM PDT 24
Finished May 12 03:49:13 PM PDT 24
Peak memory 214308 kb
Host smart-6b773079-6d64-4d7b-bb5c-17246081d100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012924357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.1012924357
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.1216206947
Short name T312
Test name
Test status
Simulation time 493859119 ps
CPU time 7.6 seconds
Started May 12 03:48:56 PM PDT 24
Finished May 12 03:49:05 PM PDT 24
Peak memory 208484 kb
Host smart-a12bb94d-5af6-44a3-864b-362f502d6503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216206947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.1216206947
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.441807124
Short name T711
Test name
Test status
Simulation time 244536292 ps
CPU time 4.86 seconds
Started May 12 03:48:58 PM PDT 24
Finished May 12 03:49:04 PM PDT 24
Peak memory 208552 kb
Host smart-6b29db8d-4805-4600-b2d2-16ae4473df44
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441807124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.441807124
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.1622536027
Short name T86
Test name
Test status
Simulation time 173857559 ps
CPU time 5.55 seconds
Started May 12 03:48:55 PM PDT 24
Finished May 12 03:49:01 PM PDT 24
Peak memory 207924 kb
Host smart-815d5ed8-e0e0-40e7-bc2f-97c020fa56ed
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622536027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.1622536027
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.2880035408
Short name T656
Test name
Test status
Simulation time 197272854 ps
CPU time 7.54 seconds
Started May 12 03:48:57 PM PDT 24
Finished May 12 03:49:05 PM PDT 24
Peak memory 207964 kb
Host smart-35037bb3-6e33-468e-8378-2b27b85fa048
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880035408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.2880035408
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.132945219
Short name T467
Test name
Test status
Simulation time 539845202 ps
CPU time 3.64 seconds
Started May 12 03:49:01 PM PDT 24
Finished May 12 03:49:05 PM PDT 24
Peak memory 209312 kb
Host smart-3e7bfd0a-8279-46d3-a1c9-a4de51a01b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132945219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.132945219
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.1899209957
Short name T622
Test name
Test status
Simulation time 582481258 ps
CPU time 2.65 seconds
Started May 12 03:48:58 PM PDT 24
Finished May 12 03:49:01 PM PDT 24
Peak memory 206612 kb
Host smart-949374f9-68ea-434f-80ed-ae4efc68f92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899209957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.1899209957
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.3967150077
Short name T154
Test name
Test status
Simulation time 769461963 ps
CPU time 16.79 seconds
Started May 12 03:49:02 PM PDT 24
Finished May 12 03:49:20 PM PDT 24
Peak memory 214940 kb
Host smart-71e93516-99bc-43d2-afb4-694c298bc865
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967150077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.3967150077
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.998948137
Short name T654
Test name
Test status
Simulation time 368876844 ps
CPU time 6.22 seconds
Started May 12 03:48:58 PM PDT 24
Finished May 12 03:49:05 PM PDT 24
Peak memory 209368 kb
Host smart-674b242b-ad82-42cd-a311-7f98ea30a01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998948137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.998948137
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.1593358192
Short name T372
Test name
Test status
Simulation time 98218980 ps
CPU time 2.39 seconds
Started May 12 03:48:59 PM PDT 24
Finished May 12 03:49:02 PM PDT 24
Peak memory 209852 kb
Host smart-de8e9f84-f5cf-409c-be24-845d82d63484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593358192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.1593358192
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.3602988591
Short name T412
Test name
Test status
Simulation time 19959717 ps
CPU time 0.75 seconds
Started May 12 03:49:02 PM PDT 24
Finished May 12 03:49:04 PM PDT 24
Peak memory 205876 kb
Host smart-8a40adf8-7b47-407d-8cfe-b1cda2ef0c5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602988591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.3602988591
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.2114600204
Short name T41
Test name
Test status
Simulation time 390889257 ps
CPU time 10.97 seconds
Started May 12 03:49:11 PM PDT 24
Finished May 12 03:49:22 PM PDT 24
Peak memory 218240 kb
Host smart-9a5198f0-0772-4236-9f0b-9a0a45ec55e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114600204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.2114600204
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.549424962
Short name T760
Test name
Test status
Simulation time 53267074 ps
CPU time 3.08 seconds
Started May 12 03:48:59 PM PDT 24
Finished May 12 03:49:03 PM PDT 24
Peak memory 214312 kb
Host smart-f91a743d-37fe-447c-ab73-058ef35cdbdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549424962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.549424962
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.514457204
Short name T272
Test name
Test status
Simulation time 1026780622 ps
CPU time 2.87 seconds
Started May 12 03:49:10 PM PDT 24
Finished May 12 03:49:14 PM PDT 24
Peak memory 215716 kb
Host smart-5ae92e88-87cd-4777-85bf-a2c4b1ddd364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514457204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.514457204
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.1495534875
Short name T250
Test name
Test status
Simulation time 70641036 ps
CPU time 3 seconds
Started May 12 03:49:01 PM PDT 24
Finished May 12 03:49:05 PM PDT 24
Peak memory 220976 kb
Host smart-8ba8a12f-b127-4ff9-874c-a1c49ea4d59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495534875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.1495534875
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.3112776953
Short name T892
Test name
Test status
Simulation time 200158008 ps
CPU time 4.19 seconds
Started May 12 03:48:59 PM PDT 24
Finished May 12 03:49:04 PM PDT 24
Peak memory 217900 kb
Host smart-1b16f692-f08f-4907-819b-15f67e1b4bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112776953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.3112776953
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.379427994
Short name T255
Test name
Test status
Simulation time 58369339 ps
CPU time 3.66 seconds
Started May 12 03:49:01 PM PDT 24
Finished May 12 03:49:06 PM PDT 24
Peak memory 214380 kb
Host smart-db6840a3-fd8b-458f-8bef-3722ba4aa5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379427994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.379427994
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.606622021
Short name T221
Test name
Test status
Simulation time 70177726 ps
CPU time 2.55 seconds
Started May 12 03:49:11 PM PDT 24
Finished May 12 03:49:14 PM PDT 24
Peak memory 207288 kb
Host smart-70447df3-2d72-426e-915e-eadb74180943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606622021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.606622021
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.3975219130
Short name T470
Test name
Test status
Simulation time 320558713 ps
CPU time 4.72 seconds
Started May 12 03:49:01 PM PDT 24
Finished May 12 03:49:06 PM PDT 24
Peak memory 208884 kb
Host smart-6f640fea-1f08-4733-aab6-010021a1b223
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975219130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.3975219130
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.3168616271
Short name T545
Test name
Test status
Simulation time 72186966 ps
CPU time 3.7 seconds
Started May 12 03:49:01 PM PDT 24
Finished May 12 03:49:05 PM PDT 24
Peak memory 208440 kb
Host smart-f334ac05-690f-4627-8521-29b9c315b5b9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168616271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.3168616271
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.3261966811
Short name T896
Test name
Test status
Simulation time 22766487 ps
CPU time 2.01 seconds
Started May 12 03:49:00 PM PDT 24
Finished May 12 03:49:03 PM PDT 24
Peak memory 206760 kb
Host smart-d31f3f94-ac73-4ae9-b84a-9578f6f45be3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261966811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.3261966811
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.1015381121
Short name T740
Test name
Test status
Simulation time 67780946 ps
CPU time 2.54 seconds
Started May 12 03:49:05 PM PDT 24
Finished May 12 03:49:08 PM PDT 24
Peak memory 208532 kb
Host smart-28468ae8-4063-463a-924e-54abcd72c324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015381121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.1015381121
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.279370877
Short name T835
Test name
Test status
Simulation time 456810716 ps
CPU time 6.63 seconds
Started May 12 03:49:05 PM PDT 24
Finished May 12 03:49:12 PM PDT 24
Peak memory 208288 kb
Host smart-77e58d8b-a95e-42c5-9f4d-9a5f194ce460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279370877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.279370877
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.18804398
Short name T563
Test name
Test status
Simulation time 1001480691 ps
CPU time 12.01 seconds
Started May 12 03:49:02 PM PDT 24
Finished May 12 03:49:14 PM PDT 24
Peak memory 209292 kb
Host smart-1e66f54b-4299-4e87-923d-c744a0e8c43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18804398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.18804398
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.1406053580
Short name T595
Test name
Test status
Simulation time 1446151833 ps
CPU time 6.24 seconds
Started May 12 03:49:02 PM PDT 24
Finished May 12 03:49:09 PM PDT 24
Peak memory 210680 kb
Host smart-d90743e9-b96f-49ce-94e7-59dbf57b5866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406053580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.1406053580
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.2525179604
Short name T174
Test name
Test status
Simulation time 38297137 ps
CPU time 0.85 seconds
Started May 12 03:49:09 PM PDT 24
Finished May 12 03:49:11 PM PDT 24
Peak memory 205940 kb
Host smart-10ed2723-7cd7-4464-8d9a-8554c273bd42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525179604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.2525179604
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.1694085014
Short name T342
Test name
Test status
Simulation time 571762983 ps
CPU time 8.82 seconds
Started May 12 03:49:05 PM PDT 24
Finished May 12 03:49:15 PM PDT 24
Peak memory 215876 kb
Host smart-04055da6-0b7b-4980-b7db-00efd7dd939b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1694085014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.1694085014
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.4033027380
Short name T33
Test name
Test status
Simulation time 281984470 ps
CPU time 3.5 seconds
Started May 12 03:49:07 PM PDT 24
Finished May 12 03:49:11 PM PDT 24
Peak memory 214196 kb
Host smart-41af4083-2895-47b9-9911-1ab3d60d5d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033027380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.4033027380
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.1017555028
Short name T77
Test name
Test status
Simulation time 724274822 ps
CPU time 3.17 seconds
Started May 12 03:49:07 PM PDT 24
Finished May 12 03:49:11 PM PDT 24
Peak memory 209796 kb
Host smart-dbbc897d-7903-45b5-b88f-c31f22767c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017555028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.1017555028
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.3233608241
Short name T95
Test name
Test status
Simulation time 197456126 ps
CPU time 7.4 seconds
Started May 12 03:49:11 PM PDT 24
Finished May 12 03:49:19 PM PDT 24
Peak memory 209112 kb
Host smart-62eff43a-ef19-4836-8dcc-896927915889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233608241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.3233608241
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.2869229077
Short name T361
Test name
Test status
Simulation time 390486083 ps
CPU time 3.91 seconds
Started May 12 03:49:08 PM PDT 24
Finished May 12 03:49:13 PM PDT 24
Peak memory 214200 kb
Host smart-aa98edd2-c559-4d36-8554-0fda8c5aca96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869229077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.2869229077
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.3598162786
Short name T385
Test name
Test status
Simulation time 348814344 ps
CPU time 4.26 seconds
Started May 12 03:49:07 PM PDT 24
Finished May 12 03:49:12 PM PDT 24
Peak memory 208380 kb
Host smart-246f2abd-f278-4b5a-9626-a21dd0697a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598162786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.3598162786
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.1373904148
Short name T186
Test name
Test status
Simulation time 822376398 ps
CPU time 12.21 seconds
Started May 12 03:49:08 PM PDT 24
Finished May 12 03:49:21 PM PDT 24
Peak memory 214268 kb
Host smart-d24daf96-3999-4273-a44c-431622f8624d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373904148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.1373904148
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.1960814408
Short name T702
Test name
Test status
Simulation time 1366465175 ps
CPU time 6.88 seconds
Started May 12 03:49:10 PM PDT 24
Finished May 12 03:49:18 PM PDT 24
Peak memory 208412 kb
Host smart-cf13985c-073f-4781-8c34-138504777feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960814408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.1960814408
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.3299622478
Short name T302
Test name
Test status
Simulation time 38458165 ps
CPU time 2.67 seconds
Started May 12 03:49:02 PM PDT 24
Finished May 12 03:49:05 PM PDT 24
Peak memory 208608 kb
Host smart-58334be4-b97e-4300-b4c6-f22fceaa1623
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299622478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.3299622478
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.3143116573
Short name T705
Test name
Test status
Simulation time 165973289 ps
CPU time 3.12 seconds
Started May 12 03:49:11 PM PDT 24
Finished May 12 03:49:14 PM PDT 24
Peak memory 206960 kb
Host smart-7d353c3b-49b2-46e3-88c7-b473f78a0f3a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143116573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.3143116573
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.3887043483
Short name T557
Test name
Test status
Simulation time 77050480 ps
CPU time 2.52 seconds
Started May 12 03:49:10 PM PDT 24
Finished May 12 03:49:13 PM PDT 24
Peak memory 206676 kb
Host smart-a4d5117b-20c0-4704-8fb4-54ac787e4087
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887043483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.3887043483
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.580381463
Short name T886
Test name
Test status
Simulation time 409851119 ps
CPU time 4.68 seconds
Started May 12 03:49:08 PM PDT 24
Finished May 12 03:49:13 PM PDT 24
Peak memory 215736 kb
Host smart-b667843f-6f8e-4172-bcd8-9c76a9c6f720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580381463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.580381463
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.3911671362
Short name T834
Test name
Test status
Simulation time 193494430 ps
CPU time 2.68 seconds
Started May 12 03:49:03 PM PDT 24
Finished May 12 03:49:06 PM PDT 24
Peak memory 208192 kb
Host smart-ac49f357-afbb-4993-931e-3e5dfee968d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911671362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.3911671362
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.944018546
Short name T776
Test name
Test status
Simulation time 464591955 ps
CPU time 13.1 seconds
Started May 12 03:49:10 PM PDT 24
Finished May 12 03:49:24 PM PDT 24
Peak memory 216148 kb
Host smart-d1cd6d63-5084-441b-b111-04cd024a2a4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944018546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.944018546
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.49386308
Short name T556
Test name
Test status
Simulation time 1731416536 ps
CPU time 46.65 seconds
Started May 12 03:49:07 PM PDT 24
Finished May 12 03:49:53 PM PDT 24
Peak memory 210224 kb
Host smart-aa8546b4-cc74-47fc-a81c-c08cf4a2e37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49386308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.49386308
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.1806584224
Short name T758
Test name
Test status
Simulation time 81625788 ps
CPU time 3.45 seconds
Started May 12 03:49:05 PM PDT 24
Finished May 12 03:49:09 PM PDT 24
Peak memory 210028 kb
Host smart-f7c60166-c8c3-460a-8095-5ee09e4f961b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806584224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.1806584224
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.1451243354
Short name T714
Test name
Test status
Simulation time 62148893 ps
CPU time 1.07 seconds
Started May 12 03:49:13 PM PDT 24
Finished May 12 03:49:14 PM PDT 24
Peak memory 206088 kb
Host smart-2b48734a-910c-46cc-8f5e-942fe40620b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451243354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.1451243354
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.3250419004
Short name T296
Test name
Test status
Simulation time 48348109 ps
CPU time 3.76 seconds
Started May 12 03:49:20 PM PDT 24
Finished May 12 03:49:24 PM PDT 24
Peak memory 214236 kb
Host smart-a24849fb-6103-4026-8042-80a31a889182
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3250419004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.3250419004
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.1021798528
Short name T386
Test name
Test status
Simulation time 428381067 ps
CPU time 4.96 seconds
Started May 12 03:49:17 PM PDT 24
Finished May 12 03:49:23 PM PDT 24
Peak memory 208772 kb
Host smart-38486de2-291a-4c3d-b8f5-dc9209419b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021798528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.1021798528
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.3889913430
Short name T671
Test name
Test status
Simulation time 78211070 ps
CPU time 1.73 seconds
Started May 12 03:49:21 PM PDT 24
Finished May 12 03:49:23 PM PDT 24
Peak memory 214232 kb
Host smart-93916b8d-870b-4747-a2fc-f9dd2a9c75e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889913430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.3889913430
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.2617106459
Short name T189
Test name
Test status
Simulation time 233303099 ps
CPU time 2.67 seconds
Started May 12 03:49:15 PM PDT 24
Finished May 12 03:49:18 PM PDT 24
Peak memory 214648 kb
Host smart-1e59c177-12a2-40e0-91d3-97eaea548155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617106459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.2617106459
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.4097117889
Short name T330
Test name
Test status
Simulation time 651784926 ps
CPU time 10.11 seconds
Started May 12 03:49:11 PM PDT 24
Finished May 12 03:49:22 PM PDT 24
Peak memory 214264 kb
Host smart-103b29fa-0337-48cd-9e8f-5a8130cdcd9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097117889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.4097117889
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.3982073901
Short name T529
Test name
Test status
Simulation time 806955178 ps
CPU time 14.1 seconds
Started May 12 03:49:09 PM PDT 24
Finished May 12 03:49:24 PM PDT 24
Peak memory 208500 kb
Host smart-0eb50c93-7a57-4e7e-a41d-dac1a8b6d795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982073901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.3982073901
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.2441233282
Short name T672
Test name
Test status
Simulation time 249216446 ps
CPU time 2.49 seconds
Started May 12 03:49:10 PM PDT 24
Finished May 12 03:49:13 PM PDT 24
Peak memory 206956 kb
Host smart-76c4f2cd-26d8-4c15-8461-7354d02759b9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441233282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.2441233282
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.3792300611
Short name T351
Test name
Test status
Simulation time 368308269 ps
CPU time 5.08 seconds
Started May 12 03:49:10 PM PDT 24
Finished May 12 03:49:15 PM PDT 24
Peak memory 208528 kb
Host smart-23752d35-7040-4b16-9764-5360c6e96765
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792300611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.3792300611
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.2602655924
Short name T266
Test name
Test status
Simulation time 20105341 ps
CPU time 1.87 seconds
Started May 12 03:49:08 PM PDT 24
Finished May 12 03:49:11 PM PDT 24
Peak memory 206836 kb
Host smart-2a5731c2-51a6-4628-b645-32a93ab63465
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602655924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.2602655924
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.3473374436
Short name T862
Test name
Test status
Simulation time 181064769 ps
CPU time 2.61 seconds
Started May 12 03:49:14 PM PDT 24
Finished May 12 03:49:17 PM PDT 24
Peak memory 214380 kb
Host smart-e6a35c94-e978-480a-8534-f5664e6d7d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473374436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.3473374436
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.1098257215
Short name T582
Test name
Test status
Simulation time 211564526 ps
CPU time 3.29 seconds
Started May 12 03:49:09 PM PDT 24
Finished May 12 03:49:13 PM PDT 24
Peak memory 206672 kb
Host smart-15823372-afb5-4a7e-8d38-af4c10df42fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098257215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.1098257215
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.419481283
Short name T826
Test name
Test status
Simulation time 50961439 ps
CPU time 3.25 seconds
Started May 12 03:49:20 PM PDT 24
Finished May 12 03:49:24 PM PDT 24
Peak memory 209316 kb
Host smart-b65b4b00-69a4-446d-8cd4-0610016a0e54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419481283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.419481283
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.1001709050
Short name T564
Test name
Test status
Simulation time 212433079 ps
CPU time 6.15 seconds
Started May 12 03:49:15 PM PDT 24
Finished May 12 03:49:21 PM PDT 24
Peak memory 218140 kb
Host smart-852f322e-a037-4e9c-8b3f-fb860eb83724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001709050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.1001709050
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.3851003831
Short name T376
Test name
Test status
Simulation time 175824287 ps
CPU time 3.82 seconds
Started May 12 03:49:13 PM PDT 24
Finished May 12 03:49:18 PM PDT 24
Peak memory 210464 kb
Host smart-490853cb-703e-4e59-9c52-d70d28d421f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851003831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.3851003831
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.2682847636
Short name T667
Test name
Test status
Simulation time 15449205 ps
CPU time 0.95 seconds
Started May 12 03:49:18 PM PDT 24
Finished May 12 03:49:19 PM PDT 24
Peak memory 206088 kb
Host smart-f42dddfe-1357-4141-9271-86ea5a4c51d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682847636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.2682847636
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.2079142038
Short name T857
Test name
Test status
Simulation time 7365655107 ps
CPU time 108.32 seconds
Started May 12 03:49:15 PM PDT 24
Finished May 12 03:51:04 PM PDT 24
Peak memory 215908 kb
Host smart-954ba4dc-7d3e-4891-8a3b-2c9457f29ccb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2079142038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.2079142038
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.240341603
Short name T754
Test name
Test status
Simulation time 44508313 ps
CPU time 2.31 seconds
Started May 12 03:49:15 PM PDT 24
Finished May 12 03:49:18 PM PDT 24
Peak memory 214276 kb
Host smart-08d8c5c0-66f1-479d-8a30-76d26a6ab429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240341603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.240341603
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.2962300027
Short name T270
Test name
Test status
Simulation time 1001288573 ps
CPU time 3.7 seconds
Started May 12 03:49:21 PM PDT 24
Finished May 12 03:49:25 PM PDT 24
Peak memory 214192 kb
Host smart-dbbe586c-a9ae-49b1-9863-e04cb332ef4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962300027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.2962300027
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.1943069737
Short name T399
Test name
Test status
Simulation time 240338812 ps
CPU time 2.07 seconds
Started May 12 03:49:19 PM PDT 24
Finished May 12 03:49:21 PM PDT 24
Peak memory 206192 kb
Host smart-9fdd04f7-2fab-47e2-b608-3eabdfa702c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943069737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.1943069737
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.4033956130
Short name T387
Test name
Test status
Simulation time 171699451 ps
CPU time 5.4 seconds
Started May 12 03:49:16 PM PDT 24
Finished May 12 03:49:22 PM PDT 24
Peak memory 209220 kb
Host smart-ca26ca5b-b8b6-46cd-8809-f0e5dd0b4491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033956130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.4033956130
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.986909664
Short name T686
Test name
Test status
Simulation time 757965163 ps
CPU time 6.68 seconds
Started May 12 03:49:14 PM PDT 24
Finished May 12 03:49:22 PM PDT 24
Peak memory 206916 kb
Host smart-bf600535-5006-4b52-a0ac-e9d2ce84f40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986909664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.986909664
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.3182700974
Short name T755
Test name
Test status
Simulation time 316935415 ps
CPU time 2.03 seconds
Started May 12 03:49:14 PM PDT 24
Finished May 12 03:49:16 PM PDT 24
Peak memory 206776 kb
Host smart-bad62a20-6bd6-4640-a060-5fbc8dd09ac6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182700974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.3182700974
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.1505425170
Short name T743
Test name
Test status
Simulation time 253999813 ps
CPU time 7.34 seconds
Started May 12 03:49:15 PM PDT 24
Finished May 12 03:49:23 PM PDT 24
Peak memory 208848 kb
Host smart-64edd0a9-fae4-4f3d-b785-90e2c29bcea0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505425170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.1505425170
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.2432857256
Short name T419
Test name
Test status
Simulation time 1195534586 ps
CPU time 10.38 seconds
Started May 12 03:49:16 PM PDT 24
Finished May 12 03:49:27 PM PDT 24
Peak memory 208128 kb
Host smart-c931f619-44f8-48b5-bafe-66a69305e64a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432857256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.2432857256
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.66272523
Short name T701
Test name
Test status
Simulation time 280970173 ps
CPU time 3.48 seconds
Started May 12 03:49:19 PM PDT 24
Finished May 12 03:49:23 PM PDT 24
Peak memory 209948 kb
Host smart-ffe76da2-4832-4ee4-b56f-d25d356ec216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66272523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.66272523
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.169066419
Short name T716
Test name
Test status
Simulation time 835487609 ps
CPU time 20.76 seconds
Started May 12 03:49:11 PM PDT 24
Finished May 12 03:49:32 PM PDT 24
Peak memory 208612 kb
Host smart-69c33ed7-d266-4cd1-847f-884aaf9d0d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169066419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.169066419
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.4019585682
Short name T247
Test name
Test status
Simulation time 20796845197 ps
CPU time 126.04 seconds
Started May 12 03:49:18 PM PDT 24
Finished May 12 03:51:25 PM PDT 24
Peak memory 216752 kb
Host smart-b533dd05-5c4c-4969-8def-79c5933c3153
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019585682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.4019585682
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.96869563
Short name T333
Test name
Test status
Simulation time 203813503 ps
CPU time 3.74 seconds
Started May 12 03:49:16 PM PDT 24
Finished May 12 03:49:20 PM PDT 24
Peak memory 207508 kb
Host smart-f9fc087d-6593-40ac-bcdf-e927096b6696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96869563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.96869563
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.1944289573
Short name T567
Test name
Test status
Simulation time 1226376863 ps
CPU time 6.15 seconds
Started May 12 03:49:23 PM PDT 24
Finished May 12 03:49:30 PM PDT 24
Peak memory 210996 kb
Host smart-4308981e-7ed2-45c8-b279-ab3f08f51e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944289573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.1944289573
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.2917266550
Short name T895
Test name
Test status
Simulation time 71657338 ps
CPU time 0.93 seconds
Started May 12 03:45:04 PM PDT 24
Finished May 12 03:45:06 PM PDT 24
Peak memory 206068 kb
Host smart-2387db49-036b-48fd-ae4b-9065e6d75330
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917266550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.2917266550
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.3149338689
Short name T401
Test name
Test status
Simulation time 739082120 ps
CPU time 22.38 seconds
Started May 12 03:44:54 PM PDT 24
Finished May 12 03:45:16 PM PDT 24
Peak memory 214784 kb
Host smart-1a676813-2ea1-4934-939a-12e28b12af53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3149338689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.3149338689
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.1570257230
Short name T603
Test name
Test status
Simulation time 76968104 ps
CPU time 3.08 seconds
Started May 12 03:44:54 PM PDT 24
Finished May 12 03:44:57 PM PDT 24
Peak memory 218112 kb
Host smart-b15e4582-e3b6-4142-8b95-dfb6e23a698c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570257230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.1570257230
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.3734970705
Short name T315
Test name
Test status
Simulation time 1106982310 ps
CPU time 23.24 seconds
Started May 12 03:45:04 PM PDT 24
Finished May 12 03:45:27 PM PDT 24
Peak memory 214480 kb
Host smart-d5acb4c4-c57b-48ff-b8b2-d89e47ea657c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734970705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.3734970705
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.2992898170
Short name T16
Test name
Test status
Simulation time 160099031 ps
CPU time 3.67 seconds
Started May 12 03:44:53 PM PDT 24
Finished May 12 03:44:57 PM PDT 24
Peak memory 214280 kb
Host smart-c083203b-8858-45f8-a9f4-a0ca2725e7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992898170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.2992898170
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.3935630493
Short name T681
Test name
Test status
Simulation time 881641873 ps
CPU time 29.26 seconds
Started May 12 03:44:50 PM PDT 24
Finished May 12 03:45:21 PM PDT 24
Peak memory 208088 kb
Host smart-0b17bb90-712c-4876-8914-cbc73b60289b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935630493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.3935630493
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sideload.721756664
Short name T287
Test name
Test status
Simulation time 1235306682 ps
CPU time 8.52 seconds
Started May 12 03:44:55 PM PDT 24
Finished May 12 03:45:04 PM PDT 24
Peak memory 207944 kb
Host smart-c7a05351-1965-4bdc-b00d-700b52b602a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721756664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.721756664
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.3931043248
Short name T752
Test name
Test status
Simulation time 49426698 ps
CPU time 1.89 seconds
Started May 12 03:44:48 PM PDT 24
Finished May 12 03:44:51 PM PDT 24
Peak memory 206824 kb
Host smart-eefc035d-996c-469f-9f10-92ee3580d2c4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931043248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.3931043248
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.530317616
Short name T847
Test name
Test status
Simulation time 550620173 ps
CPU time 3.84 seconds
Started May 12 03:44:52 PM PDT 24
Finished May 12 03:44:56 PM PDT 24
Peak memory 208776 kb
Host smart-e5d0c4a5-9814-4e89-a90a-f1d98475fc60
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530317616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.530317616
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.2748374037
Short name T663
Test name
Test status
Simulation time 997433498 ps
CPU time 2.83 seconds
Started May 12 03:44:48 PM PDT 24
Finished May 12 03:44:51 PM PDT 24
Peak memory 208232 kb
Host smart-e38e49f2-fc64-482c-8a1d-94accfd65922
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748374037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.2748374037
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.3641606614
Short name T488
Test name
Test status
Simulation time 871837430 ps
CPU time 3.35 seconds
Started May 12 03:44:56 PM PDT 24
Finished May 12 03:45:00 PM PDT 24
Peak memory 209152 kb
Host smart-70d6ea06-c7a1-4ed9-9fbd-385e77ecf84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641606614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.3641606614
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.3345221893
Short name T842
Test name
Test status
Simulation time 37742878 ps
CPU time 2.48 seconds
Started May 12 03:44:50 PM PDT 24
Finished May 12 03:44:53 PM PDT 24
Peak memory 206628 kb
Host smart-ba6b1860-c1a5-43b8-8555-148cbb7ead77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345221893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.3345221893
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.4084762706
Short name T811
Test name
Test status
Simulation time 139055873 ps
CPU time 6.68 seconds
Started May 12 03:45:12 PM PDT 24
Finished May 12 03:45:20 PM PDT 24
Peak memory 218372 kb
Host smart-a21a0eb5-2ad4-404b-84ea-4b997e36869f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084762706 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.4084762706
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.3697765858
Short name T336
Test name
Test status
Simulation time 203828245 ps
CPU time 5.17 seconds
Started May 12 03:44:55 PM PDT 24
Finished May 12 03:45:01 PM PDT 24
Peak memory 218140 kb
Host smart-4e6eaf74-e4fd-43dd-9f05-e6a7f9e52788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697765858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.3697765858
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.2047111820
Short name T465
Test name
Test status
Simulation time 28187263 ps
CPU time 1.81 seconds
Started May 12 03:44:56 PM PDT 24
Finished May 12 03:44:59 PM PDT 24
Peak memory 209884 kb
Host smart-ca17ffa5-01ae-4fe6-a4a9-06367521305b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047111820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.2047111820
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.2091975018
Short name T437
Test name
Test status
Simulation time 14509443 ps
CPU time 0.79 seconds
Started May 12 03:49:30 PM PDT 24
Finished May 12 03:49:32 PM PDT 24
Peak memory 205888 kb
Host smart-b72c8746-6f1d-4420-b3ff-62f04bf247f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091975018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.2091975018
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.1244131408
Short name T264
Test name
Test status
Simulation time 698339496 ps
CPU time 10.65 seconds
Started May 12 03:49:20 PM PDT 24
Finished May 12 03:49:31 PM PDT 24
Peak memory 214288 kb
Host smart-aa535832-62d3-4ffc-93a9-3fd98645514d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1244131408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.1244131408
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.4273169226
Short name T30
Test name
Test status
Simulation time 905968825 ps
CPU time 5.33 seconds
Started May 12 03:49:25 PM PDT 24
Finished May 12 03:49:30 PM PDT 24
Peak memory 221280 kb
Host smart-5350061e-9cc0-46d2-87ce-7e932d1d2caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273169226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.4273169226
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.1205150781
Short name T738
Test name
Test status
Simulation time 762965112 ps
CPU time 6.54 seconds
Started May 12 03:49:24 PM PDT 24
Finished May 12 03:49:31 PM PDT 24
Peak memory 214272 kb
Host smart-1c4a5850-5dc4-464a-bc4a-992afc65d489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205150781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.1205150781
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.3663494752
Short name T803
Test name
Test status
Simulation time 216237905 ps
CPU time 5.42 seconds
Started May 12 03:49:24 PM PDT 24
Finished May 12 03:49:30 PM PDT 24
Peak memory 222452 kb
Host smart-8d770c18-b57e-476a-9ba0-8503094038b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663494752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.3663494752
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.886235579
Short name T53
Test name
Test status
Simulation time 247360076 ps
CPU time 3.55 seconds
Started May 12 03:49:20 PM PDT 24
Finished May 12 03:49:24 PM PDT 24
Peak memory 215832 kb
Host smart-8e1710f0-034f-47dc-9754-777be23f6f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886235579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.886235579
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.3748066707
Short name T263
Test name
Test status
Simulation time 632229237 ps
CPU time 6.26 seconds
Started May 12 03:49:21 PM PDT 24
Finished May 12 03:49:28 PM PDT 24
Peak memory 214380 kb
Host smart-13a4dffe-8790-48ea-9eea-7b006aac70a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748066707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.3748066707
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.238451501
Short name T450
Test name
Test status
Simulation time 76355682 ps
CPU time 1.9 seconds
Started May 12 03:49:23 PM PDT 24
Finished May 12 03:49:25 PM PDT 24
Peak memory 206828 kb
Host smart-19d4bdbd-6fe8-4ba9-b3e0-871d889ef3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238451501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.238451501
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.207035289
Short name T532
Test name
Test status
Simulation time 318152641 ps
CPU time 6.46 seconds
Started May 12 03:49:23 PM PDT 24
Finished May 12 03:49:30 PM PDT 24
Peak memory 208020 kb
Host smart-c44f5cc3-0abc-4fa3-8eb6-11887cdeebdb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207035289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.207035289
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.530476704
Short name T233
Test name
Test status
Simulation time 37430974 ps
CPU time 2.48 seconds
Started May 12 03:49:21 PM PDT 24
Finished May 12 03:49:24 PM PDT 24
Peak memory 208636 kb
Host smart-b2190014-acf3-49e2-bf2a-61bd7829ea04
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530476704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.530476704
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.4188143002
Short name T809
Test name
Test status
Simulation time 291811214 ps
CPU time 5.44 seconds
Started May 12 03:49:20 PM PDT 24
Finished May 12 03:49:26 PM PDT 24
Peak memory 208464 kb
Host smart-5ec448e7-cc7a-4465-8971-aad7f7d3772c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188143002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.4188143002
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.1851906327
Short name T309
Test name
Test status
Simulation time 406472775 ps
CPU time 2.9 seconds
Started May 12 03:49:30 PM PDT 24
Finished May 12 03:49:33 PM PDT 24
Peak memory 209552 kb
Host smart-7ce43c62-8fee-433f-acfb-40ba9c8a4856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851906327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.1851906327
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.2926312318
Short name T184
Test name
Test status
Simulation time 50047982 ps
CPU time 2.92 seconds
Started May 12 03:49:27 PM PDT 24
Finished May 12 03:49:30 PM PDT 24
Peak memory 206620 kb
Host smart-0e74290d-4ede-41e8-9553-f965ee8285d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926312318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.2926312318
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.724653793
Short name T166
Test name
Test status
Simulation time 2606865926 ps
CPU time 31.33 seconds
Started May 12 03:49:29 PM PDT 24
Finished May 12 03:50:01 PM PDT 24
Peak memory 222620 kb
Host smart-97a964ab-02f8-41ab-bac8-00361f219dec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724653793 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.724653793
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.3118404829
Short name T580
Test name
Test status
Simulation time 4858665823 ps
CPU time 90.31 seconds
Started May 12 03:49:25 PM PDT 24
Finished May 12 03:50:56 PM PDT 24
Peak memory 222520 kb
Host smart-055e7ab5-dd65-444a-a2cc-b15ffe6794ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118404829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.3118404829
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.1078629282
Short name T706
Test name
Test status
Simulation time 58113667 ps
CPU time 2.95 seconds
Started May 12 03:49:24 PM PDT 24
Finished May 12 03:49:27 PM PDT 24
Peak memory 210168 kb
Host smart-fc26ed7d-e68b-4066-8064-e0e5e24e4353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078629282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.1078629282
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.2084525100
Short name T739
Test name
Test status
Simulation time 288334269 ps
CPU time 0.77 seconds
Started May 12 03:49:34 PM PDT 24
Finished May 12 03:49:36 PM PDT 24
Peak memory 205932 kb
Host smart-b59941ca-13db-4b2d-b6d7-e7b9d0bff127
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084525100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.2084525100
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.2108692710
Short name T392
Test name
Test status
Simulation time 59638825 ps
CPU time 4.31 seconds
Started May 12 03:49:29 PM PDT 24
Finished May 12 03:49:34 PM PDT 24
Peak memory 215328 kb
Host smart-d4c668fe-7e45-4bf3-80ad-340c78250ce9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2108692710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.2108692710
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.1074267935
Short name T502
Test name
Test status
Simulation time 263691260 ps
CPU time 3.13 seconds
Started May 12 03:49:30 PM PDT 24
Finished May 12 03:49:34 PM PDT 24
Peak memory 214256 kb
Host smart-8a706adc-9a00-49e4-aabd-1caf1809dacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074267935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.1074267935
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.3408771208
Short name T665
Test name
Test status
Simulation time 71333677 ps
CPU time 1.68 seconds
Started May 12 03:49:27 PM PDT 24
Finished May 12 03:49:29 PM PDT 24
Peak memory 208336 kb
Host smart-0c1bb494-5b63-458f-bb80-2e9d831cf98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408771208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.3408771208
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.2909477587
Short name T324
Test name
Test status
Simulation time 90125333 ps
CPU time 4.66 seconds
Started May 12 03:49:29 PM PDT 24
Finished May 12 03:49:35 PM PDT 24
Peak memory 214272 kb
Host smart-25ec4ef6-251c-4a5d-aa7a-c56c19937c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909477587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.2909477587
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.620355921
Short name T872
Test name
Test status
Simulation time 47032142 ps
CPU time 3.07 seconds
Started May 12 03:49:39 PM PDT 24
Finished May 12 03:49:43 PM PDT 24
Peak memory 214252 kb
Host smart-2147d288-6dfd-4edd-9928-fe0ce0e31c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620355921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.620355921
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.1841168026
Short name T802
Test name
Test status
Simulation time 148752917 ps
CPU time 3.18 seconds
Started May 12 03:49:29 PM PDT 24
Finished May 12 03:49:33 PM PDT 24
Peak memory 209604 kb
Host smart-f9bfb934-dd91-4e11-a171-24a17c02df07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841168026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.1841168026
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.1890718041
Short name T429
Test name
Test status
Simulation time 87685037 ps
CPU time 3.23 seconds
Started May 12 03:49:27 PM PDT 24
Finished May 12 03:49:31 PM PDT 24
Peak memory 214356 kb
Host smart-da864844-ecf1-49c7-b217-0b3d2f84d99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890718041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.1890718041
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.1853488981
Short name T736
Test name
Test status
Simulation time 265862953 ps
CPU time 6.01 seconds
Started May 12 03:49:28 PM PDT 24
Finished May 12 03:49:35 PM PDT 24
Peak memory 208720 kb
Host smart-547af16e-3d47-4c87-98cc-7a4243ea778b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853488981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.1853488981
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.4051328618
Short name T646
Test name
Test status
Simulation time 619497066 ps
CPU time 15.67 seconds
Started May 12 03:49:30 PM PDT 24
Finished May 12 03:49:46 PM PDT 24
Peak memory 209024 kb
Host smart-98fc0ed4-7c57-4f14-9020-150d1c2f77ce
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051328618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.4051328618
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.837371417
Short name T530
Test name
Test status
Simulation time 238147503 ps
CPU time 7.55 seconds
Started May 12 03:49:28 PM PDT 24
Finished May 12 03:49:36 PM PDT 24
Peak memory 207940 kb
Host smart-2dfd2beb-4c63-41b6-8946-f05107bc7fd9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837371417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.837371417
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.1308916373
Short name T737
Test name
Test status
Simulation time 238129372 ps
CPU time 4.49 seconds
Started May 12 03:49:30 PM PDT 24
Finished May 12 03:49:35 PM PDT 24
Peak memory 208848 kb
Host smart-2f864547-5827-42d6-b6f2-bcd5816ef66e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308916373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.1308916373
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.2696297475
Short name T581
Test name
Test status
Simulation time 45009107 ps
CPU time 2.43 seconds
Started May 12 03:49:30 PM PDT 24
Finished May 12 03:49:33 PM PDT 24
Peak memory 209428 kb
Host smart-783b180e-8d4e-4b17-b346-1c77347a0b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696297475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.2696297475
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.2498822430
Short name T866
Test name
Test status
Simulation time 150533452 ps
CPU time 2.99 seconds
Started May 12 03:49:32 PM PDT 24
Finished May 12 03:49:35 PM PDT 24
Peak memory 207300 kb
Host smart-a85e1791-4b75-40ff-9aad-de9307bc226a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498822430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.2498822430
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.4040622118
Short name T181
Test name
Test status
Simulation time 1551835382 ps
CPU time 36.05 seconds
Started May 12 03:49:34 PM PDT 24
Finished May 12 03:50:11 PM PDT 24
Peak memory 219360 kb
Host smart-89a89937-c551-48dc-af96-2ae2bd9ff7c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040622118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.4040622118
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.3727431569
Short name T718
Test name
Test status
Simulation time 1153718372 ps
CPU time 15.79 seconds
Started May 12 03:49:28 PM PDT 24
Finished May 12 03:49:44 PM PDT 24
Peak memory 208732 kb
Host smart-80cec017-b827-4cbd-846a-f41922c115ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727431569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.3727431569
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.519876744
Short name T693
Test name
Test status
Simulation time 11249734 ps
CPU time 0.87 seconds
Started May 12 03:49:39 PM PDT 24
Finished May 12 03:49:41 PM PDT 24
Peak memory 205912 kb
Host smart-3593bb20-7e16-4046-85c1-e626298f6559
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519876744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.519876744
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.2525459525
Short name T692
Test name
Test status
Simulation time 121047837 ps
CPU time 2.57 seconds
Started May 12 03:49:34 PM PDT 24
Finished May 12 03:49:37 PM PDT 24
Peak memory 218496 kb
Host smart-d4066b52-f23f-4965-9c5f-4a8316533469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525459525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.2525459525
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.2921871865
Short name T226
Test name
Test status
Simulation time 29445973 ps
CPU time 2.14 seconds
Started May 12 03:49:34 PM PDT 24
Finished May 12 03:49:36 PM PDT 24
Peak memory 214264 kb
Host smart-0e6bcb63-7569-4877-9efa-4cd2e69a8af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921871865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.2921871865
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.208681439
Short name T322
Test name
Test status
Simulation time 66881404 ps
CPU time 3.83 seconds
Started May 12 03:49:34 PM PDT 24
Finished May 12 03:49:39 PM PDT 24
Peak memory 222360 kb
Host smart-97bff3c4-999e-4870-ab31-4dac7f0aaee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208681439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.208681439
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.2031634765
Short name T897
Test name
Test status
Simulation time 256680648 ps
CPU time 3.88 seconds
Started May 12 03:49:38 PM PDT 24
Finished May 12 03:49:42 PM PDT 24
Peak memory 214480 kb
Host smart-0dfbbdd9-ea7a-453b-af3b-3fc09e02f8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031634765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.2031634765
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.2723207007
Short name T230
Test name
Test status
Simulation time 1130361911 ps
CPU time 5.04 seconds
Started May 12 03:49:39 PM PDT 24
Finished May 12 03:49:44 PM PDT 24
Peak memory 210120 kb
Host smart-de13b4ef-027b-4ef7-a183-1806f9cef8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723207007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2723207007
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.111547360
Short name T459
Test name
Test status
Simulation time 560961921 ps
CPU time 6.11 seconds
Started May 12 03:49:38 PM PDT 24
Finished May 12 03:49:45 PM PDT 24
Peak memory 206664 kb
Host smart-11eac0ff-c306-478a-92a8-de84a9445002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111547360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.111547360
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.2507218388
Short name T774
Test name
Test status
Simulation time 930330429 ps
CPU time 3.9 seconds
Started May 12 03:49:36 PM PDT 24
Finished May 12 03:49:40 PM PDT 24
Peak memory 208688 kb
Host smart-e14b8615-6519-4dba-ad43-f1da0914f2f0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507218388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.2507218388
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.4140335802
Short name T723
Test name
Test status
Simulation time 28457724 ps
CPU time 2.25 seconds
Started May 12 03:49:35 PM PDT 24
Finished May 12 03:49:38 PM PDT 24
Peak memory 208464 kb
Host smart-0fb48468-e3fa-4386-bb54-6abf05f5916f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140335802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.4140335802
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.2481662912
Short name T614
Test name
Test status
Simulation time 565740271 ps
CPU time 4.76 seconds
Started May 12 03:49:34 PM PDT 24
Finished May 12 03:49:39 PM PDT 24
Peak memory 208356 kb
Host smart-0d886d93-3995-4f0e-b3fb-a7b9da8586ed
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481662912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.2481662912
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.824269951
Short name T910
Test name
Test status
Simulation time 53693558 ps
CPU time 1.64 seconds
Started May 12 03:49:39 PM PDT 24
Finished May 12 03:49:41 PM PDT 24
Peak memory 207856 kb
Host smart-0080b774-3b7d-46f1-82bb-c190d43e2f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824269951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.824269951
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.1346484016
Short name T832
Test name
Test status
Simulation time 4428385390 ps
CPU time 17.04 seconds
Started May 12 03:49:35 PM PDT 24
Finished May 12 03:49:53 PM PDT 24
Peak memory 207792 kb
Host smart-973faef2-8f9f-4f87-9b3b-450ca13616ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346484016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.1346484016
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.2008601991
Short name T69
Test name
Test status
Simulation time 269597473 ps
CPU time 14.11 seconds
Started May 12 03:49:39 PM PDT 24
Finished May 12 03:49:54 PM PDT 24
Peak memory 215288 kb
Host smart-1bbc5f87-6c7f-4479-8221-0a77c229daa8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008601991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.2008601991
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.3078832765
Short name T167
Test name
Test status
Simulation time 2568671873 ps
CPU time 16.36 seconds
Started May 12 03:49:38 PM PDT 24
Finished May 12 03:49:55 PM PDT 24
Peak memory 222712 kb
Host smart-10f4dbbf-e580-4b37-a603-07065f9b4e6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078832765 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.3078832765
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.2524941819
Short name T303
Test name
Test status
Simulation time 181034050 ps
CPU time 7.82 seconds
Started May 12 03:49:38 PM PDT 24
Finished May 12 03:49:46 PM PDT 24
Peak memory 214328 kb
Host smart-511a58d7-79b4-451e-a137-a10db2275889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524941819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.2524941819
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.250247690
Short name T43
Test name
Test status
Simulation time 228555832 ps
CPU time 4.23 seconds
Started May 12 03:49:36 PM PDT 24
Finished May 12 03:49:40 PM PDT 24
Peak memory 211104 kb
Host smart-11c005a5-d46f-4f97-ab55-cdb50063815f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250247690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.250247690
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.922170121
Short name T448
Test name
Test status
Simulation time 9878445 ps
CPU time 0.87 seconds
Started May 12 03:49:37 PM PDT 24
Finished May 12 03:49:39 PM PDT 24
Peak memory 205940 kb
Host smart-9fb91273-f885-415a-9fb5-75bcff57a308
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922170121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.922170121
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.1518812500
Short name T539
Test name
Test status
Simulation time 448315215 ps
CPU time 4.24 seconds
Started May 12 03:49:41 PM PDT 24
Finished May 12 03:49:45 PM PDT 24
Peak memory 208140 kb
Host smart-a8a69b5e-5967-49a7-8efe-7ffef44eaa6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518812500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.1518812500
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.3013487858
Short name T97
Test name
Test status
Simulation time 328950567 ps
CPU time 3.85 seconds
Started May 12 03:49:40 PM PDT 24
Finished May 12 03:49:45 PM PDT 24
Peak memory 214380 kb
Host smart-0cc92cf5-c336-41ca-8a40-2772ec9bf833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013487858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.3013487858
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.2486353343
Short name T903
Test name
Test status
Simulation time 260508701 ps
CPU time 3.01 seconds
Started May 12 03:49:38 PM PDT 24
Finished May 12 03:49:42 PM PDT 24
Peak memory 215040 kb
Host smart-0c016acd-872f-4d31-afaf-d9d46e5adfe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486353343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.2486353343
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.1941118341
Short name T156
Test name
Test status
Simulation time 111197076 ps
CPU time 2.31 seconds
Started May 12 03:49:38 PM PDT 24
Finished May 12 03:49:42 PM PDT 24
Peak memory 209968 kb
Host smart-79f9353f-e31b-4efd-a5d2-a2a7627ed39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941118341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.1941118341
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.4270497201
Short name T616
Test name
Test status
Simulation time 132966688 ps
CPU time 6.15 seconds
Started May 12 03:49:42 PM PDT 24
Finished May 12 03:49:49 PM PDT 24
Peak memory 207500 kb
Host smart-d6d2af78-e1ab-4ab5-a8c1-88f0e5f894ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270497201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.4270497201
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.676002230
Short name T644
Test name
Test status
Simulation time 315669192 ps
CPU time 5.22 seconds
Started May 12 03:49:41 PM PDT 24
Finished May 12 03:49:47 PM PDT 24
Peak memory 208440 kb
Host smart-0881cb05-a0b8-418f-a62a-6b242ca2877b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676002230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.676002230
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.4110210723
Short name T540
Test name
Test status
Simulation time 32946464 ps
CPU time 2.61 seconds
Started May 12 03:49:40 PM PDT 24
Finished May 12 03:49:43 PM PDT 24
Peak memory 207496 kb
Host smart-00449697-bcdd-450c-ad54-d86a676c985e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110210723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.4110210723
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.1280028981
Short name T911
Test name
Test status
Simulation time 1872937480 ps
CPU time 23.51 seconds
Started May 12 03:49:45 PM PDT 24
Finished May 12 03:50:09 PM PDT 24
Peak memory 208048 kb
Host smart-bacb181b-75c5-49c3-8e30-10e0ee136b20
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280028981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.1280028981
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.2673882543
Short name T442
Test name
Test status
Simulation time 79764889 ps
CPU time 2.68 seconds
Started May 12 03:49:42 PM PDT 24
Finished May 12 03:49:45 PM PDT 24
Peak memory 206816 kb
Host smart-dfc5aff2-09b8-4f3c-a5c3-c7dff812e534
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673882543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.2673882543
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.742068382
Short name T898
Test name
Test status
Simulation time 1020592468 ps
CPU time 6.37 seconds
Started May 12 03:49:37 PM PDT 24
Finished May 12 03:49:44 PM PDT 24
Peak memory 207892 kb
Host smart-091ba45a-c539-4bad-ab5d-b1af4e58a936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742068382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.742068382
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.1828572204
Short name T476
Test name
Test status
Simulation time 49627108 ps
CPU time 2.76 seconds
Started May 12 03:49:37 PM PDT 24
Finished May 12 03:49:41 PM PDT 24
Peak memory 206920 kb
Host smart-930c3881-6f8b-42af-bf0a-a4230c3fbbf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828572204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.1828572204
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.3846713856
Short name T290
Test name
Test status
Simulation time 1969139686 ps
CPU time 49.89 seconds
Started May 12 03:49:37 PM PDT 24
Finished May 12 03:50:28 PM PDT 24
Peak memory 216660 kb
Host smart-e6b57aec-957a-4f53-8249-190ee2a4d240
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846713856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.3846713856
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.3405456839
Short name T169
Test name
Test status
Simulation time 346677590 ps
CPU time 14.52 seconds
Started May 12 03:49:38 PM PDT 24
Finished May 12 03:49:54 PM PDT 24
Peak memory 222712 kb
Host smart-3f0ae152-de50-428a-bd5e-1e2e870e7503
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405456839 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.3405456839
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.2707868925
Short name T298
Test name
Test status
Simulation time 307583947 ps
CPU time 3.53 seconds
Started May 12 03:49:40 PM PDT 24
Finished May 12 03:49:44 PM PDT 24
Peak memory 209100 kb
Host smart-1eaee16e-49fe-40fa-b53b-14d74548a25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707868925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.2707868925
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.2773835969
Short name T369
Test name
Test status
Simulation time 431997167 ps
CPU time 9.97 seconds
Started May 12 03:49:38 PM PDT 24
Finished May 12 03:49:49 PM PDT 24
Peak memory 211000 kb
Host smart-82787515-0835-46e7-87d0-0f5a665f8554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773835969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.2773835969
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.919472861
Short name T504
Test name
Test status
Simulation time 12412783 ps
CPU time 0.75 seconds
Started May 12 03:49:48 PM PDT 24
Finished May 12 03:49:50 PM PDT 24
Peak memory 205912 kb
Host smart-0ca4a225-459a-4eb7-8ac9-9802a8e6faf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919472861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.919472861
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.1627308088
Short name T220
Test name
Test status
Simulation time 171287238 ps
CPU time 3.58 seconds
Started May 12 03:49:43 PM PDT 24
Finished May 12 03:49:47 PM PDT 24
Peak memory 215608 kb
Host smart-016459ce-6081-4f2c-bf25-54b1d320bdb9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1627308088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.1627308088
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.1465517246
Short name T600
Test name
Test status
Simulation time 180064600 ps
CPU time 3.26 seconds
Started May 12 03:49:44 PM PDT 24
Finished May 12 03:49:48 PM PDT 24
Peak memory 209204 kb
Host smart-6e748d10-51c4-4c0d-97cb-ad19b73cb8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465517246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.1465517246
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.3592218371
Short name T310
Test name
Test status
Simulation time 118819251 ps
CPU time 4.26 seconds
Started May 12 03:49:45 PM PDT 24
Finished May 12 03:49:49 PM PDT 24
Peak memory 214268 kb
Host smart-671f9f61-747a-4f85-8eaa-36e465347cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592218371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.3592218371
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.2710982043
Short name T708
Test name
Test status
Simulation time 102807698 ps
CPU time 1.95 seconds
Started May 12 03:49:46 PM PDT 24
Finished May 12 03:49:48 PM PDT 24
Peak memory 214184 kb
Host smart-51621350-6c0d-4311-857b-c26a737a2098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710982043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.2710982043
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.3571309611
Short name T858
Test name
Test status
Simulation time 124876621 ps
CPU time 3.71 seconds
Started May 12 03:49:44 PM PDT 24
Finished May 12 03:49:48 PM PDT 24
Peak memory 215288 kb
Host smart-cdccc981-d10a-4079-907f-a9a24efe8b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571309611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.3571309611
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_sideload.2303451230
Short name T520
Test name
Test status
Simulation time 85213841 ps
CPU time 3.28 seconds
Started May 12 03:49:42 PM PDT 24
Finished May 12 03:49:46 PM PDT 24
Peak memory 208420 kb
Host smart-5ff09e4c-bd49-49d2-b831-b222c1e11d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303451230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.2303451230
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.1772112730
Short name T704
Test name
Test status
Simulation time 905447593 ps
CPU time 6.68 seconds
Started May 12 03:49:47 PM PDT 24
Finished May 12 03:49:55 PM PDT 24
Peak memory 208664 kb
Host smart-c42254a2-30e4-4572-a122-2ade68e84f36
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772112730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.1772112730
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.2898874293
Short name T590
Test name
Test status
Simulation time 193517981 ps
CPU time 5.14 seconds
Started May 12 03:49:42 PM PDT 24
Finished May 12 03:49:48 PM PDT 24
Peak memory 208112 kb
Host smart-4417c6ed-104d-488e-b2db-4b1c6abe1f77
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898874293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.2898874293
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.2220535314
Short name T466
Test name
Test status
Simulation time 19114761803 ps
CPU time 34.59 seconds
Started May 12 03:49:42 PM PDT 24
Finished May 12 03:50:17 PM PDT 24
Peak memory 209108 kb
Host smart-ca1557cb-1509-428a-a056-fe32f5c31b4d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220535314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.2220535314
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.3016528214
Short name T751
Test name
Test status
Simulation time 21552016 ps
CPU time 1.78 seconds
Started May 12 03:49:49 PM PDT 24
Finished May 12 03:49:51 PM PDT 24
Peak memory 209240 kb
Host smart-60dfe5d9-1ae5-44d8-865c-a609a020115b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016528214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.3016528214
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.558185204
Short name T514
Test name
Test status
Simulation time 50517669 ps
CPU time 2.75 seconds
Started May 12 03:49:42 PM PDT 24
Finished May 12 03:49:45 PM PDT 24
Peak memory 206820 kb
Host smart-9babfc3f-8dce-4095-9c4e-d45395f8d63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558185204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.558185204
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.2719226979
Short name T209
Test name
Test status
Simulation time 917662079 ps
CPU time 39.69 seconds
Started May 12 03:49:48 PM PDT 24
Finished May 12 03:50:28 PM PDT 24
Peak memory 217068 kb
Host smart-8b74182b-9ce5-44cd-b855-5fd6d5fe04b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719226979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.2719226979
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.4042174797
Short name T267
Test name
Test status
Simulation time 679884829 ps
CPU time 12.37 seconds
Started May 12 03:49:49 PM PDT 24
Finished May 12 03:50:02 PM PDT 24
Peak memory 222596 kb
Host smart-c5e63e84-632b-4fd7-85d4-e351451d4798
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042174797 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.4042174797
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.855808210
Short name T688
Test name
Test status
Simulation time 1060580451 ps
CPU time 10.91 seconds
Started May 12 03:49:42 PM PDT 24
Finished May 12 03:49:53 PM PDT 24
Peak memory 218160 kb
Host smart-09d88717-b1e3-483d-87de-d26369137cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855808210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.855808210
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.865666981
Short name T909
Test name
Test status
Simulation time 262967836 ps
CPU time 3.01 seconds
Started May 12 03:49:48 PM PDT 24
Finished May 12 03:49:51 PM PDT 24
Peak memory 210320 kb
Host smart-91a51c5d-4a07-49c4-8695-1a77ec5a0ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865666981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.865666981
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.652248134
Short name T634
Test name
Test status
Simulation time 12330015 ps
CPU time 0.79 seconds
Started May 12 03:49:53 PM PDT 24
Finished May 12 03:49:54 PM PDT 24
Peak memory 205940 kb
Host smart-0406f9f6-6143-44a6-ab26-0311755ee548
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652248134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.652248134
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.514513238
Short name T902
Test name
Test status
Simulation time 1859998140 ps
CPU time 98.42 seconds
Started May 12 03:49:49 PM PDT 24
Finished May 12 03:51:28 PM PDT 24
Peak memory 215324 kb
Host smart-cc2597bd-3a35-494b-a473-d6d2da542b1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=514513238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.514513238
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.2716530790
Short name T8
Test name
Test status
Simulation time 88914435 ps
CPU time 3.4 seconds
Started May 12 03:49:52 PM PDT 24
Finished May 12 03:49:57 PM PDT 24
Peak memory 216640 kb
Host smart-d0431edc-5300-48cf-bfcb-bc55dcd2fad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716530790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.2716530790
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.3822209555
Short name T479
Test name
Test status
Simulation time 56769928 ps
CPU time 2.18 seconds
Started May 12 03:49:50 PM PDT 24
Finished May 12 03:49:52 PM PDT 24
Peak memory 209948 kb
Host smart-45d30128-2b99-4641-a029-94708760d299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822209555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.3822209555
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.620255868
Short name T88
Test name
Test status
Simulation time 221762732 ps
CPU time 2.69 seconds
Started May 12 03:49:51 PM PDT 24
Finished May 12 03:49:54 PM PDT 24
Peak memory 209124 kb
Host smart-10e487da-71f5-416b-bddf-cb8e41a59bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620255868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.620255868
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.1166124239
Short name T307
Test name
Test status
Simulation time 196063302 ps
CPU time 3.1 seconds
Started May 12 03:49:52 PM PDT 24
Finished May 12 03:49:56 PM PDT 24
Peak memory 214252 kb
Host smart-babb27ba-72f4-44c5-b679-c32f41e4f6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166124239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.1166124239
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.4062447182
Short name T735
Test name
Test status
Simulation time 115631646 ps
CPU time 3.85 seconds
Started May 12 03:50:10 PM PDT 24
Finished May 12 03:50:15 PM PDT 24
Peak memory 215216 kb
Host smart-a76a1a09-d83b-4686-b522-ff770b8973d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062447182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.4062447182
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.3187565719
Short name T780
Test name
Test status
Simulation time 1365750691 ps
CPU time 17.28 seconds
Started May 12 03:49:46 PM PDT 24
Finished May 12 03:50:04 PM PDT 24
Peak memory 214304 kb
Host smart-9839cd6b-dc2e-47cd-83bd-082e2c63d708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187565719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.3187565719
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.1076101130
Short name T678
Test name
Test status
Simulation time 838022736 ps
CPU time 7.07 seconds
Started May 12 03:49:49 PM PDT 24
Finished May 12 03:49:57 PM PDT 24
Peak memory 206900 kb
Host smart-fc4d06e1-8fcd-4c83-8dac-5e2ce4a9c54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076101130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.1076101130
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.1394842904
Short name T664
Test name
Test status
Simulation time 263939446 ps
CPU time 3.25 seconds
Started May 12 03:49:49 PM PDT 24
Finished May 12 03:49:53 PM PDT 24
Peak memory 206972 kb
Host smart-a40d08d7-8537-4061-8f5e-eb52a7175cb5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394842904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.1394842904
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.3490443635
Short name T84
Test name
Test status
Simulation time 103555734 ps
CPU time 3.81 seconds
Started May 12 03:49:47 PM PDT 24
Finished May 12 03:49:51 PM PDT 24
Peak memory 208264 kb
Host smart-c23bf899-a8f2-48a7-9dd7-3de46facf178
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490443635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.3490443635
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.1245328727
Short name T669
Test name
Test status
Simulation time 2296448627 ps
CPU time 7.38 seconds
Started May 12 03:49:46 PM PDT 24
Finished May 12 03:49:53 PM PDT 24
Peak memory 208700 kb
Host smart-bcfe395b-7d6c-4dee-903d-ccd447fc18cf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245328727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.1245328727
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.1331756212
Short name T245
Test name
Test status
Simulation time 315288743 ps
CPU time 10.17 seconds
Started May 12 03:49:50 PM PDT 24
Finished May 12 03:50:01 PM PDT 24
Peak memory 214296 kb
Host smart-ff554fd0-ebfa-45d5-a8da-008f45b15b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331756212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.1331756212
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.822609030
Short name T800
Test name
Test status
Simulation time 56533728 ps
CPU time 2.51 seconds
Started May 12 03:49:50 PM PDT 24
Finished May 12 03:49:53 PM PDT 24
Peak memory 206072 kb
Host smart-ffdcfd2d-d7c9-40a3-bbbf-1018a44efb02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822609030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.822609030
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.2914429396
Short name T825
Test name
Test status
Simulation time 107566115 ps
CPU time 4.01 seconds
Started May 12 03:49:54 PM PDT 24
Finished May 12 03:49:59 PM PDT 24
Peak memory 208932 kb
Host smart-2fd29932-b9c7-4863-8957-1147c5fa3d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914429396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.2914429396
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.3509213
Short name T726
Test name
Test status
Simulation time 195447023 ps
CPU time 1.88 seconds
Started May 12 03:49:48 PM PDT 24
Finished May 12 03:49:51 PM PDT 24
Peak memory 209980 kb
Host smart-a49b96ee-d952-49f2-bbd2-96cc48f97713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.3509213
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.1587178795
Short name T836
Test name
Test status
Simulation time 13949203 ps
CPU time 0.92 seconds
Started May 12 03:49:58 PM PDT 24
Finished May 12 03:50:00 PM PDT 24
Peak memory 206080 kb
Host smart-366e679e-3c6a-48c1-abde-20658105c5b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587178795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.1587178795
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.1894202743
Short name T235
Test name
Test status
Simulation time 54234343 ps
CPU time 4.26 seconds
Started May 12 03:49:53 PM PDT 24
Finished May 12 03:49:58 PM PDT 24
Peak memory 214284 kb
Host smart-65cb612f-16b2-41e4-b9a9-441f699a67f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1894202743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.1894202743
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.2467567732
Short name T720
Test name
Test status
Simulation time 183032955 ps
CPU time 4.12 seconds
Started May 12 03:49:54 PM PDT 24
Finished May 12 03:49:59 PM PDT 24
Peak memory 220120 kb
Host smart-0a57037a-61d6-43f6-b9d6-575d9a243876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467567732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.2467567732
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.2106770104
Short name T1
Test name
Test status
Simulation time 119644476 ps
CPU time 2.04 seconds
Started May 12 03:49:53 PM PDT 24
Finished May 12 03:49:56 PM PDT 24
Peak memory 208120 kb
Host smart-f28c24be-41f4-468b-a61d-388cc23e2895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106770104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.2106770104
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.532609708
Short name T96
Test name
Test status
Simulation time 371941647 ps
CPU time 6.06 seconds
Started May 12 03:49:54 PM PDT 24
Finished May 12 03:50:01 PM PDT 24
Peak memory 214300 kb
Host smart-bb14ade7-e1f2-40b9-afdd-d37171578fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532609708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.532609708
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.748804528
Short name T92
Test name
Test status
Simulation time 234443464 ps
CPU time 4.94 seconds
Started May 12 03:49:53 PM PDT 24
Finished May 12 03:49:58 PM PDT 24
Peak memory 214328 kb
Host smart-318889e4-f1d3-4ac7-b4a6-1d8005d2b750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748804528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.748804528
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.711025824
Short name T201
Test name
Test status
Simulation time 483003477 ps
CPU time 11.11 seconds
Started May 12 03:49:58 PM PDT 24
Finished May 12 03:50:10 PM PDT 24
Peak memory 222448 kb
Host smart-3275580d-c6b1-418c-8dc7-6df98130180d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711025824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.711025824
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.444828840
Short name T515
Test name
Test status
Simulation time 129550075 ps
CPU time 4 seconds
Started May 12 03:49:54 PM PDT 24
Finished May 12 03:49:59 PM PDT 24
Peak memory 208740 kb
Host smart-325606c1-19fa-4cf0-b30b-a3c1d73a2a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444828840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.444828840
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.2679611603
Short name T804
Test name
Test status
Simulation time 1170822356 ps
CPU time 17.99 seconds
Started May 12 03:49:52 PM PDT 24
Finished May 12 03:50:11 PM PDT 24
Peak memory 208584 kb
Host smart-a238612f-e751-464e-86c9-3e8bac6bfdbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679611603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.2679611603
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.3308844236
Short name T574
Test name
Test status
Simulation time 75632598 ps
CPU time 3.02 seconds
Started May 12 03:49:52 PM PDT 24
Finished May 12 03:49:56 PM PDT 24
Peak memory 208880 kb
Host smart-38df6898-9bb1-4098-b5b0-ea93ef185f3b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308844236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.3308844236
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.264137197
Short name T231
Test name
Test status
Simulation time 156791089 ps
CPU time 4.97 seconds
Started May 12 03:49:51 PM PDT 24
Finished May 12 03:49:57 PM PDT 24
Peak memory 208684 kb
Host smart-93d912cb-9b3e-4077-8aa4-720abe548336
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264137197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.264137197
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.2538568289
Short name T473
Test name
Test status
Simulation time 1063398147 ps
CPU time 25.64 seconds
Started May 12 03:49:52 PM PDT 24
Finished May 12 03:50:18 PM PDT 24
Peak memory 208044 kb
Host smart-e2096d87-dd9b-4288-9666-cd9e4ae3d36a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538568289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.2538568289
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.1482430692
Short name T535
Test name
Test status
Simulation time 69504805 ps
CPU time 2.97 seconds
Started May 12 03:49:55 PM PDT 24
Finished May 12 03:49:59 PM PDT 24
Peak memory 208244 kb
Host smart-c1e17347-df27-4186-8440-6edaf796cbf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482430692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.1482430692
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.1667534652
Short name T797
Test name
Test status
Simulation time 154186027 ps
CPU time 2.58 seconds
Started May 12 03:49:54 PM PDT 24
Finished May 12 03:49:57 PM PDT 24
Peak memory 206704 kb
Host smart-1add67bd-d053-499b-8d94-81414d1343d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667534652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.1667534652
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.3067560163
Short name T304
Test name
Test status
Simulation time 687064238 ps
CPU time 8.74 seconds
Started May 12 03:49:53 PM PDT 24
Finished May 12 03:50:03 PM PDT 24
Peak memory 216664 kb
Host smart-f18f1050-e305-4351-9c3d-a456f2ea6b18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067560163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.3067560163
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.4061152348
Short name T482
Test name
Test status
Simulation time 572572977 ps
CPU time 9.25 seconds
Started May 12 03:49:54 PM PDT 24
Finished May 12 03:50:04 PM PDT 24
Peak memory 214292 kb
Host smart-c18dafd8-61e6-4af4-ab6f-2d5706d400fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061152348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.4061152348
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.281449845
Short name T114
Test name
Test status
Simulation time 793297849 ps
CPU time 4.67 seconds
Started May 12 03:49:53 PM PDT 24
Finished May 12 03:49:58 PM PDT 24
Peak memory 210620 kb
Host smart-5a14ee9b-5262-40f1-b9b9-29578b5ba74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281449845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.281449845
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.3150708629
Short name T100
Test name
Test status
Simulation time 62543656 ps
CPU time 0.85 seconds
Started May 12 03:50:02 PM PDT 24
Finished May 12 03:50:04 PM PDT 24
Peak memory 205928 kb
Host smart-3ff3ef36-259b-4587-b85f-01094572e707
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150708629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.3150708629
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.777332438
Short name T394
Test name
Test status
Simulation time 188406412 ps
CPU time 8.33 seconds
Started May 12 03:50:00 PM PDT 24
Finished May 12 03:50:08 PM PDT 24
Peak memory 215384 kb
Host smart-7fdb45e2-01cc-4de6-ba48-707abed0d1f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=777332438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.777332438
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.3605435552
Short name T60
Test name
Test status
Simulation time 116163168 ps
CPU time 3.57 seconds
Started May 12 03:50:03 PM PDT 24
Finished May 12 03:50:07 PM PDT 24
Peak memory 206888 kb
Host smart-0c1dcbae-6305-4d85-a6fd-44a633f981b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605435552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.3605435552
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.1714385543
Short name T292
Test name
Test status
Simulation time 226504644 ps
CPU time 5.77 seconds
Started May 12 03:49:55 PM PDT 24
Finished May 12 03:50:01 PM PDT 24
Peak memory 209572 kb
Host smart-6a5ed9cf-24cd-443b-8554-a1c2ca5109fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714385543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.1714385543
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.2324640487
Short name T323
Test name
Test status
Simulation time 159853059 ps
CPU time 4.32 seconds
Started May 12 03:50:00 PM PDT 24
Finished May 12 03:50:04 PM PDT 24
Peak memory 222344 kb
Host smart-40bd3164-6a93-4bbd-9182-0a51acf9bf45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324640487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.2324640487
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.4147797691
Short name T497
Test name
Test status
Simulation time 105649567 ps
CPU time 3.07 seconds
Started May 12 03:49:57 PM PDT 24
Finished May 12 03:50:00 PM PDT 24
Peak memory 209404 kb
Host smart-92787a4c-4453-46f2-8547-efbfcbe221fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147797691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.4147797691
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.3870154767
Short name T534
Test name
Test status
Simulation time 157412326 ps
CPU time 5.14 seconds
Started May 12 03:49:58 PM PDT 24
Finished May 12 03:50:03 PM PDT 24
Peak memory 214268 kb
Host smart-d54f4012-46de-4425-b316-8141c67c6b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870154767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.3870154767
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.3563796687
Short name T906
Test name
Test status
Simulation time 7243891299 ps
CPU time 54.99 seconds
Started May 12 03:49:58 PM PDT 24
Finished May 12 03:50:53 PM PDT 24
Peak memory 208560 kb
Host smart-c48947cb-1160-46ee-ba5b-6ee73815f421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563796687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.3563796687
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.188518963
Short name T460
Test name
Test status
Simulation time 237375883 ps
CPU time 3.67 seconds
Started May 12 03:50:02 PM PDT 24
Finished May 12 03:50:06 PM PDT 24
Peak memory 208668 kb
Host smart-55d8dbb4-8d9b-45df-9a2d-313d6319fc36
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188518963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.188518963
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.1875971357
Short name T576
Test name
Test status
Simulation time 483219611 ps
CPU time 4.42 seconds
Started May 12 03:49:55 PM PDT 24
Finished May 12 03:50:00 PM PDT 24
Peak memory 206808 kb
Host smart-52eb3227-f337-4a32-bbc4-6ea345fb746a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875971357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.1875971357
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.741761138
Short name T885
Test name
Test status
Simulation time 190212372 ps
CPU time 3.13 seconds
Started May 12 03:50:02 PM PDT 24
Finished May 12 03:50:06 PM PDT 24
Peak memory 207024 kb
Host smart-12b0a6c0-a8ed-46e2-9157-672550594af8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741761138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.741761138
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.3637789834
Short name T398
Test name
Test status
Simulation time 117465253 ps
CPU time 3.16 seconds
Started May 12 03:49:58 PM PDT 24
Finished May 12 03:50:02 PM PDT 24
Peak memory 210092 kb
Host smart-ab2d0877-8ef9-4d95-9582-2fc6cf3e635d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637789834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.3637789834
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.2310009378
Short name T621
Test name
Test status
Simulation time 42568105 ps
CPU time 1.94 seconds
Started May 12 03:49:58 PM PDT 24
Finished May 12 03:50:00 PM PDT 24
Peak memory 206552 kb
Host smart-cce2c440-75f3-4967-874b-9779c22b29d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310009378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.2310009378
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.772656770
Short name T846
Test name
Test status
Simulation time 2111580899 ps
CPU time 22.7 seconds
Started May 12 03:49:59 PM PDT 24
Finished May 12 03:50:23 PM PDT 24
Peak memory 214284 kb
Host smart-a2bcfd90-7a99-4cad-8592-976b33c2d850
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772656770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.772656770
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.512175257
Short name T838
Test name
Test status
Simulation time 336538619 ps
CPU time 7.11 seconds
Started May 12 03:50:05 PM PDT 24
Finished May 12 03:50:13 PM PDT 24
Peak memory 220476 kb
Host smart-6e5b3935-4c58-4537-951c-881dd816f70b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512175257 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.512175257
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.48165562
Short name T219
Test name
Test status
Simulation time 245385964 ps
CPU time 4.38 seconds
Started May 12 03:49:58 PM PDT 24
Finished May 12 03:50:03 PM PDT 24
Peak memory 209020 kb
Host smart-dee89ee9-8017-4008-b618-afa611940e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48165562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.48165562
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.3892773210
Short name T548
Test name
Test status
Simulation time 319928479 ps
CPU time 3.17 seconds
Started May 12 03:49:59 PM PDT 24
Finished May 12 03:50:03 PM PDT 24
Peak memory 210632 kb
Host smart-7270ce2d-8a54-4f3c-aff7-f509458e3ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892773210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.3892773210
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.2390667270
Short name T876
Test name
Test status
Simulation time 13664206 ps
CPU time 0.83 seconds
Started May 12 03:50:06 PM PDT 24
Finished May 12 03:50:07 PM PDT 24
Peak memory 205924 kb
Host smart-0b9c37f5-f884-4436-ab0b-1c49ac41c57d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390667270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.2390667270
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.3572551353
Short name T395
Test name
Test status
Simulation time 3168880222 ps
CPU time 43.67 seconds
Started May 12 03:50:02 PM PDT 24
Finished May 12 03:50:47 PM PDT 24
Peak memory 222524 kb
Host smart-5d88a9bf-e62e-4458-806a-6306b135236e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3572551353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.3572551353
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.2030266517
Short name T508
Test name
Test status
Simulation time 75222258 ps
CPU time 2.08 seconds
Started May 12 03:50:01 PM PDT 24
Finished May 12 03:50:03 PM PDT 24
Peak memory 209780 kb
Host smart-fdf9256e-1ad9-46ea-8d1d-75d582e73982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030266517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.2030266517
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.1359243780
Short name T317
Test name
Test status
Simulation time 921544394 ps
CPU time 6.98 seconds
Started May 12 03:50:00 PM PDT 24
Finished May 12 03:50:07 PM PDT 24
Peak memory 220732 kb
Host smart-162a3a0c-c263-48d7-98dc-496ce87c0609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359243780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.1359243780
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.1420952944
Short name T253
Test name
Test status
Simulation time 193881659 ps
CPU time 3.55 seconds
Started May 12 03:50:04 PM PDT 24
Finished May 12 03:50:08 PM PDT 24
Peak memory 214236 kb
Host smart-3d59eae6-3d00-4c88-9b36-48e2e0ebb832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420952944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.1420952944
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.3003665681
Short name T196
Test name
Test status
Simulation time 410043587 ps
CPU time 3.98 seconds
Started May 12 03:50:03 PM PDT 24
Finished May 12 03:50:08 PM PDT 24
Peak memory 214932 kb
Host smart-c61a3ef8-5f98-436d-9608-3bc78387b269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003665681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.3003665681
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.772931792
Short name T597
Test name
Test status
Simulation time 581841755 ps
CPU time 4.33 seconds
Started May 12 03:50:04 PM PDT 24
Finished May 12 03:50:09 PM PDT 24
Peak memory 207220 kb
Host smart-d9bae98f-87ff-408c-8dd2-32beaf63e6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772931792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.772931792
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.2108272763
Short name T244
Test name
Test status
Simulation time 259812501 ps
CPU time 3.41 seconds
Started May 12 03:50:04 PM PDT 24
Finished May 12 03:50:08 PM PDT 24
Peak memory 208396 kb
Host smart-d59b06ad-edce-478a-b966-4d6638fad9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108272763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.2108272763
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.1603483515
Short name T483
Test name
Test status
Simulation time 1580182002 ps
CPU time 5.16 seconds
Started May 12 03:50:04 PM PDT 24
Finished May 12 03:50:10 PM PDT 24
Peak memory 207076 kb
Host smart-8cf8a7a9-c44f-49d3-8fa1-8d9e6dab57c6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603483515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.1603483515
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.3350639992
Short name T724
Test name
Test status
Simulation time 63802764 ps
CPU time 3.56 seconds
Started May 12 03:50:01 PM PDT 24
Finished May 12 03:50:05 PM PDT 24
Peak memory 206892 kb
Host smart-83f42da2-9d1d-4c7c-a266-c4d589fcdea4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350639992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.3350639992
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.2984296040
Short name T612
Test name
Test status
Simulation time 9485120002 ps
CPU time 35.59 seconds
Started May 12 03:50:01 PM PDT 24
Finished May 12 03:50:37 PM PDT 24
Peak memory 208636 kb
Host smart-08f27609-f219-4d2c-b49f-840710a31b10
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984296040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.2984296040
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.1373815771
Short name T884
Test name
Test status
Simulation time 1874280674 ps
CPU time 3.9 seconds
Started May 12 03:50:08 PM PDT 24
Finished May 12 03:50:13 PM PDT 24
Peak memory 209664 kb
Host smart-64e9124f-cc74-4684-bfae-7f0ad57a6b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373815771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.1373815771
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.2878914998
Short name T492
Test name
Test status
Simulation time 339830470 ps
CPU time 8.7 seconds
Started May 12 03:50:03 PM PDT 24
Finished May 12 03:50:12 PM PDT 24
Peak memory 206532 kb
Host smart-5bd42353-9271-428e-bf1f-65abc48c527e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878914998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.2878914998
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.1736882324
Short name T178
Test name
Test status
Simulation time 974565494 ps
CPU time 15.3 seconds
Started May 12 03:50:14 PM PDT 24
Finished May 12 03:50:29 PM PDT 24
Peak memory 218548 kb
Host smart-45db7170-ac39-4fd3-9c71-afc0742d1f4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736882324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.1736882324
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.982670130
Short name T584
Test name
Test status
Simulation time 257170692 ps
CPU time 9.57 seconds
Started May 12 03:50:05 PM PDT 24
Finished May 12 03:50:15 PM PDT 24
Peak memory 220468 kb
Host smart-ad076b30-e56a-48a4-abb0-827dcb33d6d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982670130 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.982670130
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.2818004781
Short name T558
Test name
Test status
Simulation time 137207007 ps
CPU time 4.53 seconds
Started May 12 03:50:02 PM PDT 24
Finished May 12 03:50:07 PM PDT 24
Peak memory 207732 kb
Host smart-078f9a42-01ac-4c1c-8272-5984c7fd102d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818004781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.2818004781
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.2649655274
Short name T373
Test name
Test status
Simulation time 312853884 ps
CPU time 2.68 seconds
Started May 12 03:50:04 PM PDT 24
Finished May 12 03:50:07 PM PDT 24
Peak memory 210044 kb
Host smart-b5a6c964-1e95-4ab1-9a82-18bc1b8534e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649655274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.2649655274
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.608023609
Short name T852
Test name
Test status
Simulation time 105052780 ps
CPU time 0.85 seconds
Started May 12 03:50:14 PM PDT 24
Finished May 12 03:50:15 PM PDT 24
Peak memory 205920 kb
Host smart-7693830d-101c-4d0d-a04c-a3c817605f5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608023609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.608023609
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.1049148275
Short name T129
Test name
Test status
Simulation time 89434225 ps
CPU time 2.73 seconds
Started May 12 03:50:08 PM PDT 24
Finished May 12 03:50:11 PM PDT 24
Peak memory 214340 kb
Host smart-ce28b7e6-115e-4f2a-bbda-5a66b18a905c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1049148275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.1049148275
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.4156616975
Short name T828
Test name
Test status
Simulation time 1145545262 ps
CPU time 2.76 seconds
Started May 12 03:50:09 PM PDT 24
Finished May 12 03:50:13 PM PDT 24
Peak memory 217288 kb
Host smart-d8f610e8-5155-4183-9f8c-a5d7978f7fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156616975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.4156616975
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.2924802632
Short name T810
Test name
Test status
Simulation time 200236463 ps
CPU time 2.81 seconds
Started May 12 03:50:06 PM PDT 24
Finished May 12 03:50:10 PM PDT 24
Peak memory 210376 kb
Host smart-503e4b13-ddd2-4786-b6ff-32c2b29ead86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924802632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.2924802632
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.2583073224
Short name T676
Test name
Test status
Simulation time 65262552 ps
CPU time 3.17 seconds
Started May 12 03:50:08 PM PDT 24
Finished May 12 03:50:12 PM PDT 24
Peak memory 218984 kb
Host smart-3437637e-b3b4-4359-ad78-472952f409a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583073224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.2583073224
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.1901571349
Short name T526
Test name
Test status
Simulation time 132975222 ps
CPU time 5.11 seconds
Started May 12 03:50:07 PM PDT 24
Finished May 12 03:50:13 PM PDT 24
Peak memory 214220 kb
Host smart-8d8bbedb-290b-4d6b-9f99-ae5b04d43ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901571349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.1901571349
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.2452799673
Short name T212
Test name
Test status
Simulation time 311527329 ps
CPU time 4.56 seconds
Started May 12 03:50:08 PM PDT 24
Finished May 12 03:50:13 PM PDT 24
Peak memory 208560 kb
Host smart-268fa860-9ff0-4817-8065-94e41f91c70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452799673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.2452799673
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.3310145498
Short name T573
Test name
Test status
Simulation time 2030705806 ps
CPU time 5.58 seconds
Started May 12 03:50:04 PM PDT 24
Finished May 12 03:50:10 PM PDT 24
Peak memory 209328 kb
Host smart-785127e2-4e6c-4a76-b0b3-854e9d42695f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310145498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.3310145498
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.598628706
Short name T438
Test name
Test status
Simulation time 598580021 ps
CPU time 4.93 seconds
Started May 12 03:50:03 PM PDT 24
Finished May 12 03:50:08 PM PDT 24
Peak memory 206740 kb
Host smart-d3108bdb-55a8-4288-8ec4-64e71d034c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598628706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.598628706
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.2226878207
Short name T837
Test name
Test status
Simulation time 135452736 ps
CPU time 5.05 seconds
Started May 12 03:50:05 PM PDT 24
Finished May 12 03:50:10 PM PDT 24
Peak memory 206888 kb
Host smart-c36e286a-1923-49ba-bde5-994686ddef66
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226878207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.2226878207
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.2540412540
Short name T870
Test name
Test status
Simulation time 33274722 ps
CPU time 2.75 seconds
Started May 12 03:50:09 PM PDT 24
Finished May 12 03:50:12 PM PDT 24
Peak memory 206936 kb
Host smart-21097912-b3b7-4fd7-a5e5-c69ed4085f78
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540412540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.2540412540
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.299088010
Short name T856
Test name
Test status
Simulation time 153177176 ps
CPU time 5.09 seconds
Started May 12 03:50:09 PM PDT 24
Finished May 12 03:50:15 PM PDT 24
Peak memory 206708 kb
Host smart-7c968a23-aa4b-4299-812a-c6de7ab5ab65
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299088010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.299088010
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.3443837372
Short name T684
Test name
Test status
Simulation time 151526926 ps
CPU time 2.22 seconds
Started May 12 03:50:09 PM PDT 24
Finished May 12 03:50:12 PM PDT 24
Peak memory 208104 kb
Host smart-3cb668be-5130-458b-b7e7-e608aa94b9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443837372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.3443837372
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.441322326
Short name T855
Test name
Test status
Simulation time 74204702 ps
CPU time 3.36 seconds
Started May 12 03:50:06 PM PDT 24
Finished May 12 03:50:09 PM PDT 24
Peak memory 208684 kb
Host smart-a122eada-7fe0-460a-9ce0-a452b3609fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441322326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.441322326
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.1964707970
Short name T180
Test name
Test status
Simulation time 4217401162 ps
CPU time 54.82 seconds
Started May 12 03:50:10 PM PDT 24
Finished May 12 03:51:05 PM PDT 24
Peak memory 221216 kb
Host smart-50ae2b6f-a450-4be3-9e12-efa72aca18eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964707970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.1964707970
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.923910594
Short name T749
Test name
Test status
Simulation time 214676782 ps
CPU time 3.69 seconds
Started May 12 03:50:08 PM PDT 24
Finished May 12 03:50:12 PM PDT 24
Peak memory 207416 kb
Host smart-52afe121-0460-4274-8a3e-b92bdd94b999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923910594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.923910594
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.1182328882
Short name T52
Test name
Test status
Simulation time 66920152 ps
CPU time 2.26 seconds
Started May 12 03:50:12 PM PDT 24
Finished May 12 03:50:15 PM PDT 24
Peak memory 209772 kb
Host smart-7d916e4a-6635-4699-bd9b-f7e00b26080a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182328882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.1182328882
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.2018435836
Short name T631
Test name
Test status
Simulation time 76887305 ps
CPU time 0.79 seconds
Started May 12 03:45:25 PM PDT 24
Finished May 12 03:45:28 PM PDT 24
Peak memory 205888 kb
Host smart-881b3fc2-2d80-404c-bcf3-790bb9f37107
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018435836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.2018435836
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.782561634
Short name T36
Test name
Test status
Simulation time 95138080 ps
CPU time 4.75 seconds
Started May 12 03:45:16 PM PDT 24
Finished May 12 03:45:23 PM PDT 24
Peak memory 222632 kb
Host smart-1a3c5b1a-e357-4689-9d9d-8a1b35254fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782561634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.782561634
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.3207758407
Short name T71
Test name
Test status
Simulation time 106301423 ps
CPU time 3.27 seconds
Started May 12 03:45:11 PM PDT 24
Finished May 12 03:45:14 PM PDT 24
Peak memory 209776 kb
Host smart-75fe37eb-ea70-45ff-b5a2-858fa5d2b071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207758407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.3207758407
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.4186607796
Short name T627
Test name
Test status
Simulation time 937106408 ps
CPU time 3.94 seconds
Started May 12 03:45:13 PM PDT 24
Finished May 12 03:45:18 PM PDT 24
Peak memory 214664 kb
Host smart-64f15659-f254-4c5c-9336-efe0ed32a7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186607796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.4186607796
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.2329026796
Short name T912
Test name
Test status
Simulation time 39166733 ps
CPU time 2.8 seconds
Started May 12 03:45:28 PM PDT 24
Finished May 12 03:45:34 PM PDT 24
Peak memory 214240 kb
Host smart-16fcb1d5-745f-4a9d-bcf2-74c7cde48c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329026796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.2329026796
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.1988589936
Short name T5
Test name
Test status
Simulation time 48616066 ps
CPU time 2.58 seconds
Started May 12 03:45:10 PM PDT 24
Finished May 12 03:45:13 PM PDT 24
Peak memory 214284 kb
Host smart-6da9f007-dc56-4795-990c-a4f99dafc971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988589936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.1988589936
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.2934352162
Short name T282
Test name
Test status
Simulation time 57386654 ps
CPU time 3.51 seconds
Started May 12 03:45:07 PM PDT 24
Finished May 12 03:45:11 PM PDT 24
Peak memory 217608 kb
Host smart-0144e79a-a4bb-434b-9915-6f56152a01ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934352162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.2934352162
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.2230571025
Short name T484
Test name
Test status
Simulation time 286698322 ps
CPU time 3.82 seconds
Started May 12 03:45:04 PM PDT 24
Finished May 12 03:45:08 PM PDT 24
Peak memory 208400 kb
Host smart-83f81e75-4aba-40a0-9174-94b17a7ee763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230571025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.2230571025
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.2468860306
Short name T489
Test name
Test status
Simulation time 137510306 ps
CPU time 3.18 seconds
Started May 12 03:45:05 PM PDT 24
Finished May 12 03:45:09 PM PDT 24
Peak memory 206948 kb
Host smart-984b42a4-badc-4b80-9d8e-241ad4d14099
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468860306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.2468860306
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.672021639
Short name T604
Test name
Test status
Simulation time 110813346 ps
CPU time 3.14 seconds
Started May 12 03:45:07 PM PDT 24
Finished May 12 03:45:10 PM PDT 24
Peak memory 206808 kb
Host smart-34d502ec-d4c1-4a83-8c79-aabfbb740f51
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672021639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.672021639
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.635105168
Short name T905
Test name
Test status
Simulation time 634720561 ps
CPU time 5.54 seconds
Started May 12 03:45:14 PM PDT 24
Finished May 12 03:45:20 PM PDT 24
Peak memory 206908 kb
Host smart-f3f64ec5-d986-42be-9f2f-b3ad2ed23082
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635105168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.635105168
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.1284627665
Short name T598
Test name
Test status
Simulation time 58100729 ps
CPU time 1.6 seconds
Started May 12 03:45:13 PM PDT 24
Finished May 12 03:45:16 PM PDT 24
Peak memory 207860 kb
Host smart-54c5202e-10ab-4c05-818a-004fc9309967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284627665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.1284627665
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.181307494
Short name T632
Test name
Test status
Simulation time 44189673 ps
CPU time 2.11 seconds
Started May 12 03:45:08 PM PDT 24
Finished May 12 03:45:10 PM PDT 24
Peak memory 206708 kb
Host smart-361cc509-288e-4c95-b8de-acdc110ff4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181307494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.181307494
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.4223911461
Short name T237
Test name
Test status
Simulation time 3244558765 ps
CPU time 81.05 seconds
Started May 12 03:45:24 PM PDT 24
Finished May 12 03:46:48 PM PDT 24
Peak memory 222548 kb
Host smart-6f4f81a0-a117-4023-a1ee-31d8c6e40ad6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223911461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.4223911461
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.1521421603
Short name T819
Test name
Test status
Simulation time 1384450293 ps
CPU time 16.81 seconds
Started May 12 03:45:15 PM PDT 24
Finished May 12 03:45:33 PM PDT 24
Peak memory 222596 kb
Host smart-d65a7b27-36f4-453d-80e4-bef6cf286735
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521421603 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.1521421603
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.3456913592
Short name T844
Test name
Test status
Simulation time 70344895 ps
CPU time 2.84 seconds
Started May 12 03:45:09 PM PDT 24
Finished May 12 03:45:13 PM PDT 24
Peak memory 218192 kb
Host smart-ebfd2407-27a3-4972-9338-12c63245e38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456913592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.3456913592
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.3458250124
Short name T116
Test name
Test status
Simulation time 73609308 ps
CPU time 3.45 seconds
Started May 12 03:45:18 PM PDT 24
Finished May 12 03:45:24 PM PDT 24
Peak memory 210180 kb
Host smart-6fc743de-1cdb-402f-8747-a78057a65e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458250124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.3458250124
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.2325014359
Short name T762
Test name
Test status
Simulation time 39731474 ps
CPU time 0.95 seconds
Started May 12 03:45:25 PM PDT 24
Finished May 12 03:45:29 PM PDT 24
Peak memory 205888 kb
Host smart-775442db-dadf-4383-b965-2118496a4c64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325014359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.2325014359
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.2851336083
Short name T108
Test name
Test status
Simulation time 142603606 ps
CPU time 5.63 seconds
Started May 12 03:45:18 PM PDT 24
Finished May 12 03:45:27 PM PDT 24
Peak memory 215208 kb
Host smart-76c30e46-2c5d-4043-9b13-7832d4bab5ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2851336083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.2851336083
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.936502047
Short name T853
Test name
Test status
Simulation time 60760123 ps
CPU time 2.18 seconds
Started May 12 03:45:21 PM PDT 24
Finished May 12 03:45:25 PM PDT 24
Peak memory 214328 kb
Host smart-e4f35f58-2d98-45d5-8da0-7d5fb08898bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936502047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.936502047
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.4232427892
Short name T49
Test name
Test status
Simulation time 429867126 ps
CPU time 3.96 seconds
Started May 12 03:45:31 PM PDT 24
Finished May 12 03:45:36 PM PDT 24
Peak memory 214288 kb
Host smart-3bb103ea-9911-4e7d-895c-75681a4544d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232427892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.4232427892
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.3087902724
Short name T306
Test name
Test status
Simulation time 266439343 ps
CPU time 5.38 seconds
Started May 12 03:45:24 PM PDT 24
Finished May 12 03:45:32 PM PDT 24
Peak memory 214300 kb
Host smart-f0d1873a-379b-48ee-958d-26268dc5929e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087902724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.3087902724
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.3941517668
Short name T202
Test name
Test status
Simulation time 52936764 ps
CPU time 3.69 seconds
Started May 12 03:45:30 PM PDT 24
Finished May 12 03:45:35 PM PDT 24
Peak memory 209804 kb
Host smart-81334126-e5cb-40af-bec0-df22a32e6fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941517668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.3941517668
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.1121400691
Short name T566
Test name
Test status
Simulation time 105342087 ps
CPU time 5.33 seconds
Started May 12 03:45:17 PM PDT 24
Finished May 12 03:45:26 PM PDT 24
Peak memory 207336 kb
Host smart-3112a2b8-5539-4583-b337-cabbd60fef6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121400691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.1121400691
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.4106020496
Short name T635
Test name
Test status
Simulation time 94093897 ps
CPU time 3 seconds
Started May 12 03:45:17 PM PDT 24
Finished May 12 03:45:22 PM PDT 24
Peak memory 208652 kb
Host smart-a8b0630d-6e7c-42d9-b9e1-18d1cf5c4a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106020496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.4106020496
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.2104614031
Short name T513
Test name
Test status
Simulation time 102090929 ps
CPU time 3.42 seconds
Started May 12 03:45:18 PM PDT 24
Finished May 12 03:45:24 PM PDT 24
Peak memory 208828 kb
Host smart-96b47e7d-933e-4613-a86f-c0fd0795a910
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104614031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.2104614031
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.3118840457
Short name T703
Test name
Test status
Simulation time 779363529 ps
CPU time 9.32 seconds
Started May 12 03:45:17 PM PDT 24
Finished May 12 03:45:30 PM PDT 24
Peak memory 208176 kb
Host smart-63b001b7-eb76-4afa-9e42-c6abfa79ced5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118840457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.3118840457
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.2809284327
Short name T240
Test name
Test status
Simulation time 40835701 ps
CPU time 2.48 seconds
Started May 12 03:45:17 PM PDT 24
Finished May 12 03:45:22 PM PDT 24
Peak memory 207532 kb
Host smart-a15aed91-746b-42b4-8e0b-bee529fd982b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809284327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.2809284327
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.1163575607
Short name T261
Test name
Test status
Simulation time 697680916 ps
CPU time 2.83 seconds
Started May 12 03:45:26 PM PDT 24
Finished May 12 03:45:32 PM PDT 24
Peak memory 208712 kb
Host smart-9725af0a-f9d1-4ada-aaa0-ab34661c33a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163575607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.1163575607
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.936912986
Short name T469
Test name
Test status
Simulation time 288544518 ps
CPU time 3.25 seconds
Started May 12 03:45:17 PM PDT 24
Finished May 12 03:45:23 PM PDT 24
Peak memory 208360 kb
Host smart-35a24e74-ba29-43be-99cc-a65d6b4a718e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936912986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.936912986
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.531730063
Short name T677
Test name
Test status
Simulation time 4668048230 ps
CPU time 32.67 seconds
Started May 12 03:45:34 PM PDT 24
Finished May 12 03:46:08 PM PDT 24
Peak memory 222656 kb
Host smart-529468df-f570-4efd-b65a-a3f548733fa5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531730063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.531730063
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.1816888866
Short name T168
Test name
Test status
Simulation time 669728058 ps
CPU time 28.44 seconds
Started May 12 03:45:46 PM PDT 24
Finished May 12 03:46:16 PM PDT 24
Peak memory 222616 kb
Host smart-07262d49-019a-4919-9698-2458c7012295
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816888866 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.1816888866
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.3069607876
Short name T730
Test name
Test status
Simulation time 209004390 ps
CPU time 4.22 seconds
Started May 12 03:45:26 PM PDT 24
Finished May 12 03:45:33 PM PDT 24
Peak memory 209788 kb
Host smart-43a8f7e0-91e1-45bc-b135-af372f0d2e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069607876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.3069607876
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.556167435
Short name T516
Test name
Test status
Simulation time 49951316 ps
CPU time 2.73 seconds
Started May 12 03:45:32 PM PDT 24
Finished May 12 03:45:36 PM PDT 24
Peak memory 209932 kb
Host smart-4250c592-0c06-4d69-9e6a-81f4af9c1994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556167435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.556167435
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.3381233645
Short name T744
Test name
Test status
Simulation time 19341651 ps
CPU time 0.74 seconds
Started May 12 03:45:46 PM PDT 24
Finished May 12 03:45:47 PM PDT 24
Peak memory 205912 kb
Host smart-9c98de1b-037e-4368-92f0-97a478d92b03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381233645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.3381233645
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.305073421
Short name T286
Test name
Test status
Simulation time 86507617 ps
CPU time 3.66 seconds
Started May 12 03:45:31 PM PDT 24
Finished May 12 03:45:36 PM PDT 24
Peak memory 215320 kb
Host smart-d01d47d2-652a-42ca-ad4c-f090806140bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=305073421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.305073421
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.2401901142
Short name T62
Test name
Test status
Simulation time 73028359 ps
CPU time 4.55 seconds
Started May 12 03:45:37 PM PDT 24
Finished May 12 03:45:42 PM PDT 24
Peak memory 220944 kb
Host smart-4fa4fad3-10b4-4741-90fc-7ffc2729b809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401901142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.2401901142
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.95294021
Short name T78
Test name
Test status
Simulation time 274667650 ps
CPU time 4.32 seconds
Started May 12 03:45:31 PM PDT 24
Finished May 12 03:45:37 PM PDT 24
Peak memory 218540 kb
Host smart-9addbaff-4a8a-48bb-b3fe-8da8aa0e637c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95294021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.95294021
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.2378622391
Short name T367
Test name
Test status
Simulation time 389953789 ps
CPU time 5.91 seconds
Started May 12 03:45:32 PM PDT 24
Finished May 12 03:45:39 PM PDT 24
Peak memory 215152 kb
Host smart-ebcf1d23-7b6f-47e3-a57b-3db4db4cc0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378622391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.2378622391
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.2992373869
Short name T210
Test name
Test status
Simulation time 463824678 ps
CPU time 12.23 seconds
Started May 12 03:45:33 PM PDT 24
Finished May 12 03:45:46 PM PDT 24
Peak memory 222500 kb
Host smart-d16c8d94-eab0-4f9b-9a72-1b04dbd44af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992373869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.2992373869
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.1545592317
Short name T641
Test name
Test status
Simulation time 60257100 ps
CPU time 4.01 seconds
Started May 12 03:45:41 PM PDT 24
Finished May 12 03:45:46 PM PDT 24
Peak memory 209228 kb
Host smart-d8bba906-6451-43e7-9e76-c3fbb72a6052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545592317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.1545592317
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.2671502988
Short name T784
Test name
Test status
Simulation time 329968593 ps
CPU time 5.6 seconds
Started May 12 03:45:29 PM PDT 24
Finished May 12 03:45:37 PM PDT 24
Peak memory 208640 kb
Host smart-99c95e9c-ac17-4333-874f-c96d982c1167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671502988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.2671502988
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.2946019894
Short name T652
Test name
Test status
Simulation time 498456380 ps
CPU time 3.7 seconds
Started May 12 03:45:33 PM PDT 24
Finished May 12 03:45:38 PM PDT 24
Peak memory 208108 kb
Host smart-6d4a4715-5941-4d7e-bc8e-693da3072950
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946019894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.2946019894
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.691493038
Short name T775
Test name
Test status
Simulation time 83372091 ps
CPU time 2.53 seconds
Started May 12 03:45:27 PM PDT 24
Finished May 12 03:45:33 PM PDT 24
Peak memory 206780 kb
Host smart-8499da4c-3d30-43e9-ba96-85f53cfc9183
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691493038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.691493038
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.3795611517
Short name T443
Test name
Test status
Simulation time 205323215 ps
CPU time 4.27 seconds
Started May 12 03:45:45 PM PDT 24
Finished May 12 03:45:50 PM PDT 24
Peak memory 208452 kb
Host smart-c72de70a-aa96-417e-b3aa-9c6a661d4577
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795611517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.3795611517
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.3182792183
Short name T700
Test name
Test status
Simulation time 192062765 ps
CPU time 2.28 seconds
Started May 12 03:45:45 PM PDT 24
Finished May 12 03:45:48 PM PDT 24
Peak memory 207992 kb
Host smart-9657df2f-2bc6-44f5-b099-7417def3e815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182792183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.3182792183
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.3592938762
Short name T777
Test name
Test status
Simulation time 295780222 ps
CPU time 3.91 seconds
Started May 12 03:45:29 PM PDT 24
Finished May 12 03:45:35 PM PDT 24
Peak memory 206820 kb
Host smart-27b86350-4b2b-4c90-9959-97f4044e0948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592938762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.3592938762
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.2340789564
Short name T193
Test name
Test status
Simulation time 2831068827 ps
CPU time 32.81 seconds
Started May 12 03:45:42 PM PDT 24
Finished May 12 03:46:15 PM PDT 24
Peak memory 215932 kb
Host smart-ef0325ff-a1f1-4d4f-83d3-ed69f0f961dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340789564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.2340789564
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.3759563312
Short name T715
Test name
Test status
Simulation time 1092712448 ps
CPU time 8.14 seconds
Started May 12 03:45:33 PM PDT 24
Finished May 12 03:45:42 PM PDT 24
Peak memory 218332 kb
Host smart-bf8ad3b0-0389-4d98-8976-ead270f65a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759563312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.3759563312
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.3588345448
Short name T900
Test name
Test status
Simulation time 546175377 ps
CPU time 1.71 seconds
Started May 12 03:45:38 PM PDT 24
Finished May 12 03:45:40 PM PDT 24
Peak memory 209672 kb
Host smart-e08e40af-477b-4f97-9953-48af5480ed46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588345448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.3588345448
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.195574050
Short name T410
Test name
Test status
Simulation time 21356795 ps
CPU time 0.81 seconds
Started May 12 03:45:50 PM PDT 24
Finished May 12 03:45:51 PM PDT 24
Peak memory 205884 kb
Host smart-5c2dd4bc-d9e4-40c0-996f-c0284a936b2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195574050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.195574050
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.2253709995
Short name T332
Test name
Test status
Simulation time 43883766 ps
CPU time 3.46 seconds
Started May 12 03:45:45 PM PDT 24
Finished May 12 03:45:49 PM PDT 24
Peak memory 214968 kb
Host smart-f6d24431-96d6-4480-99ca-070ac5907dba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2253709995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.2253709995
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.2759701538
Short name T19
Test name
Test status
Simulation time 98048422 ps
CPU time 2.08 seconds
Started May 12 03:45:46 PM PDT 24
Finished May 12 03:45:49 PM PDT 24
Peak memory 221820 kb
Host smart-b92dcb25-1260-43f6-96b4-918a39eb9490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759701538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.2759701538
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.1041808276
Short name T486
Test name
Test status
Simulation time 110773624 ps
CPU time 2.8 seconds
Started May 12 03:45:45 PM PDT 24
Finished May 12 03:45:48 PM PDT 24
Peak memory 218132 kb
Host smart-0b8240d8-7739-48df-80d5-6ae5e2160933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041808276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.1041808276
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.2477459581
Short name T894
Test name
Test status
Simulation time 174585722 ps
CPU time 4.4 seconds
Started May 12 03:46:16 PM PDT 24
Finished May 12 03:46:22 PM PDT 24
Peak memory 209480 kb
Host smart-06f382cf-dc4c-456e-ad51-bf1ce3162c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477459581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.2477459581
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.4278910476
Short name T275
Test name
Test status
Simulation time 405607689 ps
CPU time 3.31 seconds
Started May 12 03:45:47 PM PDT 24
Finished May 12 03:45:51 PM PDT 24
Peak memory 214212 kb
Host smart-cbb0f263-8f57-4671-9ed2-8ad944fe05b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278910476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.4278910476
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.1265100180
Short name T155
Test name
Test status
Simulation time 103632739 ps
CPU time 4.25 seconds
Started May 12 03:45:49 PM PDT 24
Finished May 12 03:45:53 PM PDT 24
Peak memory 209496 kb
Host smart-846b41ee-4306-4645-b633-22f477595a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265100180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.1265100180
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.2618469918
Short name T668
Test name
Test status
Simulation time 117115688 ps
CPU time 5.04 seconds
Started May 12 03:45:42 PM PDT 24
Finished May 12 03:45:47 PM PDT 24
Peak memory 208632 kb
Host smart-2c9661a3-0dfb-4ef5-b407-cf11d89417c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618469918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.2618469918
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.1209283899
Short name T806
Test name
Test status
Simulation time 1666790266 ps
CPU time 18.31 seconds
Started May 12 03:45:40 PM PDT 24
Finished May 12 03:45:59 PM PDT 24
Peak memory 208032 kb
Host smart-25f06633-4b9c-41c3-8ca6-c0fa52b7136f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209283899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.1209283899
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.1805878241
Short name T840
Test name
Test status
Simulation time 172244346 ps
CPU time 2.98 seconds
Started May 12 03:45:43 PM PDT 24
Finished May 12 03:45:46 PM PDT 24
Peak memory 206980 kb
Host smart-37d946fc-5ad3-4037-a152-a04d73d0371a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805878241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.1805878241
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.1123285006
Short name T501
Test name
Test status
Simulation time 4496855559 ps
CPU time 78.62 seconds
Started May 12 03:45:45 PM PDT 24
Finished May 12 03:47:04 PM PDT 24
Peak memory 208092 kb
Host smart-56b0a3a3-c2dd-48ed-8977-7586a74cf9ea
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123285006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.1123285006
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.544924650
Short name T675
Test name
Test status
Simulation time 99822546 ps
CPU time 2.7 seconds
Started May 12 03:45:55 PM PDT 24
Finished May 12 03:45:58 PM PDT 24
Peak memory 206992 kb
Host smart-3b5633e2-bc87-4b5b-a83b-a4854f47770c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544924650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.544924650
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.3192483792
Short name T331
Test name
Test status
Simulation time 45141052 ps
CPU time 2.37 seconds
Started May 12 03:45:49 PM PDT 24
Finished May 12 03:45:52 PM PDT 24
Peak memory 208136 kb
Host smart-eef3af7d-ce53-4c01-a859-23a5ee23d800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192483792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.3192483792
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.2058775671
Short name T533
Test name
Test status
Simulation time 80720476 ps
CPU time 3.9 seconds
Started May 12 03:46:03 PM PDT 24
Finished May 12 03:46:07 PM PDT 24
Peak memory 208572 kb
Host smart-c8c3e9f8-37a3-4245-ae73-7cacb2528efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058775671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.2058775671
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.1045448700
Short name T198
Test name
Test status
Simulation time 4671139058 ps
CPU time 68.92 seconds
Started May 12 03:45:46 PM PDT 24
Finished May 12 03:46:55 PM PDT 24
Peak memory 222088 kb
Host smart-e624e702-258a-485e-b1e9-41fe5d549583
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045448700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.1045448700
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.2738112498
Short name T283
Test name
Test status
Simulation time 181827297 ps
CPU time 6.43 seconds
Started May 12 03:45:53 PM PDT 24
Finished May 12 03:46:00 PM PDT 24
Peak memory 214292 kb
Host smart-53e8210a-aae2-4ea6-8dc6-200dac63c364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738112498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.2738112498
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.970333075
Short name T544
Test name
Test status
Simulation time 614643173 ps
CPU time 15.6 seconds
Started May 12 03:45:49 PM PDT 24
Finished May 12 03:46:05 PM PDT 24
Peak memory 210924 kb
Host smart-ef6ef03d-35b3-4b00-a6bd-9911e92980dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970333075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.970333075
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.27953996
Short name T613
Test name
Test status
Simulation time 69933240 ps
CPU time 0.91 seconds
Started May 12 03:46:01 PM PDT 24
Finished May 12 03:46:03 PM PDT 24
Peak memory 205924 kb
Host smart-c2d76043-baea-4a3c-8457-e801e589b401
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27953996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.27953996
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.363334240
Short name T689
Test name
Test status
Simulation time 63529648 ps
CPU time 2.1 seconds
Started May 12 03:45:58 PM PDT 24
Finished May 12 03:46:01 PM PDT 24
Peak memory 217924 kb
Host smart-1f2dec39-da96-46ba-ae65-0d1e8d2f6f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363334240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.363334240
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.3608148342
Short name T381
Test name
Test status
Simulation time 776159646 ps
CPU time 6.48 seconds
Started May 12 03:46:15 PM PDT 24
Finished May 12 03:46:22 PM PDT 24
Peak memory 210032 kb
Host smart-997ea9c5-137c-4b1b-9d41-f9c5ea675e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608148342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.3608148342
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.1043826100
Short name T99
Test name
Test status
Simulation time 348146679 ps
CPU time 6.46 seconds
Started May 12 03:45:58 PM PDT 24
Finished May 12 03:46:05 PM PDT 24
Peak memory 214292 kb
Host smart-f71fcb8c-52e8-4062-9357-313131b2e3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043826100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.1043826100
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.126548416
Short name T273
Test name
Test status
Simulation time 133498305 ps
CPU time 3.37 seconds
Started May 12 03:45:57 PM PDT 24
Finished May 12 03:46:01 PM PDT 24
Peak memory 220040 kb
Host smart-9487128b-fb2a-4788-8078-76ed4bfff503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126548416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.126548416
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.2248578362
Short name T771
Test name
Test status
Simulation time 315247389 ps
CPU time 3.9 seconds
Started May 12 03:45:52 PM PDT 24
Finished May 12 03:45:57 PM PDT 24
Peak memory 216488 kb
Host smart-421e07a6-2876-45dc-9422-37e0a4932134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248578362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.2248578362
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.1806709667
Short name T328
Test name
Test status
Simulation time 128830217 ps
CPU time 6.13 seconds
Started May 12 03:45:53 PM PDT 24
Finished May 12 03:46:00 PM PDT 24
Peak memory 210040 kb
Host smart-39dee2df-53b7-49a9-bd10-249a08506edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806709667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.1806709667
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.2713420915
Short name T786
Test name
Test status
Simulation time 298672689 ps
CPU time 3.57 seconds
Started May 12 03:45:48 PM PDT 24
Finished May 12 03:45:52 PM PDT 24
Peak memory 208440 kb
Host smart-49b3c3ca-99b8-4a5b-a533-03191f08d027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713420915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.2713420915
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.4205239601
Short name T710
Test name
Test status
Simulation time 1553054242 ps
CPU time 9.14 seconds
Started May 12 03:45:53 PM PDT 24
Finished May 12 03:46:02 PM PDT 24
Peak memory 208456 kb
Host smart-e2bc1d16-ca52-42bb-8706-d43cd799dbb2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205239601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.4205239601
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.2577107485
Short name T265
Test name
Test status
Simulation time 431049903 ps
CPU time 9.38 seconds
Started May 12 03:45:53 PM PDT 24
Finished May 12 03:46:03 PM PDT 24
Peak memory 208712 kb
Host smart-1e78bafc-25c5-4950-a497-ea8f474bcb69
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577107485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.2577107485
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.3264112032
Short name T682
Test name
Test status
Simulation time 407976842 ps
CPU time 5.8 seconds
Started May 12 03:45:57 PM PDT 24
Finished May 12 03:46:03 PM PDT 24
Peak memory 208332 kb
Host smart-59084b28-e2f3-4991-9aa8-df80462719a1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264112032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.3264112032
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.520454043
Short name T868
Test name
Test status
Simulation time 107040269 ps
CPU time 3.51 seconds
Started May 12 03:45:55 PM PDT 24
Finished May 12 03:45:59 PM PDT 24
Peak memory 209608 kb
Host smart-b3970c36-7154-4455-b61a-e1eb30b4b00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520454043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.520454043
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.2137063519
Short name T453
Test name
Test status
Simulation time 193332641 ps
CPU time 2.81 seconds
Started May 12 03:45:52 PM PDT 24
Finished May 12 03:45:55 PM PDT 24
Peak memory 206796 kb
Host smart-d939287e-1093-4d62-aaf6-760594cf461a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137063519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.2137063519
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.3315923922
Short name T746
Test name
Test status
Simulation time 243343760 ps
CPU time 16.06 seconds
Started May 12 03:45:58 PM PDT 24
Finished May 12 03:46:14 PM PDT 24
Peak memory 221344 kb
Host smart-3e6cedfa-d440-43e3-91c6-e89c655ce25f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315923922 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.3315923922
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.673403241
Short name T446
Test name
Test status
Simulation time 359737425 ps
CPU time 5.21 seconds
Started May 12 03:45:56 PM PDT 24
Finished May 12 03:46:02 PM PDT 24
Peak memory 208784 kb
Host smart-d83ea47d-33ae-4aff-9b39-dfb24762823e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673403241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.673403241
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.3220742506
Short name T642
Test name
Test status
Simulation time 319491093 ps
CPU time 2.3 seconds
Started May 12 03:45:59 PM PDT 24
Finished May 12 03:46:01 PM PDT 24
Peak memory 210420 kb
Host smart-42e1b206-9b1e-4644-8868-3552ec805f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220742506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.3220742506
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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