Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
55095 |
1 |
|
|
T1 |
40 |
|
T2 |
43 |
|
T3 |
33 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
32330 |
1 |
|
|
T1 |
10 |
|
T2 |
43 |
|
T4 |
185 |
auto[1] |
22765 |
1 |
|
|
T1 |
30 |
|
T3 |
33 |
|
T4 |
282 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
27250 |
1 |
|
|
T1 |
1 |
|
T2 |
22 |
|
T3 |
17 |
auto[1] |
27845 |
1 |
|
|
T1 |
39 |
|
T2 |
21 |
|
T3 |
16 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for intr_cg_cc
Bins
cp_intr | cp_intr_en | cp_intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
15836 |
1 |
|
|
T2 |
22 |
|
T4 |
93 |
|
T5 |
33 |
all_values[0] |
auto[0] |
auto[1] |
16494 |
1 |
|
|
T1 |
10 |
|
T2 |
21 |
|
T4 |
92 |
all_values[0] |
auto[1] |
auto[0] |
11414 |
1 |
|
|
T1 |
1 |
|
T3 |
17 |
|
T4 |
141 |
all_values[0] |
auto[1] |
auto[1] |
11351 |
1 |
|
|
T1 |
29 |
|
T3 |
16 |
|
T4 |
141 |