Summary for Variable op_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
5 |
1 |
4 |
80.00 |
Automatically Generated Bins for op_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
auto[OpDisable] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[OpAdvance] |
44 |
1 |
|
|
T26 |
1 |
|
T42 |
1 |
|
T6 |
1 |
auto[OpGenId] |
11 |
1 |
|
|
T53 |
1 |
|
T75 |
1 |
|
T190 |
1 |
auto[OpGenSwOut] |
12 |
1 |
|
|
T53 |
1 |
|
T28 |
1 |
|
T68 |
1 |
auto[OpGenHwOut] |
19 |
1 |
|
|
T7 |
1 |
|
T8 |
1 |
|
T44 |
1 |
Summary for Variable state_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
7 |
0 |
7 |
100.00 |
Automatically Generated Bins for state_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[StReset] |
1659 |
1 |
|
|
T9 |
180 |
|
T58 |
2 |
|
T59 |
5 |
auto[StInit] |
70 |
1 |
|
|
T33 |
1 |
|
T6 |
1 |
|
T51 |
1 |
auto[StCreatorRootKey] |
52 |
1 |
|
|
T5 |
1 |
|
T42 |
1 |
|
T7 |
1 |
auto[StOwnerIntKey] |
43 |
1 |
|
|
T26 |
1 |
|
T53 |
1 |
|
T61 |
1 |
auto[StOwnerKey] |
33 |
1 |
|
|
T32 |
1 |
|
T43 |
1 |
|
T67 |
1 |
auto[StDisabled] |
425 |
1 |
|
|
T4 |
10 |
|
T70 |
1 |
|
T58 |
3 |
auto[StInvalid] |
48 |
1 |
|
|
T39 |
1 |
|
T191 |
1 |
|
T192 |
1 |
Summary for Variable wip_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wip_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
3322 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
auto[1] |
86 |
1 |
|
|
T26 |
1 |
|
T42 |
1 |
|
T6 |
1 |
Summary for Cross state_x_wip_cross
Samples crossed: state_cp wip_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
14 |
1 |
13 |
92.86 |
1 |
Automatically Generated Cross Bins for state_x_wip_cross
Uncovered bins
state_cp | wip_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[StInvalid]] |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
state_cp | wip_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[StReset] |
auto[0] |
1655 |
1 |
|
|
T9 |
180 |
|
T58 |
2 |
|
T59 |
5 |
auto[StReset] |
auto[1] |
4 |
1 |
|
|
T69 |
1 |
|
T47 |
1 |
|
T48 |
1 |
auto[StInit] |
auto[0] |
41 |
1 |
|
|
T33 |
1 |
|
T51 |
1 |
|
T34 |
1 |
auto[StInit] |
auto[1] |
29 |
1 |
|
|
T6 |
1 |
|
T53 |
1 |
|
T193 |
1 |
auto[StCreatorRootKey] |
auto[0] |
35 |
1 |
|
|
T5 |
1 |
|
T7 |
1 |
|
T74 |
1 |
auto[StCreatorRootKey] |
auto[1] |
17 |
1 |
|
|
T42 |
1 |
|
T53 |
1 |
|
T113 |
1 |
auto[StOwnerIntKey] |
auto[0] |
28 |
1 |
|
|
T61 |
1 |
|
T38 |
1 |
|
T37 |
1 |
auto[StOwnerIntKey] |
auto[1] |
15 |
1 |
|
|
T26 |
1 |
|
T53 |
1 |
|
T62 |
1 |
auto[StOwnerKey] |
auto[0] |
25 |
1 |
|
|
T32 |
1 |
|
T65 |
1 |
|
T66 |
1 |
auto[StOwnerKey] |
auto[1] |
8 |
1 |
|
|
T43 |
1 |
|
T67 |
1 |
|
T68 |
1 |
auto[StDisabled] |
auto[0] |
412 |
1 |
|
|
T4 |
10 |
|
T70 |
1 |
|
T58 |
3 |
auto[StDisabled] |
auto[1] |
13 |
1 |
|
|
T7 |
2 |
|
T8 |
1 |
|
T113 |
1 |
auto[StInvalid] |
auto[0] |
48 |
1 |
|
|
T39 |
1 |
|
T191 |
1 |
|
T192 |
1 |
Summary for Cross state_x_op_cross
Samples crossed: state_cp op_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
35 |
15 |
20 |
57.14 |
15 |
Automatically Generated Cross Bins for state_x_op_cross
Element holes
state_cp | op_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[StInvalid]] |
* |
-- |
-- |
5 |
|
Uncovered bins
state_cp | op_cp | COUNT | AT LEAST | NUMBER | STATUS |
[auto[StReset]] |
[auto[OpGenId] , auto[OpGenSwOut]] |
-- |
-- |
2 |
|
[auto[StReset]] |
[auto[OpDisable]] |
0 |
1 |
1 |
|
[auto[StInit]] |
[auto[OpDisable]] |
0 |
1 |
1 |
|
[auto[StCreatorRootKey]] |
[auto[OpGenId]] |
0 |
1 |
1 |
|
[auto[StCreatorRootKey]] |
[auto[OpDisable]] |
0 |
1 |
1 |
|
[auto[StOwnerIntKey]] |
[auto[OpDisable]] |
0 |
1 |
1 |
|
[auto[StOwnerKey]] |
[auto[OpGenId]] |
0 |
1 |
1 |
|
[auto[StOwnerKey]] |
[auto[OpDisable]] |
0 |
1 |
1 |
|
[auto[StDisabled]] |
[auto[OpDisable]] |
0 |
1 |
1 |
|
Covered bins
state_cp | op_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[StReset] |
auto[OpAdvance] |
3 |
1 |
|
|
T47 |
1 |
|
T48 |
1 |
|
T49 |
1 |
auto[StReset] |
auto[OpGenHwOut] |
1 |
1 |
|
|
T69 |
1 |
|
- |
- |
|
- |
- |
auto[StInit] |
auto[OpAdvance] |
14 |
1 |
|
|
T6 |
1 |
|
T193 |
1 |
|
T71 |
1 |
auto[StInit] |
auto[OpGenId] |
6 |
1 |
|
|
T53 |
1 |
|
T75 |
1 |
|
T190 |
1 |
auto[StInit] |
auto[OpGenSwOut] |
3 |
1 |
|
|
T28 |
1 |
|
T134 |
1 |
|
T194 |
1 |
auto[StInit] |
auto[OpGenHwOut] |
6 |
1 |
|
|
T44 |
1 |
|
T195 |
1 |
|
T196 |
1 |
auto[StCreatorRootKey] |
auto[OpAdvance] |
11 |
1 |
|
|
T42 |
1 |
|
T53 |
1 |
|
T113 |
1 |
auto[StCreatorRootKey] |
auto[OpGenSwOut] |
3 |
1 |
|
|
T167 |
1 |
|
T169 |
1 |
|
T197 |
1 |
auto[StCreatorRootKey] |
auto[OpGenHwOut] |
3 |
1 |
|
|
T198 |
1 |
|
T199 |
1 |
|
T138 |
1 |
auto[StOwnerIntKey] |
auto[OpAdvance] |
6 |
1 |
|
|
T26 |
1 |
|
T62 |
1 |
|
T63 |
1 |
auto[StOwnerIntKey] |
auto[OpGenId] |
3 |
1 |
|
|
T200 |
1 |
|
T194 |
1 |
|
T201 |
1 |
auto[StOwnerIntKey] |
auto[OpGenSwOut] |
2 |
1 |
|
|
T53 |
1 |
|
T137 |
1 |
|
- |
- |
auto[StOwnerIntKey] |
auto[OpGenHwOut] |
4 |
1 |
|
|
T202 |
1 |
|
T203 |
1 |
|
T204 |
1 |
auto[StOwnerKey] |
auto[OpAdvance] |
4 |
1 |
|
|
T43 |
1 |
|
T67 |
1 |
|
T205 |
1 |
auto[StOwnerKey] |
auto[OpGenSwOut] |
1 |
1 |
|
|
T68 |
1 |
|
- |
- |
|
- |
- |
auto[StOwnerKey] |
auto[OpGenHwOut] |
3 |
1 |
|
|
T206 |
1 |
|
T144 |
1 |
|
T207 |
1 |
auto[StDisabled] |
auto[OpAdvance] |
6 |
1 |
|
|
T7 |
1 |
|
T113 |
1 |
|
T168 |
2 |
auto[StDisabled] |
auto[OpGenId] |
2 |
1 |
|
|
T208 |
1 |
|
T209 |
1 |
|
- |
- |
auto[StDisabled] |
auto[OpGenSwOut] |
3 |
1 |
|
|
T76 |
1 |
|
T168 |
1 |
|
T209 |
1 |
auto[StDisabled] |
auto[OpGenHwOut] |
2 |
1 |
|
|
T7 |
1 |
|
T8 |
1 |
|
- |
- |