Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

10552

1

T1

10

T2

10

T3

4

auto[Attestation]

7557

1

T2

3

T3

6

T4

85

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2686	1			T1	2		T3	1		T4	23
auto[Aes]	3245	1			T1	1		T3	1		T4	19
auto[Kmac]	3279	1			T1	2		T4	25		T14	3
auto[Otbn]	3198	1			T2	13		T3	2		T4	22

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7376	1			T1	1		T2	8		T3	5
auto[OpGenId]	5701	1			T1	5		T3	6		T4	67
auto[OpGenSwOut]	5610	1			T1	2		T3	4		T4	56
auto[OpGenHwOut]	6798	1			T1	3		T2	13		T4	33
auto[OpDisable]	129	1			T3	1		T30	1		T31	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10361

1

T1

1

T2

8

T3

10

auto[OpDoneFail]

15253

1

T1

10

T2

13

T3

6

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	5998	1			T1	11		T2	6		T3	1
auto[StInit]	3599	1			T2	2		T3	5		T4	29
auto[StCreatorRootKey]	3155	1			T2	2		T3	2		T4	37
auto[StOwnerIntKey]	2740	1			T2	2		T3	3		T4	29
auto[StOwnerKey]	2391	1			T2	2		T3	3		T4	31
auto[StDisabled]	7731	1			T2	7		T3	2		T4	76

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	301	1			T1	1		T4	1		T14	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	88	1			T32	1		T70	1		T24	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	84	1			T4	1		T32	2		T173	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	73	1			T4	1		T24	2		T174	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	69	1			T4	1		T131	1		T163	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	203	1			T4	2		T15	1		T101	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	298	1			T1	1		T4	1		T33	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	107	1			T4	1		T5	1		T175	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	82	1			T41	1		T32	1		T70	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	66	1			T4	1		T31	1		T58	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	61	1			T3	1		T32	1		T173	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	206	1			T31	1		T173	1		T175	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	262	1			T14	2		T101	1		T24	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	79	1			T4	1		T32	1		T58	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	59	1			T4	1		T31	1		T121	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	66	1			T176	1		T106	1		T131	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	52	1			T24	1		T176	1		T177	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	203	1			T4	4		T41	1		T175	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	294	1			T14	1		T101	1		T24	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	101	1			T3	1		T4	1		T33	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	90	1			T4	2		T14	1		T31	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	61	1			T3	1		T26	1		T178	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	55	1			T4	2		T58	1		T106	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	206	1			T4	3		T175	1		T98	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	71	1			T4	2		T59	3		T7	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	100	1			T3	1		T4	2		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	77	1			T4	1		T70	1		T176	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	66	1			T163	1		T179	1		T91	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	54	1			T4	1		T173	1		T180	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	227	1			T4	3		T106	1		T131	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	59	1			T59	4		T7	5		T74	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	101	1			T4	2		T14	1		T176	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	79	1			T30	1		T58	1		T177	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	91	1			T4	2		T24	1		T7	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	67	1			T4	1		T164	1		T7	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	216	1			T4	4		T14	1		T15	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	59	1			T4	2		T7	4		T74	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	107	1			T4	1		T31	1		T181	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	96	1			T4	2		T173	1		T181	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	91	1			T4	1		T58	1		T182	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	70	1			T4	1		T14	1		T41	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	228	1			T4	2		T24	1		T98	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	70	1			T4	3		T59	2		T7	5
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	98	1			T183	1		T58	1		T177	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	81	1			T24	1		T42	1		T174	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	69	1			T24	1		T131	1		T164	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	55	1			T58	1		T43	1		T184	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	212	1			T4	3		T31	1		T173	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	270	1			T1	1		T173	2		T26	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	106	1			T5	1		T101	1		T131	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	67	1			T26	1		T185	1		T59	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	58	1			T4	3		T106	1		T86	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	39	1			T4	1		T101	1		T58	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	194	1			T4	1		T173	1		T58	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	403	1			T13	4		T32	1		T100	16
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	103	1			T13	1		T30	1		T32	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	130	1			T4	1		T13	1		T100	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	90	1			T15	1		T100	1		T176	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	78	1			T4	1		T176	1		T186	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	272	1			T15	1		T100	3		T101	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	496	1			T1	2		T24	1		T173	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	121	1			T70	1		T173	2		T64	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	118	1			T26	1		T187	1		T188	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	88	1			T70	1		T173	1		T188	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	88	1			T4	2		T176	3		T58	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	263	1			T4	2		T31	1		T41	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	384	1			T2	5		T12	10		T33	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	117	1			T30	1		T87	1		T98	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	123	1			T2	1		T4	1		T87	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	102	1			T87	1		T173	1		T175	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	83	1			T2	1		T12	1		T31	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	269	1			T2	3		T4	1		T12	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	73	1			T59	5		T7	2		T44	7
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	84	1			T5	1		T31	1		T33	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	78	1			T31	1		T24	1		T8	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	73	1			T4	1		T15	1		T173	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	60	1			T58	1		T121	1		T59	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	171	1			T4	2		T15	1		T24	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	63	1			T59	4		T7	3		T74	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	107	1			T32	1		T100	1		T24	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	111	1			T4	1		T32	1		T177	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	92	1			T13	1		T98	1		T189	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	88	1			T4	2		T13	1		T31	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	275	1			T4	2		T13	4		T100	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	67	1			T59	6		T7	4		T74	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	116	1			T33	1		T176	1		T42	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	97	1			T4	4		T15	1		T181	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	97	1			T4	1		T176	1		T106	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	91	1			T4	1		T70	1		T176	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	265	1			T31	1		T24	3		T173	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	53	1			T59	2		T74	1		T73	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	125	1			T2	1		T4	2		T12	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	102	1			T12	1		T42	1		T185	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	92	1			T2	1		T4	1		T12	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	89	1			T32	1		T87	1		T24	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	267	1			T2	1		T4	3		T12	2

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	211	1			T4	2		T32	2		T24	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	607	1			T1	1		T4	4		T14	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	195	1			T3	1		T4	1		T31	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	625	1			T1	1		T4	2		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	160	1			T4	1		T31	1		T24	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	561	1			T4	5		T14	2		T41	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	196	1			T3	1		T4	4		T14	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	611	1			T3	1		T4	4		T14	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	182	1			T4	2		T70	1		T173	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	413	1			T3	1		T4	7		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	221	1			T4	3		T30	1		T58	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	392	1			T4	6		T14	2		T15	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	235	1			T4	3		T14	1		T41	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	416	1			T4	6		T31	1		T24	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	185	1			T24	1		T42	1		T174	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	400	1			T4	6		T31	1		T24	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	153	1			T4	4		T101	1		T26	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	581	1			T1	1		T4	1		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	276	1			T4	2		T13	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	800	1			T13	5		T15	1		T30	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	271	1			T4	2		T70	1		T173	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	903	1			T1	2		T4	2		T31	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	288	1			T2	2		T4	1		T12	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	790	1			T2	8		T4	1		T12	12
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	188	1			T31	1		T24	1		T173	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	351	1			T4	3		T5	1		T15	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	277	1			T4	2		T13	2		T31	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	459	1			T4	3		T13	4		T32	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	269	1			T4	6		T15	1		T70	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	464	1			T31	1		T33	1		T24	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	262	1			T2	1		T12	2		T32	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	466	1			T2	2		T4	6		T12	3