Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31405

1

T1

45

T2

24

T3

17

auto[1]

304

1

T106

6

T121

7

T131

17

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	31414	1			T1	45		T2	24		T3	17
auto[134217728:268435455]	14	1			T132	1		T211	1		T227	3
auto[268435456:402653183]	5	1			T121	1		T131	1		T313	1
auto[402653184:536870911]	9	1			T121	1		T279	1		T396	1
auto[536870912:671088639]	5	1			T82	1		T227	1		T257	1
auto[671088640:805306367]	7	1			T131	2		T227	1		T379	1
auto[805306368:939524095]	10	1			T273	1		T374	1		T397	2
auto[939524096:1073741823]	10	1			T106	1		T227	1		T379	1
auto[1073741824:1207959551]	12	1			T82	1		T180	1		T313	1
auto[1207959552:1342177279]	6	1			T121	1		T353	1		T398	1
auto[1342177280:1476395007]	10	1			T131	1		T227	1		T239	1
auto[1476395008:1610612735]	3	1			T131	1		T399	1		T400	1
auto[1610612736:1744830463]	6	1			T263	1		T122	1		T227	1
auto[1744830464:1879048191]	6	1			T313	1		T239	1		T374	1
auto[1879048192:2013265919]	11	1			T131	2		T82	1		T232	1
auto[2013265920:2147483647]	14	1			T131	2		T82	1		T132	2
auto[2147483648:2281701375]	11	1			T121	1		T82	1		T122	1
auto[2281701376:2415919103]	10	1			T132	1		T236	1		T257	2
auto[2415919104:2550136831]	12	1			T82	2		T211	1		T353	1
auto[2550136832:2684354559]	16	1			T131	1		T313	1		T122	1
auto[2684354560:2818572287]	9	1			T106	1		T131	1		T239	1
auto[2818572288:2952790015]	10	1			T106	1		T131	2		T232	1
auto[2952790016:3087007743]	10	1			T106	1		T82	1		T227	1
auto[3087007744:3221225471]	7	1			T239	1		T257	3		T230	1
auto[3221225472:3355443199]	8	1			T211	2		T263	1		T232	1
auto[3355443200:3489660927]	12	1			T106	1		T121	1		T131	2
auto[3489660928:3623878655]	11	1			T106	1		T122	1		T227	1
auto[3623878656:3758096383]	10	1			T122	1		T396	1		T230	3
auto[3758096384:3892314111]	10	1			T131	1		T122	1		T232	1
auto[3892314112:4026531839]	12	1			T263	1		T227	1		T379	1
auto[4026531840:4160749567]	13	1			T121	1		T131	1		T227	2
auto[4160749568:4294967295]	6	1			T263	1		T353	1		T239	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	31405	1			T1	45		T2	24		T3	17
auto[0:134217727]	auto[1]	9	1			T121	1		T227	1		T401	1
auto[134217728:268435455]	auto[1]	14	1			T132	1		T211	1		T227	3
auto[268435456:402653183]	auto[1]	5	1			T121	1		T131	1		T313	1
auto[402653184:536870911]	auto[1]	9	1			T121	1		T279	1		T396	1
auto[536870912:671088639]	auto[1]	5	1			T82	1		T227	1		T257	1
auto[671088640:805306367]	auto[1]	7	1			T131	2		T227	1		T379	1
auto[805306368:939524095]	auto[1]	10	1			T273	1		T374	1		T397	2
auto[939524096:1073741823]	auto[1]	10	1			T106	1		T227	1		T379	1
auto[1073741824:1207959551]	auto[1]	12	1			T82	1		T180	1		T313	1
auto[1207959552:1342177279]	auto[1]	6	1			T121	1		T353	1		T398	1
auto[1342177280:1476395007]	auto[1]	10	1			T131	1		T227	1		T239	1
auto[1476395008:1610612735]	auto[1]	3	1			T131	1		T399	1		T400	1
auto[1610612736:1744830463]	auto[1]	6	1			T263	1		T122	1		T227	1
auto[1744830464:1879048191]	auto[1]	6	1			T313	1		T239	1		T374	1
auto[1879048192:2013265919]	auto[1]	11	1			T131	2		T82	1		T232	1
auto[2013265920:2147483647]	auto[1]	14	1			T131	2		T82	1		T132	2
auto[2147483648:2281701375]	auto[1]	11	1			T121	1		T82	1		T122	1
auto[2281701376:2415919103]	auto[1]	10	1			T132	1		T236	1		T257	2
auto[2415919104:2550136831]	auto[1]	12	1			T82	2		T211	1		T353	1
auto[2550136832:2684354559]	auto[1]	16	1			T131	1		T313	1		T122	1
auto[2684354560:2818572287]	auto[1]	9	1			T106	1		T131	1		T239	1
auto[2818572288:2952790015]	auto[1]	10	1			T106	1		T131	2		T232	1
auto[2952790016:3087007743]	auto[1]	10	1			T106	1		T82	1		T227	1
auto[3087007744:3221225471]	auto[1]	7	1			T239	1		T257	3		T230	1
auto[3221225472:3355443199]	auto[1]	8	1			T211	2		T263	1		T232	1
auto[3355443200:3489660927]	auto[1]	12	1			T106	1		T121	1		T131	2
auto[3489660928:3623878655]	auto[1]	11	1			T106	1		T122	1		T227	1
auto[3623878656:3758096383]	auto[1]	10	1			T122	1		T396	1		T230	3
auto[3758096384:3892314111]	auto[1]	10	1			T131	1		T122	1		T232	1
auto[3892314112:4026531839]	auto[1]	12	1			T263	1		T227	1		T379	1
auto[4026531840:4160749567]	auto[1]	13	1			T121	1		T131	1		T227	2
auto[4160749568:4294967295]	auto[1]	6	1			T263	1		T353	1		T239	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1515

1

T1

5

T3

2

T4

5

auto[1]

1744

1

T1

1

T3

3

T4

20

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	113	1			T4	2		T24	2		T173	1
auto[134217728:268435455]	103	1			T3	1		T176	1		T121	1
auto[268435456:402653183]	109	1			T30	1		T70	1		T7	1
auto[402653184:536870911]	93	1			T4	1		T173	1		T26	1
auto[536870912:671088639]	104	1			T1	1		T173	1		T58	1
auto[671088640:805306367]	107	1			T31	1		T70	1		T26	2
auto[805306368:939524095]	99	1			T3	1		T58	1		T182	1
auto[939524096:1073741823]	105	1			T177	1		T106	1		T121	1
auto[1073741824:1207959551]	99	1			T177	1		T6	1		T131	2
auto[1207959552:1342177279]	90	1			T4	1		T58	1		T7	2
auto[1342177280:1476395007]	82	1			T4	1		T15	1		T177	1
auto[1476395008:1610612735]	112	1			T1	2		T3	1		T4	1
auto[1610612736:1744830463]	105	1			T4	1		T5	1		T173	1
auto[1744830464:1879048191]	113	1			T24	1		T45	1		T106	1
auto[1879048192:2013265919]	101	1			T5	1		T24	1		T164	1
auto[2013265920:2147483647]	115	1			T4	1		T15	1		T24	1
auto[2147483648:2281701375]	107	1			T182	1		T121	1		T7	3
auto[2281701376:2415919103]	99	1			T30	1		T26	1		T181	2
auto[2415919104:2550136831]	97	1			T4	1		T70	1		T6	1
auto[2550136832:2684354559]	96	1			T4	1		T24	1		T173	1
auto[2684354560:2818572287]	80	1			T4	2		T15	1		T42	1
auto[2818572288:2952790015]	85	1			T15	1		T98	1		T164	1
auto[2952790016:3087007743]	104	1			T4	3		T70	1		T42	1
auto[3087007744:3221225471]	111	1			T31	1		T24	1		T42	1
auto[3221225472:3355443199]	107	1			T42	1		T177	1		T6	1
auto[3355443200:3489660927]	93	1			T31	2		T42	1		T58	2
auto[3489660928:3623878655]	106	1			T4	1		T70	1		T106	1
auto[3623878656:3758096383]	92	1			T3	1		T4	2		T24	1
auto[3758096384:3892314111]	114	1			T4	2		T173	1		T177	1
auto[3892314112:4026531839]	104	1			T1	1		T3	1		T4	3
auto[4026531840:4160749567]	111	1			T1	1		T4	1		T31	1
auto[4160749568:4294967295]	103	1			T1	1		T4	1		T24	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	47	1			T4	1		T24	2		T26	1
auto[0:134217727]	auto[1]	66	1			T4	1		T173	1		T20	1
auto[134217728:268435455]	auto[0]	43	1			T176	1		T226	1		T44	1
auto[134217728:268435455]	auto[1]	60	1			T3	1		T121	1		T7	2
auto[268435456:402653183]	auto[0]	46	1			T7	1		T215	1		T74	1
auto[268435456:402653183]	auto[1]	63	1			T30	1		T70	1		T60	1
auto[402653184:536870911]	auto[0]	40	1			T173	1		T177	1		T6	1
auto[402653184:536870911]	auto[1]	53	1			T4	1		T26	1		T7	2
auto[536870912:671088639]	auto[0]	53	1			T1	1		T173	1		T8	1
auto[536870912:671088639]	auto[1]	51	1			T58	1		T20	1		T64	1
auto[671088640:805306367]	auto[0]	49	1			T26	2		T132	1		T46	1
auto[671088640:805306367]	auto[1]	58	1			T31	1		T70	1		T163	1
auto[805306368:939524095]	auto[0]	50	1			T58	1		T132	1		T53	1
auto[805306368:939524095]	auto[1]	49	1			T3	1		T182	1		T121	1
auto[939524096:1073741823]	auto[0]	43	1			T106	1		T74	1		T44	1
auto[939524096:1073741823]	auto[1]	62	1			T177	1		T121	1		T131	1
auto[1073741824:1207959551]	auto[0]	43	1			T6	1		T131	1		T59	1
auto[1073741824:1207959551]	auto[1]	56	1			T177	1		T131	1		T132	1
auto[1207959552:1342177279]	auto[0]	46	1			T4	1		T58	1		T7	2
auto[1207959552:1342177279]	auto[1]	44	1			T67	1		T215	1		T278	1
auto[1342177280:1476395007]	auto[0]	42	1			T15	1		T177	1		T53	1
auto[1342177280:1476395007]	auto[1]	40	1			T4	1		T182	1		T7	4
auto[1476395008:1610612735]	auto[0]	50	1			T1	2		T177	1		T59	1
auto[1476395008:1610612735]	auto[1]	62	1			T3	1		T4	1		T7	1
auto[1610612736:1744830463]	auto[0]	43	1			T185	1		T7	1		T53	1
auto[1610612736:1744830463]	auto[1]	62	1			T4	1		T5	1		T173	1
auto[1744830464:1879048191]	auto[0]	53	1			T45	1		T106	1		T7	2
auto[1744830464:1879048191]	auto[1]	60	1			T24	1		T163	1		T7	3
auto[1879048192:2013265919]	auto[0]	57	1			T164	1		T7	1		T82	1
auto[1879048192:2013265919]	auto[1]	44	1			T5	1		T24	1		T21	1
auto[2013265920:2147483647]	auto[0]	65	1			T15	1		T24	1		T173	1
auto[2013265920:2147483647]	auto[1]	50	1			T4	1		T20	1		T86	1
auto[2147483648:2281701375]	auto[0]	51	1			T182	1		T7	2		T91	1
auto[2147483648:2281701375]	auto[1]	56	1			T121	1		T7	1		T90	1
auto[2281701376:2415919103]	auto[0]	47	1			T26	1		T181	1		T8	1
auto[2281701376:2415919103]	auto[1]	52	1			T30	1		T181	1		T7	2
auto[2415919104:2550136831]	auto[0]	40	1			T6	1		T45	1		T7	1
auto[2415919104:2550136831]	auto[1]	57	1			T4	1		T70	1		T45	1
auto[2550136832:2684354559]	auto[0]	39	1			T24	1		T173	1		T98	1
auto[2550136832:2684354559]	auto[1]	57	1			T4	1		T164	2		T51	1
auto[2684354560:2818572287]	auto[0]	31	1			T15	1		T7	1		T21	2
auto[2684354560:2818572287]	auto[1]	49	1			T4	2		T42	1		T64	1
auto[2818572288:2952790015]	auto[0]	33	1			T15	1		T164	1		T7	2
auto[2818572288:2952790015]	auto[1]	52	1			T98	1		T82	1		T211	1
auto[2952790016:3087007743]	auto[0]	48	1			T4	1		T58	1		T182	1
auto[2952790016:3087007743]	auto[1]	56	1			T4	2		T70	1		T42	1
auto[3087007744:3221225471]	auto[0]	52	1			T42	1		T6	1		T20	1
auto[3087007744:3221225471]	auto[1]	59	1			T31	1		T24	1		T185	1
auto[3221225472:3355443199]	auto[0]	58	1			T177	1		T6	1		T59	1
auto[3221225472:3355443199]	auto[1]	49	1			T42	1		T181	1		T189	1
auto[3355443200:3489660927]	auto[0]	43	1			T58	1		T7	1		T215	1
auto[3355443200:3489660927]	auto[1]	50	1			T31	2		T42	1		T58	1
auto[3489660928:3623878655]	auto[0]	55	1			T7	1		T278	1		T74	1
auto[3489660928:3623878655]	auto[1]	51	1			T4	1		T70	1		T106	1
auto[3623878656:3758096383]	auto[0]	44	1			T3	1		T4	1		T24	1
auto[3623878656:3758096383]	auto[1]	48	1			T4	1		T59	1		T180	1
auto[3758096384:3892314111]	auto[0]	59	1			T4	1		T173	1		T45	1
auto[3758096384:3892314111]	auto[1]	55	1			T4	1		T177	1		T64	1
auto[3892314112:4026531839]	auto[0]	55	1			T3	1		T7	1		T132	1
auto[3892314112:4026531839]	auto[1]	49	1			T1	1		T4	3		T64	2
auto[4026531840:4160749567]	auto[0]	45	1			T1	1		T58	1		T278	1
auto[4026531840:4160749567]	auto[1]	66	1			T4	1		T31	1		T6	1
auto[4160749568:4294967295]	auto[0]	45	1			T1	1		T59	2		T8	1
auto[4160749568:4294967295]	auto[1]	58	1			T4	1		T24	1		T173	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1512

1

T1

5

T3

2

T4

6

auto[1]

1748

1

T1

1

T3

3

T4

19

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	87	1			T1	1		T4	1		T30	1
auto[134217728:268435455]	101	1			T4	1		T173	1		T7	5
auto[268435456:402653183]	106	1			T1	1		T4	1		T26	1
auto[402653184:536870911]	81	1			T24	2		T6	1		T50	1
auto[536870912:671088639]	104	1			T4	2		T31	1		T181	1
auto[671088640:805306367]	104	1			T3	1		T30	1		T164	1
auto[805306368:939524095]	99	1			T15	1		T70	1		T58	1
auto[939524096:1073741823]	118	1			T4	2		T5	1		T42	1
auto[1073741824:1207959551]	125	1			T26	1		T42	1		T177	1
auto[1207959552:1342177279]	98	1			T4	1		T24	1		T176	1
auto[1342177280:1476395007]	99	1			T31	1		T26	1		T58	1
auto[1476395008:1610612735]	102	1			T3	1		T31	1		T45	2
auto[1610612736:1744830463]	112	1			T4	1		T173	1		T26	1
auto[1744830464:1879048191]	92	1			T4	1		T24	1		T173	1
auto[1879048192:2013265919]	102	1			T6	1		T131	1		T20	1
auto[2013265920:2147483647]	112	1			T58	2		T64	1		T59	1
auto[2147483648:2281701375]	116	1			T15	1		T177	1		T6	1
auto[2281701376:2415919103]	98	1			T3	1		T4	2		T70	1
auto[2415919104:2550136831]	91	1			T4	1		T70	1		T131	1
auto[2550136832:2684354559]	91	1			T1	1		T173	1		T42	1
auto[2684354560:2818572287]	101	1			T4	1		T7	3		T82	1
auto[2818572288:2952790015]	101	1			T173	1		T7	2		T21	1
auto[2952790016:3087007743]	94	1			T4	3		T70	1		T24	1
auto[3087007744:3221225471]	78	1			T1	2		T4	1		T185	1
auto[3221225472:3355443199]	110	1			T5	1		T15	1		T6	1
auto[3355443200:3489660927]	112	1			T4	1		T31	1		T70	1
auto[3489660928:3623878655]	118	1			T4	1		T24	1		T173	1
auto[3623878656:3758096383]	103	1			T3	1		T4	2		T24	1
auto[3758096384:3892314111]	114	1			T3	1		T121	1		T7	1
auto[3892314112:4026531839]	94	1			T1	1		T173	1		T42	1
auto[4026531840:4160749567]	104	1			T4	2		T15	1		T24	1
auto[4160749568:4294967295]	93	1			T4	1		T31	1		T7	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	46	1			T1	1		T26	1		T98	1
auto[0:134217727]	auto[1]	41	1			T4	1		T30	1		T45	1
auto[134217728:268435455]	auto[0]	45	1			T4	1		T173	1		T7	1
auto[134217728:268435455]	auto[1]	56	1			T7	4		T67	1		T132	1
auto[268435456:402653183]	auto[0]	48	1			T1	1		T58	1		T106	1
auto[268435456:402653183]	auto[1]	58	1			T4	1		T26	1		T59	1
auto[402653184:536870911]	auto[0]	32	1			T6	1		T392	1		T51	1
auto[402653184:536870911]	auto[1]	49	1			T24	2		T50	1		T180	1
auto[536870912:671088639]	auto[0]	52	1			T181	1		T215	1		T278	2
auto[536870912:671088639]	auto[1]	52	1			T4	2		T31	1		T179	1
auto[671088640:805306367]	auto[0]	43	1			T164	1		T22	1		T73	1
auto[671088640:805306367]	auto[1]	61	1			T3	1		T30	1		T7	2
auto[805306368:939524095]	auto[0]	42	1			T15	1		T6	1		T164	1
auto[805306368:939524095]	auto[1]	57	1			T70	1		T58	1		T177	1
auto[939524096:1073741823]	auto[0]	54	1			T4	1		T58	1		T7	2
auto[939524096:1073741823]	auto[1]	64	1			T4	1		T5	1		T42	1
auto[1073741824:1207959551]	auto[0]	52	1			T177	1		T46	1		T22	1
auto[1073741824:1207959551]	auto[1]	73	1			T26	1		T42	1		T182	1
auto[1207959552:1342177279]	auto[0]	46	1			T164	1		T86	1		T94	1
auto[1207959552:1342177279]	auto[1]	52	1			T4	1		T24	1		T176	1
auto[1342177280:1476395007]	auto[0]	54	1			T26	1		T58	1		T59	1
auto[1342177280:1476395007]	auto[1]	45	1			T31	1		T181	1		T7	1
auto[1476395008:1610612735]	auto[0]	43	1			T3	1		T45	2		T185	1
auto[1476395008:1610612735]	auto[1]	59	1			T31	1		T182	1		T106	1
auto[1610612736:1744830463]	auto[0]	47	1			T26	1		T177	1		T7	1
auto[1610612736:1744830463]	auto[1]	65	1			T4	1		T173	1		T59	1
auto[1744830464:1879048191]	auto[0]	39	1			T4	1		T24	1		T173	1
auto[1744830464:1879048191]	auto[1]	53	1			T177	2		T43	1		T7	1
auto[1879048192:2013265919]	auto[0]	44	1			T6	1		T131	1		T86	1
auto[1879048192:2013265919]	auto[1]	58	1			T20	1		T59	2		T8	1
auto[2013265920:2147483647]	auto[0]	47	1			T58	1		T91	1		T17	1
auto[2013265920:2147483647]	auto[1]	65	1			T58	1		T64	1		T59	1
auto[2147483648:2281701375]	auto[0]	61	1			T15	1		T6	1		T182	1
auto[2147483648:2281701375]	auto[1]	55	1			T177	1		T181	1		T182	1
auto[2281701376:2415919103]	auto[0]	46	1			T177	2		T182	1		T121	1
auto[2281701376:2415919103]	auto[1]	52	1			T3	1		T4	2		T70	1
auto[2415919104:2550136831]	auto[0]	45	1			T7	1		T53	1		T113	1
auto[2415919104:2550136831]	auto[1]	46	1			T4	1		T70	1		T131	1
auto[2550136832:2684354559]	auto[0]	41	1			T131	1		T7	1		T50	1
auto[2550136832:2684354559]	auto[1]	50	1			T1	1		T173	1		T42	1
auto[2684354560:2818572287]	auto[0]	45	1			T7	2		T82	1		T8	1
auto[2684354560:2818572287]	auto[1]	56	1			T4	1		T7	1		T74	1
auto[2818572288:2952790015]	auto[0]	51	1			T173	1		T21	1		T86	2
auto[2818572288:2952790015]	auto[1]	50	1			T7	2		T53	1		T62	1
auto[2952790016:3087007743]	auto[0]	45	1			T4	1		T59	2		T7	1
auto[2952790016:3087007743]	auto[1]	49	1			T4	2		T70	1		T24	1
auto[3087007744:3221225471]	auto[0]	34	1			T1	2		T185	1		T7	1
auto[3087007744:3221225471]	auto[1]	44	1			T4	1		T163	1		T164	1
auto[3221225472:3355443199]	auto[0]	50	1			T6	1		T20	1		T215	1
auto[3221225472:3355443199]	auto[1]	60	1			T5	1		T15	1		T163	1
auto[3355443200:3489660927]	auto[0]	58	1			T70	1		T132	1		T51	1
auto[3355443200:3489660927]	auto[1]	54	1			T4	1		T31	1		T24	1
auto[3489660928:3623878655]	auto[0]	51	1			T24	1		T173	1		T58	1
auto[3489660928:3623878655]	auto[1]	67	1			T4	1		T121	1		T211	1
auto[3623878656:3758096383]	auto[0]	51	1			T3	1		T4	1		T24	1
auto[3623878656:3758096383]	auto[1]	52	1			T4	1		T7	1		T53	1
auto[3758096384:3892314111]	auto[0]	58	1			T74	1		T92	1		T222	1
auto[3758096384:3892314111]	auto[1]	56	1			T3	1		T121	1		T7	1
auto[3892314112:4026531839]	auto[0]	45	1			T1	1		T173	1		T42	1
auto[3892314112:4026531839]	auto[1]	49	1			T98	1		T64	1		T59	1
auto[4026531840:4160749567]	auto[0]	52	1			T4	1		T15	1		T24	1
auto[4026531840:4160749567]	auto[1]	52	1			T4	1		T106	1		T20	1
auto[4160749568:4294967295]	auto[0]	45	1			T7	1		T21	2		T54	1
auto[4160749568:4294967295]	auto[1]	48	1			T4	1		T31	1		T392	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1538

1

T1

6

T3

2

T4

6

auto[1]

1720

1

T3

3

T4

19

T5

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	87	1			T4	2		T121	1		T86	1
auto[134217728:268435455]	106	1			T3	1		T58	1		T121	1
auto[268435456:402653183]	109	1			T4	3		T24	1		T182	1
auto[402653184:536870911]	84	1			T31	1		T181	1		T164	1
auto[536870912:671088639]	96	1			T5	1		T24	1		T6	2
auto[671088640:805306367]	95	1			T1	1		T3	1		T4	2
auto[805306368:939524095]	109	1			T1	1		T4	1		T59	1
auto[939524096:1073741823]	100	1			T70	1		T58	1		T45	1
auto[1073741824:1207959551]	119	1			T4	2		T181	1		T7	2
auto[1207959552:1342177279]	113	1			T15	1		T24	1		T26	1
auto[1342177280:1476395007]	106	1			T1	1		T15	1		T173	1
auto[1476395008:1610612735]	103	1			T4	1		T173	1		T185	1
auto[1610612736:1744830463]	88	1			T3	1		T58	1		T177	1
auto[1744830464:1879048191]	118	1			T3	1		T4	1		T70	2
auto[1879048192:2013265919]	103	1			T1	1		T20	1		T7	1
auto[2013265920:2147483647]	93	1			T4	1		T30	1		T31	1
auto[2147483648:2281701375]	101	1			T4	2		T31	1		T6	1
auto[2281701376:2415919103]	90	1			T24	1		T173	1		T42	1
auto[2415919104:2550136831]	92	1			T4	1		T177	1		T59	1
auto[2550136832:2684354559]	83	1			T4	1		T163	1		T7	2
auto[2684354560:2818572287]	99	1			T4	1		T24	1		T173	1
auto[2818572288:2952790015]	101	1			T15	1		T26	1		T182	1
auto[2952790016:3087007743]	111	1			T4	3		T31	1		T176	1
auto[3087007744:3221225471]	98	1			T24	1		T173	1		T177	1
auto[3221225472:3355443199]	108	1			T4	2		T173	1		T26	1
auto[3355443200:3489660927]	103	1			T31	1		T173	1		T177	1
auto[3489660928:3623878655]	125	1			T5	1		T70	1		T177	1
auto[3623878656:3758096383]	110	1			T1	2		T4	1		T24	1
auto[3758096384:3892314111]	110	1			T3	1		T70	1		T24	1
auto[3892314112:4026531839]	100	1			T4	1		T58	1		T6	1
auto[4026531840:4160749567]	107	1			T58	2		T7	1		T21	1
auto[4160749568:4294967295]	91	1			T82	1		T21	1		T74	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	37	1			T4	1		T60	1		T340	1
auto[0:134217727]	auto[1]	50	1			T4	1		T121	1		T86	1
auto[134217728:268435455]	auto[0]	53	1			T3	1		T58	1		T7	2
auto[134217728:268435455]	auto[1]	53	1			T121	1		T164	1		T53	1
auto[268435456:402653183]	auto[0]	43	1			T4	1		T24	1		T7	2
auto[268435456:402653183]	auto[1]	66	1			T4	2		T182	1		T64	1
auto[402653184:536870911]	auto[0]	38	1			T164	1		T54	1		T74	1
auto[402653184:536870911]	auto[1]	46	1			T31	1		T181	1		T211	1
auto[536870912:671088639]	auto[0]	40	1			T24	1		T6	2		T182	1
auto[536870912:671088639]	auto[1]	56	1			T5	1		T131	2		T64	1
auto[671088640:805306367]	auto[0]	45	1			T1	1		T15	1		T42	1
auto[671088640:805306367]	auto[1]	50	1			T3	1		T4	2		T30	1
auto[805306368:939524095]	auto[0]	59	1			T1	1		T7	2		T21	1
auto[805306368:939524095]	auto[1]	50	1			T4	1		T59	1		T67	1
auto[939524096:1073741823]	auto[0]	44	1			T58	1		T20	1		T92	1
auto[939524096:1073741823]	auto[1]	56	1			T70	1		T45	1		T182	1
auto[1073741824:1207959551]	auto[0]	57	1			T7	2		T8	1		T215	1
auto[1073741824:1207959551]	auto[1]	62	1			T4	2		T181	1		T8	1
auto[1207959552:1342177279]	auto[0]	49	1			T15	1		T24	1		T26	1
auto[1207959552:1342177279]	auto[1]	64	1			T177	1		T45	1		T7	1
auto[1342177280:1476395007]	auto[0]	54	1			T1	1		T173	1		T26	1
auto[1342177280:1476395007]	auto[1]	52	1			T15	1		T106	1		T121	1
auto[1476395008:1610612735]	auto[0]	50	1			T173	1		T185	1		T132	1
auto[1476395008:1610612735]	auto[1]	53	1			T4	1		T64	1		T7	2
auto[1610612736:1744830463]	auto[0]	33	1			T3	1		T58	1		T106	1
auto[1610612736:1744830463]	auto[1]	55	1			T177	1		T59	1		T163	1
auto[1744830464:1879048191]	auto[0]	50	1			T6	1		T45	1		T50	1
auto[1744830464:1879048191]	auto[1]	68	1			T3	1		T4	1		T70	2
auto[1879048192:2013265919]	auto[0]	58	1			T1	1		T7	1		T211	1
auto[1879048192:2013265919]	auto[1]	45	1			T20	1		T46	1		T259	2
auto[2013265920:2147483647]	auto[0]	45	1			T4	1		T173	1		T42	1
auto[2013265920:2147483647]	auto[1]	48	1			T30	1		T31	1		T64	1
auto[2147483648:2281701375]	auto[0]	54	1			T6	1		T106	1		T8	1
auto[2147483648:2281701375]	auto[1]	47	1			T4	2		T31	1		T121	1
auto[2281701376:2415919103]	auto[0]	39	1			T177	1		T7	1		T132	1
auto[2281701376:2415919103]	auto[1]	51	1			T24	1		T173	1		T42	1
auto[2415919104:2550136831]	auto[0]	44	1			T177	1		T59	1		T7	1
auto[2415919104:2550136831]	auto[1]	48	1			T4	1		T22	1		T238	1
auto[2550136832:2684354559]	auto[0]	45	1			T7	2		T8	1		T54	1
auto[2550136832:2684354559]	auto[1]	38	1			T4	1		T163	1		T8	1
auto[2684354560:2818572287]	auto[0]	47	1			T4	1		T173	1		T88	1
auto[2684354560:2818572287]	auto[1]	52	1			T24	1		T121	1		T131	1
auto[2818572288:2952790015]	auto[0]	48	1			T15	1		T26	1		T164	1
auto[2818572288:2952790015]	auto[1]	53	1			T182	1		T7	1		T278	1
auto[2952790016:3087007743]	auto[0]	55	1			T4	1		T6	1		T181	1
auto[2952790016:3087007743]	auto[1]	56	1			T4	2		T31	1		T176	1
auto[3087007744:3221225471]	auto[0]	43	1			T24	1		T173	1		T59	1
auto[3087007744:3221225471]	auto[1]	55	1			T177	1		T164	1		T7	1
auto[3221225472:3355443199]	auto[0]	50	1			T4	1		T26	1		T45	1
auto[3221225472:3355443199]	auto[1]	58	1			T4	1		T173	1		T42	1
auto[3355443200:3489660927]	auto[0]	42	1			T173	1		T182	1		T7	2
auto[3355443200:3489660927]	auto[1]	61	1			T31	1		T177	1		T7	2
auto[3489660928:3623878655]	auto[0]	62	1			T177	1		T59	1		T278	1
auto[3489660928:3623878655]	auto[1]	63	1			T5	1		T70	1		T163	1
auto[3623878656:3758096383]	auto[0]	49	1			T1	2		T24	1		T58	1
auto[3623878656:3758096383]	auto[1]	61	1			T4	1		T26	1		T20	1
auto[3758096384:3892314111]	auto[0]	57	1			T45	1		T182	1		T7	1
auto[3758096384:3892314111]	auto[1]	53	1			T3	1		T70	1		T24	1
auto[3892314112:4026531839]	auto[0]	43	1			T6	1		T7	2		T132	1
auto[3892314112:4026531839]	auto[1]	57	1			T4	1		T58	1		T121	1
auto[4026531840:4160749567]	auto[0]	57	1			T58	1		T21	1		T278	1
auto[4026531840:4160749567]	auto[1]	50	1			T58	1		T7	1		T52	1
auto[4160749568:4294967295]	auto[0]	48	1			T82	1		T21	1		T74	1
auto[4160749568:4294967295]	auto[1]	43	1			T22	1		T224	2		T184	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1510

1

T1

6

T3

3

T4

5

auto[1]

1748

1

T3

2

T4

20

T5

2